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Folded Cascode Amplifier Report

The document summarizes the design process of a folded cascode amplifier. It describes: 1. The initial transistor sizing using equations to set widths and lengths (W/L ratios) to achieve target currents. 2. Modifying the ratios through simulation to optimize performance. Key modifications included increasing lengths to boost output resistance and gain. 3. Designing the bias voltages and currents, including adjusting widths to ensure currents remained as intended. 4. A tradeoff between gain and bandwidth, where higher gain requires larger W and L, increasing capacitance and reducing bandwidth.

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马宗宇
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371 views

Folded Cascode Amplifier Report

The document summarizes the design process of a folded cascode amplifier. It describes: 1. The initial transistor sizing using equations to set widths and lengths (W/L ratios) to achieve target currents. 2. Modifying the ratios through simulation to optimize performance. Key modifications included increasing lengths to boost output resistance and gain. 3. Designing the bias voltages and currents, including adjusting widths to ensure currents remained as intended. 4. A tradeoff between gain and bandwidth, where higher gain requires larger W and L, increasing capacitance and reducing bandwidth.

Uploaded by

马宗宇
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Folded Cascode Amplifier Report

Ma Zongyu 20644450
Amplifier Design Process
We assume all the transistor work based on nmos1.mod and pmos1.mod, and bias current and
supply voltage we select are 20uA and 5V respectively. In order to drive the power transistor of
linear regulator, we set output capacitor 50pF.

○
1 W/L ratio Design

IDS11=40uA and IDS1,2 = 20uA, by assuming All overdrive voltage are 0.2V, the W/L ratio can
be given that
𝑊 2𝐼!
=
𝐿 𝜇𝐶"# (𝑉$% − 𝑉& )'
W W
- 0 = 10.26 , - 0 = 24.64
L (,' L ((
The gm9,10 should be made as twice as gm1,2 for lower SNR，and I9,10 = 2I1,2, then
𝑊 g '*
=
𝐿 2𝜇𝐶"# I+,
Table 1 W/L Ratio Design
M1 M2 M3 M4 M5 M6
W/L (um) 10.26/1.2 10.26/1.2 10.26/1.2 10.26/1.2 10.26/1.2 10.26/1.2
M7 M8 M9 M10 M11
W/L (um) 2.25/1.2 2.25/1.2 5/1.2 5/1.2 24.64/1.2

○
2 Table for all biasing voltage

Fig. 1
From Model file, we can get Vtn and |Vtp| are between 0.3V and 0.4V. By assuming Vdssat=0.2V, then
the biasing voltage can be derived.
Table 2 biasing voltage
Vp1 Vdd - |Vtp| - VSDsat =4.4V
Vp2 Vdd - |Vtp| - 2VSDsat =4.2V
Vn1 Vss + Vtn + VDSsat = 0.6V
Vn2 Max{Vdd – VSDsat-Vtn,Vss+Vtn+2VDSsat}

③Indicate all Currents


Table 3 Currents
M1 M2 M3 M4 M5 M6
IDS（uA） 20 20 20 20 20 20
M7 M8 M9 M10 M11
IDS（uA） 20 20 40 40 40

④Explain design work


The calculation work in ratio design has been done in part ①，then modification work has been
done with simulation, and the modified ratio is as follows:

Table 4 Modified W/L Ratio


M1 M2 M3 M4 M5 M6
W/L (um) 9/1.2 9/1.2 21/1.2 21/1.2 21/1.2 21/1.2
M7 M8 M9 M10 M11
W/L (um) 2.25/1.2 2.25/1.2 5/1.2 5/1.2 28.6/1.2

⑤Gain Adjustment
The gain equation of this amplifier can be derived as below:

|𝐴" | = 𝑔-( (𝑟". (1 + 𝑔-. 𝑟"/ )‖𝑟"0 (1 + g *0 (𝑟"( ‖𝑟1(2 ))

For cascode amplifier, the most way to increasing gain is to enhance output resistance, which
means the gain can be improved by increasing the length of ro3 ~ro10, and adjusting width to make
sure the current not change too much, because

r1 ∝ (L − 2L+ − x+ )

So, some of length are increased to get high resistance, and modification result is given below:

Table 5 Modified W/L Ratio for high gain


M1 M2 M3 M4 M5 M6
W/L (um) 9/1.2 9/1.2 42/2.4 42/2.4 42/2.4 42/2.4
M7 M8 M9 M10 M11
W/L (um) 12.5/6 12.5/6 17.6/6 17.6/6 29.2/1.2
⑥ Tradeoff
The total capacitance Cgtot will increase with W and L going up, and the unity-gain frequency
fT will be reduced with it.
C3414 ∝ WLC15
1
f6 ∝
W 2.8 L(.8
High-Swing Cascode Biasing Design Process

The biasing circuit has been designed, and the graph is shown:

Fig. 2 Circuit Design

According to simulation and modification, the bias voltages are designed:


Table 6 Modified Bias Voltage Design
Vp1 4.412V
Vp2 4.2V
Vn1 0.6V
Vn2 2.3V

I DS12 and ID13 are set to 40uA, and VSG12= 588mV while VSG13 =800mV, So the overdrive voltage
is about 410mV for M13.
𝑊 2𝐼!
=
𝐿 𝜇𝐶"# (𝑉$% − 𝑉& )'

W 12.9 W 27.1
- 0 = , - 0 =
L (9 2.4 L (' 1.2
Then IDS16 and IDS14 are equal to 40mA, so

W 17.6 W 29.2
- 0 = , - 0 =
L (. 6 L (/ 1.2

For M15, its VGS = 2.3V, so its width is very small even it has 6um length.

W 1.23
- 0 =
L (8 6
After simulation, we modified some value of them, and the designed value and modified value are
compared in the following table.

Table 7 Comparison of designed and Modified Ratio


M1 M1 M2 M2 M3 M3 M4 M4
W/L(um) 9/1.2 9/1.2 9/1.2 9/1.2 42/2.4 42/2.4 42/2.4 42/2.4
M5 M5 M6 M6 M7 M7 M8 M8
W/L(um) 42/2.4 42/2.4 42/2.4 42/2.4 12.5/6 11.25/6 12.5/6 11.25/6
M9 M9 M10 M10 M11 M11 M12 M12
W/L(um) 17.6/6 17.7/6 17.6/6 17.7/6 29.2/1.2 30/1.2 27.1/1.2 27.7/1.2
M13 M!3 M14 M14 M15 M15 M16 M16
W/L(um) 12.9/2.4 16.8/2.4 29.2/1.2 30.5/1.2 1.23/6 0.63/6 26.8/6 17.7/6

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