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CMOS Inverter

The document summarizes the design and analysis of a CMOS inverter in Cadence Virtuoso. Key steps included: 1) Designing the schematic and symbol of the CMOS inverter. 2) Plotting the voltage transfer characteristics (VTC) using DC analysis and observing how varying the width of the PMOS or NMOS affects the switching threshold. 3) Plotting input/output waveforms, power dissipation, and energy and calculating average and peak power dissipation.

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163 views3 pages

CMOS Inverter

The document summarizes the design and analysis of a CMOS inverter in Cadence Virtuoso. Key steps included: 1) Designing the schematic and symbol of the CMOS inverter. 2) Plotting the voltage transfer characteristics (VTC) using DC analysis and observing how varying the width of the PMOS or NMOS affects the switching threshold. 3) Plotting input/output waveforms, power dissipation, and energy and calculating average and peak power dissipation.

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t19125 t19125
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© © All Rights Reserved
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Design CMOS inverter in Cadence Virtuoso and to study it’s dc and

transient analysis.
Rishabh Soni (T19125)
CMOS Digital IC Design Practicum
Date Performed: August 21,2019
Instructor: Dr. Rahul Shrestha

I. O BJECTIVE voltage.The VTC indicates that for low input voltage,the


• To design the schematic and symbol of the CMOS circuit output is high and for high input ,the output goes
inverter in Cadence Virtuoso. towards zero volts.
• To plot the voltage transfer characteristics of CMOS
inverter by DC analysis. B. Power dissipation
• TO observe the change in switching threshold in VTC by
varying the width of P or N type mos. The CMOS inverter dissipates the negligible power during
• To plot the waveform of input voltage, output voltage, the steady state operation ,power dissipation only occurs
power dissipated and energy for CMOS inverter. during the charging and discharging of the load capacitance
• To calculate the average and peak power dissipation of through the PMOS and NMOS respectively .there are the
above mentioned. following classification of the power dissipation in the CMOS
inverter i.e. dynamic power dissipation,static power dissipation
II. T HEORY and direct path power dissipation or we can call it as short
The inverter is the most basic logic and the Fig.1 shows the circuit power dissipation.the dynamic power dissipation is
symbol,truth table,and the structure of a CMOS inverter.As the dominating among the above three and the static power
shown the structure consists of a combination of a PMOS dissipation is very less or negligible.
transistor at the top and a NMOS transistor at the bottom.
CMOS is also called as complementary-symmetry metal III. S IMULATION RESULTS
oxide semiconductor.The word complementary symmetry re-
fer to the fact that during designing of CMOS we uses
complementary and symmetrical pair of P-type and N-type
MOSFET’s.
dia.jpg

Fig. 2. Schematic of CMOS inverter

Fig. 1. Block diagram of CMOS inverter

A. Voltage Transfer Characteristics


The quality of the CMOS inverter is measured using the Fig. 3. Symbol
voltage transfer curve,it is a plot of input voltage Vs output
Fig. 4. Testbentch of CMOS inverter Fig. 8. Waveforms(Input,Output,Power,Energy)

1.jpg

Fig. 9. Waveforms showing glitches during transition


Fig. 5. VTC curve of inverter for equal w/l

2.jpg

Fig. 10. waveforms for delay measurement

Fig. 6. VTC curve of CMOS with (W/L)p=2.5(W/L)n


IV. C ONCLUSION

• The CMOS inverter has been studied by the schematic


and symbol designed in Cadence Virtuoso.
• When the ratio of the width over length of PMOS
is equal to the ratio of NMOS, the switching thresh-
old voltage(Vm) of inverter is 529.9mV and when
(W/L)p=2.5(W/L)n ,the switching threshold voltage of
inverter is 596.14mV which is approximately equal to
the half of the supply voltage (1.2V) and we got the
symmetrical VTC for CMOS inverter and this condition
is also stands for equal rise time and fall time situation.
• The average and peak power dissipation obtained as a
Fig. 7. VTC curve with variable PMOS width
result simulation are 213.5nW and 2.031mW respectively.
• A delay of 3.6ps is observed.
R EFERENCES
[1] Behzad razavi, Design of analog CMOS integrated circuits,indian edi-
tion, 2002
[2] Jan M Rabaey, Anantha P Chandrakasan, Borivoje Nikolic, Digital
integrated circuits:A design perspective-Pearson, 2003

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