INTRODUCTION

An inverter is a basic logic gate performing Boolean operation on a single input variable. Its
structure consists of a combination of a pMOS transistor at the top and an nMOS transistor at the
bottom [1].

Figure 1; CMOS inverter diagram [2].

Static Inverter Characteristics.

Static inverter quality and operation is often measured using the Voltage Transfer Curve which is
a plot of input vs. output voltage. From such a graph, device parameters including noise tolerance,
gain, and operating logic-levels can be obtained.

Figure 2; Static Inverter Characteristics [2].

Ideally, the voltage transfer curve (VTC) appears as an inverted step-function - this would indicate
precise switching between On and Off or High and Low states, but in real devices, a gradual
transition region exists.
The VTC indicates that for low input voltage, the circuit outputs high voltage; for high input, the
output tapers off towards 0 volts. The slope of this transition region is a measure of the slope which
yields precise switching.

EXPERIMENTS
A) Designing an inverter circiut using the package Microwind2
The experiments were carried out using the package Microwind2 simulator tool.

Figure 3; CMOS inverter designer from Microwind2 software.

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In figure 3, It can be seen that an inverter circuit was designed using the package Microwind2. The
‘N Well’ layer of dimension 50 λ by 50 λ was used as a basis for the pMOS transistor which was
placed at the top half of the screen.The polysilicon was then selected for both transistors.
The n+ diffusion region for the nMOS transistor was created using the ‘N+ Diffusion’ with the
dimmessions of 12 λ by 12 λ centred across the polysilicon line. Then the p+ diffusion region for
the pMOS transistor with dimmesions 24 λ by 24 λ was also created centred across the polysilicon
line in the middle of the n-well area.
The contacts for both transistors were then placed on both sides of the transistor’s diffusion
regions, then the transistors were connected together using a Metal 1 layer of dimession 4 λ.
Power supply lines of dimension 4 λ by 20 λ were placed above and below the inverters for the
unconnected p-contact to the top power line and from the n-contact to the ground line. The inverter
circuit was successfully designed and the ‘drc’was run to confirm that the design had no errors.

B) Investigating the basic static behaviour of the inverter.

Using the designed CMOS inverter from section A, the Vdd (supply)and Vss (ground) were assigned
using the the icons and from the palette window respectively to the two metal lines as shown
in figure…
Then the input of the inverter was assigned as 2.00ns for the value of the rise, fall, high and low
time, then labeled as the ‘input’using the icon from the palette window as shown in figure 4

Figure 4; Setting the clock pulse time

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Finally the icon was used to indicate the output of the inverter and was labeled as output, the
simulation was later run successfully.
Draw the voltage transform V0 vs.Vin.

Figure 5; Voltage output waveform for V0 vs Vin

In figure 5, it can be seen from the voltage transform Vo vs Vin that low input voltages givehigh
outputs and high inputs voltages give low output voltages at the output.
Draw time vs. input and output voltage showing rise and fall time.

Figure 6; Time vs Voltage waveforms

In figure 6, it can be seen that there is a variation between time and the input and output voltages
with the rise time at 2ns and fall time at 2ns.

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Draw time vs. output voltage and output current. Explain the cause of this current using the
transistor diagram of the inverter.

Figure 7; Time vs Output Voltage and Current waveforms

In figure 7, it can be seen that there is a variation of time with respect to the current for a static
inverter with a maximum current at 0.5mA and a maximum voltage of 5v.

Figure 8; Current flow in the CMOS inverter [3]

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In figure 8, it can be seen that current flows through the static inverter depending on the level of
the input signal.
Considering a LOW input to the CMOS inverter, pMOS will be ON while nMOS will be OFF.
Therefore the pMOS will be seen as a resistor with low current flowing through the inverter, since
nMOS is OFF the capacitor charges as current goes to through to the ground.
For a HIGH input to the CMOS inveter, nMOS transitor will be ON while the pMOS transistor
will be OFF. The capacitor will discharge current through the nMOS transistor giving rise to the
current flow from the capacitor through nMOS to the ground.
Calculate the maximum power consumption.
Pmax = Vmax × Imax (1)
= Vdd × Imax
= 5V × 0.537 × 10−3A
= 2.69 × 10−3W
= 2.69mW

Calculate the average power consumption. Explain the difference between the Current taken
out of the supply and the power dissipated as heat.
Pavg = Vavg × Iavg (2)
𝑇
= Vdd × ∫0 𝐼 𝑑𝑡
(0.5×0.6×10−3 𝐴×1.6×10−9 𝑆)
=5V× A Current obtained by approximation
(8×10−9 𝑆)

= 0.3mW
= 300µW
The inverter consumes power during transitions, due to two separate effects. The first is short
circuit power arising from momentary short-circuit current that flow from VDD to VSS when the
transistor functions in the incomplete-on/off state. During this time, both the nMOS and pMOS
transistors are on, and current can flow from the power supply to ground. The second is the
charging/discharging power, which depends on the output wire capacitance. The power
consumption occurs briefly during transitions of the output, either from 0 to 1 or from 1 to 0.

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Calculate the maximum frequency of operation.

Figure 9; Rise time and Fall time

In figure 9, it can be seen that there is equal time of 2ns for the rising time(tr) and falling time
(tf)
1 1
Maximum Frequency = 𝑡 ≅ (3)
𝑟 +𝑡𝑓 𝑡𝑟 ×𝑓𝑎𝑐𝑡𝑜𝑟

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=(2×10−9 )×2 where the factor lies between 2 to 3

= 250MHz
Measure the gate response time (propagation delay). Explain what this figure qualifies.

Figure 10; Inverter propagation delays

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In figure 10, it can be seen that there are two propagation delay times for a static inverter. That is
the propagation delay from high to low (tpHL = 315ps ) and the propagation delay from low to
high (tpLH = 456ps). Considering the highest value to be the propagation delay for the entire
CMOS inverter therefore the propagation delay is 456ps.

The gate response time (propagation delay) of a static inverter is the difference in time calculated
at 50% of input-output transition, when output switches after application of input. The gate
response time provides the measure for how long it takes for a signal to move from thr input to the
output.

CONCLUSIONS
A CMOS inverter is always constructed from a pMOS at the top and nMOS transistor at the botton
with defined dimension for the different regions.
A CMOS inverter always gives an output HIGH for a low input and an output Low for a HIGH
input.
Power is only consumed during switching, when the inverter is chaing states
Gate respone time is a very important parameter for the inverter which indicates how long it takes
for a signal to move from the input to the output.

REFERENCES
[1] “CMOS Inverter (Theory) : Digital VLSI Design Virtual lab : Electronics &
Communications : Amrita Vishwa Vidyapeetham Virtual Lab.” [Online]. Available:
http://vlab.amrita.edu/index.php?sub=59&brch=165&sim=901&cnt=1. [Accessed: 15-
Oct-2019].
[2] S. Andreas, Class Lecture, “Introduction to CMOS VLSI Design.” School of Electronic and
Electrical Engineering, Technological University of Dublin.
[3] “Embedded Computer Architecture 5SAI0 Technology - ppt download.” [Online].
Available: https://slideplayer.com/slide/16084316/. [Accessed: 17-Oct-2019].