VHDL

5051158-3002

Lecture 3
VHDL Basics – part 2
Test benches
Contents of this lecture
• VHDL Basics – part 2
• Arrays and indexing, user types
• Generics
• Using generics in hierarchical design
• Test bench (for simulation)
Arrays in VHDL
signal b_bus: std_logic_vector (3 downto 0);
• 2 ways to combine “bits” to signal x,y,z,w: std_logic;
“arrays”
b_bus <= x & "00" & w;
• Concatenation
• Aggregate b_bus <= (2=>x,1=>y,3=>z,0=>d);
• Named association
b_bus <= (x,y,z,d);
• Positional association
• Indexing signal z_bus: std_logic_vector(3 downto 0);
• Accessing a “slice” of an array signal a_bus: std_logic_vector (1 to 4);
• The direction of the slice (i.e. a_bus <= z_bus; -- ok
to or downto) must match z_bus(3 downto 2) <= "00"; --ok
the direction in which the a_bus(2 to 4) <= z_bus(3 downto 1); --ok
array is declared z_bus(2 to 3) <= "00"; -- NOT OK
Multi-dimensional Arrays and User Types
• An array contains multiple
elements of same type
• Note: std_locic_vector is type MY_BUS is array (3 downto 0) of std_logic_vector(15 downto 0);
also an array, composed of type RAM is array (0 to 31) of integer range 0 to 255;
several std_logic types – signal A_BUS : MY_BUS;
defined in std_logic_1164- signal RAM_0 : RAM;
package
• When any array object is
declared, an existing array
type must be used
• Multi-dimensional arrays
are especially useful, when
using generate loops (we’ll
see that later)
Entity - Generics
• To improve the reusability and flexibility of your entity entity_name is
code (especially true for components), you can
use generics generic (generic list);
port (port list);
end entity_name;
• generic is a parameter- or a “specification”,
which value is evaluated during component component_name
compilation/synthesis
• NOTE: it does not “change” your block run-time generic (generic_list);
port (port_list);
• Generics are listed in entity, before port list.
Similarly, component needs to have a generic list end component;
as well, as it represents the “interface” of an
entity instance_label: component_name
• On instantiation, values are associated to generic map (generic_association_list)
generics – the default value of generic (in a port map (port_association_list);
component) is overridden
Generics – an example
• Consider a clocked 4:1 bus multiplexer architecture rtl of busmux4to1 is
• What if the width of the data bus begin
sync_mux_p: process(clk, n_Reset)
changes? begin
• In this case the architecture does not if n_Reset = '0' then
require any change (note how we reset the Y <= (others => '0');
elsif rising_edge(clk) then
output), but entity need to be changed case S is
when "00" => Y <= A;
entity busmux4to1 is
when "01" => Y <= B;
port (
when "10" => Y <= C;
clk, n_Reset: in std_logic;
when others => Y <= D;
A,B,C,D : in std_logic_vector(7 downto 0);
end case;
S : in std_logic_vector(1 downto 0);
end if; --clk/rst
Y : out std_logic_vector(7 downto 0)
end process sync_mux_p;
);
end architecture rtl;
end busmux4to1;
 Generics – an example (cont.)
• Added a generic
• Default value: 8 architecture rtl of gen_busmux4to1 is
begin
• Note: No change in architecture (in this sync_mux_p: process(clk, n_Reset)
case) begin
if n_Reset = '0' then
entity gen_busmux4to1 is Y <= (others => '0');
generic ( elsif rising_edge(clk) then
DATA_WIDTH : integer := 8 case S is
); when "00" => Y <= A;
port ( when "01" => Y <= B;
clk, n_Reset: in std_logic; when "10" => Y <= C;
A,B,C,D : in std_logic_vector(DATA_WIDTH-1 downto 0); when others => Y <= D;
S : in std_logic_vector(1 downto 0); end case;
Y : out std_logic_vector(DATA_WIDTH-1 downto 0) end if; --clk/rst
); end process sync_mux_p;
end gen_busmux4to1; end architecture rtl;
 Generics – an example (cont.)
• How about making it 16-bits wide? Or 32-bits?
• Change the value of generic
• But, we really don’t want to change it every time – better to use it as a component
and override the default value when instantiating the component

entity gen_busmux4to1 is entity gen_busmux4to1 is

generic ( generic (
DATA_WIDTH : integer := 16 DATA_WIDTH : integer := 32
); );
port ( port (
clk, n_Reset: in std_logic; clk, n_Reset: in std_logic;
A,B,C,D : in std_logic_vector(DATA_WIDTH-1 downto 0); A,B,C,D : in std_logic_vector(DATA_WIDTH-1 downto 0);
S : in std_logic_vector(1 downto 0); S : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(DATA_WIDTH-1 downto 0) Y : out std_logic_vector(DATA_WIDTH-1 downto 0)
); );
end gen_busmux4to1; end gen_busmux4to1;
 RECAP: VHDL Components and hierarchical design
component component_name is
• A component declaration declares a virtual generic (generic_list);
design entity interface that may be used in
component instantiation statement port (port_list);
• A component represents an end
entity/architecture pair. It specifies a component component_name;
subsystem, which can be instantiated in
another architecture leading to a hierarchical
specification. architecture rtl of xxx is
• Component instantiation is like plugging a component XOR_4 is
hardware component into a socket in a board port(A,B: in std_logic_vector(0 to 3);
C: out std_logic_vector(0 to 3));
• A component must be declared before it is end component XOR_4;
instantiated
• The component declaration defines the virtual
interface of the instantiated design entity ("the signal S1,S2 : std_logic_vector(0 to 3);
socket") signal S3 : std_logic_vector(0 to 3);
• Most often, the declaration takes in the main
code ( in the architecture, before “begin”) or begin
in separate packages (more on this later) X1 : XOR_4
• Generics and ports of a component are copies port map(A => S1,B => S2,C => S3);
of generics and ports of the entity the
component represents. end architecture rtl;
 Generics and hierarchy begin
entity mux_top is
n_Reset <= ‘1';
port (
sysclk: in std_logic;
i_busmux16: gen_busmux4to1
S: in std_logic_vector(1 downto 0);
generic map (
Q : out std_logic_vector(15 downto 0);
DATA_WIDTH => 16
Q_wide : out std_logic_vector(31 downto 0));
)
end mux_top;
port map (n_Reset => n_Reset,
clk => sysclk,
architecture rtl of mux_top is A => E, B => F, C => G, D => H,
component gen_busmux4to1 is S => S,
generic ( DATA_WIDTH : integer := 8 ); Y => Q);
port (
clk, n_Reset: in std_logic; i_busmux32: gen_busmux4to1
A,B,C,D : in std_logic_vector(DATA_WIDTH-1 downto 0); generic map (
S : in std_logic_vector(1 downto 0); DATA_WIDTH => 32
Y : out std_logic_vector(DATA_WIDTH-1 downto 0) )
); port map (n_Reset => n_Reset,
end component gen_busmux4to1; clk => sysclk,
A => X, B => Y, C => Z, D => W,
signal E,F,G,H: std_logic_vector(15 downto 0); S => S,
signal X,Y,Z,W: std_logic_vector(31 downto 0); Y => Q_wide);
signal n_Reset: std_logic;
end rtl;
VHDL test benches
• Test benches are top-level design units for simulation purposes only
• Why test bench?
• Creating a stimulus manually is tedious/difficult
• Large/complex designs often require automatic testing of outputs (vs inputs).
• In hierarchical designs, it is useful and easier to test each block separately - comparable to
unit testing in SW world
• Isolation of DUTs makes things easier!
• Test bench contains:
• Instantiation of Device Under Test (DUT)
• Stimulus signals for DUT (generators for input waveforms, clock driver, reset etc)
• (Optionally) generation of reference outputs and comparison to DUT outputs
• Can provide automatically a pass or fail indication
VHDL functions/commands for TB’s
• Not all VHDL is synthesizable - some commands/functions are
intended for simulation only, to be used in test benches

• For example: -- Non-Synthesizable Delay Statement:

r_Enable <= '0';
• Delay statements wait for 100 ns;
r_Enable <= '1';

assert (A and B = 0) report ”A and B

• Assertions simultaneously zero” severity warning;
 VHDL functions/commands for TB’s (2)
library STD;
use STD.textio.all;
• File/Text I/O ...
architecture behavioral of Pate_Top_TB is
• enables reading of -- file handlers & file op related stuff
stimulus and file S_Stimulus : text open read_mode is "S_stimulus.prn";
writing of results to ...
a file -- read analoque stimulus from files
analoque_stimulus: process
• In this example variable S_row: line;
stimulus file (ASCII) variable v_data_read : integer := 0;
begin
is created with wait until S_SamClk_P'event and S_SamClk_P='1';
MATLAB, test bench if(n_Reset='0') then
reads it row by row, v_data_read := 0;
else
on rising edge of a -- read from input file in "row" variable
sampling clock and if(not endfile(S_Stimulus)) then
places the data to readline(S_Stimulus,S_row);
stimulus vectors for i in 0 to 7 loop
read(S_row,v_data_read); -- read the integer value
(matrix) S_Anal_Data(i) <= std_logic_vector(to_unsigned(v_data_read,14));
end loop;
end if;
end if;
end process;
An example test bench
• Get it from RedMine and try it out:
• https://vm0758.kaj.pouta.csc.fi/attachments/download/1467/mux_tb_sourc
es.zip
• Notes:
• The test bench -file (mux_tb.vhd) needs to be added as “simulation source” in
Vivado
• Make sure that mux_tb.vhd is set as top for simulation