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Class 08: NMOS, Pseudo-NMOS

This document discusses NMOS and pseudo-NMOS logic gates. It covers topics including NMOS inverter circuits using resistive and depletion loads, NMOS NOR and NAND gates, and the schematic representation of pseudo-NMOS gates including inverters with a PMOS load. It also discusses evaluating logic functions from schematics and transistor equivalency including how scaling transistor widths and lengths or connecting transistors in series or parallel can modify their effective behavior.

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Poonam Pratap Kadam
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350 views

Class 08: NMOS, Pseudo-NMOS

This document discusses NMOS and pseudo-NMOS logic gates. It covers topics including NMOS inverter circuits using resistive and depletion loads, NMOS NOR and NAND gates, and the schematic representation of pseudo-NMOS gates including inverters with a PMOS load. It also discusses evaluating logic functions from schematics and transistor equivalency including how scaling transistor widths and lengths or connecting transistors in series or parallel can modify their effective behavior.

Uploaded by

Poonam Pratap Kadam
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Class 08: NMOS, Pseudo-NMOS

Topics:
•02 NMOS Logic Gates
•03 NMOS Logic Gates
•04 Pseudo-NMOS
•05 Pseudo-NMOS
•06 Transistor Equivalency

Dr. Joseph Elias; Dr. Andrew Mason 1


Class 08: NMOS, Pseudo-NMOS
NMOS (Martin c. 1)
§ nMOS Inverter with resistive load § nMOS Inverter with depletion load

Depletion nMOS, Vtn < 0


always ON for VGS = 0

§ switch level model


W/L Q1 > W/L Q2 so Q1 can “pull down” Vout

§ nMOS NOR gate

c = a+b
(a) NMOS off (b) NMOS on
want to realize resistor with a transistor
§ nMOS NAND gate
§ Including transistor resistance

c = ab
rds ≡ channel resistance
RL >> rds so output close to 0V
Dr. Joseph Elias; Dr. Andrew Mason 2
Class 08: NMOS, Pseudo-NMOS
NMOS (Martin c. 1)
• General nMOS schematic
Examples: depletion-load nMOS logic

– single load transistor


– parallel and series nMOS transistor to
complete the compliment of the desired
function
i.e., they determine when the output is
low “0” rather than high “1”

Dr. Joseph Elias; Dr. Andrew Mason 3


Class 08: NMOS, Pseudo-NMOS
Pseudo-NMOS (Martin c. 4)
•NMOS Common-Source Amplifier with •Pseudo-NMOS inverter with PMOS load
current sourrce load and load capacitor •Choose W/L so that:

•Choose Vbias in between VDD and ground

Q2 always on since |Vgs| > |Vtp|


Q2 in saturation if (for VDD=3.3)
|Vds| > |Veff| > |Vgs| – |Vt|
VDD – Vout > |Vgs| - |Vt|
Vout < VDD - |Vgs| + |Vt|
Vout < 1.65 + Vt < 2.45
Q1 in saturation if
Vgs = Vin > Vt
Vds > Veff > Vgs – Vt =>
•Current-source realized with a PMOS transistor Vout > Vin - Vt

•Power Dissipation:

Veff = Vgs - Vt output low (Vin is high): P = IL * VDD


Vds = Vgs + Vdg
at saturation, Vdg=-Vt output high (Vin is low): P=0

Valid if: average static dissipation: P = ½ * IL * VDD


Veff = |Vds-sat| > |Vgs| - |Vtp|
-want drain at least Vt from gate

Dr. Joseph Elias; Dr. Andrew Mason 4


Class 08: NMOS, Pseudo-NMOS
Pseudo-NMOS (Martin c. 4)
Evaluating functions from schematics
XOR Logic in Pseudo-NMOS 1. start with any transistor connected to ground
2. OR parallel and AND series transistors, combining all
remember: subnets in same manner
3. do again for each transistor connected to ground, and
a’+b’ = (ab)’
combine groups
a’b’ = (a+b)’ 4. take the compliment of the result
Example:

Vout’ = [ x1 (x4 + (x2+x3) (x5+x6+x7) ) ]


Vout = [ x1 (x4 + (x2+x3) (x5+x6+x7) ) ]’

Dr. Joseph Elias; Dr. Andrew Mason 5


Class 08: NMOS, Pseudo-NMOS
Transistor Equivalency (Martin c.2, c.4)
• Scaling both W and L
Example: Parallel Transistors

– transistors act the same (to first order)


• Series Transistors

– effectively increases L
• Parallel Transistors

– effectively increases W
Figure 2.17: (a) layout, (b) schematic
direct from layout, (c) simplified schematic
Dr. Joseph Elias; Dr. Andrew Mason 6

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