®

INK
THE COMPUTER APPLICATIONS JOURNAL

FEATURE
ARTICLE

BitScope Norman Jackson

A Mixed-Signal Capture Engine

Has your office

s ome time ago, I
had a bad experi-
ence with a bus—a
triumphs over bug.
By employing a high-tech piece of
test equipment, I could trigger on a
logic bus. It had six ram- complex digital event and correlate this
become so cluttered paging DSP cards and a SCSI control- event to an oscilloscope trace that
ler all trying to ride at the same time. showed what was really happening in
that you can’t find About once an hour, there was a the analog domain. I was saved in the
sickening crash. After going through nick of time, but despite having formed
your oscilloscope or the usual stages of blaming the soft- a deep attachment to the trusty ’scope,
ware, I relented, admitted possible I had to give it back.
logic analyzer? No culpability, and borrowed a mixed- Following this adventure, I started
mode DSO. musing about how to roll my own
problem, Norman will This machine has a digital sampling version of that useful electronic gadget.
oscilloscope and a logic analyzer effec- After some mental tinkering and with
help you build a low- tively joined at the hip. They share a the added incentive of Design98, I was
common trigger module that enables soon sketching electronic stuff on the
cost, mixed-signal the user to identify a complex event grid pad. BitScope began to emerge
and record the state of the target hard- (see Photo 1).
capture engine that ware before and after the trigger—in
both the analog and digital domains. THE BIG PICTURE
connects to your In the case of my erratic bus logic, The basic idea behind BitScope is
the culprit turned out to be a delin- that of a specialized piece of data-
computer via the quent GAL with a ground bounce capture hardware that doesn’t include
problem. The offending chip had its any user interface other than an RS-232
serial port. duties reassigned and the documenta- plug. Most engineers have more com-
tion police were alerted. Engineer puters, mice, and keyboards than they
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Circuit Cellar INK® Issue 97 August 1998 1
know what to do with. If I was going troller firmware is designed as a
to build a cheap ’scope, I certainly virtual machine (VM). The Analog Power
A B div Supply Supply
didn’t want any more of that stuff. BitScope design is novel because n

What I needed was an electronic it has an unusual arrangement of

Mux Data
drone that could capture and disgorge the VM program code. The in- Range Mux Clock PIC
data on command. No more, no less. structions are not located in CPU
The commands had to be simple memory on the microcontroller Flash 32K × 8
ADC SRAM PLD
ASCII characters that are intuitive but reside in the user interface Logic
Digital 32K × 8
and easy to learn. The PC-based user and are executed atomically Pod SRAM
Control
Serial
interface can then synthesize func- direct from the serial port.
tionality of arbitrary complexity by If you study BitScope’s vir- Figure 1—This block diagram of the mixed-signal capture engine
sending scripts of command charac- tual instruction set, you see that shows basic design architecture.
ters and receiving the replies. arranging things in this crazy
The answer: a virtual instrument way has its advantages. All instruc- SERIAL CONNECTION
where specialized hardware does the tions are atomic. In other words, there While a serial interface may seem a
electronic test job and a PC lets the is no inherent syntax associated with bottleneck for a capture engine that can
engineer drive it. One big advantage of any command byte. potentially store 64 KB of data, this is
this setup is that changing the way All instruction bytes are echoed to not a problem. Thanks to the Internet
the virtual instrument works doesn’t provide a simple handshake mechanism. and 56k modems, most PCs now have
usually involve reprogramming chips And, all instructions are preemptive, fast, buffered UARTs.
(hard) but may be done by download- so you can always abort the previous The transmission speed of the Bit-
ing a new program from the ’Net (easy). command and regain control simply Scope serial link can be scaled to
As described in the sidebar “Virtual by sending a new command. 115 kbps using a fast microcontroller.
Machine Architecture,” the microcon- At this rate, you can transfer enough

Figure 2a—The BitScope CPU and storage

engine includes the PIC, PLD logic, clock, data
muxes, and sample RAM.

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2 Issue 97 August 1998 ®
Circuit Cellar INK
 Virtual-Machine Architecture R0 Byte Input Reg Assemble input data here
A virtual machine (VM) consists of a fully functional R1 Register Pointer Pointer to R(0–ff)
processor hosted on an unrelated substrate machine. R2 Register Source Pointer to R(0–ff)
VM design has advantages over conventional coding. R3 Sample Preload L Low byte of RAM addr to load to Spock
R4 Sample Preload H High byte of RAM addr to load to Spock
Each instruction may be highly optimized for perfor- R5 TRIG Logic Byte Logic levels for Spock to match, loaded
mance—unlike a general-purpose interpreter like BASIC, during Spock Init
which can do anything but inefficiently. VM instructions R6 TRIG Mask Byte Don’t Care bits in trigger match, loaded
are compact like assembly but perform extremely during Spock Init
R7 Spock OPTION byte TRIG and PG1 setup in Spock
complex tasks. Once a register and command set are R8 Trace Register Trace Option controls Sample operation
devised, you can add new instructions to enhance the of BitScope
machine. The original instructions remain the same, R9 Counter capture Lo Counter low byte shifted out of Spock
which promotes modularity. Since the operational R10 Counter capture Hi Counter high byte shifted out of Spock
R11 DELAY-L Post TRIG delay before halting
definition of the VM is rigid, firmware changes tend to R12 DELAY-H Post TRIG delay before halting
be straightforward, even to the point of hosting the R13 TimeBase TimeBase expander count
target architecture on a completely new substrate. R14 Channel-A/B Channel Range settings for Chop
In this design, the PIC16F84 is a substrate to imple- R15 Dump Length Counter for number of samples trans-
mitted per request
ment a custom BitScope machine with its instruction set R16 EEPROM Data Data register for EEPROM
becoming microcode to implement the VM. So, the R17 EEPROM Address Address register for EEPROM
BitScope VM has instructions and registers but they’re R18 POD Transmit Register holds byte for POD
unrelated to the PIC native instruction set. The virtual R19 POD Receive Register gets byte from POD
registers are hosted by PIC memory registers but have Table i—The BitScope virtual machine has a set of 20 registers. The operation of the
meaning only to the BitScope. Similarly, BitScope has no machine and all its instructions refer to these registers.
use for XOR- or DECFSZ-type instructions. Instead, it has
instructions for manipulating registers, starting sample the serial port. BitScope’s instruction set is designed to
RAM, and dumping captured data. BitScope registers may have no syntax, so there can be a maximum of 256 in-
be option bits, timer constants, sample address, and so structions and each is stand alone—just like a RISC in-
on. The exact function of the register set is detailed in struction set. An atomic protocol means the software at
Table i. Table ii shows the current command set. both ends of the serial line is simple and does not have to
Most interpreters run from a program stored in memory. preserve state information. In a PIC with 1024 words of
BitScope is different because it executes directly from program, it’s advisable to be economical with code, espe-

00 • Reset Reset the machine and print its ID 54 T Trace with TRIG stop Begin sample with Opt mode, until Trig
string then Delay, Halt Sample Clk, and
23 # Load Source Reg Store R0 into R2. Set up R2 which is a print sample add.
source reg. A reg-to-reg move may be 5b [ Clear R0 Reg R0 is cleared. This usually
done by pointing to a source (R2) and precedes a nibble load
destination (R1). 5d ] Nibble swap R0 R0:(0–3) is swapped with R0:(4–7).
2b +Inc REG Incr the reg pointed to by R1 This command puts the entered
2d –
Dec REG Decr the reg pointed to by R1 nibbles in the correct order.
30 0
Enter nibble 0 Incr R0 by 0 and nibble swap R0 61 a Enter nibble 'a' hex Incr R0 by 10 and nibble swap R0
31 1
Enter nibble 1 Incr R0 by 1 and nibble swap R0 62 b Enter nibble 'b' hex Incr R0 by 11 and nibble swap R0
32 2
Enter nibble 2 Incr R0 by 2 and nibble swap R0 63 c Enter nibble 'c' hex Incr R0 by 12 and nibble swap R0
33 3
Enter nibble 3 Incr R0 by 3 and nibble swap R0 64 d Enter nibble 'd' hex Incr R0 by 13 and nibble swap R0
34 4
Enter nibble 4 Incr R0 by 4 and nibble swap R0 65 e Enter nibble 'e' hex Incr R0 by 14 and nibble swap R0
35 5
Enter nibble 5 Incr R0 by 5 and nibble swap R0 66 f Enter nibble 'f' hex Incr R0 by 15 and nibble swap R0
36 6
Enter nibble 6 Incr R0 by 6 and nibble swap R0 6c l Load R0 from @R2 Copy contents of reg pointed to by R2
37 7
Enter nibble 7 Incr R0 by 7 and nibble swap R0 toR0
38 8
Enter nibble 8 Incr R0 by 8 and nibble swap R0 6e n Next Address Incr addr reg R1
39 9
Enter nibble 9 Incr R0 by 9 and nibble swap R0 70 p Print REG value @R1 Print <CR>ASCII,ASCII<CR>
3c <
Get ctr value Shift the current 16 bit ctr value from 73 s Store R0 to @R1 Copy contents of R0 to reg pointed to
from Spock Spock into R9, R10 by R1
3e > Program Spock Load 5 bytes of data from R3–R7 into 75 u Update RAM pointers Copy contents of R3,4 to R9,10.
from Registers Spock. Previous contents of ctr are Updates sample addr value from
destroyed sample preload reg.
3f ? Print Machine ID Print <CR>CHAR8–CHAR1<CR> 78 x Exchange byte with Transmit byte in POD_TX to POD
where CHARn is part of a string POD IO-0. Wait for reply byte on IO-1
identifying the type and revision of this and put it inPOD_RX then return it to
device. host.
40 @ Load Address Reg Store R0 into R1. Use to set up reg ptr. 7c | Pass Through byte Transmit byte in POD_TX to POD IO-0.
53 S Dump Sample Dump lines of 16 Sample RAM to POD Connect IO-1 to Serial Out for host.
RAM (CSV) values (digital and analog)

Table ii—The command set for the BitScope virtual machine is a subset of the byte values between 0 and 255. Active commands are confined to the ASCII range from 0 to 127.

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Circuit Cellar INK® Issue 97 August 1998 3
 samples to draw a 640 × 480 screen— For the engineer dealing with micro-
cially given the importance of at most 640 bytes—in about 55 ms, or controller circuits, it’s unlikely that
reliably transmitting packets over 18 screens per second. frequencies of interest will exceed
a serial link. For lower frequency data or simple 20 MHz—at least for the time being.
I decided the BitScope command sine waves, it’s necessary to only send a Later on, when 3-V logic becomes
set should use common printable handful of samples to the host and have more prevalent, that 50-MS/s rate can
ASCII commands. Since the assign- the user interface do some curve fitting. probably stretch to 100 MS/s in an
ment of byte codes is arbitrary, Small bursts of contiguous sample data SMT version of the design.
any value could mean “enter hex may be used to enhance a waveform To make BitScope as useful as
nibble 3,” but obviously 3 is a display to show high-frequency noise. possible, I was determined that it should
good choice. The general scheme Logic analyzers don’t need to rapidly physically stand alone. It needed to be
for allocating byte-code values and update their display at all. After a trigger unconstrained to a particular machine
their ASCII symbol is: event, the data may stay in the sample or bus standard, and I wanted it to
RAM and be downloaded only when communicate with any computer
• numerals—data entry the host needs it. At 115 kbps, the using the ubiquitous RS-232 interface.
• operators—manipulation of reg- total contents of a 16-KB buffer can From my experience, the most
ister values download in less than 2 s. The user commonly required features of this
• lower case—general machine interface may then draw logic state or type of test equipment are two analog
operation timing diagrams and manipulate them input channels and eight digital logic
• upper case—major machine func- as necessary. inputs. Combine those features with a
tions flexible trigger capability, and you get
• nonprintables—reserved for fu- USER INTERFACE a pretty useful instrument. I set a
ture commands Don’t think shrink-wrapped mono- design goal of about $100 for the cost
lithic Windows software for this design. of required components, all of which
An example script for loading R6 Think more about the Linux model should be readily available.
with 0x5a is [6]@[5a]s. It may where the engineering community For the core of BitScope, I selected
seem obscure, but if you study it, builds its own tools and can custom- a PIC16F84 micro tightly coupled with
it should make sense. Ultimately, ize them as needs arise. a Lattice 1016 PLD. The PIC controls
a user interface will debug scripts Because BitScope uses simple ASCII the serial port and implements a VM
and writing scripts will only be commands, in a pinch, you can use a architecture. The Lattice counts RAM
necessary if a user develops a new terminal program and spreadsheet to addresses and waits for a trigger.
mode of operation or drives it display waveforms. For complex applica- These chips are cheap and solid
directly from a terminal. tions, you need more advanced software performers. Both are flash-memory
All BitScope operations, including based on C, Delphi, or Visual Basic. based for easy upgrades, and they have
wait on trigger, may be interrupted A BitScope user interface can run excellent entry-level development
by any serial command. The first under many possible environments, software. Sample RAM is provided by
part of the software UART ensures including Windows, MAC, Unix, two 32-KB 15-ns cache memories.
that the sample clock is halted. When WinCE, Palm Pilot, Psion, DOS, or These devices will take the design to
a serial byte is assembled and Amiga. Basically, it can work on any 50 MS/s and have the great advantage
echoed, the UART turns on and, machine with a serial port. that about eight of them are perched
once activated, aborts all previous No single person could write all that on every ’486 motherboard ever built.
operation. In this sense, BitScope’s software. Instead, I made the BitScope That should put their head count at
command protocol is truly atomic. design open and documented so you about one billion, so don’t tell me you
Each command ends in a halt, if could create what you need. can’t find any!
not prematurely aborted. ASCII code On INK’s Web site, you’ll find some Every DSO must be built around a
00 is the reset vector, so it can get user-interface software with source flash ADC. These chips were exotic
the PIC’s attention with a <break>. listings to start the ball rolling. Via the until a few years ago when digital ma-
Inevitably, a VM like this will Internet, you can also find existing nipulation of video became popular.
get enhanced firmware. Microchip programs that already simulate oscillo- Now, several companies have devices
has devices that potentially double scopes, logic circuits, and data displays. that can provide 40 MS/s or better for
the number of byte codes imple- DESIGN PHILOSOPHY less than $10. Even an older device like
mented. To cope with the poten- A good place to start designing is with Motorola’s MC10319P can sample
tial of other feature sets, ? returns a functional specification. For BitScope, from DC to 25 MS/s and is available
a 32-bit ID code. User-interface the main issue was sample rate. While in a DIP package.
software may keep a register of it seemed clear that a 200-MHz sample In fact, I used this device for Bit-
feature sets supported by each rate was out of reach, I could easily Scope. By selecting a 600-mil DIP
byte-code revision. get to about 50 MS/s and still be ahead package, I could accommodate any of
on the price/performance curve. the new SMD devices as a plug-in
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4 Issue 97 August 1998 ®
Circuit Cellar INK
module and avoid the need tioned ready for storage
for multiple PCB versions. in the digital sample
For vertical amplifiers RAM.
that process analog signals You might guess from
to the ADC, the video in- the extra signals on the
dustry again provides a pod that it’s not just
solution. Maxim and Ana- eight logic levels in. As
log Devices both have well as fused balanced
cheap, stable 300-MHz op- power supplies, there is a
amps that make wide-band digital I/O communica-
amplifier design easy. tion port. Everything you
Using these devices lets need is there to connect
the vertical-amplifier band- an active, programmable
width get close to 100 MHz, extension module.
matching the input specs on Most of the analog
the new flash ADC chips Photo 1—BitScope was prototyped on a two-layer PCB. Notice that the components are conditioning circuits and
arranged to separate analog and digital sections of the circuit.
from Analog Devices and the flash ADC are shown
TI. For an insight into why we need that it’s necessary to read in data from in Figure 2d. The circuit consists of an
such wide-bandwidth vertical amplifi- the RAM chips one bit at a time be- amplifier chain driving through a pair
ers, see the sidebar “Subsampling— cause there are no spare eight-bit of 4:1 analog mux devices.
Bending Nyquist.” ports available. Modern video op-amps help here.
WALKING THRU SCHEMATICS One fundamental rule in mixing They give you high input impedance,
Before delving into the schematics, analog and digital circuits is to avoid low output impedance, and unity gain
take a look at Figure 1, which overviews contamination of the analog grounds. stability.
the functionality of the BitScope design. Figure 2b shows that great care was The PIC controls the mux sources
The PIC, the Lattice PLD, and the taken to isolate the analog and digital that allow implementation of range
SRAMs are shown in Figure 2a. These sections of this circuit at high frequen- switching and channel chop functions.
chips are closely coupled to form the cies. Similarly with the RS-232 port, To accommodate different ADC
sample capture functions at the core it’s best not to allow PC noise to have chips, there are adjustment pots for
of this design. any path to a test circuit. both the range and offset voltages as
By using a synchronous tristate Digital test signals and two spare required by the manufacturers.
clocking circuit, the PIC is able to stop, analog signals are shown on Figure 2c Figure 2e shows the final part of the
start, and preload the Lattice PLD connecting to the DB25M pod connec- analog conditioning circuit. Channels
using just a handful of signals. Notice tor. Logic levels are latched and condi- A and B are standard 1-MB input im-
pedance AC/DC BNC connectors. A
classic source follower tree driving a
unity gain buffer for each channel
completes the vertical-amplifier sec-
tion.
For engineers who like to measure
high frequencies, I added a small 1-GHz
prescaler circuit, which includes a swit-
chable 50-Ω terminator hanging off the
Channel B input circuit. Note that
BitScope has a couple of ways to mea-
sure the frequencies of applied signals.
I explain the motivation behind this
in the sidebar “Subsampling—Bending
Nyquist.”

THAT IS LOGICAL, CAPTAIN

PLDs such as the Lattice 1016 can
swallow a whole swag of logic func-
tions. In this case, about 18 medium
TTL devices with all their wiring
disappear into a 44-pin PLCC device.
Figure 2b—BitScope power supply and comms deal with filtering, rectification, and
regulation as well as RS-232 level shifting and indicators. Radial PLDs like the Lattice are
like eight PALs in a circle surround-
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Circuit Cellar INK® Issue 97 August 1998 5
ing a big breadboard. This vice on its own is an ex-
architecture favors the tight tremely useful DSO and
timing requirements of logic analyzer, but it is not
counters and glue logic. everything.
Mostly, this PLD is a The pod connector pro-
16-bit shift register and vides an electronic lens
counter with a configurable mount for test equipment.
comparator for triggering. Think of the sample RAM
The PIC can load a five-byte in BitScope as a roll of 35-
configuration word that sets mm film, and the data you
the operation of the chip, store there may come from
after which it may be either built-in connectors
clocked at full speed. or any weird and wonderful
“data lens” you care to
THRU THE LENS attach via the data pod.
MEASURING Because the pod architec-
The SLR lens-mount sys- ture and protocol is open
tem from the photographic and documented, anyone
world is a great design that may design a specialized
Figure 2c—The BitScope digital capture unit has a logic pod circuit with latching buffer
has stood the test of time. and pod I/O switches. data lens for BitScope.
You start with a camera
body with a general-purpose 50-mm as long as the mounts match, you VOLTAGE RANGES
lens, and for specialized work, you have a new camera. The BitScope DSO includes four
screw in any of a hundred matching I tried to use the same SLR prin- internal attenuation ranges and four
lens types. From fisheye to telescopic, ciple in the BitScope design. The de- channel inputs. Channel A and B are

Subsampling—Bending Nyquist
In data-acquisition applications, there is often some on the waveform and the regions between will forever
confusion about the relationship between bandwidth and remain a mystery.
sample rate. The Nyquist rate of half of the sampling Another concern has to do with resolving the am-
frequency (Fs) is well known to be the maximum fre- biguous period of the subsampled waveform. Let’s say
quency that can be captured by periodic sampling at Fs. you have a signal of 28 MHz and are sampling at 40 MS/s.
Given that mathematical constraint, why would we In the sample buffer, you’ll see a sequence of values
want an instrument that has a bandwidth of 100 MHz with components at 12 and 68 MHz. How can these be
and yet samples at a maximum rate of only 50 MS/s? plotted to build up a profile of the original 28-MHz
The answer lies with subsampling. signal? Well, if you can measure the fundamental fre-
The Nyquist rate applies to continuous time varying quency of the sampled wave, that will imply period.
signals. In that general case, the highest-frequency com- Since you know the sample rate accurately, you can
ponent should be less than half of Fs (25 MHz at 50 MS/s) fractionally chop the sample buffer up into segments of
to avoid aliasing. Repetitive waveforms are a different n wave periods and then plot them overlaid. You will
matter. They’re the only high-frequency waveforms you have traded the freedom for those n waveforms to vary
ever see on an analog CRO. The same waveform is redrawn in exchange for n different points on the waveform. It
each sweep, and the eye sees a solid trace. Subsampling may now be apparent why the BitScope design has pro-
is similar. You use multiple samples and overlay them vision to measure the frequency of any signal presented
to build an image. Providing that your ADC has a wide to the ADC.
bandwidth and a small aperture, it is possible to sample Even if you can’t measure the frequency of a subsampled
a repetitive waveform over many cycles and build up a waveform directly, all is not lost. DSP engineers have
snapshot of the exact waveform, limited only by the some fancy autocorrelation algorithms that can be let
bandwidth of the signal path. This technique, known as loose on a chunk of acquired data to pull a waveform out of
subsampling, is just an example of the RF mixer in the meaningless numbers. It is important to note, however,
digital world. that for resolving single event (such as high-frequency
Subsampling has a few constraints. It isn’t possible to pulses like logic glitches), there is only one solution:
subsample a waveform that’s harmonically related to the oversample by at least a factor of 10. This performance
sampling frequency. Practically, this means that if the is exclusively in the domain of specialized test equip-
waveform of interest is related to the sample frequency, ment using state-of-the-art circuit techniques to resolve
the sample points always fall at the same relative position samples to 1 ns or better.

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6 Issue 97 August 1998 ®
Circuit Cellar INK
 Figure 2d—The BitScope analog
capture features the vertical channel
muxes, attenuation switch, ADC
buffer, and ADC.

Figure 2e—The BitScope Input

Channel Buffers are high-
impedance voltage followers
and op-amp buffers with a
1-GHz prescaler circuit.

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Circuit Cellar INK® Issue 97 August 1998 7
 Range BNCx1 BNCx10 POD SOFTWARE
00 ±130 mV ±1.30 V ±632 mV The Circuit Cellar Web site has
01 ±600 mV ±6.00 V ±2.90 V downloadable software listings,
10 ±1.20 V ±12.00 V ±5.80 V
technical documents, programmable
11 ±3.16 V ±31.60 V ±15.28 V
binaries, and PCB overlays. Informa-
Table 1—Here are the BitScope input ranges for an ADC tion about BitScope is available at
span of 2 V. Resistor attenuators can be found in the
schematic. www.discrete.net or via bitscope@
discrete.net.
BNC connectors that may have ×1 or
×10 probes connected. Channel C and SOURCES
D (pod inputs) have a fixed attenuator,
PIC16F84
and possibly, there’s some extra cir-
Microchip Technology, Inc.
cuitry in the pod.
(602) 786-7200
Table 1 details the range sensitivities.
Fax: (602) 786-7277
The ranges aren’t nearly as compre-
www.microchip.com
hensive as a bench CRO, but it covers
those most useful to digital and analog 1016 PLD
circuits. As well, I intended for the Lattice Semiconductor Corp.
pod connector to deal with unusual or (503) 681-0118
high voltage signals by way of an Fax: (503) 681-3037
active pod adapter. www.latticesemi.com
It’s also possible to alter the gain of MC10319P ADC
some ranges. Since the ADC output is Motorola SPS
an eight-bit number that ranges from (800) 521-6274
00 to FF, the final interface just needs Fax: (602) 897-5725
to ratiometrically apply this hex value www.mot-sps.com
to the voltage range of each stage.
Preprogrammed PIC, 1016 PLD,
A little thought reveals that for a
MC10319P ADC, and PCB
digital oscilloscope, volts per division
Discrete Time Systems
and microseconds per division are quite
+612 9212 3469
arbitrary notions. Provided that the
Fax: +612 9212 3470
signal under consideration is within the
[email protected]
ADC range and the sample-buffer size, a
www.discrete.net
display can be of any size and grid spac-
ing. Similarly, the notion of y offset
becomes a display function, which has
nothing to do with the sample engine.

IN YOUR HANDS
With this design, I hope to have
presented a low-cost solution to the
engineer’s needs for sophisticated test
equipment. I have heeded the call for
more open designs and liberation from
the single-platform juggernaut.
In the coming months, I look forward
to hearing from any of you who can
think of applications for this device
that I haven’t even dreamed of. I

Norman Jackson is principal hardware

design engineer for Discrete Time
Systems P/L in Sydney, Australia. He
designs DSP-based digital audio systems
for use in film and TV postproduction.
©Circuit Cellar INK, the Computer Applications Journal.
You may reach Norman at normj@ Reprinted by permission. For subscription information,
discrete.net. call (860) 875-2199 or subscribe ©circellar.com

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8 Issue 97 August 1998 ®
Circuit Cellar INK