GENERTION OF PWM USING VERILOG IN FPGA

ABSTRACT :

In this paper a new approach of generating the Pulse width modulation

(PWM) signals which are to be used in various power electronics application
like power converters and inverters is presented. Pulse Width Modulation
(PWM) triggers the gate terminals of the power electronic semiconductor
devices like thyristors, Insulated-Gate Bipolar Transistors (IGBTS), Metal Oxide
Semiconductor Field Effect Transistors (MOSFET) etc. which are used as
switches for voltage regulation. The pulses are generated using hardware
description language (HDL) which is suitable for usage in Spartan-3E Field
Programmable Gate Array (FPGA) board which is used as high performance
controller in vector control of induction motor. Simulation is done in Model Sim
6.2b environment and results are obtained validated with register transfer level
(RTL) schematic.

INTRODUCTION :

In last two decades, the Pulse width modulation (PWM) techniques are
extensively used for controlling the analog circuitry. In particular, it is more
commonly used for controlling the power converters employed in various
industrial/domestic applications. In power converters it is used for firing of
power electronic devices like thyristors, Insulated- Gate Bipolar Transistors
(IGBTS), Metal Oxide Semiconductor Field Effect Transistors (MOSFET) etc.

Inverter fed AC motor drives has wide area of domestic/industrial

application. Controlled Inverter can control both the magnitude as well as
frequency of voltage and current applied to the motor. The Pulse Width
Modulation (PWM) has made possible for three phase voltage level inverter to
convert DC link voltage into three phase voltages by controlling the on and off
time of power electronic devices. The main parameter of PWM signal is duty
cycle which is a part of PWM period. The electric motors usually run at duty
cycle less than 100 per-cents.

Duty cycle (D) can be defined as ratio of ON time over to total ON and
OFF time and is shown in Fig. .

D= Ton *100

(Ton+Toff)

Whereas Time period (T) is defined as sum of Ton and Toff Ton- time
for which switch is on
Toff – time for which witch is off

Period
Duty cycle

ton
toff

The main advantage of Pulse width modulation is that it has very low power
loss in switching devices and higher frequency that affects the devices which
uses power. Only digital circuits can produce PWM signals. In this paper
counters are used to generate PWM signals which will be in the form of
square wave.

The conventional method of generating the PWM pulses using analog circuitry
have disadvantages of complex circuitry, limited function and low flexibility in
circuit modification. Due to limitations offered by analog circuit designing, the
digital methods of generating the pulses are getting more popularity. Today
basically engineers use various micro-controllers to make control system but
these microcontrollers are being replaced by FPGA. The FPGA (Field
Programmable Gate Array) allows user to have all features on a single chip. It
is an array of programmable logic blocks which can be connected to each
other by using Hardware Description Language. The most common HDL used
are VERILOG and VHDL. This paper describes or propose how to generate
PWM in Verilog for implementation on FPGA for further applications.FPGA
Board, ISE software is necessary for this implementation

STRATEGY FOR BUILDING PWM SIGNALS IN FPGA USING VERILOG :

There is one counter used for each PWM signal generated. A clock and a
reset is taken common for all counters. Total six counters are taken for
generation of six PWM signals. Now system clock which is of 50 MHz is
divided to provide delay and the duty cycle is taken as 50%. As we know in
India the frequency is of 50 Hz for AC supply, so time period can be
calculated as T= 1/50 = 20 msec which are converted to nanoseconds.
1 cycle = 3600

Therefore 10= 20 msecs/3600

So the counters are turned on at specified interval of time and then they are
turned off according to 50% of duty cycle which shown in Table 1

Table.1. CONVERSION OF FIRING ANGLE TO TIME PERIOD

Firing Angle Time

00 0msecs

600 3.33msecs

1200 6.66msecs

1800 10msecs

2400 13.33msecs

3000 16.66msecs
IMPLEMENTATION OF VERILOG CODES IN XILINX :

When the codes are written in Xilinx one can get output waveforms on Model
Sim as well as one can view the RTL schematic (Fig.2) so the RTL
schematic which is shown below in parts from Fig.3-Fig.6 which provides a
brief overview of the functioning of our proposed PWM generator. The code
used is mentioned in appendix in which the functionality is described of
proposed design for PWM generator.
Before we proceed its most important to understand that what is RTL
(Register Transfer Level) schematic. RTL schematic tells us how our HDL
code is interpreted and implemented. It helps to do analysis in one go and to
derive actual wiring from higher level representation for lower level design
implementation.
The detailed RTL schematic is bit complex but it is not so difficult to
understand. Once if we look carefully to the RTL schematic we are able to
understand how the proposed design is working.

Basically Verilog is a hardware description language which is standardized as

IEEE 1364 which is most commonly used for designing and verification of
designed digital circuits at the register transfer level (RTL). We have used
Verilog instead of VHDL because of various advantages of Verilog over
VHDL.

RTL schematic of proposed PWM generator

 Part 1 of RTL schematic Part 2 of RTL schematic

Part 3 of RTL schematic part 4 of RTL schematic

 Simulation result

RESULT AND DISCUSSION :

The simulation results are obtained in Model Sim software environment.

Verilog codes are synthesized in Xilinx ISE and simulation is carried in Model
Sim which provides the output of design developed.

The simulation results obtained and are shown in Fig.7 and Fig.8. As shown
in Fig. 7, no pulses are generated as the reset port is high only system clock
is visible whereas in Fig.8 the PWM pulse are generated when reset port is
low. The pulses generated are suitable for firing six power devices in three
phase inverter.

CONCLUSION :

In this study the generation of PWM pulses using Verilog is investigated. A

program is developed for the study of PWM generation of fixed frequency in
the Verilog which is implemented on FPGA. FPGA are more reliable and
suitable than traditional MCUs. RTL schematic validates the output of
developed program for Pulse generation. The simulation results showed that
an effective PWM pulses can be generated using proposed approach.
FUTURE SCOPE :

The proposed model can be refined and modified for better performance and
more accurate PWM generation. The counters can be turned on and off at
more précised intervals or instead of counters comparator may be used for
the PWM generation purpose in which waveforms can be compared to
generate PWM.

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