Module 13: Multichannel Buffered Serial Port F2833x

32-Bit-Digital Signal Controller

TMS320F2833x
Texas Instruments Incorporated
European Customer Training Centre
University of Applied Sciences Zwickau

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 Multi
ultic
channel Buffered Serial Port (McBSP)
Introduction:
• Two High – Speed multichannel synchronous serial ports (McBSP-
A and McBSP-B)
• Maximum data rate: 20 MHz
• Each McBSP consists of a data - flow – path and a control - path

• Six Pins per channel

• MDX: data transmit
• MDR: data received
• MCLKX: transmit clock
• MCLKR: receive clock
• MFSX: frame sync transmit
• MFSR: frame sync receive

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 McBSP Block Diagram

Peripheral / DMA Bus MFSXx

16 16
MCLKXx
DXR2 TX Buffer DXR1 TX Buffer
16 16

XSR2 XSR1 MDXx

CPU
RSR2 RSR1 MDRx
16 16

RBR2 Register RBR1 Register

16 16

DRR2 RX Buffer DRR1 RX Buffer MCLKRx

16 16
MFSRx
Peripheral / DMA Bus

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 Features of McBSP
• Full - duplex communication
• Double-buffered transmission and triple-buffered reception,
allowing a continuous data stream
• Independent clocking and framing for reception and transmission
• send interrupts to the CPU and send DMA events to the DMA -
controller
• 128 channels for transmission and reception
• Multichannel selection modes that enable or disable block
transfers in each of the channels
• Direct interface to industry-standard CODECs, analog interface
chips (AICs), and other serially connected A/D and D/A devices
• Support for external generation of clock signals and frame -
synchronization signals
• A programmable sample rate generator for internal generation and
control of clock signals and frame - synchronization signals
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 Features of McBSP
• Direct interface to:
• T1/E1 framers
• IOM-2 compliant devices
• AC97-compliant devices with multiphase
frame capability
• I2S compliant devices
• SPI devices
• Variable data sizes: 8, 12, 16, 20, 24, and 32 bits
• A-law (Europe) and µ-law (US & Japan)
hardware compression / expanding
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 Definition: Word and Frame

FS

D w6 w7 w0 w1 w2 w3 w4 w5 w6 w7

Frame
Word

u “Frame” - contains one or multiple words

u Number of words per frame: 1-128

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 Definition: Bit and Word

CLK

FS

D a1 a0 b7 b6 b5 b4 b3 b2 b1 b0

Word
Bit

u “Bit” - one data bit per serial clock period

u “Word” or “channel” contains number of bits
(8, 12, 16, 20, 24, 32)

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 Multi--Channel Selection
Multi
Ch0-0
Multi-channel
Frame TDM Bit Stream Ch0-1
M Transmit
C 0 Ch31 ... Ch1 Ch0
c &
O Ch5-0
D ... B Receive
1 Ch31 Ch1 Ch0 Ch5-1
E S only selected
C P Channels Ch27-0
Ch27-1
u Allows multiple channels (words) to be independently selected for transmit
and receive (e.g. only enable Ch0, 5, 27 for receive, then process via CPU)

u The McBSP keeps time sync with all channels, but only “listens” or “talks”
if the specific channel is enabled (reduces processing/bus overhead)

u Multi-channel mode controlled primarily via two registers:

Multi-channel Control Reg Rec/Xmt Channel Enable Regs
MCR R/XCER (A-H)
(enables Mc-mode) (enable/disable channels)
u Up to 128 channels can be enabled/disabled
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Compression & Expanding Data

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 McBSP - Clocking

• Data is shifted one bit at a time

• from the DR pin to the RSR(s) or
• from the XSR(s) to the DX pin.

• The receive clock signal (CLKR) controls bit transfers

from the DR pin to the RSR(s).

• The transmit clock signal (CLKX) controls bit transfers

from the XSR(s) to the DX pin.

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 McBSP – Frame Phases
Single Phase Frame, 8 bits per word

Dual Phase Frame

Phase 1: 2 words of 12 bits each

Phase 2: 3 words of 8 bit each
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 McBSP – Reception
Reception physical data path

Reception signal activity

DRR = Data Receive Register

RRDY = status bit “Receiver Ready”
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 McBSP – Transmission
Transmission physical data path

Transmission signal activity

DXR = Data Transmit Register

XRDY = status bit “Transmitter Ready”
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 McBSP – Interrupts and DMA
Internal Signals from McBSP to CPU or DMA:

Internal Signal Description

RINT Receiver Interrupt from McBSP to CPU; based
on a selected condition in the receiver
XINT Transmitter Interrupt from McBSP to CPU;
based on a selected condition in the transmitter
REVT Receive synchronization event from McBSP to
DMA; triggered when data has been received in
DRR.
XEVT Transmit synchronization event from McBSP to
DMA; triggered when DXR is ready to accept
new data.

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 McBSP – Register Set
McBSP Control & Data Registers:
Register Description
DRR2 Data Receive Register 2 (high)
DRR1 Data Receive Register 1 (low)
DXR2 Data Transmit Register 2 (high)
DXR1 Data Receive Register 1 (low)
SPCR2 Serial Port Control Register 2
SPCR1 Serial Port Control Register 1
RCR2 Receive Control Register 2
RCR1 Receive Control Register 1
XCR2 Transmit Control Register 2
XCR1 Transmit Control Register 1
SRGR2 Sample Rate Generator Register 2
SRGR1 Sample Rate Generator Register 1

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 McBSP – Register Set
McBSP Multi Channel Control Registers:
Register Description
MCR2 Multichannel Control Register 2
MCR1 Multichannel Control Register 1
RCERx Receive Channel Enable Register Partition x
XCERx Transmit Channel Enable Register Partition x
PCR Pin Control Register
XCERB Transmit Channel Enable Register Partition B
PCR Pin Control Register Partition Channels
MFFINT Interrupt Enable Register A 0 -15
B 16 – 31
x = Partition A, B, C, D, E, F, G, H C 32 – 47
D 48 – 63
E 64 – 79
F 80 – 95
G 96 – 111
H 112 - 127
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 McBSP – Data Register
McBSP Data Receive Register (DRR2 and DRR1):

McBSP Data Transmit Register (DXR2 and DXR1):

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McBSP – Serial Port Control Register (SPCR1)

DLB: Digital Loopback Mode 0 = disabled; 1 = enabled

RJUST: Receive Justification Mode0 = Right justify data and zero fill MSBs
1 = Right justify data and sign – extend MSBs
2 = Left justify data and zero fill LSBs
CLKSTP: Clock Stop Mode 0 and 1 = disabled
2 = enabled, without clock delay (SPI – Mode)
3 = enabled, with half-cycle clock delay (SPI – Mode)
DXENA: DX Delay Enable 0 = OFF
1 = ON; extra delay for turn – ON - time
RINTM: Receiver Interrupt Mode 0 = INT when RRDY = 1
1 = INT after 16 channels (multichannel mode)
2 = INT of frame sync pulse
3 = INT on Receive Frame Sync Error
RSYNCERR: Receive Frame Sync Error 0 = no error; 1 = error
RFULL: Receiver Full Status bit 1 = Receiver Full condition (RSR, RBR and DRR full)
RRDY: Receiver Ready Status bit 1 = Receiver Ready; new data in DRR
RRST: Receiver Reset Control Bit 0 = Reset Receiver; 1 = release Receiver from Reset
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McBSP – Serial Port Control Register (SPCR2)

FREE: Free Run JTAG Mode 0 = Stop at breakpoint; 1 = Free Run

Soft: Soft Stop JTAG Mode 0 = if FREE = 0, stop immediately in case of breakpoint
1 = if FREE = 0, stop at end of frame

FRST: Frame Sync Logic Reset 0 = Reset; 1 = release Frame Logic from Reset
GRST: Sample Rate Generator Reset 0 = Reset; 1 = release SRG from Reset
XINTM: Transmit Interrupt Mode 0 = INT when XRDY = 1
1 = INT after 16 channels (multichannel mode)
2 = INT of frame sync pulse
3 = INT on Transmit Frame Sync Error
XSYNCERR: Receive Frame Sync Error 0 = no error; 1 = error
XEMPTY: Transmitter Empty Status bit 0 = Transmitter empty (DXR1); 1 = not empty
XRDY: Transmitter Ready Status bit 1 = Transmitter ready (DXR1,2) to accept new data
XRST: Transmitter Reset Control Bit 0=Reset Transmitter; 1=release Transmitter from Reset

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McBSP – Receive Control Register 1 (RCR1)

RFRLEN1: Receive Frame Length1(0…0x7F)

Single Phase Frame: Number of Words in a frame (1…128)
Dual Phase Frame: Number of Words in frame – phase 1 (1...128)

RWDLEN1: Receive Word Length1 (0…7)

Single Phase Frame: Number of Bits in a Word
Dual Phase Frame: Number of Bits in a Word of frame - phase 1
0 = 8 Bit
1 = 12 Bit
2 = 16 Bit
3 = 20 Bit
4 = 24 Bit
5 = 32 Bit
6 and 7: reserved

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McBSP – Receive Control Register 2 (RCR2)

RPHASE: Receive Phase Number 0 = Single Phase Frame

1 = Dual Phase Frame

RFRLEN2: Receive Frame Length 2 (0…0x7F)

Single Phase Frame: don’t care
Dual Phase Frame: Number of Words in frame – phase 2 (1...128)

RWDLEN2: Receive Word Length 2 (0…7)

Single Phase Frame: don’t care
Dual Phase Frame: Number of Bits in a Word of frame - phase 2
0 = 8 Bit, 1 = 12 Bit, 2 = 16 Bit, 3 = 20 Bit, 4 = 24 Bit, 5 = 32 Bit
RCOMPAND: Receive Companding Mode 0 = no companding, MSB received first
1 = no companding, 8-bit-data, LSB first
2 = µ-law; 8-bit-data, MSB received first
3 = A-law; 8-bit-data, MSB received first
RFIG: Receive Frame Sync Ignore 1 = unexpected Frame Sync ignored
RDATDLY: Receive Data Delay 0 = 0 clock cycles delay after frame Sync
1 = 1 cycle; 2 = 2 cycles; 3 =reserved
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McBSP – Transmit Control Register 1 (XCR1)

XFRLEN1: Transmit Frame Length1(0…0x7F)

Single Phase Frame: Number of Words in a frame (1…128)
Dual Phase Frame: Number of Words in frame – phase 1 (1...128)

XWDLEN1: Transmit Word Length1 (0…7)

Single Phase Frame: Number of Bits in a Word
Dual Phase Frame: Number of Bits in a Word of frame - phase 1
0 = 8 Bit
1 = 12 Bit
2 = 16 Bit
3 = 20 Bit
4 = 24 Bit
5 = 32 Bit
6 and 7: reserved

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McBSP – Transmit Control Register 2 (XCR2)

XPHASE: Transmit Phase Number 0 = Single Phase Frame

1 = Dual Phase Frame

XFRLEN2: Transmit Frame Length 2 (0…0x7F)

Single Phase Frame: don’t care
Dual Phase Frame: Number of Words in frame – phase 2 (1...128)

XWDLEN2: Transmit Word Length 2 (0…7)

Single Phase Frame: don’t care
Dual Phase Frame: Number of Bits in a Word of frame - phase 2
0 = 8 Bit, 1 = 12 Bit, 2 = 16 Bit, 3 = 20 Bit, 4 = 24 Bit, 5 = 32 Bit
XCOMPAND: Transmit Companding Mode 0 = no companding, MSB transmitted first
1 = no companding, 8-bit-data, LSB first
2 = µ-law; 8-bit-data, MSB transmitted first
3 = A-law; 8-bit-data, MSB transmitted first
XFIG: Transmit Frame Sync Ignore 1 = unexpected Frame Sync ignored
XDATDLY: Transmit Data Delay 0 = 0 clock cycles delay after frame Sync
1 = 1 cycle; 2 = 2 cycles; 3 =reserved 13 - 23
 McBSP – Sample Rate Generator (SRGR1)

FWID: Frame Sync Pulse Width 0…255

Pulse Width of Frame Sync Signal in McBSP
clock cycles

CLKGDV: Divide Down Value for Clock-Generator 0…255

CLKG frequency = (Input clock frequency)/ (CLKGDV + 1)

The input clock is selected by the SCLKME (Register PCR) and CLKSM
(Register SRGR) bits:

SCLKME CLKSM Input Clock Source

0 0 Reserved
0 1 LSPCLK
1 0 Signal on pin MCLKR
1 1 Signal on pin MCLKX
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 McBSP – Sample Rate Generator (SRGR2)

GSYNC: Clock Sync Mode only used, if clock source is external

1 = Clock Synchronization;
CLKG is adjusted to MCLKR / MCLKX
0 = no clock sync;
CLKG free running, FSG every FPER-cycles
CLKSM: Sample Clock Mode
SCLKME CLKSM Input Clock Source
0 0 Reserved
0 1 LSPCLK
1 0 Signal on pin MCLKR
1 1 Signal on pin MCLKX
FSGM: Frame Sync Mode; Frame Pulse from pin FSX (if FSXM = 0)
0: if FSXM = 1, generate frame pulse when DXR is copied into XSR
1: if FSXM = 1, generate frame pulse based on FPER and FWID
FPER: Frame Sync Period (1…4096); Number of CLKG cycles between frame
pulses 13 - 25
 McBSP – Pin Control Register (PCR)

FSXM: Transmit Frame Sync Mode 0 = Frame Pulse is supplied externally via pin FSX
1 = Frame Pulse generated internally by Sample Rate
Generator (bit FSGM of register SRGR2)
FSRM: Receive Frame Sync Mode 0 = Frame Pulse is supplied externally via pin FSR
1 = Frame Pulse generated internally by Sample Rate
Generator (bit FSGM of register SRGR2)
CLKXM: Transmit Clock Mode if CLKSTP = 0 or 1:
0 = external transmit clock from pin MCLKX
1 = internal transmit clock; MCLKX is output
if CLKSTP = 2 or 3:
0 = McBSP is slave in SPI – Protocol; MCLKX is input
1 = McBSP is master in SPI – Mode; MCLKX is output
SCLKME: Sample Rate Generator Input Mode (see CLKSM in Register SRGR2)
DXSTAT: DX pin Status Bit 1 = drive DX pin high; 0 = DX pin low (GPIO mode)
DRSTAT: DR pin Status Bit 1 = drive DR pin high; 0 = DR pin low (GPIO mode)
FSXP: Transmit Frame Sync Polarity 0 = active high; 1 = active low
FSRP: Receive Frame Sync Polarity 0 = active high; 1 = active low
CLKXP: Transmit Clock Polarity data valid on rising (0) or falling (1) edge of CLKX
CLKRP: Receive Clock Polarity data sampled on rising (1) or falling (0) edge 13 - 26
McBSP – Interrupt Enable Register (MFFINT)

RINT ENA: 0 = disable McBSP Receive Interrupts

1 = enable McBSP Receive Interrupts

XINT ENA: 0 = disable McBSP Transmit Interrupts

1 = enable McBSP Transmit Interrupts

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Stereo Audio Codec TLV320AIC23B
Main Features:

• 90dB SNR Multibit Sigma-Delta ADC

• 100-dB SNR Multibit Sigma-Delta DAC
• 8 kHz …96 kHz Sampling-Frequency
• SPI- Interface for Control Channel Compatible Serial-
Port Protocols
• 2 - Phase Audio - Data Input/Output via McBSP
• Standard I2S, MSB, or LSB Justified-Data Transfers
• 16/20/24/32-Bit Audio Data Word Length
• Volume Control With Mute on Input and Output
• ADC Multiplexed Input for Stereo-Line Inputs and
Microphone
• Highly Efficient Linear Headphone Amplifier (30 mW into
32 Ohm from a 3.3-V Analogue Supply Voltage
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 Stereo Audio Codec TLV320AIC23B
Functional Block
Diagram:

Signals:
RHPOUT =
right headphone out
LHPOUT =
left headphone out

© Document Number : SLWS106H,

page 1-3 (www.ti.com)

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Stereo Audio Codec TLV320AIC23B
GPIO -MUX F2833x – Function Description AIC23–
signal
GPIO20 = 2 McBSPA – MDXA Audio data out DIN
GPIO21 = 2 McBSPA – MDRA Audio data in DOUT
GPIO22 = 2 McBSPA – MCLKXA Transmit clock BCLK

GPIO23 = 2 McBSPA – MFSXA Transmit frame LRCIN

sync
GPIO58 = 1 McBSPA – MCLKRA Receive Clock BCLK
GPIO59 = 1 McBSPA – MFRA Receive frame LRCOUT
sync
GPIO16 = 1 SPIA – SPISIMO Control data out SDIN

GPIO18 = 1 SPIA – SPICLK Control data SCLK

clock
GPIO19 = 1 SPIA – SPISTE Slave trans. /CS
enable
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 Stereo Audio Codec TLV320AIC23B
Reset Register:

Power Down Control Register:

LINE = Line Input

MIC = Microphone Input
ADC = Internal ADC
DAC = Internal DAC
OUT = Output Signals
0 = ON; 1 = OFF
OSC = Oscillator
CLK = CLOCK
OFF = Device Power
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 Stereo Audio Codec TLV320AIC23B
Left Channel Headphone Volume Control Register:

LRS = Left / Right simultaneous update volume ( 0 = OFF, 1 = ON)

LZC = Left channel zero cross (0 = OFF, 1 = ON). If ON, volume updates
only at zero crossings
LHV = Left Headphone Volume (0x7F = +6dB; 0x79 = 0dB; 0x30 = -73dB (mute)

Right Channel Headphone Volume Control Register:

RLS = Right / Left simultaneous update volume ( 0 = OFF, 1 = ON)

RZC = Right channel zero cross (0 = OFF, 1 = ON). If ON, volume updates only
at zero crossings
RHV = Right Headphone Volume (0x7F = +6dB; 0x79 = 0dB; 0x30 = -73dB (mute)
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 Stereo Audio Codec TLV320AIC23B
Analogue Audio Path Control Register:

MICB = Microphone boost (0 = 0dB; 1 = 20dB)

MICM = Microphone mute (0 = normal; 1 = muted)
INSEL = Input Select for Audio (0 = line; 1 = Microphone)
BYP = Bypass (0 = disabled; 1 = enabled (line in to line out))
DAC = DAC select ( 0 = DAC OFF; 1 = DAC ON)
STE = Added Side Tone ( 0 = OFF; 1 = ON)
STA = Side Tone Volume (If STE = ON, MIC is routed both to headphone & line out ).

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 Stereo Audio Codec TLV320AIC23B
Digital Audio Path Control Register:

ADCHP = ADC High Pass Filter (0 = enabled; 1 = disabled)

DEEMP = De-emphasis control (0 = disabled, 1 = 32kHz, 2 = 44.1kHz, 3 = 48kHz)
DACM = DAC soft mute (0 = disabled; 1 = enabled)

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 Stereo Audio Codec TLV320AIC23B
Digital Audio Interface Format Register:

FOR = Data Format 0 = MSB first, right aligned

1 = MSB first, left aligned
2 = I2S – Format, MSB first, left -1 aligned
3 = DSP – Format; Frame sync followed by 2 words
IWL = Input word length 0 = 16 bit
1 = 20 bit
2 = 24 bit
3 = 32 bit
LRP = DAC left /right phase 0 = right channel on and LRCIN = high
1 = right channel on and LRCIN = low
LRSWAP = DAC left / right swap (0 = NO, 1 = YES)
MS = Master Mode ( 0 = Slave; 1 = Master)

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 Stereo Audio Codec TLV320AIC23B
Sample Rate Control Register:

USB = Clock Mode Select (0 = Normal, 1 = USB)

BOSR = Base Oversampling Rate
USB – Mode: 0 = 250fs, 1 = 272fs;
Normal – Mode: 0 = 256fs; 1 = 384fs
SR = Sampling Rate

CLKIN = Clock Input Divider (0 = MCLK; 1 = MCLK/2)

CLKOUT = Clock Output Divider (0 = MCLK; 1 = MCLK/2) 13 - 36
 Stereo Audio Codec TLV320AIC23B
Digital Interface Activation Register:

ACT = Activate Interface (0 = NO, 1 = YES)

RES = reserved

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 AIC23B Exercises:
Lab13_1:
• Initialize SPI-A as control channel for AIC23B
• Initialize McBSP-A as data channel for AIC23B
• AIC23B is master and sends the 12MHz base clock
• AIC23B sends a 44.1 kHz frame sync signal to McBSP
• Send a sinusoidal signal, based on the BOOT-ROM
look-up table to the DAC of the AIC23B; sample rate is
44.1 kHz

Lab13_2:
• Send two different signals to left and right audio channel
• Add volume control

Lab13_3:
• Improvement of Lab13_2; reduce Interrupt Service time
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 EEPROM AT25256 Exercise:
Lab13_4:
• Initialize McBSP-B in SPI-Mode for AT25256
• Write data to EEPROM, if button PB1 (GPIO17) is
pushed. Read the current value from Hex-Encoder
(GPIO12…15) and store it into EEPROM-address
0x0040, bits 3…0.
• Read data from EEPROM-address 0x0040, when button
PB2 (GPIO48) is pushed and display bits 2…0 at LEDs
LD4 (GPOI49), LD3 (GPIO34) and LD1 (GPIO9).

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 EEPROM AT25256
Timing Diagram:

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 EEPROM AT25256
Access Status Register:

7 6 5 4 3 2 1 0
WPEN 0 0 0 BP1 BP0 WEN /RDY

Block protect select Write in progress

00 = no protection
0 = no write cycle
01 = 0x6000 – 0x7FFF protected 1 = write in progress
10 = 0x4000 – 0x7FFF protected
11 = 0x0000 – 0x7FFF protected

Write Enable Latch

Write Protect Enable 0 = write disabled
1 = no write access 1 = write enabled
0 = normal operation
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 EEPROM AT25256
Instruction Register:

Instruction Description Code

WREN Write Enable 0000 0110

WRDI Write Disable 0000 0100

RDSR Read Status 0000 0101

Register
WDSR Write Status 0000 0001
Register
READ Read Data 0000 0011

WRITE Write Data 0000 0010

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 EEPROM AT25256
Write – Enable (WREN) Timing:

© Atmel Corporation; Datasheet AT25256 (doc0872.pdf) – 2005; Page 10

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 EEPROM AT25256
Read Status Register (RDSR) Timing:

© Atmel Corporation; Datasheet AT25256 (doc0872.pdf) – 2005; Page 10

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 EEPROM AT25256
Read (READ) Timing:

© Atmel Corporation; Datasheet AT25256 (doc0872.pdf) – 2005; Page 11

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 EEPROM AT25256
Write (WRITE) Timing:

© Atmel Corporation; Datasheet AT25256 (doc0872.pdf) – 2005; Page 11

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