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VLSI design power cells

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 VLSI design power cells
Sunit Fulari
CEO Ovation

of the core area, cell orientation and core to

input output clearance are also taken care
Abstract:Floorplan is a very important
during the floor stage.
step in vlsi. The issue is a chicken and egg
problem in which an accurate plan is Design flow for floorplanning
difficult without knowing the details , and
yet, building the details is greatly
facilitated with a floorplan. We discuss
the detailed process of floorplanning.
Introduction: So what does floor plan helps
us determine. It helps us in determining the
size of the vlsi chip or cell besides it creates
the boundary and core area and it creates
wire tracks for placement of standard cells
finally it is also a process of positioning
blocks or macros in the chip.
First step in floor planning is determining
the total size of the die. So in this again two If the design meets the specification then we
types of design processings. Block level for placement and extract parasitics.
designs will be recitilinear and chip level Inputs for floorplanning:
designs will be rectangular in shape.
The following are the input requirements
So when we dived into these two type of which cannot be denied. Design netlist, area
rectilinear and rectangular designs we come requirements, power requirements, timing
to know that rectilinear requires more constraints, physical partitioning
coordinates to determine this zie besides information and die size to performance
rectangular requires only the height and tradeoff. While the optional requirements
width of the die. The following parameters are input outpur placement and macro
are decided in the floor planning stage. placement information.
That is the die size, core size and chip is The output design ready for standard cell
whether it is rectilinear or rectangular. placement are die or block area, input output
Input/output pads location, plan for power placed, macros places, power grid designed
and row configuration. In broader sense pad and power pre routing standard cell
info, power planning and macro placement placement areas.
together is known as floor planning. Apart
from this aspect ratio of the core, utilization
So what are the inputs to floor planning:
Netlist which are the different files such as
ddc. And vhdl files , physical and logical
libraries, design constraints, pin and pad
location file, partition info files which are
optional and macro placement location file Decap cells: they are temporary capacitors
which is also optional with floor planning which are added in the design between
control parameters. power and ground rails to counter the
functional failure due to dynamic IR drop.
Aspects ratio: this is the ratio of height Dynamic IR drop happens at the active edge
divided by width and determines whether of the clock at which a high current is drawn
you get a square or rectangular floorplan. An from the power grid for a small duration. If
aspect ratio of 1 gives you a square power source is far from a flop the chances
floorplan. are there that flop can go into metastable
What is utilization factor: utilization defines state. To overcome decaps are added, when
the area occupied by standard cell. Macros current requirements if high this decaps
and blockages. In general 70 to 80 percent discharge and provide boost to the power
of utilization is fixed because more number grid.
of inverters and buffers will be added during Tie cells:Tie-high and tie-low cells are used
the process of clock tree synthesis in order to connect the gate of the transistor to either
to maintain minimum skew. power or ground. In lower technology
Design process. Placement of special cells nodes, if the gate is connected to
during floorplanning before placement of power/ground the transistor might be turned
standard cell are known as preplaced cell. on or off due to power or ground bounce.
These cells are part of standard cell library.
There are different types of preplaced cell as The cells which require voltage connect to
below. tie high cells. The cells which require
Well taps(tap cells):they are traditionally voltage to ground connect to tie low cells.
used so that voltage and ground are Filler cells:filler cells are used to establish
connected to substrate or n well the continuity of the N well and the implant
respectively. This is to help tie voltage of layers on the standard cell rows, some of the
junction to ground which results in lesser small cells also don’t have the bulk
drift and prevention from latchup. connection because of their small size. In
End cap cells:the library cells do not have those cases, the abutment of cells through
cell connectivity as they are only connected inserting filler cells can connect those
to power and ground rails, thus to ensure sunstrates of small cells to the power and
that gaps do not occur between well and ground nets. This is those thin cells can use
implant layer and to prevent the DRC the bulk connection of the other cells.
violations by satisfying well tie off Spare cells:these are extra cells placed in
requirements for core rows we use end-cap layout in anticipation of a future ECO. For
cells. example, if a logic change requires addition
of an AND cell, can use an existing spare VLSI floorplanning. Soft Computing, 14(12),
AND to make this change. This way, ensure pp.1329-1337.
that the base layer masks need no [3] Nakaya, S., Koide, T. and Wakabayashi, S.,
regeneration for the next fabrication. 2000, May. An adaptive genetic algorithm for
VLSI floorplanning based on sequence-pair.
Kinds of spare cells: there are many variants In 2000 IEEE International Symposium on
of spare cells in the design, designs are full Circuits and Systems. Emerging Technologies
of spare inverters, buffers, nand, nor and for the 21st Century. Proceedings (IEEE Cat No.
00CH36353) (Vol. 3, pp. 65-68). IEEE.
specially designed configuratble spare cells.
[4] Chen, J., Zhu, W. and Ali, M.M., 2010. A
There are mainly two types of power hybrid simulated annealing algorithm for
planning namely core cell power nonslicing VLSI floorplanning. IEEE
management and input output power Transactions on Systems, Man, and
management. Cybernetics, Part C (Applications and
Reviews), 41(4), pp.544-553.
Basic SR flip flop as memory device. [5] Ma, Y., Dong, S., Hong, X., Cai, Y., Cheng,
C.K. and Gu, J., 2001, January. VLSI
floorplanning with boundary constraints based
on corner block list. In Proceedings of the 2001
Asia and South Pacific Design Automation
Conference (pp. 509-514). ACM.

[6] Rosenberg, E., 1989. Optimal module sizing

in VLSI floorplanning by nonlinear
programming. Zeitschrift für Operations
Research, 33(2), pp.131-143.

[7] Tang, M. and Sebastian, A., 2005, March. A

genetic algorithm for VLSI floorplanning using O-
tree representation. In Workshops on
Applications of Evolutionary Computation (pp.
215-224). Springer, Berlin, Heidelberg.

[8] Anjos, M.F. and Liers, F., 2012. Global

approaches for facility layout and VLSI
floorplanning. In Handbook on semidefinite,
conic and polynomial optimization (pp. 849-877).
Conclusion: we have shown the various Springer, Boston, MA.
floorplanning and design of the basic steps
[9] Weste, N.H. and Eshraghian, K., 1985.
in vlsi design.
Principles of CMOS VLSI design: a systems
References: perspective. NASA STI/Recon Technical Report
A, 85.
[1] Tang, M. and Yao, X., 2007. A memetic
[10] Weste, N.H. and Harris, D., 2015. CMOS
algorithm for VLSI floorplanning. IEEE
VLSI design: a circuits and systems perspective.
Transactions on Systems, Man, and
Pearson Education India.
Cybernetics, Part B (Cybernetics), 37(1), pp.62-
69.

[2] Chen, G., Guo, W. and Chen, Y., 2010. A

PSO-based intelligent decision algorithm for
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