Ph.D.

Marving Omar Aguilar Justo

Engineering School - Mechatronics Engineering

Combinational Logic
Logic Circuits

Notes extracted from the book: “Sistemas Digitales: Principios y Aplicaciones”,

Ronald D. Tocci, Ed. Pearson Prentice Hall, 10ª Ed., 2007.

Febreruary – June 2020

 ➢ Generalities
➢ Sum of Products and Product of Sums
➢ Logic Circuits Simplification
➢ Design
➢ Karnaugh Maps
➢ Parity Generator and Parity Checker
Combinational Logic
Logic Circuits

➢ Inhibited Circuits
➢ Basic Characteristics of Digital ICs
Ph.D. Marving O. Aguilar J.
 Generalities
Combinational Logic
Logic Circuits

Ph.D. Marving O. Aguilar J.

 Definition

Combinational logic is defined as any digital system in which its

outputs are exclusive function of the value of its inputs at a given
time, without intervening in any case prior states of the inputs or
outputs.

The Boolean functions -composed by OR, AND, NAND, XOR operators-

can be represented entirely by a truth table. Therefore, they lack
memory and feedback.

In digital electronics, combinational logic is formed by simple

equations from the basic operations of Boolean algebra.

Ph.D. Marving O. Aguilar J.

 Sum of Products
and
Product of Sums
Combinational Logic
Logic Circuits

Ph.D. Marving O. Aguilar J.

 Representations

Sum of Products:

Product of Sums:

Ph.D. Marving O. Aguilar J.

 Simplification of
Logic Circuits

Combinational Logic
Logic Circuits

Ph.D. Marving O. Aguilar J.

 Example 2.1
Simplification

Show through truth tables that the circuits below are equivalent. Also
indicate which one is more convenient and why.

Ph.D. Marving O. Aguilar J.

 Example 2.2
Simplification

Simplify the logic circuit shown in the following figure:

Ph.D. Marving O. Aguilar J.

 Example 2.2
Simplification

Simplify the logic circuit shown in the following figure:

z = ABC + AB’(A’C’)’

Ph.D. Marving O. Aguilar J.

 Example 2.2
Simplification

Simplify the logic circuit shown in the following figure:

z = ABC + AB’(A’C’)’
z = ABC + AB’(A’’ + C’’)

Ph.D. Marving O. Aguilar J.

 Example 2.2
Simplification

Simplify the logic circuit shown in the following figure:

z = ABC + AB’(A’C’)’
z = ABC + AB’(A’’ + C’’)
z = ABC + AB’(A + C)

Ph.D. Marving O. Aguilar J.

 Example 2.2
Simplification

Simplify the logic circuit shown in the following figure:

z = ABC + AB’(A’C’)’
z = ABC + AB’(A’’ + C’’)
z = ABC + AB’(A + C)
z = ABC + AB’A + AB’C

Ph.D. Marving O. Aguilar J.

 Example 2.2
Simplification

Simplify the logic circuit shown in the following figure:

z = ABC + AB’(A’C’)’
z = ABC + AB’(A’’ + C’’)
z = ABC + AB’(A + C)
z = ABC + AB’A + AB’C
z = ABC + AB’ + AB’C

Ph.D. Marving O. Aguilar J.

 Example 2.2
Simplification

Simplify the logic circuit shown in the following figure:

z = ABC + AB’(A’C’)’ z = AC(B+B’) + AB’

z = ABC + AB’(A’’ + C’’)
z = ABC + AB’(A + C)
z = ABC + AB’A + AB’C
z = ABC + AB’ + AB’C

Ph.D. Marving O. Aguilar J.

 Example 2.2
Simplification

Simplify the logic circuit shown in the following figure:

z = ABC + AB’(A’C’)’ z = AC(B+B’) + AB’

z = ABC + AB’(A’’ + C’’) z = AC(1) + AB’
z = ABC + AB’(A + C)
z = ABC + AB’A + AB’C
z = ABC + AB’ + AB’C

Ph.D. Marving O. Aguilar J.

 Example 2.2
Simplification

Simplify the logic circuit shown in the following figure:

z = ABC + AB’(A’C’)’ z = AC(B+B’) + AB’

z = ABC + AB’(A’’ + C’’) z = AC(1) + AB’
z = ABC + AB’(A + C) z = AC + AB’
z = ABC + AB’A + AB’C
z = ABC + AB’ + AB’C

Ph.D. Marving O. Aguilar J.

 Example 2.2
Simplification

Simplify the logic circuit shown in the following figure:

z = ABC + AB’(A’C’)’ z = AC(B+B’) + AB’

z = ABC + AB’(A’’ + C’’) z = AC(1) + AB’
z = ABC + AB’(A + C) z = AC + AB’
z = ABC + AB’A + AB’C z = A(C + B’)
z = ABC + AB’ + AB’C

Ph.D. Marving O. Aguilar J.

 Example 2.2
Simplification

Simplify the logic circuit shown in the following figure:

z = A(C + B’)

Ph.D. Marving O. Aguilar J.

 Example 2.3
Simplification

Simplify the logic circuit that results from the expression:

z = ( A’ + B ) ( A + B + D ) D’
Also, develop the circuit of the initial expression and the simplified
expression.

Ph.D. Marving O. Aguilar J.

 Example 2.3
Simplification

Simplify the logic circuit that results from the expression:

z = ( A’ + B ) ( A + B + D ) D’
Also, develop the circuit of the initial expression and the simplified
expression.

z = ( A’ + B ) ( A + B + D ) D’

Ph.D. Marving O. Aguilar J.

 Example 2.3
Simplification

Simplify the logic circuit that results from the expression:

z = ( A’ + B ) ( A + B + D ) D’
Also, develop the circuit of the initial expression and the simplified
expression.

z = ( A’ + B ) ( A + B + D ) D’
z = ( A’ A + A’ B + A’ D + B A + B B + B D ) D’

Ph.D. Marving O. Aguilar J.

 Example 2.3
Simplification

Simplify the logic circuit that results from the expression:

z = ( A’ + B ) ( A + B + D ) D’
Also, develop the circuit of the initial expression and the simplified
expression.

z = ( A’ + B ) ( A + B + D ) D’
z = ( A’ A + A’ B + A’ D + B A + B B + B D ) D’
z = A’ A D’ + A’ B D’ + A’ D D’ + B A D’ + B B D’ + B D D’

Ph.D. Marving O. Aguilar J.

 Example 2.3
Simplification

Simplify the logic circuit that results from the expression:

z = ( A’ + B ) ( A + B + D ) D’
Also, develop the circuit of the initial expression and the simplified
expression.

z = ( A’ + B ) ( A + B + D ) D’
z = ( A’ A + A’ B + A’ D + B A + B B + B D ) D’
z = A’ A D’ + A’ B D’ + A’ D D’ + B A D’ + B B D’ + B D D’
z = (0) D’ + A’ B D’ + A’ (0) + B A D’ + (B) D’ + B (0)

Ph.D. Marving O. Aguilar J.

 Example 2.3
Simplification

Simplify the logic circuit that results from the expression:

z = ( A’ + B ) ( A + B + D ) D’
Also, develop the circuit of the initial expression and the simplified
expression.

z = ( A’ + B ) ( A + B + D ) D’
z = ( A’ A + A’ B + A’ D + B A + B B + B D ) D’
z = A’ A D’ + A’ B D’ + A’ D D’ + B A D’ + B B D’ + B D D’
z = (0) D’ + A’ B D’ + A’ (0) + B A D’ + (B) D’ + B (0)
z = A’ B D’ + B A D’ + B D’

Ph.D. Marving O. Aguilar J.

 Example 2.3
Simplification

Simplify the logic circuit that results from the expression:

z = ( A’ + B ) ( A + B + D ) D’
Also, develop the circuit of the initial expression and the simplified
expression.

z = ( A’ + B ) ( A + B + D ) D’
z = ( A’ A + A’ B + A’ D + B A + B B + B D ) D’
z = A’ A D’ + A’ B D’ + A’ D D’ + B A D’ + B B D’ + B D D’
z = (0) D’ + A’ B D’ + A’ (0) + B A D’ + (B) D’ + B (0)
z = A’ B D’ + B A D’ + B D’
z = B D’ ( A’ + A + 1)

Ph.D. Marving O. Aguilar J.

 Example 2.3
Simplification

Simplify the logic circuit that results from the expression:

z = ( A’ + B ) ( A + B + D ) D’
Also, develop the circuit of the initial expression and the simplified
expression.

z = ( A’ + B ) ( A + B + D ) D’
z = ( A’ A + A’ B + A’ D + B A + B B + B D ) D’
z = A’ A D’ + A’ B D’ + A’ D D’ + B A D’ + B B D’ + B D D’
z = (0) D’ + A’ B D’ + A’ (0) + B A D’ + (B) D’ + B (0)
z = A’ B D’ + B A D’ + B D’
z = B D’ ( A’ + A + 1)
z = B D’ (1)

Ph.D. Marving O. Aguilar J.

 Example 2.3
Simplification

Simplify the logic circuit that results from the expression:

z = ( A’ + B ) ( A + B + D ) D’
Also, develop the circuit of the initial expression and the simplified
expression.

z = ( A’ + B ) ( A + B + D ) D’
z = ( A’ A + A’ B + A’ D + B A + B B + B D ) D’
z = A’ A D’ + A’ B D’ + A’ D D’ + B A D’ + B B D’ + B D D’
z = (0) D’ + A’ B D’ + A’ (0) + B A D’ + (B) D’ + B (0)
z = A’ B D’ + B A D’ + B D’
z = B D’ ( A’ + A + 1)
z = B D’ (1)
z = B D’

Ph.D. Marving O. Aguilar J.

 Design
Combinational Logic
Logic Circuits

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Step 1: Establish the truth table.

A B C x

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Step 1: Establish the truth table.

A B C x

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Step 1: Establish the truth table.

A B C x
0
1
0
1
0
1
0
1

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Step 1: Establish the truth table.

A B C x
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Step 1: Establish the truth table.

A B C x
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Step 1: Establish the truth table.

A B C x
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Step 2: Write the AND term for each x = 1.

A B C x
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 A’ B C
1 0 0 0
1 0 1 1 A B’ C
1 1 0 1 A B C’
1 1 1 1 ABC

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Step 3: Write the sum of products equal to x.

A B C x
x = A’ B C + A B’ C 0 0 0 0
+ A B C’ + A B C
0 0 1 0
0 1 0 0
0 1 1 1 A’ B C
1 0 0 0
1 0 1 1 A B’ C
1 1 0 1 A B C’
1 1 1 1 ABC

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Step 4: Simplify x.
A B C x
x = A’ B C + A B’ C 0 0 0 0
+ A B C’ + A B C
0 0 1 0
.
0 1 0 0
.
. 0 1 1 1 A’ B C
x=BC+AC 1 0 0 0
+AB 1 0 1 1 A B’ C
1 1 0 1 A B C’
1 1 1 1 ABC

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Step 5: Develop the logic circuit.

x = A’ B C + A B’ C
+ A B C’ + A B C
.
.
.
x=BC+AC
+AB

Ph.D. Marving O. Aguilar J.

 Example 2.4
Design of a Combinational Logic Circuit

Design a logic circuit that has 3 inputs and whose output is high only
when most inputs are high.

Step 6 (optional): Analyze if it is possible to change the gates to save ICs.

Ph.D. Marving O. Aguilar J.

 Example 2.5
Design of a Combinational Logic Circuit

Consider the figure shown where 4 input lines (A, B, C and D) are
used to represent a 4-bit binary number with A as the MSB and D as
the LSB.

The binary inputs feed a combinational logic circuit that produces a

high output only when the binary number is greater than 01102 =
610.

Design the logic circuit.

analog-
Logic
digital
circuit
converter

Ph.D. Marving O. Aguilar J.

 Example 2.5
Design of a Combinational Logic Circuit

Consider the figure shown where 4 input lines (A, B, C and D) are
used to represent a 4-bit binary number with A as the MSB and D as
the LSB.

The binary inputs feed a combinational logic circuit that produces a

high output only when the binary number is greater than 01102 =
610.

Design the logic circuit.

Ph.D. Marving O. Aguilar J.

 Karnaugh Maps
Combinational Logic
Logic Circuits

Ph.D. Marving O. Aguilar J.

 Karnaugh Map

The Karnaugh map (map K) is a graphical method

that is used to simplify a logic equation to convert
a truth table to its corresponding logic circuit in a
simple and orderly process.

Ph.D. Marving O. Aguilar J.

 Example 2.6
Karnaugh Map

A B x
0 0 0
0 1 1
1 0 0
1 1 1

x = A’ B + A B

Ph.D. Marving O. Aguilar J.

 Example 2.6
Karnaugh Map

A B x B’ B
0 0 0 A’
0 1 1 A
1 0 0
1 1 1

x = A’ B + A B

Ph.D. Marving O. Aguilar J.

 Example 2.6
Karnaugh Map

A B x B’ B
0 0 0 A’ 0 1
0 1 1 A 0 1
1 0 0
1 1 1

x = A’ B + A B

Ph.D. Marving O. Aguilar J.

 Example 2.6
Karnaugh Map

A B x B’ B
0 0 0 A’ 0 1
0 1 1 A 0 1
1 0 0
1 1 1

x = A’ B + A B

Ph.D. Marving O. Aguilar J.

 Example 2.6
Karnaugh Map

A B x B’ B
0 0 0 A’ 0 1
0 1 1 A 0 1
1 0 0
x=B
1 1 1

x = A’ B + A B

Ph.D. Marving O. Aguilar J.

 Example 2.7
Karnaugh Map

A B x
0 0 0
0 1 0
1 0 1
1 1 1

x = A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.7
Karnaugh Map

A B x B’ B
0 0 0 A’
0 1 0 A
1 0 1
1 1 1

x = A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.7
Karnaugh Map

A B x B’ B
0 0 0 A’ 0 0
0 1 0 A 1 1
1 0 1
1 1 1

x = A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.7
Karnaugh Map

A B x B’ B
0 0 0 A’ 0 0
0 1 0 A 1 1
1 0 1
1 1 1

x = A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.7
Karnaugh Map

A B x B’ B
0 0 0 A’ 0 0
0 1 0 A 1 1
1 0 1
x=A
1 1 1

x = A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.8
Karnaugh Map

A B x
0 0 1
0 1 0
1 0 0
1 1 0

x = A’ B’

Ph.D. Marving O. Aguilar J.

 Example 2.8
Karnaugh Map

A B x B’ B
0 0 1 A’
0 1 0 A
1 0 0
1 1 0

x = A’ B’

Ph.D. Marving O. Aguilar J.

 Example 2.8
Karnaugh Map

A B x B’ B
0 0 1 A’ 1 0
0 1 0 A 0 0
1 0 0
1 1 0

x = A’ B’

Ph.D. Marving O. Aguilar J.

 Example 2.8
Karnaugh Map

A B x B’ B
0 0 1 A’ 1 0
0 1 0 A 0 0
1 0 0
1 1 0

x = A’ B’

Ph.D. Marving O. Aguilar J.

 Example 2.8
Karnaugh Map

A B x B’ B
0 0 1 A’ 1 0
0 1 0 A 0 0
1 0 0
x = A’ B’
1 1 0

x = A’ B’

Ph.D. Marving O. Aguilar J.

 Example 2.9
Karnaugh Map

A B x
0 0 0
0 1 1
1 0 1
1 1 1

x = A’ B + A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.9
Karnaugh Map

A B x B’ B
0 0 0 A’
0 1 1 A
1 0 1
1 1 1

x = A’ B + A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.9
Karnaugh Map

A B x B’ B
0 0 0 A’ 0 1
0 1 1 A 1 1
1 0 1
1 1 1

x = A’ B + A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.9
Karnaugh Map

A B x B’ B
0 0 0 A’ 0 1
0 1 1 A 1 1
1 0 1
1 1 1

x = A’ B + A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.9
Karnaugh Map

A B x B’ B
0 0 0 A’ 0 1
0 1 1 A 1 1
1 0 1
x=A+B
1 1 1

x = A’ B + A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.10
Karnaugh Map

A B x
0 0 1
0 1 1
1 0 1
1 1 1

x = A’ B’ + A’ B + A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.10
Karnaugh Map

A B x B’ B
0 0 1 A’
0 1 1 A
1 0 1
1 1 1

x = A’ B’ + A’ B + A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.10
Karnaugh Map

A B x B’ B
0 0 1 A’ 1 1
0 1 1 A 1 1
1 0 1
1 1 1

x = A’ B’ + A’ B + A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.10
Karnaugh Map

A B x B’ B
0 0 1 A’ 1 1
0 1 1 A 1 1
1 0 1
1 1 1

x = A’ B’ + A’ B + A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.10
Karnaugh Map

A B x B’ B
0 0 1 A’ 1 1
0 1 1 A 1 1
1 0 1
x=1
1 1 1

x = A’ B’ + A’ B + A B’ + A B

Ph.D. Marving O. Aguilar J.

 Example 2.11
Karnaugh Map

A B C x
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

x = A’ B’ C’ + A’ B C’+ A’ B C
+ A B’ C’ + A B C’

Ph.D. Marving O. Aguilar J.

 Example 2.11
Karnaugh Map

A B C x C’ C
0 0 0 1 A’B’

0 0 1 0 A’B

0 1 0 1 AB

0 1 1 1 AB’

1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

x = A’ B’ C’ + A’ B C’+ A’ B C
+ A B’ C’ + A B C’

Ph.D. Marving O. Aguilar J.

 Example 2.11
Karnaugh Map

A B C x C’ C
0 0 0 1 A’B’ 1 0
0 0 1 0 A’B 1 1
0 1 0 1 AB 1 0
0 1 1 1 AB’ 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

x = A’ B’ C’ + A’ B C’+ A’ B C
+ A B’ C’ + A B C’

Ph.D. Marving O. Aguilar J.

 Example 2.11
Karnaugh Map

A B C x C’ C
0 0 0 1 A’B’ 1 0
0 0 1 0 A’B 1 1
0 1 0 1 AB 1 0
0 1 1 1 AB’ 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

x = A’ B’ C’ + A’ B C’+ A’ B C
+ A B’ C’ + A B C’

Ph.D. Marving O. Aguilar J.

 Example 2.11
Karnaugh Map

A B C x C’ C
0 0 0 1 A’B’ 1 0
0 0 1 0 A’B 1 1
0 1 0 1 AB 1 0
0 1 1 1 AB’ 1 0
1 0 0 1
x = C’ + A’ B
1 0 1 0
1 1 0 1
1 1 1 0

x = A’ B’ C’ + A’ B C’+ A’ B C
+ A B’ C’ + A B C’

Ph.D. Marving O. Aguilar J.

 Example 2.12
Karnaugh Map

A B C x
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

x = A’ B’ C’ + A’ B C’+ A’ B C
+ A B’ C’ + A B C’

Ph.D. Marving O. Aguilar J.

 Example 2.12
Karnaugh Map

A B C x C’ C
0 0 0 1 A’B’

0 0 1 1 A’B

0 1 0 0 AB

0 1 1 0 AB’

1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

x = A’ B’ C’ + A’ B C’+ A’ B C
+ A B’ C’ + A B C’

Ph.D. Marving O. Aguilar J.

 Example 2.12
Karnaugh Map

A B C x C’ C
0 0 0 1 A’B’ 1 1
0 0 1 1 A’B 0 0
0 1 0 0 AB 0 0
0 1 1 0 AB’ 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

x = A’ B’ C’ + A’ B C’+ A’ B C
+ A B’ C’ + A B C’

Ph.D. Marving O. Aguilar J.

 Example 2.12
Karnaugh Map

A B C x C’ C
0 0 0 1 A’B’ 1 1
0 0 1 1 A’B 0 0
0 1 0 0 AB 0 0
0 1 1 0 AB’ 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

x = A’ B’ C’ + A’ B C’+ A’ B C
+ A B’ C’ + A B C’

Ph.D. Marving O. Aguilar J.

 Example 2.12
Karnaugh Map

A B C x C’ C
0 0 0 1 A’B’ 1 1
0 0 1 1 A’B 0 0
0 1 0 0 AB 0 0
0 1 1 0 AB’ 1 1
1 0 0 1
x = B’
1 0 1 1
1 1 0 0
1 1 1 0

x = A’ B’ C’ + A’ B C’+ A’ B C
+ A B’ C’ + A B C’

Ph.D. Marving O. Aguilar J.

 A B C D x
Example 2.13
0 0 0 0 1
0 0 0 1 1
Karnaugh Map
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0 x = A’ B’ C’ D’ + A’ B’ C’ D +
1 1 0 1 0 A’ B C’ D’ + A’ B C’ D +
A’ B C D’ + A’ B C D +
1 1 1 0 0
A B’ C’ D’ + A B’ C’ D +
1 1 1 1 1
ABCD

Ph.D. Marving O. Aguilar J.

 A B C D x
Example 2.13
0 0 0 0 1
0 0 0 1 1
Karnaugh Map
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
C’D’ C’D CD CD’
0 1 0 1 1
A’B’
0 1 1 0 1
A’B
0 1 1 1 1
AB
1 0 0 0 1
AB’
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0 x = A’ B’ C’ D’ + A’ B’ C’ D +
1 1 0 1 0 A’ B C’ D’ + A’ B C’ D +
A’ B C D’ + A’ B C D +
1 1 1 0 0
A B’ C’ D’ + A B’ C’ D +
1 1 1 1 1
ABCD

Ph.D. Marving O. Aguilar J.

 A B C D x
Example 2.13
0 0 0 0 1
0 0 0 1 1
Karnaugh Map
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
C’D’ C’D CD CD’
0 1 0 1 1
A’B’ 1 1 0 0
0 1 1 0 1
A’B 1 1 1 1
0 1 1 1 1
AB 0 0 1 0
1 0 0 0 1
AB’ 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0 x = A’ B’ C’ D’ + A’ B’ C’ D +
1 1 0 1 0 A’ B C’ D’ + A’ B C’ D +
A’ B C D’ + A’ B C D +
1 1 1 0 0
A B’ C’ D’ + A B’ C’ D +
1 1 1 1 1
ABCD

Ph.D. Marving O. Aguilar J.

 A B C D x
Example 2.13
0 0 0 0 1
0 0 0 1 1
Karnaugh Map
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
C’D’ C’D CD CD’
0 1 0 1 1
A’B’ 1 1 0 0
0 1 1 0 1
A’B 1 1 1 1
0 1 1 1 1
AB 0 0 1 0
1 0 0 0 1
AB’ 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0 x = A’ B’ C’ D’ + A’ B’ C’ D +
1 1 0 1 0 A’ B C’ D’ + A’ B C’ D +
A’ B C D’ + A’ B C D +
1 1 1 0 0
A B’ C’ D’ + A B’ C’ D +
1 1 1 1 1
ABCD

Ph.D. Marving O. Aguilar J.

 A B C D x
Example 2.13
0 0 0 0 1
0 0 0 1 1
Karnaugh Map
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
C’D’ C’D CD CD’
0 1 0 1 1
A’B’ 1 1 0 0
0 1 1 0 1
A’B 1 1 1 1
0 1 1 1 1
AB 0 0 1 0
1 0 0 0 1
AB’ 1 1 0 0
1 0 0 1 1
1 0 1 0 0 x = C’ B’ + A’ B + B C D
1 0 1 1 0
1 1 0 0 0 x = A’ B’ C’ D’ + A’ B’ C’ D +
1 1 0 1 0 A’ B C’ D’ + A’ B C’ D +
A’ B C D’ + A’ B C D +
1 1 1 0 0
A B’ C’ D’ + A B’ C’ D +
1 1 1 1 1
ABCD

Ph.D. Marving O. Aguilar J.

 A B C D x
Example 2.14
0 0 0 0 0
0 0 0 1 0
Karnaugh Map
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1 x = A’ B’ C D + A’ B C’ D +
1 1 0 1 0 A’ B C D’ + A B’ C’ D +
A B’ C D’ + A B C’ D’
1 1 1 0 0
1 1 1 1 0

Ph.D. Marving O. Aguilar J.

 A B C D x
Example 2.14
0 0 0 0 0
0 0 0 1 0
Karnaugh Map
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
C’D’ C’D CD CD’
0 1 0 1 1
A’B’
0 1 1 0 1
A’B
0 1 1 1 0
AB
1 0 0 0 0
AB’
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1 x = A’ B’ C D + A’ B C’ D +
1 1 0 1 0 A’ B C D’ + A B’ C’ D +
A B’ C D’ + A B C’ D’
1 1 1 0 0
1 1 1 1 0

Ph.D. Marving O. Aguilar J.

 A B C D x
Example 2.14
0 0 0 0 0
0 0 0 1 0
Karnaugh Map
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
C’D’ C’D CD CD’
0 1 0 1 1
A’B’ 0 0 1 0
0 1 1 0 1
A’B 0 1 0 1
0 1 1 1 0
AB 1 0 0 0
1 0 0 0 0
AB’ 0 1 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1 x = A’ B’ C D + A’ B C’ D +
1 1 0 1 0 A’ B C D’ + A B’ C’ D +
A B’ C D’ + A B C’ D’
1 1 1 0 0
1 1 1 1 0

Ph.D. Marving O. Aguilar J.

 A B C D x
Example 2.14
0 0 0 0 0
0 0 0 1 0
Karnaugh Map
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
C’D’ C’D CD CD’
0 1 0 1 1
A’B’ 0 0 1 0
0 1 1 0 1
A’B 0 1 0 1
0 1 1 1 0
AB 1 0 0 0
1 0 0 0 0
AB’ 0 1 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1 x = A’ B’ C D + A’ B C’ D +
1 1 0 1 0 A’ B C D’ + A B’ C’ D +
A B’ C D’ + A B C’ D’
1 1 1 0 0
1 1 1 1 0

Ph.D. Marving O. Aguilar J.

 A B C D x
Example 2.14
0 0 0 0 0
0 0 0 1 0
Karnaugh Map
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
C’D’ C’D CD CD’
0 1 0 1 1
A’B’ 0 0 1 0
0 1 1 0 1
A’B 0 1 0 1
0 1 1 1 0
AB 1 0 0 0
1 0 0 0 0
AB’ 0 1 0 1
1 0 0 1 1
1 0 1 0 1 x = A’ B’ C D + A’ B C’ D +
1 0 1 1 0 A’ B C D’ + A B’ C’ D +
1 1 0 0 1 x = A’ B’ C D + A’ B C’ D + A B’ C D’ + A B C’ D’

1 1 0 1 0 A’ B C D’ + A B’ C’ D +
A B’ C D’ + A B C’ D’
1 1 1 0 0
1 1 1 1 0

Ph.D. Marving O. Aguilar J.

 Parity Generator and
Parity Check
Combinational Logic
Logic Circuits

Ph.D. Marving O. Aguilar J.

 Parity

In the circuit shown, a 4-bit group is used as data to be transmitted

and uses an even parity (it can be adapted to use odd parity any
number of bits).

Original
data Parity (P)

Even parity generator To the

Receiver

Original Data: Data to the Receiver:

D3 D2 D1 D0 D3 D2 D1 D0 P
0 0 1 0 0 0 1 0 1
1 1 0 0 1 1 0 0 0
Ph.D. Marving O. Aguilar J.
 Parity

In the circuit shown, a group of 5 bits is used as data to be received,

where 1 of them is the one of even parity. The output is activated at
"1" if there is a 1-bit error in the received data.

Error (E)
Transmitter (1 = Error
0 = no error)

Even parity checker

Transmitter Data: Receiver Data:

D3 D2 D1 D0 P E D3 D2 D1 D0 P E
0 0 1 0 1 0 1 0 1 0 1 1
1 1 0 0 0 0 0 1 0 0 0 1
Ph.D. Marving O. Aguilar J.
 Inhibited Circuits
Combinational Logic
Logic Circuits

Ph.D. Marving O. Aguilar J.

 Activation Gates

ENABLE

Cases 1 and 2
Ph.D. Marving O. Aguilar J.
 Activation Gates

Cases 3 and 4

Ph.D. Marving O. Aguilar J.

 Inhibitory Gates

DISABLE

Cases 1 and 2
Ph.D. Marving O. Aguilar J.
 Inhibitory Gates

Cases 3 and 4
Ph.D. Marving O. Aguilar J.
 Example 2.15
Activation Gates and/or Inhibitory Gates

Design a logic circuit that allows a signal A to pass to the output only
when control inputs B and C are HIGH; otherwise, the output will
continue to be LOW.

Ph.D. Marving O. Aguilar J.

 Example 2.15
Activation Gates and/or Inhibitory Gates

Design a logic circuit that allows a signal A to pass to the output only
when control inputs B and C are HIGH; otherwise, the output will
continue to be LOW.

Ph.D. Marving O. Aguilar J.

 Example 2.16
Activation Gates and/or Inhibitory Gates

Design a logic circuit that allows a signal to pass to the output only
when one, but not both control inputs are HIGH; otherwise, the
output will continue to be HIGH.

Ph.D. Marving O. Aguilar J.

 Example 2.16
Activation Gates and/or Inhibitory Gates

Design a logic circuit that allows a signal to pass to the output only
when one, but not both control inputs are HIGH; otherwise, the
output will continue to be HIGH.

Ph.D. Marving O. Aguilar J.

 Example 2.17
Activation Gates and/or Inhibitory Gates

Design a logic circuit with input signal A, control input B and outputs X
and Y to operate as follows:
• When B = 1, output X will follow input A, and output Y will be
0.
• When B = 0, the output X will be 0, and the output Y will follow
the input A.

Ph.D. Marving O. Aguilar J.

 Example 2.17
Activation Gates and/or Inhibitory Gates

Design a logic circuit with input signal A, control input B and outputs X
and Y to operate as follows:
• When B = 1, output X will follow input A, and output Y will be
0.
• When B = 0, the output X will be 0, and the output Y will follow
the input A.

If
If

If

If

Ph.D. Marving O. Aguilar J.

 Basic Characteristics
of Digital ICs

Combinational Logic
Logic Circuits

Ph.D. Marving O. Aguilar J.

 ➢ Generalities
➢ Sum of Products and Product of Sums
➢ Logic Circuits Simplification
➢ Design
➢ Karnaugh Maps
➢ Parity Generator and Parity Checker
Combinational Logic
Logic Circuits

➢ Inhibited Circuits
➢ Basic Characteristics of Digital ICs
Ph.D. Marving O. Aguilar J.
 Ph.D. Marving Omar Aguilar Justo
Engineering School - Mechatronics Engineering

Combinational Logic
Logic Circuits

Notes extracted from the book: “Sistemas Digitales: Principios y Aplicaciones”,

Ronald D. Tocci, Ed. Pearson Prentice Hall, 10ª Ed., 2007.

February – June 2020