Intel MPX
Intel MPX
SECS003
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Agenda
• Overview
• Intel® Memory Protection Extensions (Intel® MPX)
Examples
• Storing Bounds in Memory
• Enabling Approach
• Summary
• Resources
2
Overview
• New instructions to enable runtime buffer overflow
checks
• Most C/C++ applications should able to use Intel®
Memory Protection Extensions (Intel® MPX) by:
– Recompilation of existing code without source changes
– Interoperate with legacy libraries
– Run Intel MPX enabled binary on legacy systems (no
benefits)
– Enable or disable Intel MPX for each application dynamically
• Working with OS/Tool vendors to facilitate broad use
– Intel MPX instructions are not limited to a specific use
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Overview
• Four new registers to store bounds 128-bit boundary
– Existing register usage not impacted
registers BND0..BND3
• New instructions to check bounds 0xFFFF FFFFF
prior to memory access
…
– Exception on bound violations
• New instructions to load/store
bounds in separate memory region 0x00F3 2250
– CPU manages pointer to bounds Buffer
association in memory
0x00F3 2210
– No changes to data structure layout
• Run-time “opt-in” capability
…
• Intel MPX extensions are NOP
when opted-out or on legacy 0x0000 0000
systems
Upper Bound Lower Bound
• Overview
• Intel® Memory Protection Extensions (Intel® MPX)
Examples
• Storing Bounds in Memory
• Enabling Approach
• Summary & Resources
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Example: strcpy (check write bounds)
// s2 is RDX, and s1 in RCX, bounds for s1 in BND0 by calling
convention
strcpy(char *s1, char *s2) {
while (*s1++ = *s2++) {} New Register
}
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Example: MPX Off or Legacy CPU
// s2 is RDX, and s1 in RCX, bounds for s1 in BND0 by calling convention
strcpy(char *s1, char *s2) {
while (*s1++ = *s2++) {}
}
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Managing Bounds
• Bounds are associated with pointers and not buffers
• Bounds are created at time of allocation
– By compiler (e.g., for buffers on stack)
– Runtime (e.g., malloc): e.g., p = malloc(size)
malloc: … existing malloc code
BNDMK BND0, [p+size-1]
BND RET
OR
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Example: Call to strcpy
MOV RCX, $str1
char str1[100], str2[120];
strcpy(str1, str2);
BNDMK BND0, [RCX+99]
MOV RDX, $str2
…
BND CALL $strcpy
strcpy(char *s1, char *s2) {
BNDCL BND0, [RCX]
while (*s1++ = *s2++) {}
L1: MOVB RAX, [RDX]
}
INC RDX
#BR if s2 was >100 BNDCU BND0, [RCX]
char long MOVB [RCX], AL
…
BND RET
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Example: Legacy Call to MPX Enabled strcpy
Near CALL, RET, JMP/Jcc without BND prefix will INIT all bound reg
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Example: MPX Enabled Call to Legacy strcpy
MOV RCX, $str1
char str1[100], str2[120];
strcpy(str1, str2);
BNDMK BND0, [RCX+99]
MOV RDX, $str2
…
BND CALL $strcpy
strcpy(char *s1, char *s2) {
BNDCL BND0, [RCX]
while (*s1++ = *s2++) {}
L1: MOVB RAX, [RDX]
}
INC RDX
#BR if s2 was >100 BNDCU BND0, [RCX]
char long MOVB [RCX], AL
…
BND RET
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Agenda
• Overview
• Intel® Memory Protection Extensions (Intel® MPX)
Examples
• Storing Bounds in Memory
• Enabling Approach
• Summary & Resources
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Storing Bounds in Memory
Fat Pointers Today Outlying bounds
Compatibility with
Bounds 1 Pointer 2 Pointer 2
Pointer 2 Data Data
layout
Bounds 2
Data
Bounds 1
Bounds 2
Application allocates
memory for storing
bounds
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Storing and Loading Bounds
Address
Ptr to buf 1 translation
Bnds of ptr to buf 1
Ptr to buf 25
Bnds of ptr to buf 25
MOV RAX, [RDX]
BNDLDX RAX, BND0, [RDX]
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Interoperability With Legacy
MPX code Legacy code MPX code
MOV [RDX], RAX … MOV RAX, [RDX]
MOV [RDX], buf2 BNDLDX RAX, BND0, [RDX]
BNDSTX [RDX], RAX, BND0 …
BND0 INIT on
no match
Ptr to buf 1 Ptr to buf 2 Ptr to buf 2
Ptr to buf 25 Ptr to buf 25 Ptr to buf 25
Data Data Data
Bound memory
BND INIT when two copies of pointers are not same helps with
legacy interoperability
RDX points to memory location where pointer is stored
RCX contains pointer value, BND0 contains bounds for pointer
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Interoperability: MPX Code
MPX code – module 1 MPX Code – module 2 MPX code
MOV [RX], RAX … MOV RAX, [RDX]
MOV [RDX], buf2 BNDLDX RAX, BND0, [RDX]
BNDSTX [RDX], RAX, BND0
BNDSTX [RDX], RAX, BND0
BND0 is loaded
Because of match
…
Ptr to buf 1 Ptr to buf 2 Ptr to buf 2
Ptr to buf 25 Ptr to buf 25 Ptr to buf 25
Data Data Data
Bound n
BD: Bound Directory BT: Bound Table
Application Memory
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Proposed MPX ABI Summary
• Caller save bound registers
– Use BNDMOV instruction to save/restore bound registers
• Calling convention extensions
– Bi contains bounds for ith pointer passed in register
– The bounds for pointer passed in memory are passed using
BNDLDX/STX
• Data layout
– No changes
– Use BNDLDX/STX to load/store bounds for pointers
• Proposed Linux* ABI
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Agenda
• Overview
• Intel® Memory Protection Extensions (Intel® MPX)
Examples
• Storing Bounds in Memory
• Enabling Approach
• Summary & Resources
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Enabling Approach
• Start using Intel® Memory Protection Extensions (Intel® MPX)
during development process to find buffer overflow bugs
• If performance of Intel MPX enabled application is acceptable,
release Intel MPX enabled product
• If performance impact is unacceptable
– Consider partial enabling, enable non-performance critical code with
Intel MPX
– Consider performance tuning of performance critical application
code (link to Intel performance optimization tools)
• If performance impact is still unacceptable
– Consider release of product with Intel MPX off by default
– Intel MPX can be turned on in field till fix is release in case of
attacks
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Agenda
• Overview
• Intel® Memory Protection Extensions (Intel® MPX)
Examples
• Storing Bounds in Memory
• Enabling Approach
• Summary & Resources
21
Summary
• New instructions to enable runtime buffer overflow checks
– Prevent most buffer overflows at runtime
– Pin-point location of attempted overflow
– Fewer attacks (virus, worm, root kits, bots)
• Most C/C++ applications should able to use Intel® Memory
Protection Extensions (Intel® MPX) by:
– Recompilation of existing code without source changes
– Interoperate with legacy libraries
– Run Intel MPX enabled binary on legacy systems (no benefits)
– Enable or disable Intel MPX for each application dynamically
• Working with OS/Tool vendors to facilitate broad use
– Intel MPX instructions are not limited to a specific use
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Additional Sources of Information
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Risk Factors
The above statements and any others in this document that refer to plans and expectations for the third quarter, the year and
the future are forward-looking statements that involve a number of risks and uncertainties. Words such as “anticipates,”
“expects,” “intends,” “plans,” “believes,” “seeks,” “estimates,” “may,” “will,” “should” and their variations identify forward-looking
statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking
statements. Many factors could affect Intel’s actual results, and variances from Intel’s current expectations regarding such factors
could cause actual results to differ materially from those expressed in these forward-looking statements. Intel presently considers
the following to be the important factors that could cause actual results to differ materially from the company’s expectations.
Demand could be different from Intel's expectations due to factors including changes in business and economic conditions;
customer acceptance of Intel’s and competitors’ products; supply constraints and other disruptions affecting customers; changes
in customer order patterns including order cancellations; and changes in the level of inventory at customers. Uncertainty in global
economic and financial conditions poses a risk that consumers and businesses may defer purchases in response to negative
financial events, which could negatively affect product demand and other related matters. Intel operates in intensely competitive
industries that are characterized by a high percentage of costs that are fixed or difficult to reduce in the short term and product
demand that is highly variable and difficult to forecast. Revenue and the gross margin percentage are affected by the timing of
Intel product introductions and the demand for and market acceptance of Intel's products; actions taken by Intel's competitors,
including product offerings and introductions, marketing programs and pricing pressures and Intel’s response to such actions; and
Intel’s ability to respond quickly to technological developments and to incorporate new features into its products. The gross
margin percentage could vary significantly from expectations based on capacity utilization; variations in inventory valuation,
including variations related to the timing of qualifying products for sale; changes in revenue levels; segment product mix; the
timing and execution of the manufacturing ramp and associated costs; start-up costs; excess or obsolete inventory; changes in
unit costs; defects or disruptions in the supply of materials or resources; product manufacturing quality/yields; and impairments
of long-lived assets, including manufacturing, assembly/test and intangible assets. Intel's results could be affected by adverse
economic, social, political and physical/infrastructure conditions in countries where Intel, its customers or its suppliers operate,
including military conflict and other security risks, natural disasters, infrastructure disruptions, health concerns and fluctuations in
currency exchange rates. Expenses, particularly certain marketing and compensation expenses, as well as restructuring and asset
impairment charges, vary depending on the level of demand for Intel's products and the level of revenue and profits. Intel’s
results could be affected by the timing of closing of acquisitions and divestitures. Intel's results could be affected by adverse
effects associated with product defects and errata (deviations from published specifications), and by litigation or regulatory
matters involving intellectual property, stockholder, consumer, antitrust, disclosure and other issues, such as the litigation and
regulatory matters described in Intel's SEC reports. An unfavorable ruling could include monetary damages or an injunction
prohibiting Intel from manufacturing or selling one or more products, precluding particular business practices, impacting Intel’s
ability to design its products, or requiring other remedies such as compulsory licensing of intellectual property. A detailed
discussion of these and other factors that could affect Intel’s results is included in Intel’s SEC filings, including the company’s
most recent reports on Form 10-Q, Form 10-K and earnings release.
Rev. 7/17/13
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