課程名稱: 數位邏輯設計

P-1/79 2019/5/9

Textbook: Digital Design, 6th. Edition

M. Morris Mano and Michael D. Ciletti
Prentice-Hall, Inc.

教 師 : 蘇 慶 龍
Instructor : Ching-Lung Su
E-mail: [email protected]
Chapter 5
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Chapter 5
Synchronous Sequential Logic
Outline of Chapter 5
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5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 HDL for Sequential Circuits
5.7 State Reduction and Assignment
5.8 Design Procedure
5.1 Introduction
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5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 HDL for Sequential Circuits
5.7 State Reduction and Assignment
5.8 Design Procedure
5.1 Introduction to Sequential Circuits
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◼ Combinational and Sequential Circuits

Combinational Circuit:
◆ Output only depends on the present
combination of inputs
◆ Specified by a set of Boolean Functions
Logic Circuit
Sequential Circuit:
◆ Output depends on the input and the state of
the storage (past inputs)
◆ Most real digital system
5.2 Sequential Circuits
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5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 HDL for Sequential Circuits
5.7 State Reduction and Assignment
5.8 Design Procedure
5.2 Sequential Circuits
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◼ Block Diagram of Sequential Circuits

The present state and inputs determine
the output and the next state.

Inputs Outputs
Combinational
Circuits Next Memory
State Elements

Present
State
Feedback Path
5.2 Sequential Circuits
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◼ Classifications of Sequential Circuits

Synchronous Sequential Circuit:

o The behavior can be defined form the
knowledge of its signals at discrete instants
Sequential of time.
Circuit
Asynchronous Sequential Circuit:
o The behavior depends on the input signals at
any time instant of time and the order in
which the inputs change.
5.2 Sequential Circuits
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◼ Synchronous Clocked Sequential Circuits

Clocked Sequential
Circuit

Inputs Outputs
Combinational
Circuits
Flip-Flops

Periodic
Clock Pulse
Clock Storing 1 bit information
Generator
5.3 Storage Elements: Latches
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5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 HDL for Sequential Circuits
5.7 State Reduction and Assignment
5.8 Design Procedure
5.3 Storage Elements: Latches
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◼ Flip-Flop
A Flip-flop circuit can maintain a binary state
indefinitely until directed by an input signal to
switch states.
5.3 Storage Elements: Latches
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◼ SR Latch with NOR Gates

Functional Table
Logic Diagram
S R Q Q
R
(reset) Q
1 0 1 0
0 0 1 0 After S=1, R=0
S Q 0 1 0 1
(set) 0 0 0 1 After S=0, R=1
1 1 0 0

R 0 1 R 0 1
(reset) Q (reset) Q

S 1 Q S 0 Q
(set) 0 (set) 0

R 1 0 R 0 0
(reset) Q (reset) Q

S 0 Q S 0 Q
(set) 1 (set) 1
5.3 Storage Elements: Latches
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◼ SR Latch with NAND Gates

Functional Table
Logic Diagram
S R Q Q
S
(set) Q
1 0 0 1
1 1 0 1 After S=1, R=0
R Q 0 1 1 0
(reset) 1 1 1 0 After S=0, R=1
0 0 1 1

S 1 0 S 1 0
(set) Q (set) Q

R 0 Q R 1 Q
(reset) 1 (reset) 1

S 0 1 S 1 1
(set) Q (set) Q

R 1 Q R 1 Q
(reset) 0 (reset) 0
5.3 Storage Elements: Latches
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◼ SR Latch with Control Input

Function Table
Logic Diagram
C S R Next State
S
Q
0 X X No Change
C 1 0 0 No Change
Q 1 0 1 Q=0; Reset
R 1 1 0 Q=1; Set
1 1 1 Indeterminate

No Change No Change
S 1 S 0 1
Q Q
C 0 C 1
Q Q
R 1 R 1
0
Set Reset
S 1 0 1 Q S 0 1
0 Q

C 1 C 1
Q Q
R 1 0 R 0 1
0 1
5.3 Storage Elements: Latches
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◼ D Latch: Elimination the undesirable condition of

the indeterminate state in SR latch
Logic Diagram Function Table
D C D Next State
Q
C 0 X No Change
Q 1 0 Q=0; Reset
1 1 Q=1; Set

No Change Set
D 1 D 1 0 1 Q
Q
C 0 C 1
1 Q 0 Q

0 1
5.3 Storage Elements: Latches
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◼ Graphic Symbols for Latches

SR Latch SR Latch

S S

R R

D Latch

C
5.4 Storage Elements: Flip-Flops
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5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 HDL for Sequential Circuits
5.7 State Reduction and Assignment
5.8 Design Procedure
5.4 Storage Elements: Flip-Flops
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◼ Trigger: The change of the input control signal to

switch the state of a latch or flip-flop
Level Trigger: Latch
Trigger
Edge Trigger: Flip-flop

Positive Level Trigger:

Positive Edge Trigger: Flip-flop or Latch

State Change

Negative Edge Trigger:

5.4 Storage Elements: Flip-Flops
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◼ Problem of Level Trigger:

During the period of level triggers, the feedback
loops cause the unpredictable results.

Inputs Outputs
Combinational Unpredictable Results
Circuits
Flip-Flops

Loops

Clock
Generator
5.4 Storage Elements: Flip-Flops
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◼ Edge-Triggered D Flip-Flop

D X D X D Q
D Latch D Latch
(Master) (Slave)
C C

Clock

Negative Edge Trigger Data Transfer

5.4 Storage Elements: Flip-Flops
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◼ Positive-Edge-Triggered D Flip-Flop
Keeping Data
1 S
Positive Edge Q
0
Trigger Clock 0
0 R Q
1

D
Clock = 0 Clock = 0
1 0
Clock = 1 Clock = 1 1
Set Reset
1 S 0 S
0 Q 1 Q
1 1
Clock 1 Clock 1
1 0 R 1 Q 1 R 0 Q
1 1
1

D 0 1 D 1 0
5.4 Storage Elements: Flip-Flops
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◼ Setup Time and Hold Time for Flip-Flop

Input D must be a
stable data !!

Clock

Input data D
Setup Time

Hold Time
5.4 Storage Elements: Flip-Flops
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◼ Graphic Symbols for D Flip-Flop

D D

C C

Positive-Edge Negative-Edge
Triggered D FF Triggered D FF
5.4 Storage Elements: Flip-Flops
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◼ Characteristic Table of D Flip-Flop

D Q(t+1)

0 0 Reset
1 1 Set
Characteristic Table
5.4 Storage Elements: Flip-Flops
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◼ JK Flip-Flop

J
D Q J
K
C

Clock C Q K

Circuit Diagram Graphic Symbol

J K D(t+1)

0 0 Q(t) No change
D = JQ + K Q 0 1 0 Reset
1 0 1 Set
1 1 Q (t) Complement

Characteristic Table
5.4 Storage Elements: Flip-Flops
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◼ T (toggle) Flip-Flop

T D T J

C K

T FF from D FF T FF from JK FF

T Q(t+1)

D = T + Q = TQ + T Q 0 Q(t) No Change
1 Q (t) Complement
Characteristic Table

Graphic Symbol
5.4 Storage Elements: Flip-Flops
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◼ Characteristic Equations:
The logical properties of a flip-flop as described
in the characteristic table can be expressed also
algebraically with a characteristic equation.

D FF: Q(t+1) = D
JK FF: Q(t+1) = JQ + K Q
T FF: Q(t+1) = T + Q = TQ + T Q
5.4 Storage Elements: Flip-Flops
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◼ Direct Inputs (Asynchronous Inputs)

Circuit Diagram

S Q 1 S 1 0 Q
0
Clock Clock
R Q R 1 Q
0

D D 1
0
Direct Reset
Reset (Clear) 0

Graphic Symbol
Function Table
Data D Q
R C D Q Q

0 X X 0 1
Clock C Q 1 0 0 1
R 1 1 1 0

Reset
5.5 Analysis of Clocked Sequential Circuits
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5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 HDL for Sequential Circuits
5.7 State Reduction and Assignment
5.8 Design Procedure
5.5 Analysis of Clocked Sequential Circuits
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◼ State Equation (Transition Equation):

A state equation (also called transition equation)
specified the next state as a function of the present
state and inputs.
5.5 Analysis of Clocked Sequential Circuits
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◼ Example of Sequential Circuit

x
D A A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) = A (t)x(t)
C A
A(t+1) = Ax + Bx
B(t+1) = A x

D B
y(t) = [A(t)+B(t)]x (t)
Clock C B

y = (A+B)x
y
5.5 Analysis of Clocked Sequential Circuits
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◼ State Table (Transition Table)

Table Consist of 4 sections:

1. Present State
2. Inputs
3. Next State
4. Outputs
5.5 Analysis of Clocked Sequential Circuits
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◼ Example of State Table (Transition Table)

Example State Table
Depend on Circuit

x
D A Present Next
State Input State Output
A B x A B y
C A
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
23 Items 0 1 1 1 1 0
D B
1 0 0 0 0 1
1 0 1 1 0 0
Clock C B 1 1 0 0 0 1
1 1 1 1 0 0

y
5.5 Analysis of Clocked Sequential Circuits
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◼ Example of State Table (Transition Table)

Example Second Form of the

State Table
x Present State Next State Output
D A
x=0 x=1 x=0 x=1
C A AB AB AB y y

00 00 01 0 0
01 00 11 1 0
D B 10 00 10 1 0
11 00 10 1 0
Clock C B

y
5.5 Analysis of Clocked Sequential Circuits
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0/0 1/0

00 0/1 10
Input/Output
0/1
1/0 0/1 1/0
State
01 11
1/0
◼ State Diagram
Present State Next State Output
x=0 x=1 x=0 x=1
AB AB AB y y

00 00 01 0 0
01 00 11 1 0
10 00 10 1 0
11 00 10 1 0
5.5 Analysis of Clocked Sequential Circuits
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◼ Flip-Flop Input Equations

1. The logic diagram of a sequential circuit consists of flip-
flops and gates.
2. The part of combination circuit that generates external
outputs is described algebraically by a set of Boolean
functions called output equations.
3. The part of the circuit that generates the inputs to flip-
flops is described algebraically by a set of Boolean
functions called flip-flop input equations (sometimes
called excitation equations).
4. The designer adopts the convention of using the flip-
flop input symbol to denote the input variable and
subscript to designate the name of the flip-flop outputs.
5.5 Analysis of Clocked Sequential Circuits
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◼ Example of Flip-Flop Input Equations

x
D A

C A

DA = Ax + Bx
DB = A x
D B y = (A+B)x

Clock C B

y
5.5 Analysis of Clocked Sequential Circuits
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◼ Analysis with D Flip-Flops

Circuit Diagram
State Table
x D A Present Next
y
State Inputs State
Clock C A xy A

0 00 0
A(t+1) = A + x + y 0 01 1
0 10 1
State Diagram 0 11 0
01,10 1 00 1
1 01 0
1 10 0
00,11 0 1 00,11 1 11 1

01,10
5.5 Analysis of Clocked Sequential Circuits
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◼ The next-state can be derived by following

procedure
1. Determine the flip-flop equations in terms of the
present state and input variables
2. List the binary values of each input equation
3. Use the corresponding flip-flop characteristic table
to determine the next state values in the state table
5.5 Analysis of Clocked Sequential Circuits
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◼ Analysis with JK Flip-Flops

Sequential Circuit with JK Flip-Flop Flip-Flop Input Equations

J A JA = B
C KA = Bx
x
K JB = x
KB = A x + Ax = A + x
J B
C
K

Clock
5.5 Analysis of Clocked Sequential Circuits
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◼ Analysis with JK Flip-Flops (Continued)

Sequential Circuit with JK Flip-Flop

Present Next Flip-Flop
State Input State Inputs
A B x A B JA KA JB KB

0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0
0 1 1 1 0 1 0 0 1
1 0 0 1 1 2 0 0 1 1
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1
1 1 1 1 1 1 0 0 0

1
5.5 Analysis of Clocked Sequential Circuits
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◼ The next-state can be obtained by evaluating the

state equation from the characteristic equation
1. Determine the flip-flop equations in terms of the
present state and input variables
2. Substitute the input equations into the flip-flop
characteristic equation to obtain the state equation
3. Use the corresponding state equations to determine
the next state values in the state table
5.5 Analysis of Clocked Sequential Circuits
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◼ Analysis with JK Flip-Flops (Continued)

JK Flip-Flop Characteristic Equations Flip-Flop Input Equations

A(t+1) = JA + K A JA = B
B(t+1) = JB + K B KA = Bx

A(t+1) = BA + (Bx) A = A B + AB + Ax JB = x
B(t+1) = x B + (A + x ) B = B x + ABx + A Bx KB = A x + Ax = A + x

1 1

00 0 11
Sequential Circuit with JK Flip-Flop

J A State Diagram 0 0 0
C
x
K

J B 01 10
C 1
K

Clock
1
5.5 Analysis of Clocked Sequential Circuits
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◼ Analysis with T Flip-Flops

Sequential Circuit with T FF Characteristic Equation
x T A Q(t+1) = T + Q = T Q + TQ
y

C R
TA = Bx
TB = x
B y = AB
T

C R A(t+1) = (Bx) A + (Bx)A = AB + Ax + A Bx

B(t+1) = x + B

Clock Reset
5.5 Analysis of Clocked Sequential Circuits
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◼ Analysis with T Flip-Flops (Continued)

State Table State Diagram

Present Next 0 0
State Input State Output
AB x AB y
1
00/0 01/0
00 0 00 0
00 1 01 0
01 0 01 0
1 1
01 1 10 0
10 0 10 0
10 1 11 0 11/1 10/0
11 0 11 1 1
11 1 00 1

0 0
5.5 Analysis of Clocked Sequential Circuits
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◼ Mealy and Moore Models

Model Classification of Sequential Circuits

Mealy Model (Mealy FSM, Mealy Machine):
The output is a function of both the present state
and input.
Moore Model (Moore FSM, Moore Machine):
The output is a function of present state only.
The output are synchronous with the clock.
5.5 Analysis of Clocked Sequential Circuits
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Mealy Machine

Inputs Next State Output Outputs

Combinational Logic State Register Combinational Logic (Mealy-type)

Clock

Moore Machine
Inputs Next State Output Outputs
Combinational Logic State Register Combinational Logic (Mealy-type)

Clock
5.5 Analysis of Clocked Sequential Circuits
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◼ Example of Mealy Model

x
D A

C A

D B

Clock C B

y
5.5 Analysis of Clocked Sequential Circuits
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Sequential Circuit with JK Flip-Flop

J A
C
x
K

J B
C
K

◼ Example of Clock

Moore Model Sequential Circuit with T FF Characteristic Equation

x T A Q(t+1) = T + Q = T Q + TQ
y

C R
TA = Bx
TB = x
B y = AB
T

C R A(t+1) = (Bx) A + (Bx)A = AB + Ax + A Bx

B(t+1) = x + B

Clock Reset
5.6 HDL for Sequential Circuits
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5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 HDL for Sequential Circuits
5.7 State Reduction and Assignment
5.8 Design Procedure
5.6 HDL for Sequential Circuits
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◼ Referred to TA
5.7 State Reduction and Assignment
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5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 HDL for Sequential Circuits
5.7 State Reduction and Assignment
5.8 Design Procedure
5.7 State Reduction and Assignment
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◼ State Reduction of Sequential Circuits

1. State Reduction: Lower the requirement of flip-flop
2. m flip-flop produce 2m states
3. The characteristic of a sequential circuit: input-
output sequences (not the internal circuits)
5.7 State Reduction and Assignment
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◼ Example of State Reduction

0/0
State Diagram Initial state a, I/O sequence:
State a a b c d e f f g f g a
a Input 0 1 0 1 0 1 1 0 1 0 0
Output 0 0 0 0 0 1 1 0 1 0 0
1/0 0/0 0/0

0/0 0/0
b c

1/0 1/0

g d 0/0 e
1/1
1/1
1/1
0/0 f

1/1
5.7 State Reduction and Assignment
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◼ Example of State Reduction (Continued)

State Table
Next State Output
Present State x=0 x=1 x=0 x=1

a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1 Equivalent State
f g f 0 1
g a f 0 1 Removed State
5.7 State Reduction and Assignment
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◼ Example of State Reduction (Continued)

State Table
Next State Output
Present State x=0 x=1 x=0 x=1

a a b 0 0
b c d 0 0 g replaced by e
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
5.7 State Reduction and Assignment
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◼ Example of State Reduction (Continued)

State Table
Next State Output
Present State x=0 x=1 x=0 x=1

a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1 Equivalent State
e a f 0 1
f e f 0 1 Removed State
5.7 State Reduction and Assignment
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◼ Example of State Reduction (Continued)

State Table
Next State Output
Present State x=0 x=1 x=0 x=1

a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1 f replaced by d
e a f 0 1
5.7 State Reduction and Assignment
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◼ Example of State Reduction (Continued)

State Table
Next State Output
Present State x=0 x=1 x=0 x=1

a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
5.7 State Reduction and Assignment
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◼ Example of State Reduction (Continued)

State Diagram Initial state a, I/O sequence:
State a a b c d e d d e d e a
0/0 Input 0 1 0 1 0 1 1 0 1 0 0
Output 0 0 0 0 0 1 1 0 1 0 0

a
0/0 1/0 0/0

0/0
e b c

1/1 1/0 1/0

0/0
d

1/1
5.7 State Reduction and Assignment
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◼ State Assignment
State Assignment 1 Assignment 2 Assignment 3
Binary Gray Code One-hot

Possible Binary State a 000 000 00001

Assignments b 001 001 00010
c 010 011 00100
d 011 010 01000
e 100 110 10000

Next State Output

Present State x=0 x=1 x=0 x=1

Reduced State Table with 000 000 001 0 0

Binary Assignment 1 001 010 011 0 0
010 000 011 0 0
011 100 011 0 1
100 000 011 0 1
5.8 Design Procedure
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5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip-Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 HDL for Sequential Circuits
5.7 State Reduction and Assignment
5.8 Design Procedure
5.8 Design Procedure
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◼ Design Procedure for Synchronous Sequential Circuits

1. Derive a state diagram
2. Reduce the number of states if necessary
3. Assign binary values to the state
4. Obtain the binary-coded state table
5. Choose the type of flip-flops to be used
6. Derive the simplified flip-flop input equations and
output equations
7. Draw the logic diagram
5.8 Design Procedure
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◼ Design Example: Problem Description

Design a circuit that detects three or more
consecutive 1’s in a string of bits coming through an
input line.
0
0

1
S0/0 S1/0

0 0 1

S3/1 S2/0
1

1
5.8 Design Procedure
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◼ Synthesis Using D Flip-Flops

1. Design by EDA Tools: Transfer the problem
description into the synthesizable HDL Language
and employ the synthesis tool to generate the
circuit netlist (Reference to 5.6).
2. Design by hand: Next transparency …
5.8 Design Procedure
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◼ Assign Binary Code to the States

S0  00 (AB)
S1  01 (AB)
S2  10 (AB)
S3  11 (AB)
5.8 Design Procedure
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◼ List State Table with D FFs

State Table
Present Next
State Input State Output
AB x AB y

m0 00 0 00 0
m1 00 1 01 0
m2 01 0 00 0
m3 01 1 10 0
m4 10 0 00 0
m5 10 1 11 0
m6 11 0 00 1
m7 11 1 11 1
5.8 Design Procedure
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◼ Find the Next State and Output Equations

A(t+1) = DA (A,B,x) =  (3,5,7)

B(t+1) = DB (A,B,x) =  (1,5,7)
y = (A,B,x) =  (6,7)

DA = Ax + Bx
DB = Ax + B x
y = AB
5.8 Design Procedure
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◼ Logic Simplification
DA DB
Bx B=1 Bx B=1
A 00 01 11 10 A 00 01 11 10
0 1 0 1

A=1 1 1 1 A=1 1 1 1

x=1 x=1
DA = Ax + Bx DB = Ax + B x

y
Bx B=1
A 00 01 11 10
0

A=1 1 1 1

x=1
y = AB
5.8 Design Procedure
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◼ Draw the Logic Diagram of Sequential Circuits

Ax
D A
Bx
x
C

D B
Bx

Clock C B

y
5.8 Design Procedure
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◼ Excitation Tables
A table lists the required inputs for a given change of
state. Q(t)  Q(t+1)

JK Flip-Flop
J K Q(t+1) Q(t) Q(t+1) J K

0 0 Q(t) No change 0 0 0 x
0 x
0 1 0 Reset 0 1 1 x
1 0 1 Set 1 0 x 1
1 1 Q (t) Complement 1 1 x 0

Characteristic Table Excitation Table

5.8 Design Procedure
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◼ Excitation Tables (Continued)

T Flip-Flop
Characteristic Table Excitation Table
T Q(t+1) Q(t) Q(t+1) T

0 Q(t) No Change 0 0 0
1 Q (t) Complement 0 1 1
1 0 1
1 1 0
5.8 Design Procedure
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◼ Synthesis Using JK Flip-Flops

State Table
Present Next Flip-Flop
State Input State Input
AB x AB JA KA JB KB

00 0 00 0 x 0 x
00 1 01 0 x 1 x
01 0 10 1 x x 1
01 1 01 0 x x 0
10 0 10 x 0 0 x
10 1 11 x 0 1 x
11 0 11 x 0 x 0
11 1 00 x 1 x 1
5.8 Design Procedure
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◼ K-Map Logic Simplification

JA = Bx KA = Bx
Bx B=1 Bx B=1
A 00 01 11 10 A 00 01 11 10
0 1 0 x x x x

A=1 1 x x x x A=1 1 1

x=1 x=1
JB = x KB = (A + x)
Bx B=1 Bx B=1
A 00 01 11 10 A 00 01 11 10
0 1 x x 0 x x 1

A=1 1 1 x x A=1 1 x x 1

x=1 x=1
5.8 Design Procedure
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◼ Draw the Sequential Circuits with JK FFs

x Bx J A

C
Bx K A

x J B

K B
(A + x)
Clock
5.8 Design Procedure
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◼ Synthesis Using T Flip-Flops

Design Example: 3-bit Binary Counter Using T FFs

1. N-bit binary counter consists of n flip-flops
2. N-bit binary counter can count 0 to 2n-1
3. 3-bit counter 0 to 7
4. 3-bit counter internal states 000 to 111
5.8 Design Procedure
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◼ State Diagram and State Table of 3-bit Binary Counter

State Diagram State Table

Present State Next State Flip-Flop Inputs

000
A2 A1 A0 A2 A1 A0 TA2 TA1 TA0
001 111
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
010 110
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
011 101
1 0 1 1 1 0 0 1 1
100
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

Refer to T-FF Excitation Table

5.8 Design Procedure
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◼ K-Map Logic Simplification for 3-bit Binary Counter

TA2 = A1A0 TA1 = A0
A0A1 A1 A0A1 A1
A2 00 01 11 10 A2 00 01 11 10
0 1 0 1 1

A2=1 1 1 A2=1 1 1 1

A0 A0
TA0 = 1
A0A1 A1
A2 00 01 11 10
0 1 1 1 1

A2=1 1 1 1 1 1

A0
5.8 Design Procedure
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◼ Draw the 3-bit Binary Counter Circuits with T FFs

A2 A1 A0

C T C T C T

Clock