0

Spartan-3A FPGA Family:

Data Sheet
DS529 December 18, 2018 0 0 Product Specification

Module 1: Module 3:
Introduction and Ordering Information DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 DS529 (v2.1) December 18, 2018
• Introduction • DC Electrical Characteristics
• Features • Absolute Maximum Ratings
• Architectural and Configuration Overview • Supply Voltage Specifications
• Recommended Operating Conditions
• General I/O Capabilities
• Switching Characteristics
• Production Status
• I/O Timing
• Supported Packages and Package Marking
• Configurable Logic Block (CLB) Timing
• Ordering Information • Multiplier Timing
• Block RAM Timing
Module 2: • Digital Clock Manager (DCM) Timing
Spartan-3A FPGA Family: Functional • Suspend Mode Timing
Description • Device DNA Timing
DS529 (v2.1) December 18, 2018 • Configuration and JTAG Timing
The functionality of the Spartan®-3A FPGA family is Module 4:
described in the following documents. Pinout Descriptions
• UG331: Spartan-3 Generation FPGA User Guide DS529 (v2.1) December 18, 2018
• Clocking Resources
• Digital Clock Managers (DCMs) • Pin Descriptions
• Block RAM • Package Overview
• Configurable Logic Blocks (CLBs) • Pinout Tables
- Distributed RAM • Footprint Diagrams
- SRL16 Shift Registers
- Carry and Arithmetic Logic
• I/O Resources For more information on the Spartan-3A FPGA family, go to
• Embedded Multiplier Blocks www.xilinx.com/spartan3a
• Programmable Interconnect
• ISE® Design Tools and IP Cores
• Embedded Processing and Control Solutions Spartan-3A FPGA Status
• Pin Types and Package Overview
• Package Drawings XC3S50A Production
• Powering FPGAs
• Power Management XC3S200A Production
• UG332: Spartan-3 Generation Configuration User Guide XC3S400A Production
• Configuration Overview
• Configuration Pins and Behavior XC3S700A Production
• Bitstream Sizes
• Detailed Descriptions by Mode XC3S1400A Production
- Master Serial Mode using Platform Flash PROM
- Master SPI Mode using Commodity Serial Flash
- Master BPI Mode using Commodity Parallel Flash
- Slave Parallel (SelectMAP) using a Processor
- Slave Serial using a Processor
- JTAG Mode
• ISE iMPACT Programming Examples
• MultiBoot Reconfiguration
• Design Authentication using Device DNA
• UG334: Spartan-3A/3AN FPGA Starter Kit User Guide

© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.

DS529 December 18, 2018 www.xilinx.com 1

Product Specification
Spartan-3A FPGA Family: Data Sheet

2 www.xilinx.com DS529 December 18, 2018

Product Specification
 8
Spartan-3A FPGA Family:
Introduction and Ordering Information
DS529 (v2.1) December 18, 2018 Product Specification

Introduction
The Spartan®-3A family of Field-Programmable Gate • 640+ Mb/s data transfer rate per differential I/O
Arrays (FPGAs) solves the design challenges in most • LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O
with integrated differential termination resistors
high-volume, cost-sensitive, I/O-intensive electronic • Enhanced Double Data Rate (DDR) support
applications. The five-member family offers densities ranging • DDR/DDR2 SDRAM support up to 400 Mb/s
from 50,000 to 1.4 million system gates, as shown in Table 1. • Fully compliant 32-/64-bit, 33/66 MHz PCI® technology
support
The Spartan-3A FPGAs are part of the Extended • Abundant, flexible logic resources
Spartan-3A family, which also include the non-volatile • Densities up to 25,344 logic cells, including optional shift
Spartan-3AN and the higher density Spartan-3A DSP register or distributed RAM support
FPGAs. The Spartan-3A family builds on the success of the • Efficient wide multiplexers, wide logic
earlier Spartan-3E and Spartan-3 FPGA families. New • Fast look-ahead carry logic
• Enhanced 18 x 18 multipliers with optional pipeline
features improve system performance and reduce the cost
• IEEE 1149.1/1532 JTAG programming/debug port
of configuration. These Spartan-3A family enhancements, • Hierarchical SelectRAM™ memory architecture
combined with proven 90 nm process technology, deliver • Up to 576 Kbits of fast block RAM with byte write enables
more functionality and bandwidth per dollar than ever before, for processor applications
setting the new standard in the programmable logic industry. • Up to 176 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
Because of their exceptionally low cost, Spartan-3A FPGAs
• Clock skew elimination (delay locked loop)
are ideally suited to a wide range of consumer electronics • Frequency synthesis, multiplication, division
applications, including broadband access, home networking, • High-resolution phase shifting
display/projection, and digital television equipment. • Wide frequency range (5 MHz to over 320 MHz)
The Spartan-3A family is a superior alternative to mask • Eight low-skew global clock networks, eight additional
clocks per half device, plus abundant low-skew routing
programmed ASICs. FPGAs avoid the high initial cost,
• Configuration interface to industry-standard PROMs
lengthy development cycles, and the inherent inflexibility of
• Low-cost, space-saving SPI serial Flash PROM
conventional ASICs, and permit field design upgrades. • x8 or x8/x16 BPI parallel NOR Flash PROM
• Low-cost Xilinx® Platform Flash with JTAG
Features • Unique Device DNA identifier for design authentication
• Very low cost, high-performance logic solution for • Load multiple bitstreams under FPGA control
high-volume, cost-conscious applications • Post-configuration CRC checking
• Dual-range VCCAUX supply simplifies 3.3V-only design • Complete Xilinx ISE® and WebPACK™ development
• Suspend, Hibernate modes reduce system power system software support plus Spartan-3A Starter Kit
• Multi-voltage, multi-standard SelectIO™ interface pins • MicroBlaze™ and PicoBlaze embedded processors
• Up to 502 I/O pins or 227 differential signal pairs • Low-cost QFP and BGA packaging, Pb-free options
• LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O • Common footprints support easy density migration
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling • Compatible with select Spartan-3AN nonvolatile FPGAs
• Selectable output drive, up to 24 mA per pin • Compatible with higher density Spartan-3A DSP FPGAs
• QUIETIO standard reduces I/O switching noise • XA Automotive version available
• Full 3.3V ± 10% compatibility and hot swap compliance
Table 1: Summary of Spartan-3A FPGA Attributes
CLB Array
(One CLB = Four Slices) Distributed Block Maximum
System Equivalent RAM bits(1) RAM Dedicated Maximum Differential
Device Gates Logic Cells Rows Columns CLBs Slices bits(1) Multipliers DCMs User I/O I/O Pairs
XC3S50A 50K 1,584 16 12 176 704 11K 54K 3 2 144 64
XC3S200A 200K 4,032 32 16 448 1,792 28K 288K 16 4 248 112
XC3S400A 400K 8,064 40 24 896 3,584 56K 360K 20 4 311 142
XC3S700A 700K 13,248 48 32 1,472 5,888 92K 360K 20 8 372 165
XC3S1400A 1400K 25,344 72 40 2,816 11,264 176K 576K 32 8 502 227
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.

© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.

DS529 (v2.1) December 18, 2018 www.xilinx.com 3

Introduction and Ordering Information

Architectural Overview
The Spartan-3A family architecture consists of five • Digital Clock Manager (DCM) Blocks provide
fundamental programmable functional elements: self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
• Configurable Logic Blocks (CLBs) contain flexible signals.
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs These elements are organized as shown in Figure 1. A dual
perform a wide variety of logical functions as well as ring of staggered IOBs surrounds a regular array of CLBs.
store data. Each device has two columns of block RAM except for the
• Input/Output Blocks (IOBs) control the flow of data XC3S50A, which has one column. Each RAM column
between the I/O pins and the internal logic of the consists of several 18-Kbit RAM blocks. Each block RAM is
device. IOBs support bidirectional data flow plus 3-state associated with a dedicated multiplier. The DCMs are
operation. Supports a variety of signal standards, positioned in the center with two at the top and two at the
including several high-performance differential bottom of the device. The XC3S50A has DCMs only at the
standards. Double Data-Rate (DDR) registers are top, while the XC3S700A and XC3S1400A add two DCMs in
included.
the middle of the two columns of block RAM and multipliers.
• Block RAM provides data storage in the form of 18-Kbit
dual-port blocks. The Spartan-3A family features a rich network of routing that
• Multiplier Blocks accept two 18-bit binary numbers as interconnect all five functional elements, transmitting signals
inputs and calculate the product. among them. Each functional element has an associated
switch matrix that permits multiple connections to the
routing.

IOBs

CLB

Block RAM

Multiplier
DCM

IOBs
OBs
DCM
Block RAM / Multiplier

CLBs
IOBs

IOBs

DCM

IOBs
DS312-1_01_032606

Notes:
1. The XC3S700A and XC3S1400A have two additional DCMs on both the left and right sides as indicated by the
dashed lines. The XC3S50A has only two DCMs at the top and only one Block RAM/Multiplier column.
Figure 1: Spartan-3A FPGA Architecture

4 www.xilinx.com DS529 (v2.1) December 18, 2018

 Introduction and Ordering Information

Configuration I/O Capabilities

Spartan-3A FPGAs are programmed by loading The Spartan-3A FPGA SelectIO interface supports many
configuration data into robust, reprogrammable, static popular single-ended and differential standards. Table 2
CMOS configuration latches (CCLs) that collectively control shows the number of user I/Os as well as the number of
all functional elements and routing resources. The FPGA’s differential I/O pairs available for each device/package
configuration data is stored externally in a PROM or some combination. Some of the user I/Os are unidirectional
other non-volatile medium, either on or off the board. After input-only pins as indicated in Table 2.
applying power, the configuration data is written to the
Spartan-3A FPGAs support the following single-ended
FPGA using any of seven different modes:
standards:
• Master Serial from a Xilinx Platform Flash PROM
• 3.3V low-voltage TTL (LVTTL)
• Serial Peripheral Interface (SPI) from an
• Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
industry-standard SPI serial Flash
1.5V, or 1.2V
• Byte Peripheral Interface (BPI) Up from an
• 3.3V PCI at 33 MHz or 66 MHz
industry-standard x8 or x8/x16 parallel NOR Flash
• HSTL I, II, and III at 1.5V and 1.8V, commonly used in
• Slave Serial, typically downloaded from a processor
memory applications
• Slave Parallel, typically downloaded from a processor
• SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
• Boundary Scan (JTAG), typically downloaded from a for memory applications
processor or system tester
Spartan-3A FPGAs support the following differential
Furthermore, Spartan-3A FPGAs support MultiBoot
standards:
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single SPI serial Flash or a BPI • LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
parallel NOR Flash. The FPGA application controls which 3.3V
configuration to load next and when to load it. • Bus LVDS I/O at 2.5V
• TMDS I/O at 3.3V
Additionally, each Spartan-3A FPGA contains a unique,
• Differential HSTL and SSTL I/O
factory-programmed Device DNA identifier useful for
• LVPECL inputs at 2.5V or 3.3V
tracking purposes, anti-cloning designs, or IP protection.
Table 2: Available User I/Os and Differential (Diff) I/O Pairs

Package VQ100 TQ144 FT256 FG320 FG400 FG484 FG676

VQG100 TQG144 FTG256 FGG320 FGG400 FGG484 FGG676
Body Size 14 x 14(2) 20 x 20(2) 17 x 17 19 x 19 21 x 21 23 x 23 27 x 27
(mm)
Device User Diff User Diff User Diff User Diff User Diff User Diff User Diff
68 60 108 50 144 64
XC3S50A - - - - - - - -
(13) (24) (7) (24) (32) (32)
68 60 195 90 248 112
XC3S200A - - - - - - - -
(13) (24) (35) (50) (56) (64)
195 90 251 112 311 142
XC3S400A - - - - - - - -
(35) (50) (59) (64) (63) (78)

XC3S700A 161 74 311 142 372 165

- - - - - - - -
(13) (36) (63) (78) (84) (93)
161 74 375 165 502 227
XC3S1400A - - - - - - - -
(13) (36) (87) (93) (94) (131)

Notes:
1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
2. The footprints for the VQ/TQ packages are larger than the package body. See the Package Drawings for details.

DS529 (v2.1) December 18, 2018 www.xilinx.com 5

Introduction and Ordering Information

Production Status
Table 3 indicates the production status of each Spartan-3A a production configuration bitstream. Later versions are also
FPGA by temperature range and speed grade. The table supported.
also lists the earliest speed file version required for creating

Table 3: Spartan-3A FPGA Production Status (Production Speed File)

Temperature Range Commercial (C) Industrial
Speed Grade Standard (–4) High-Performance (–5) Standard (–4)
Production Production Production
XC3S50A (v1.35) (v1.35) (v1.35)
Production Production Production
XC3S200A
Part Number

(v1.35) (v1.35) (v1.35)

Production Production Production
XC3S400A (v1.36) (v1.36) (v1.36)
Production Production Production
XC3S700A (v1.34) (v1.35) (v1.34)
Production Production Production
XC3S1400A (v1.34) (v1.35) (v1.34)

Package Marking
Figure 2 provides a top marking example for Spartan-3A The “5C” and “4I” Speed Grade/Temperature Range part
FPGAs in the quad-flat packages. Figure 3 shows the top combinations may be dual marked as “5C/4I”. Devices with
marking for Spartan-3A FPGAs in BGA packages. The a single mark are only guaranteed for the marked speed
markings for the BGA packages are nearly identical to those grade and temperature range.
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator.

Mask Revision Code

R
Fabrication Code

SPARTAN
R

Process Technology
TM
Device Type XC3S50A
Package TQ144AGQ0625 Date Code
D1234567A
Speed Grade 4C Lot Code
Temperature Range

Pin P1 DS529-1_03_080406

Figure 2: Spartan-3A QFP Package Marking Example

Mask Revision Code

BGA Ball A1 R

Fabrication Code
SPARTAN
R

Process Code
Device Type XC3S50ATM
Package FT256 AGQ0625 Date Code
D1234567A
4C Lot Code
Speed Grade
Temperature Range
DS529-1_02_021206

Figure 3: Spartan-3A BGA Package Marking Example

6 www.xilinx.com DS529 (v2.1) December 18, 2018

 Introduction and Ordering Information

Ordering Information
Spartan-3A FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a ‘G’ character in the ordering code.

Example: XC3S50A -4 FT 256 C

Device Type Temperature Range

Speed Grade

Package Type/Number of Pins

DS529-1_05_011309

Device Speed Grade Package Type / Number of Pins(1) Temperature Range ( TJ )

XC3S50A –4 Standard Performance VQ100/ 100-pin Very Thin Quad Flat Pack (VQFP) C Commercial (0°C to 85°C)
VQG100
XC3S200A –5 High Performance TQ144/ 144-pin Thin Quad Flat Pack (TQFP) I Industrial (–40°C to 100°C)
(Commercial only) TQG144
XC3S400A FT256/ 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
FTG256
XC3S700A FG320/ 320-ball Fine-Pitch Ball Grid Array (FBGA)
FGG320
XC3S1400A FG400/ 400-ball Fine-Pitch Ball Grid Array (FBGA)
FGG400
FG484/ 484-ball Fine-Pitch Ball Grid Array (FBGA)
FGG484
FG676 676-ball Fine-Pitch Ball Grid Array (FBGA)
FGG676

Notes:
1. See Table 2 for specific device/package combinations.
2. See DS681 for the XA Automotive Spartan-3A FPGAs.

Revision History
The following table shows the revision history for this document.

Date Version Revision

12/05/06 1.0 Initial release.
02/02/07 1.1 Promoted to Preliminary status. Updated maximum differential I/O count for XC3S50A in Table 1.
Updated differential input-only pin counts in Table 2.
03/16/07 1.2 Minor formatting updates.
04/23/07 1.3 Added "Production Status" section.
05/08/07 1.4 Updated XC3S400A to Production.
07/10/07 1.4.1 Minor updates.
04/15/08 1.6 Added VQ100 for XC3S50A and XC3S200A and extended FT256 to XC3S700A and XC3S1400A
Added reference to SCD 4103 for 750 Mbps performance.
05/28/08 1.7 Added reference to XA Automotive version.
03/06/09 1.8 Simplified Ordering Information. Added references to Extended Spartan-3A Family.
Removed reference to SCD 4103.
08/19/10 2.0 Updated Table 2 to clarify TQ/VQ size.
12/18/2018 2.1 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).

DS529 (v2.1) December 18, 2018 www.xilinx.com 7

Introduction and Ordering Information

8 www.xilinx.com DS529 (v2.1) December 18, 2018

 10
Spartan-3A FPGA Family:
Functional Description
DS529 (v2.1) December 18, 2018 0 Product Specification

Spartan-3A FPGA Design Documentation

The functionality of the Spartan®-3A FPGA Family is • Detailed Descriptions by Mode
described in the following documents. The topics covered in - Master Serial Mode using Xilinx® Platform
each guide is listed below. Flash PROM
• DS706: Extended Spartan-3A Family Overview - Master SPI Mode using Commodity SPI Serial
www.xilinx.com/support/documentation/ Flash PROM
data_sheets/ds706.pdf
- Master BPI Mode using Commodity Parallel
• UG331: Spartan-3 Generation FPGA User Guide NOR Flash PROM
www.xilinx.com/support/documentation/
- Slave Parallel (SelectMAP) using a Processor
user_guides/ug331.pdf
- Slave Serial using a Processor
• Clocking Resources
- JTAG Mode
• Digital Clock Managers (DCMs)
• ISE iMPACT Programming Examples
• Block RAM
• MultiBoot Reconfiguration
• Configurable Logic Blocks (CLBs)
• Design Authentication using Device DNA
- Distributed RAM
- SRL16 Shift Registers For application examples, see the Spartan-3A FPGA
application notes.
- Carry and Arithmetic Logic
• Spartan-3A FPGA Application Notes
• I/O Resources
www.xilinx.com/support/documentation/
• Embedded Multiplier Blocks spartan-3a_application_notes.htm
• Programmable Interconnect For specific hardware examples, please see the Spartan-3A
• ISE® Software Design Tools FPGA Starter Kit board web page, which has links to
• IP Cores various design examples and the user guide.

• Embedded Processing and Control Solutions • Spartan-3A/3AN FPGA Starter Kit Board Page
www.xilinx.com/s3astarter
• Pin Types and Package Overview
• UG334: Spartan-3A/3AN FPGA Starter Kit User
• Package Drawings
Guide
• Powering FPGAs www.xilinx.com/support/documentation/
• Power Management boards_and_kits/ug334.pdf
• UG332: Spartan-3 Generation Configuration User For information on the XA Automotive version of the
Guide Spartan-3A family, see the following data sheet.
www.xilinx.com/support/documentation/
• XA Spartan-3A Automotive FPGA Family Data Sheet
user_guides/ug332.pdf
www.xilinx.com/support/documentation/data_sheets/
• Configuration Overview ds681.pdf
- Configuration Pins and Behavior Create a Xilinx user account and sign up to receive
- Bitstream Sizes automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
• Sign Up for Alerts
www.xilinx.com/support/answers/18683.htm

© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.

DS529 (v2.1) December 18, 2018 www.xilinx.com 9

Spartan-3A FPGA Family: Functional Description

Related Product Families

The Spartan-3AN nonvolatile FPGA family is architecturally The compatible Spartan-3A DSP FPGA family replaces the
identical to the Spartan-3A FPGA family, except that it has 18-bit multiplier with the DSP48A block, while also
in-system flash memory and is offered in select increasing the block RAM capability and quantity. The two
pin-compatible package options. members of the Spartan-3A DSP FPGA family extend the
Spartan-3A density range up to 37,440 and 53,712 logic
• DS557: Spartan-3AN Family Data Sheet
cells.
www.xilinx.com/support/documentation/
data_sheets/ds557.pdf • DS610: Spartan-3A DSP FPGA Family Data Sheet
www.xilinx.com/support/documentation/
data_sheets/ds610.pdf
• UG431: XtremeDSP DSP48A for Spartan-3A DSP
FPGAs
www.xilinx.com/support/documentation/
user_guides/ug431.pdf

Revision History
The following table shows the revision history for this document.

Date Version Revision

12/05/06 1.0 Initial release.
02/02/07 1.1 Promoted to Preliminary status.
03/16/07 1.2 Added cross-reference to nonvolatile Spartan-3AN FPGA family.
04/23/07 1.3 Added cross-reference to compatible Spartan-3A DSP family.
07/10/07 1.4 Updated Starter Kit reference to new UG334.
04/15/08 1.6 Updated trademarks.
05/28/08 1.7 Added reference to XA Automotive version.
03/06/09 1.8 Added link to DS706 on Extended Spartan-3A family.
08/19/10 2.0 Updated link to sign up for Alerts.
12/18/18 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).

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 64
Spartan-3A FPGA Family:
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018 0 Product Specification

DC Electrical Characteristics
In this section, specifications may be designated as All parameter limits are representative of worst-case supply
Advance, Preliminary, or Production. These terms are voltage and junction temperature conditions. Unless
defined as follows: otherwise noted, the published parameter values apply
to all Spartan®-3A devices. AC and DC characteristics
Advance: Initial estimates are based on simulation, early
are specified using the same numbers for both
characterization, and/or extrapolation from the
commercial and industrial grades.
characteristics of other families. Values are subject to
change. Use as estimates, not for production.
Absolute Maximum Ratings
Preliminary: Based on characterization. Further changes
are not expected. Stresses beyond those listed under Table 4: Absolute
Maximum Ratings may cause permanent damage to the
Production: These specifications are approved once the device. These are stress ratings only; functional operation
silicon has been characterized over numerous production of the device at these or any other conditions beyond those
lots. Parameter values are considered stable with no future listed under the Recommended Operating Conditions is not
changes expected. implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.

Table 4: Absolute Maximum Ratings

Symbol Description Conditions Min Max Units
VCCINT Internal supply voltage –0.5 1.32 V
VCCAUX Auxiliary supply voltage –0.5 3.75 V
VCCO Output driver supply voltage –0.5 3.75 V
VREF Input reference voltage –0.5 VCCO + 0.5 V
Voltage applied to all User I/O pins and Driver in a high-impedance state –0.95 4.6 V
VIN dual-purpose pins
Voltage applied to all Dedicated pins –0.5 4.6 V
IIK Input clamp current per I/O pin –0.5V < VIN < (VCCO + 0.5V) (1) – ±100 mA
Human body model – ±2000 V
VESD Electrostatic Discharge Voltage Charged device model – ±500 V
Machine model – ±200 V
TJ Junction temperature – 125 °C
TSTG Storage temperature –65 150 °C

Notes:
1. Upper clamp applies only when using PCI IOSTANDARDs.
2. For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow
Guidelines for Pb-Free Packages.

© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.

DS529 (v2.1) December 18, 2018 www.xilinx.com 11

DC and Switching Characteristics

Power Supply Specifications

Table 5: Supply Voltage Thresholds for Power-On Reset
Symbol Description Min Max Units
VCCINTT Threshold for the VCCINT supply 0.4 1.0 V
VCCAUXT Threshold for the VCCAUX supply 1.0 2.0 V
VCCO2T Threshold for the VCCO Bank 2 supply 1.0 2.0 V

Notes:
1. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. Apply VCCINT last for lowest overall power consumption (see UG331 chapter “Powering Spartan-3 Generation FPGAs” for more
information).
2. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.

Table 6: Supply Voltage Ramp Rate

Symbol Description Min Max Units
VCCINTR Ramp rate from GND to valid VCCINT supply level 0.2 100 ms
VCCAUXR Ramp rate from GND to valid VCCAUX supply level 0.2 100 ms
VCCO2R Ramp rate from GND to valid VCCO Bank 2 supply level 0.2 100 ms

Notes:
1. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. Apply VCCINT last for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for more
information).
2. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.

Table 7: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM
Data
Symbol Description Min Units
VDRINT VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data 1.0 V
VDRAUX VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data 2.0 V

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 DC and Switching Characteristics

General Recommended Operating Conditions

Table 8: General Recommended Operating Conditions
Symbol Description Min Nominal Max Units
Commercial 0 – 85 °C
TJ Junction temperature
Industrial –40 – 100 °C
VCCINT Internal supply voltage 1.14 1.20 1.26 V
VCCO (1) Output driver supply voltage 1.10 – 3.60 V
VCCAUX = 2.5 2.25 2.50 2.75 V
VCCAUX Auxiliary supply voltage(2)
VCCAUX = 3.3 3.00 3.30 3.60 V
PCI IOSTANDARD –0.5 – VCCO+0.5 V
VIN Input voltage(3) All other IP or IO_# –0.5 – 4.10 V
IOSTANDARDs IO_Lxxy_# (4) –0.5 – 4.10 V
TIN Input signal transition time(5) – – 500 ns

Notes:
1. This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 11 lists the recommended VCCO
range specific to each of the single-ended I/O standards, and Table 13 lists that specific to the differential standards.
2. Define VCCAUX selection using CONFIG VCCAUX constraint.
3. See XAPP459, “Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.”
4. For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide .
5. Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations.

DS529 (v2.1) December 18, 2018 www.xilinx.com 13

DC and Switching Characteristics

General DC Characteristics for I/O Pins

Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (1)
Symbol Description Test Conditions Min Typ Max Units
IL (2) Leakage current at User I/O, Driver is in a high-impedance state, –10 – +10 µA
input-only, dual-purpose, and VIN = 0V or VCCO max, sample-tested
dedicated pins, FPGA powered
IHS Leakage current on pins during All pins except INIT_B, PROG_B, DONE, and JTAG –10 – +10 µA
hot socketing, FPGA unpowered pins when PUDC_B = 1.
INIT_B, PROG_B, DONE, and JTAG pins or other Add IHS + IRPU µA
pins when PUDC_B = 0.
IRPU(3) Current through pull-up resistor VIN = GND VCCO or VCCAUX = –151 –315 –710 µA
at User I/O, dual-purpose, 3.0V to 3.6V
input-only, and dedicated pins.
Dedicated pins are powered by VCCO or VCCAUX = –82 –182 –437 µA
VCCAUX. 2.3V to 2.7V
VCCO = 1.7V to 1.9V –36 –88 –226 µA
VCCO = 1.4V to 1.6V –22 –56 –148 µA
VCCO = 1.14V to 1.26V –11 –31 –83 µA
RPU(3) Equivalent pull-up resistor value VIN = GND VCCO = 3.0V to 3.6V 5.1 11.4 23.9 kΩ
at User I/O, dual-purpose,
input-only, and dedicated pins VCCO = 2.3V to 2.7V 6.2 14.8 33.1 kΩ
(based on IRPU per Note 3) VCCO = 1.7V to 1.9V 8.4 21.6 52.6 kΩ
VCCO = 1.4V to 1.6V 10.8 28.4 74.0 kΩ
VCCO = 1.14V to 1.26V 15.3 41.1 119.4 kΩ
IRPD (3) Current through pull-down VCCAUX = 3.0V to 3.6V 167 346 659 µA
VIN = VCCO
resistor at User I/O,
dual-purpose, input-only, and VCCAUX = 2.25V to 2.75V
dedicated pins. Dedicated pins 100 225 457 µA
are powered by VCCAUX.
RPD(3) Equivalent pull-down resistor VCCAUX = 3.0V to 3.6V VIN = 3.0V to 3.6V 5.5 10.4 20.8 kΩ
value at User I/O, dual-purpose,
input-only, and dedicated pins VIN = 2.3V to 2.7V 4.1 7.8 15.7 kΩ
(based on IRPD per Note 3) VIN = 1.7V to 1.9V 3.0 5.7 11.1 kΩ
VIN = 1.4V to 1.6V 2.7 5.1 9.6 kΩ
VIN = 1.14V to 1.26V 2.4 4.5 8.1 kΩ
VCCAUX = 2.25V to 2.75V VIN = 3.0V to 3.6V 7.9 16.0 35.0 kΩ
VIN = 2.3V to 2.7V 5.9 12.0 26.3 kΩ
VIN = 1.7V to 1.9V 4.2 8.5 18.6 kΩ
VIN = 1.4V to 1.6V 3.6 7.2 15.7 kΩ
VIN = 1.14V to 1.26V 3.0 6.0 12.5 kΩ
IREF VREF current per pin All VCCO levels –10 – +10 µA
CIN Input capacitance – – – 10 pF
RDT Resistance of optional differential VCCO = 3.3V ± 10% LVDS_33, 90 100 115 Ω
termination circuit within a MINI_LVDS_33,
differential I/O pair. Not available RSDS_33
on Input-only pairs.
VCCO = 2.5V ± 10% LVDS_25, 90 110 – Ω
MINI_LVDS_25,
RSDS_25

Notes:
1. The numbers in this table are based on the conditions set forth in Table 8.
2. For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See "Parasitic Leakage" in UG331, Spartan-3 Generation FPGA User Guide .
3. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD.

14 www.xilinx.com DS529 (v2.1) December 18, 2018

 DC and Switching Characteristics

Quiescent Current Requirements

Table 10: Quiescent Supply Current Characteristics
Commercial Industrial
Symbol Description Device Typical(2) Maximum(2) Maximum(2) Units
ICCINTQ Quiescent VCCINT supply current XC3S50A 2 20 30 mA
XC3S200A 7 50 70 mA
XC3S400A 10 85 125 mA
XC3S700A 13 120 185 mA
XC3S1400A 24 220 310 mA
ICCOQ Quiescent VCCO supply current XC3S50A 0.2 2 3 mA
XC3S200A 0.2 2 3 mA
XC3S400A 0.3 3 4 mA
XC3S700A 0.3 3 4 mA
XC3S1400A 0.3 3 4 mA
ICCAUXQ Quiescent VCCAUX supply current XC3S50A 3 8 10 mA
XC3S200A 5 12 15 mA
XC3S400A 5 18 24 mA
XC3S700A 6 28 34 mA
XC3S1400A 10 50 58 mA

Notes:
1. The numbers in this table are based on the conditions set forth in Table 8.
2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. Typical values are characterized using typical devices at room temperature (TJ of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX
= 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage
limits with VCCINT = 1.26V, VCCO = 3.6V, and VCCAUX = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design
with no functional elements instantiated). For conditions other than those described above (for example, a design including functional
elements), measured quiescent current levels will be different than the values in the table.
3. For more accurate estimates for a specific design, use the Xilinx XPower tools. There are two recommended ways to estimate the total power
consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3A FPGA XPower Estimator provides quick, approximate,
typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as
well as more accurate typical estimates.
4. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
5. For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode
typically saves 40% total power consumption compared to quiescent current.

DS529 (v2.1) December 18, 2018 www.xilinx.com 15

DC and Switching Characteristics

Single-Ended I/O Standards

Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
VCCO for Drivers(2) VREF VIL VIH
IOSTANDARD
Attribute Min (V) Nom (V) Max (V) Min (V) Nom (V) Max (V) Max (V) Min (V)
LVTTL 3.0 3.3 3.6 0.8 2.0
LVCMOS33(4) 3.0 3.3 3.6 0.8 2.0
LVCMOS25(4,5) 2.3 2.5 2.7 0.7 1.7
LVCMOS18 1.65 1.8 1.95 VREF is not used for 0.4 0.8
LVCMOS15 1.4 1.5 1.6 these I/O standards 0.4 0.8
LVCMOS12 1.1 1.2 1.3 0.4 0.7
PCI33_3(6) 3.0 3.3 3.6 0.3 • VCCO 0.5 • VCCO
PCI66_3(6) 3.0 3.3 3.6 0.3 • VCCO 0.5 • VCCO
HSTL_I 1.4 1.5 1.6 0.68 0.75 0.9 VREF – 0.1 VREF + 0.1
HSTL_III 1.4 1.5 1.6 – 0.9 - VREF – 0.1 VREF + 0.1
HSTL_I_18 1.7 1.8 1.9 0.8 0.9 1.1 VREF – 0.1 VREF + 0.1
HSTL_II_18 1.7 1.8 1.9 – 0.9 – VREF – 0.1 VREF + 0.1
HSTL_III_18 1.7 1.8 1.9 – 1.1 – VREF – 0.1 VREF + 0.1
SSTL18_I 1.7 1.8 1.9 0.833 0.900 0.969 VREF – 0.125 VREF + 0.125
SSTL18_II 1.7 1.8 1.9 0.833 0.900 0.969 VREF – 0.125 VREF + 0.125
SSTL2_I 2.3 2.5 2.7 1.13 1.25 1.38 VREF – 0.150 VREF + 0.150
SSTL2_II 2.3 2.5 2.7 1.13 1.25 1.38 VREF – 0.150 VREF + 0.150
SSTL3_I 3.0 3.3 3.6 1.3 1.5 1.7 VREF – 0.2 VREF + 0.2
SSTL3_II 3.0 3.3 3.6 1.3 1.5 1.7 VREF – 0.2 VREF + 0.2

Notes:
1. Descriptions of the symbols used in this table are as follows:
VCCO – the supply voltage for output drivers
VREF – the reference voltage for setting the input switching threshold
VIL – the input voltage that indicates a Low logic level
VIH – the input voltage that indicates a High logic level
2. In general, the VCCO rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when VCCAUX = 3.3V range
and for PCI I/O standards.
3. For device operation, the maximum signal voltage (VIH max) can be as high as VIN max. See Table 8.
4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
5. All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail and use the LVCMOS25 or
LVCMOS33 standard depending on VCCAUX. The dual-purpose configuration pins use the LVCMOS standard before the User mode. When
using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as
throughout configuration.
6. For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. The PCIX
IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.

16 www.xilinx.com DS529 (v2.1) December 18, 2018

 DC and Switching Characteristics

Table 12: DC Characteristics of User I/Os Using Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards Single-Ended Standards(Continued)
Test Logic Level Test Logic Level
Conditions Characteristics Conditions Characteristics

IOL IOH VOL VOH IOSTANDARD IOL IOH VOL VOH

IOSTANDARD
Attribute (mA) (mA) Max (V) Min (V) Attribute (mA) (mA) Max (V) Min (V)

LVTTL(3) 2 2 –2 0.4 2.4 PCI33_3(5) 1.5 –0.5 10% VCCO 90% VCCO

4 4 –4 PCI66_3(5) 1.5 –0.5 10% VCCO 90% VCCO

6 6 –6 HSTL_I(4) 8 –8 0.4 VCCO - 0.4

8 8 –8 HSTL_III(4) 24 –8 0.4 VCCO - 0.4

12 12 –12 HSTL_I_18 8 –8 0.4 VCCO - 0.4

16 16 –16 HSTL_II_18(4) 16 –16 0.4 VCCO - 0.4

24 24 –24 HSTL_III_18 24 –8 0.4 VCCO - 0.4

LVCMOS33(3) 2 2 –2 0.4 VCCO – 0.4 SSTL18_I 6.7 –6.7 VTT – 0.475 VTT + 0.475

4 4 –4 SSTL18_II(4) 13.4 –13.4 VTT – 0.603 VTT + 0.603

6 6 –6 SSTL2_I 8.1 –8.1 VTT – 0.61 VTT + 0.61

8 8 –8 SSTL2_II(4) 16.2 –16.2 VTT – 0.81 VTT + 0.81

12 12 –12 SSTL3_I 8 –8 VTT – 0.6 VTT + 0.6

16 16 –16 SSTL3_II 16 –16 VTT – 0.8 VTT + 0.8

24(4) 24 –24 Notes:

1. The numbers in this table are based on the conditions set forth in
LVCMOS25(3) 2 2 –2 0.4 VCCO – 0.4 Table 8 and Table 11.
4 4 –4 2. Descriptions of the symbols used in this table are as follows:
IOL – the output current condition under which VOL is tested
6 6 –6 IOH – the output current condition under which VOH is tested
8 8 –8 VOL – the output voltage that indicates a Low logic level
VOH – the output voltage that indicates a High logic level
12 12 –12 VCCO – the supply voltage for output drivers
VTT – the voltage applied to a resistor termination
16(4) 16 –16
3. For the LVCMOS and LVTTL standards: the same VOL and VOH
24(4) 24 –24 limits apply for the Fast, Slow, and QUIETIO slew attributes.
4. These higher-drive output standards are supported only on
LVCMOS18(3) 2 2 –2 0.4 VCCO – 0.4 FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
"Using I/O Resources" in UG331.
4 4 –4 5. Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/pci. The
6 6 –6 PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
8 8 –8
12(4) 12 –12
16(4) 16 –16
LVCMOS15(3) 2 2 –2 0.4 VCCO – 0.4
4 4 –4
6 6 –6
8(4) 8 –8
12(4) 12 –12
LVCMOS12(3) 2 2 –2 0.4 VCCO – 0.4
4(4) 4 –4
6(4) 6 –6

DS529 (v2.1) December 18, 2018 www.xilinx.com 17

DC and Switching Characteristics

Differential I/O Standards

Differential Input Pairs

VINP
P Differential
Internal N I/O Pair Pins
VINN
Logic

VINN
50% VID
VINP
VICM
GND level
VINP + VINN
VICM = Input common mode voltage =
2
VID = Differential input voltage = VINP - VINN DS529-3_10_012907

Figure 4: Differential Input Voltages

Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
VCCO for Drivers(1) VID VICM(2)
IOSTANDARD Attribute Min (V) Nom (V) Max (V) Min (mV) Nom (mV) Max (mV) Min (V) Nom (V) Max (V)
LVDS_25(3) 2.25 2.5 2.75 100 350 600 0.3 1.25 2.35
LVDS_33(3) 3.0 3.3 3.6 100 350 600 0.3 1.25 2.35
BLVDS_25(4) 2.25 2.5 2.75 100 300 – 0.3 1.3 2.35
MINI_LVDS_25(3) 2.25 2.5 2.75 200 – 600 0.3 1.2 1.95
MINI_LVDS_33(3) 3.0 3.3 3.6 200 – 600 0.3 1.2 1.95
LVPECL_25(5) Inputs Only 100 800 1000 0.3 1.2 1.95
LVPECL_33(5) Inputs Only 100 800 1000 0.3 1.2 2.8(6)
RSDS_25(3) 2.25 2.5 2.75 100 200 – 0.3 1.2 1.5
RSDS_33(3) 3.0 3.3 3.6 100 200 – 0.3 1.2 1.5
TMDS_33(3, 4, 7) 3.14 3.3 3.47 150 – 1200 2.7 – 3.23
PPDS_25(3) 2.25 2.5 2.75 100 – 400 0.2 – 2.3
PPDS_33(3) 3.0 3.3 3.6 100 – 400 0.2 – 2.3
DIFF_HSTL_I_18 1.7 1.8 1.9 100 – – 0.8 – 1.1
DIFF_HSTL_II_18(8) 1.7 1.8 1.9 100 – – 0.8 – 1.1
DIFF_HSTL_III_18 1.7 1.8 1.9 100 – – 0.8 – 1.1
DIFF_HSTL_I 1.4 1.5 1.6 100 – – 0.68 0.9
DIFF_HSTL_III 1.4 1.5 1.6 100 – – – 0.9 –
DIFF_SSTL18_I 1.7 1.8 1.9 100 – – 0.7 – 1.1
DIFF_SSTL18_II(8) 1.7 1.8 1.9 100 – – 0.7 – 1.1
DIFF_SSTL2_I 2.3 2.5 2.7 100 – – 1.0 – 1.5
DIFF_SSTL2_II(8) 2.3 2.5 2.7 100 – – 1.0 – 1.5
DIFF_SSTL3_I 3.0 3.3 3.6 100 – – 1.1 – 1.9
DIFF_SSTL3_II 3.0 3.3 3.6 100 – – 1.1 – 1.9
Notes:
1. The VCCO rails supply only differential output drivers, not input circuits.
2. VICM must be less than VCCAUX.
3. These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
4. See "External Termination Requirements for Differential I/O," page 20.
5. LVPECL is supported on inputs only, not outputs. LVPECL_33 requires VCCAUX=3.3V ± 10%.
6. LVPECL_33 maximum VICM = the lower of 2.8V or VCCAUX – (VID / 2)
7. Requires VCCAUX = 3.3V ± 10% for inputs. (VCCAUX – 300 mV) ≤ VICM ≤ (VCCAUX – 37 mV)
8. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
9. All standards except for LVPECL and TMDS can have VCCAUX at either 2.5V or 3.3V. Define your VCCAUX level using the CONFIG VCCAUX constraint.

18 www.xilinx.com DS529 (v2.1) December 18, 2018

 DC and Switching Characteristics

Differential Output Pairs

VOUTP
P Differential
Internal N I/O Pair Pins
VOUTN
Logic

VOH
VOUTN
50% VOD
VOUTP
VOL
VOCM
GND level
VOUTP + VOUTN
VOCM = Output common mode voltage =
2
VOD = Output differential voltage = VOUTP - VOUTN

VOH = Output voltage indicating a High logic level

VOL = Output voltage indicating a Low logic levelDS529-3_11_012907

Figure 5: Differential Output Voltages

Table 14: DC Characteristics of User I/Os Using Differential Signal Standards

VOD VOCM VOH VOL
Typ
IOSTANDARD Attribute Min (mV) (mV) Max (mV) Min (V) Typ (V) Max (V) Min (V) Max (V)
LVDS_25 247 350 454 1.125 – 1.375 – –
LVDS_33 247 350 454 1.125 – 1.375 – –
BLVDS_25 240 350 460 – 1.30 – – –
MINI_LVDS_25 300 – 600 1.0 – 1.4 – –
MINI_LVDS_33 300 – 600 1.0 – 1.4 – –
RSDS_25 100 – 400 1.0 – 1.4 – –
RSDS_33 100 – 400 1.0 – 1.4 – –
TMDS_33 400 – 800 VCCO – 0.405 – VCCO – 0.190 – –
PPDS_25 100 – 400 0.5 0.8 1.4 – –
PPDS_33 100 – 400 0.5 0.8 1.4 – –
DIFF_HSTL_I_18 – – – – – – VCCO – 0.4 0.4
DIFF_HSTL_II_18 – – – – – – VCCO – 0.4 0.4
DIFF_HSTL_III_18 – – – – – – VCCO – 0.4 0.4
DIFF_HSTL_I – – – – – – VCCO – 0.4 0.4
DIFF_HSTL_III – – – – – – VCCO – 0.4 0.4
DIFF_SSTL18_I – – – – – – VTT + 0.475 VTT – 0.475
DIFF_SSTL18_II – – – – – – VTT + 0.603 VTT – 0.603
DIFF_SSTL2_I – – – – – – VTT + 0.61 VTT – 0.61
DIFF_SSTL2_II – – – – – – VTT + 0.81 VTT – 0.81
DIFF_SSTL3_I – – – – – – VTT + 0.6 VTT – 0.6
DIFF_SSTL3_II – – – – – – VTT + 0.8 VTT – 0.8
Notes:
1. The numbers in this table are based on the conditions set forth in Table 8 and Table 13.
2. See "External Termination Requirements for Differential I/O," page 20.
3. Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins of the
differential signal pair.
4. At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25,
MINI_LVDS_25, PPDS_25 when VCCO=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when VCCO = 3.3V

DS529 (v2.1) December 18, 2018 www.xilinx.com 19

DC and Switching Characteristics

External Termination Requirements for Differential I/O

LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards

Bank 0 and 2 Any Bank

Bank 0 Bank 0

Bank 1
Bank 3
1/4 th of Bourns No VCCO Restrictions
Bank 2
Part Number Bank 2
LVDS_33, LVDS_25,
Z0 = 50Ω CAT16-PT4F4 MINI_LVDS_33,
MINI_LVDS_25,
RSDS_33, RSDS_25,
VCCO = 3.3V VCCO = 2.5V PPDS_33, PPDS_25
LVDS_33, LVDS_25,
MINI_LVDS_33, MINI_LVDS_25, Z0 = 50Ω 100Ω
RSDS_33, RSDS_25,
PPDS_33 PPDS_25

DIFF_TERM=No
a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint

VCCO = 3.3V VCCO = 2.5V

Z0 = 50Ω LVDS_33, LVDS_25,
MINI_LVDS_33, MINI_LVDS_25,
VCCO = 3.3V VCCO = 2.5V RSDS_33, RSDS_25,
LVDS_33, LVDS_25, PPDS_33 PPDS_25
MINI_LVDS_33, MINI_LVDS_25,
Z0 = 50Ω RDT
RSDS_33, RSDS_25,
PPDS_33 PPDS_25

DIFF_TERM=Yes
b) Differential pairs using DIFF_TERM=Yes constraint DS529-3_09_020107

Figure 6: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards

BLVDS_25 I/O Standard

Any Bank Any Bank

Bank 0 Bank 0
1/4 th of Bourns
Bank 1

Bank 1
Bank 3

Bank 3
1/4 th of Bourns
Part Number Part Number
Bank 2 CAT16-LV4F12 CAT16-PT4F4 Bank 2
VCCO = 2.5V 165Ω Z0 = 50Ω No VCCO Requirement

BLVDS_25 140Ω Z0 = 50Ω 100Ω BLVDS_25

165Ω
DS529-3_07_020107

Figure 7: External Output and Input Termination Resistors for BLVDS_25 I/O Standard

TMDS_33 I/O Standard

Bank 0 and 2 Any Bank

Bank 0 Bank 0
Bank 1
Bank 3

3.3V
Bank 2 Bank 2
50Ω 50Ω
VCCO = 3.3V VCCAUX = 3.3V

TMDS_33 TMDS_33

DVI/HDMI cable DS529-3_08_020107

Figure 8: External Input Resistors Required for TMDS_33 I/O Standard

Device DNA Read Endurance

Table 15: Device DNA Identifier Memory Characteristics
Symbol Description Minimum Units
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by Read
DNA_CYCLES 30,000,000
HOLD or SHIFT operations. cycles

20 www.xilinx.com DS529 (v2.1) December 18, 2018

 DC and Switching Characteristics

Switching Characteristics
All Spartan-3A FPGAs ship in two speed grades: –4 and the To create a Xilinx user account and sign up for automatic
higher performance –5. Switching characteristics in this E-mail notification whenever this data sheet is updated:
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as follows:
Timing parameters and their representative values are
Advance: These specifications are based on simulations
selected for inclusion below either because they are
only and are typically available soon after establishing
important as general design requirements or they indicate
FPGA specifications. Although speed grades with this
fundamental device performance characteristics. The
designation are considered relatively stable and
Spartan-3A FPGA speed files (v1.41), part of the Xilinx
conservative, some under-reporting might still occur.
Development Software, are the original source for many but
Preliminary: These specifications are based on complete not all of the values. The speed grade designations for these
early silicon characterization. Devices and speed grades files are shown in Table 16. For more complete, more
with this designation are intended to give a better indication precise, and worst-case data, use the values reported by the
of the expected performance of production silicon. The Xilinx static timing analyzer (TRACE in the Xilinx
probability of under-reporting preliminary delays is greatly development software) and back-annotated to the
reduced compared to Advance data. simulation netlist.
Production: These specifications are approved once Table 16: Spartan-3A v1.41 Speed Grade Designation
enough production silicon of a particular device has been
Device Advance Preliminary Production
characterized to provide full correlation between speed files
and devices over numerous production lots. There is no XC3S50A -4, -5
under-reporting of delays, and customers receive formal XC3S200A -4, -5
notification of any subsequent changes. Typically, the
XC3S400A -4, -5
slowest speed grades transition to Production before faster
speed grades. XC3S700A -4, -5
XC3S1400A -4, -5
Software Version Requirements
Table 17 provides the recent history of the Spartan-3A
Production-quality systems must use FPGA designs FPGA speed files.
compiled using a speed file designated as PRODUCTION
status. FPGA designs using a less mature speed file Table 17: Spartan-3A Speed File Version History
designation should only be used during system prototyping ISE
or pre-production qualification. FPGA designs with speed Version Release Description
files designated as Advance or Preliminary should not be
1.41 ISE 10.1.03 Updated Automotive output delays
used in a production-quality system.
1.40 ISE 10.1.02 Updated Automotive input delays.
Whenever a speed file designation changes, as a device
1.39 ISE 10.1.01 Added Automotive parts.
matures toward Production status, rerun the latest Xilinx®
ISE® software on the FPGA design to ensure that the FPGA 1.38 ISE 9.2.03i Added Absolute Minimum values.
design incorporates the latest timing information and Updated pin-to-pin setup and hold
software updates. times (Table 19), TMDS output
1.37 ISE 9.2.01i adjustment (Table 26) multiplier
All parameter limits are representative of worst-case supply setup/hold times (Table 34), and block
voltage and junction temperature conditions. Unless RAM clock width (Table 35).
otherwise noted, the published parameter values apply ISE 9.2i; XC3S400A, all speed grades and all
to all Spartan-3A devices. AC and DC characteristics previously temperature grades, upgraded to
available via Production
are specified using the same numbers for both 1.36 Answer
commercial and industrial grades. Record
AR24992

Answer XC3S50A, XC3S200A, XC3S700A,

Record XC3S1400A, all speed grades and all
1.35 temperature grades, upgraded to
AR24992 Production.
XC3S700A and XC3S1400A -4 speed
1.34 ISE 9.1.03i grade upgraded to Production. Updated
pin-to-pin timing numbers.

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DC and Switching Characteristics

I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
-5 -4
Symbol Description Conditions Device Max Max Units
Clock-to-Output Times
TICKOFDCM When reading from the Output LVCMOS25(2), 12mA XC3S50A 3.18 3.42 ns
Flip-Flop (OFF), the time from the output drive, Fast slew
active transition on the Global rate, with DCM(3) XC3S200A 3.21 3.27 ns
Clock pin to data appearing at the
Output pin. The DCM is in use. XC3S400A 2.97 3.33 ns
XC3S700A 3.39 3.50 ns
XC3S1400A 3.51 3.99 ns
TICKOF When reading from OFF, the time LVCMOS25(2), 12mA XC3S50A 4.59 5.02 ns
from the active transition on the output drive, Fast slew
Global Clock pin to data appearing rate, without DCM XC3S200A 4.88 5.24 ns
at the Output pin. The DCM is not
in use. XC3S400A 4.68 5.12 ns
XC3S700A 4.97 5.34 ns
XC3S1400A 5.06 5.69 ns

Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 23. If the latter is true, add the appropriate Output adjustment from Table 26.
3. DCM output jitter is included in all measurements.

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 DC and Switching Characteristics

Pin-to-Pin Setup and Hold Times

Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Speed Grade
-5 -4
Symbol Description Conditions Device Min Min Units
Setup Times
TPSDCM When writing to the Input LVCMOS25(2), XC3S50A 2.45 2.68 ns
Flip-Flop (IFF), the time from the IFD_DELAY_VALUE = 0,
setup of data at the Input pin to with DCM(4) XC3S200A 2.59 2.84 ns
the active transition at a Global
Clock pin. The DCM is in use. No XC3S400A 2.38 2.68 ns
Input Delay is programmed. XC3S700A 2.38 2.57 ns
XC3S1400A 1.91 2.17 ns
TPSFD When writing to IFF, the time from LVCMOS25(2), XC3S50A 2.55 2.76 ns
the setup of data at the Input pin IFD_DELAY_VALUE = 5,
to an active transition at the without DCM XC3S200A 2.32 2.76 ns
Global Clock pin. The DCM is not
in use. The Input Delay is XC3S400A 2.21 2.60 ns
programmed. XC3S700A 2.28 2.63 ns
XC3S1400A 2.33 2.41 ns
Hold Times
TPHDCM When writing to IFF, the time from LVCMOS25(3), XC3S50A -0.36 -0.36 ns
the active transition at the Global IFD_DELAY_VALUE = 0,
Clock pin to the point when data with DCM(4) XC3S200A -0.52 -0.52 ns
must be held at the Input pin. The
DCM is in use. No Input Delay is XC3S400A -0.33 -0.29 ns
programmed. XC3S700A -0.17 -0.12 ns
XC3S1400A -0.07 0.00 ns
TPHFD When writing to IFF, the time from LVCMOS25(3), XC3S50A -0.63 -0.58 ns
the active transition at the Global IFD_DELAY_VALUE = 5,
Clock pin to the point when data without DCM XC3S200A -0.56 -0.56 ns
must be held at the Input pin. The
DCM is not in use. The Input XC3S400A -0.42 -0.42 ns
Delay is programmed. XC3S700A -0.80 -0.75 ns
XC3S1400A -0.69 -0.69 ns

Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 23. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 23. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4. DCM output jitter is included in all measurements.

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DC and Switching Characteristics

Input Setup and Hold Times

Table 20: Setup and Hold Times for the IOB Input Path
Speed Grade
IFD_
-5 -4
DELAY_
Symbol Description Conditions VALUE Device Min Min Units
Setup Times
TIOPICK Time from the setup of data at the LVCMOS25(2) 0 XC3S50A 1.56 1.58 ns
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF). XC3S200A 1.71 1.81 ns
No Input Delay is programmed.
XC3S400A 1.30 1.51 ns
XC3S700A 1.34 1.51 ns
XC3S1400A 1.36 1.74 ns
TIOPICKD Time from the setup of data at the LVCMOS25(2) 1 XC3S50A 2.16 2.18 ns
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF). 2 3.10 3.12 ns
The Input Delay is programmed.
3 3.51 3.76 ns
4 4.04 4.32 ns
5 3.88 4.24 ns
6 4.72 5.09 ns
7 5.47 5.94 ns
8 5.97 6.52 ns
1 XC3S200A 2.05 2.20 ns
2 2.72 2.93 ns
3 3.38 3.78 ns
4 3.88 4.37 ns
5 3.69 4.20 ns
6 4.56 5.23 ns
7 5.34 6.11 ns
8 5.85 6.71 ns
1 XC3S400A 1.79 2.02 ns
2 2.43 2.67 ns
3 3.02 3.43 ns
4 3.49 3.96 ns
5 3.41 3.95 ns
6 4.20 4.81 ns
7 4.96 5.66 ns
8 5.44 6.19 ns

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 DC and Switching Characteristics

Table 20: Setup and Hold Times for the IOB Input Path(Continued)
Speed Grade
IFD_
-5 -4
DELAY_
Symbol Description Conditions VALUE Device Min Min Units
TIOPICKD Time from the setup of data at the LVCMOS25(2) 1 XC3S700A 1.82 1.95 ns
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF). 2 2.62 2.83 ns
The Input Delay is programmed.
3 3.32 3.72 ns
4 3.83 4.31 ns
5 3.69 4.14 ns
6 4.60 5.19 ns
7 5.39 6.10 ns
8 5.92 6.73 ns
1 XC3S1400A 1.79 2.17 ns
2 2.55 2.92 ns
3 3.38 3.76 ns
4 3.75 4.32 ns
5 3.81 4.19 ns
6 4.39 5.09 ns
7 5.16 5.98 ns
8 5.69 6.57 ns
Hold Times
TIOICKP Time from the active transition at the LVCMOS25(3) 0 XC3S50A –0.66 –0.64 ns
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held XC3S200A –0.85 –0.65 ns
at the Input pin. No Input Delay is
programmed. XC3S400A –0.42 –0.42 ns
XC3S700A –0.81 –0.67 ns
XC3S1400A –0.71 –0.71 ns
TIOICKPD Time from the active transition at the LVCMOS25(3) 1 XC3S50A –0.88 –0.88 ns
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held 2 –1.33 –1.33 ns
at the Input pin. The Input Delay is
programmed. 3 –2.05 –2.05 ns
4 –2.43 –2.43 ns
5 –2.34 –2.34 ns
6 –2.81 –2.81 ns
7 –3.03 –3.03 ns
8 –3.83 –3.57 ns
1 XC3S200A –1.51 –1.51 ns
2 –2.09 –2.09 ns
3 –2.40 –2.40 ns
4 –2.68 –2.68 ns
5 –2.56 –2.56 ns
6 –2.99 –2.99 ns
7 –3.29 –3.29 ns
8 –3.61 –3.61 ns

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DC and Switching Characteristics

Table 20: Setup and Hold Times for the IOB Input Path(Continued)
Speed Grade
IFD_
-5 -4
DELAY_
Symbol Description Conditions VALUE Device Min Min Units
TIOICKPD Time from the active transition at the LVCMOS25(3) 1 XC3S400A –1.12 –1.12 ns
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held 2 –1.70 –1.70 ns
at the Input pin. The Input Delay is
programmed. 3 –2.08 –2.08 ns
4 –2.38 –2.38 ns
5 –2.23 –2.23 ns
6 –2.69 –2.69 ns
7 –3.08 –3.08 ns
8 –3.35 –3.35 ns
1 XC3S700A –1.67 –1.67 ns
2 –2.27 –2.27 ns
3 –2.59 –2.59 ns
4 –2.92 –2.92 ns
5 –2.89 –2.89 ns
6 –3.22 –3.22 ns
7 –3.52 –3.52 ns
8 –3.81 –3.81 ns
1 XC3S1400A –1.60 –1.60 ns
2 –2.06 –2.06 ns
3 –2.46 –2.46 ns
4 –2.86 –2.86 ns
5 –2.88 –2.88 ns
6 –3.24 –3.24 ns
7 –3.55 –3.55 ns
8 –3.89 –3.89 ns
Set/Reset Pulse Width
Minimum pulse width to SR control - - All 1.33 1.61 ns
TRPW_IOB input on IOB

Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 23.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 23. When the hold time is negative, it is possible to change the data before the clock’s active
edge.

Table 21: Sample Window (Source Synchronous)

Symbol Description Max Units
TSAMP Setup and hold The input capture sample window value is highly specific to a particular application, device, ps
capture window of package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
an IOB flip-flop. appropriate Xilinx Answer Record for application-specific values.
• Answer Record 30879

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 DC and Switching Characteristics

Input Propagation Times

Table 22: Propagation Times for the IOB Input Path
Speed Grade
-5 -4
Symbol Description Conditions DELAY_VALUE Device Max Max Units
Propagation Times
TIOPI The time it takes for data to travel LVCMOS25(2) IBUF_DELAY_VALUE=0 XC3S50A 1.04 1.12 ns
from the Input pin to the I output with
no input delay programmed XC3S200A 0.87 0.87 ns
XC3S400A 0.65 0.72 ns
XC3S700A 0.92 0.92 ns
XC3S1400A 0.96 1.21 ns
TIOPID The time it takes for data to travel LVCMOS25(2) 1 XC3S50A 1.79 2.07 ns
from the Input pin to the I output with
the input delay programmed 2 2.13 2.46 ns
3 2.36 2.71 ns
4 2.88 3.21 ns
5 3.11 3.46 ns
6 3.45 3.84 ns
7 3.75 4.19 ns
8 4.00 4.47 ns
9 3.61 4.11 ns
10 3.95 4.50 ns
11 4.18 4.67 ns
12 4.75 5.20 ns
13 4.98 5.44 ns
14 5.31 5.95 ns
15 5.62 6.28 ns
16 5.86 6.57 ns
1 XC3S200A 1.57 1.65 ns
2 1.87 1.97 ns
3 2.16 2.33 ns
4 2.68 2.96 ns
5 2.87 3.19 ns
6 3.20 3.60 ns
7 3.57 4.02 ns
8 3.79 4.26 ns
9 3.42 3.86 ns
10 3.79 4.25 ns
11 4.02 4.55 ns
12 4.62 5.24 ns
13 4.86 5.53 ns
14 5.18 5.94 ns

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DC and Switching Characteristics

Table 22: Propagation Times for the IOB Input Path(Continued)

Speed Grade
-5 -4
Symbol Description Conditions DELAY_VALUE Device Max Max Units
TIOPID The time it takes for data to travel LVCMOS25(2) 15 XC3S200A 5.43 6.24 ns
from the Input pin to the I output with
the input delay programmed 16 5.75 6.59 ns
1 XC3S400A 1.32 1.43 ns
2 1.67 1.83 ns
3 1.90 2.07 ns
4 2.33 2.52 ns
5 2.60 2.91 ns
6 2.94 3.20 ns
7 3.23 3.51 ns
8 3.50 3.85 ns
9 3.18 3.55 ns
10 3.53 3.95 ns
11 3.76 4.20 ns
12 4.26 4.67 ns
13 4.51 4.97 ns
14 4.85 5.32 ns
15 5.14 5.64 ns
16 5.40 5.95 ns
1 XC3S700A 1.84 1.87 ns
2 2.20 2.27 ns
3 2.46 2.60 ns
4 2.93 3.15 ns
5 3.21 3.45 ns
6 3.54 3.80 ns
7 3.86 4.16 ns
8 4.13 4.48 ns
9 3.82 4.19 ns
10 4.17 4.58 ns
11 4.43 4.89 ns
12 4.95 5.49 ns
13 5.22 5.83 ns
14 5.57 6.21 ns
15 5.89 6.55 ns
16 6.16 6.89 ns
1 XC3S1400A 1.95 2.18 ns
2 2.29 2.59 ns
3 2.54 2.84 ns
4 2.96 3.30 ns

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 DC and Switching Characteristics

Table 22: Propagation Times for the IOB Input Path(Continued)

Speed Grade
-5 -4
Symbol Description Conditions DELAY_VALUE Device Max Max Units
TIOPID The time it takes for data to travel LVCMOS25(2) 5 XC3S1400A 3.17 3.52 ns
from the Input pin to the I output with
the input delay programmed 6 3.52 3.92 ns
7 3.82 4.18 ns
8 4.10 4.57 ns
9 3.84 4.31 ns
10 4.20 4.79 ns
11 4.46 5.06 ns
12 4.87 5.51 ns
13 5.07 5.73 ns
14 5.43 6.08 ns
15 5.73 6.33 ns
16 6.01 6.77 ns
TIOPLI The time it takes for data to travel LVCMOS25(2) IFD_DELAY_VALUE=0 XC3S50A 1.70 1.81 ns
from the Input pin through the IFF
latch to the I output with no input XC3S200A 1.85 2.04 ns
delay programmed
XC3S400A 1.44 1.74 ns
XC3S700A 1.48 1.74 ns
XC3S1400A 1.50 1.97 ns
TIOPLID The time it takes for data to travel LVCMOS25(2) 1 XC3S50A 2.30 2.41 ns
from the Input pin through the IFF
latch to the I output with the input 2 3.24 3.35 ns
delay programmed
3 3.65 3.98 ns
4 4.18 4.55 ns
5 4.02 4.47 ns
6 4.86 5.32 ns
7 5.61 6.17 ns
8 6.11 6.75 ns
1 XC3S200A 2.19 2.43 ns
2 2.86 3.16 ns
3 3.52 4.01 ns
4 4.02 4.60 ns
5 3.83 4.43 ns
6 4.70 5.46 ns
7 5.48 6.33 ns
8 5.99 6.94 ns
1 XC3S400A 1.93 2.25 ns
2 2.57 2.90 ns
3 3.16 3.66 ns
4 3.63 4.19 ns

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DC and Switching Characteristics

Table 22: Propagation Times for the IOB Input Path(Continued)

Speed Grade
-5 -4
Symbol Description Conditions DELAY_VALUE Device Max Max Units
TIOPLID The time it takes for data to travel LVCMOS25(2) 5 XC3S400A 3.55 4.18 ns
from the Input pin through the IFF
latch to the I output with the input 6 4.34 5.03 ns
delay programmed
7 5.09 5.88 ns
8 5.58 6.42 ns
1 XC3S700A 1.96 2.18 ns
2 2.76 3.06 ns
3 3.45 3.95 ns
4 3.97 4.54 ns
5 3.83 4.37 ns
6 4.74 5.42 ns
7 5.53 6.33 ns
8 6.06 6.96 ns
1 XC3S1400A 1.93 2.40 ns
2 2.69 3.15 ns
3 3.52 3.99 ns
4 3.89 4.55 ns
5 3.95 4.42 ns
6 4.53 5.32 ns
7 5.30 6.21 ns
8 5.83 6.80 ns

Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 23.

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 DC and Switching Characteristics

Input Timing Adjustments

Table 23: Input Timing Adjustments by IOSTANDARD Table 23: Input Timing Adjustments by IOSTANDARD(Continued)

Add the Add the

Convert Input Time from Adjustment Below Convert Input Time from Adjustment Below
LVCMOS25 to the Following LVCMOS25 to the Following Speed Grade
Speed Grade Signal Standard
Signal Standard
(IOSTANDARD) -5 -4 Units (IOSTANDARD) -5 -4 Units
Single-Ended Standards Differential Standards
LVTTL 0.62 0.62 ns LVDS_25 0.76 0.76 ns
LVCMOS33 0.54 0.54 ns LVDS_33 0.79 0.79 ns
LVCMOS25 0 0 ns BLVDS_25 0.79 0.79 ns
LVCMOS18 0.83 0.83 ns MINI_LVDS_25 0.78 0.78 ns
LVCMOS15 0.60 0.60 ns MINI_LVDS_33 0.79 0.79 ns
LVCMOS12 0.31 0.31 ns LVPECL_25 0.78 0.78 ns
PCI33_3 0.41 0.41 ns LVPECL_33 0.79 0.79 ns
PCI66_3 0.41 0.41 ns RSDS_25 0.79 0.79 ns
HSTL_I 0.72 0.72 ns RSDS_33 0.77 0.77 ns
HSTL_III 0.77 0.77 ns TMDS_33 0.79 0.79 ns
HSTL_I_18 0.69 0.69 ns PPDS_25 0.79 0.79 ns
HSTL_II_18 0.69 0.69 ns PPDS_33 0.79 0.79 ns
HSTL_III_18 0.79 0.79 ns DIFF_HSTL_I_18 0.74 0.74 ns
SSTL18_I 0.71 0.71 ns DIFF_HSTL_II_18 0.72 0.72 ns
SSTL18_II 0.71 0.71 ns DIFF_HSTL_III_18 1.05 1.05 ns
SSTL2_I 0.68 0.68 ns DIFF_HSTL_I 0.72 0.72 ns
SSTL2_II 0.68 0.68 ns DIFF_HSTL_III 1.05 1.05 ns
SSTL3_I 0.78 0.78 ns DIFF_SSTL18_I 0.71 0.71 ns
SSTL3_II 0.78 0.78 ns DIFF_SSTL18_II 0.71 0.71 ns
DIFF_SSTL2_I 0.74 0.74 ns
DIFF_SSTL2_II 0.75 0.75 ns
DIFF_SSTL3_I 1.06 1.06 ns
DIFF_SSTL3_II 1.06 1.06 ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating conditions
set forth in Table 8, Table 11, and Table 13.
2. These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.

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DC and Switching Characteristics

Output Propagation Times

Table 24: Timing for the IOB Output Path
Speed Grade
-5 -4
Symbol Description Conditions Device Max Max Units
Clock-to-Output Times
TIOCKP When reading from the Output Flip-Flop (OFF), LVCMOS25(2), 12 mA output All 2.87 3.13 ns
the time from the active transition at the OCLK drive, Fast slew rate
input to data appearing at the Output pin
Propagation Times
TIOOP The time it takes for data to travel from the IOB’s LVCMOS25(2), 12 mA output All 2.78 2.91 ns
O input to the Output pin drive, Fast slew rate
Set/Reset Times
TIOSRP Time from asserting the OFF’s SR input to LVCMOS25(2), 12 mA output All 3.63 3.89 ns
setting/resetting data at the Output pin drive, Fast slew rate
TIOGSRQ Time from asserting the Global Set Reset (GSR) 8.62 9.65 ns
input on the STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin

Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.

Three-State Output Propagation Times

Table 25: Timing for the IOB Three-State Path
Speed Grade
-5 -4
Symbol Description Conditions Device Max Max Units
Synchronous Output Enable/Disable Times
TIOCKHZ Time from the active transition at the OTCLK input of LVCMOS25, 12 mA All 0.63 0.76 ns
the Three-state Flip-Flop (TFF) to when the Output output drive, Fast slew
pin enters the high-impedance state rate
TIOCKON(2) Time from the active transition at TFF’s OTCLK input All 2.80 3.06 ns
to when the Output pin drives valid data
Asynchronous Output Enable/Disable Times
TGTS Time from asserting the Global Three State (GTS) LVCMOS25, 12 mA All 9.47 10.36 ns
input on the STARTUP_SPARTAN3A primitive to output drive, Fast slew
when the Output pin enters the high-impedance rate
state
Set/Reset Times
TIOSRHZ Time from asserting TFF’s SR input to when the LVCMOS25, 12 mA All 1.61 1.86 ns
Output pin enters a high-impedance state output drive, Fast slew
rate
TIOSRON(2) Time from asserting TFF’s SR input at TFF to when All 3.57 3.82 ns
the Output pin drives valid data

Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.

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 DC and Switching Characteristics

Output Timing Adjustments

Table 26: Output Timing Adjustments for IOB Table 26: Output Timing Adjustments for IOB(Continued)
Add the Add the
Adjustment Adjustment
Convert Output Time from Below Convert Output Time from Below
LVCMOS25 with 12mA Drive and LVCMOS25 with 12mA Drive and Speed Grade
Speed Grade Fast Slew Rate to the Following
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD) -5 -4 Units Signal Standard (IOSTANDARD) -5 -4 Units
Single-Ended Standards LVCMOS33 Slow 2 mA 5.58 5.58 ns
LVTTL Slow 2 mA 5.58 5.58 ns 4 mA 3.17 3.17 ns
4 mA 3.16 3.16 ns 6 mA 3.17 3.17 ns
6 mA 3.17 3.17 ns 8 mA 2.09 2.09 ns
8 mA 2.09 2.09 ns 12 mA 1.24 1.24 ns
12 mA 1.62 1.62 ns 16 mA 1.15 1.15 ns
16 mA 1.24 1.24 ns 24 mA 2.55(3) 2.55(3) ns
24 mA 2.74(3) 2.74(3) ns Fast 2 mA 3.02 3.02 ns
Fast 2 mA 3.03 3.03 ns 4 mA 1.71 1.71 ns
4 mA 1.71 1.71 ns 6 mA 1.72 1.72 ns
6 mA 1.71 1.71 ns 8 mA 0.53 0.53 ns
8 mA 0.53 0.53 ns 12 mA 0.59 0.59 ns
12 mA 0.53 0.53 ns 16 mA 0.59 0.59 ns
16 mA 0.59 0.59 ns 24 mA 0.51 0.51 ns
24 mA 0.60 0.60 ns QuietIO 2 mA 27.67 27.67 ns
QuietIO 2 mA 27.67 27.67 ns 4 mA 27.67 27.67 ns
4 mA 27.67 27.67 ns 6 mA 27.67 27.67 ns
6 mA 27.67 27.67 ns 8 mA 16.71 16.71 ns
8 mA 16.71 16.71 ns 12 mA 16.29 16.29 ns
12 mA 16.67 16.67 ns 16 mA 16.18 16.18 ns
16 mA 16.22 16.22 ns 24 mA 12.11 12.11 ns
24 mA 12.11 12.11 ns

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DC and Switching Characteristics

Table 26: Output Timing Adjustments for IOB(Continued) Table 26: Output Timing Adjustments for IOB(Continued)
Add the Add the
Adjustment Adjustment
Convert Output Time from Below Convert Output Time from Below
LVCMOS25 with 12mA Drive and Speed Grade LVCMOS25 with 12mA Drive and Speed Grade
Fast Slew Rate to the Following Fast Slew Rate to the Following
Signal Standard (IOSTANDARD) -5 -4 Units Signal Standard (IOSTANDARD) -5 -4 Units
LVCMOS25 Slow 2 mA 5.33 5.33 ns LVCMOS15 Slow 2 mA 5.82 5.82 ns
4 mA 2.81 2.81 ns 4 mA 3.97 3.97 ns
6 mA 2.82 2.82 ns 6 mA 3.21 3.21 ns
8 mA 1.14 1.14 ns 8 mA 2.53 2.53 ns
12 mA 1.10 1.10 ns 12 mA 2.06 2.06 ns
16 mA 0.83 0.83 ns Fast 2 mA 5.23 5.23 ns
24 mA 2.26(3) 2.26(3) ns 4 mA 3.05 3.05 ns
Fast 2 mA 4.36 4.36 ns 6 mA 1.95 1.95 ns
4 mA 1.76 1.76 ns 8 mA 1.60 1.60 ns
6 mA 1.25 1.25 ns 12 mA 1.30 1.30 ns
8 mA 0.38 0.38 ns QuietIO 2 mA 34.11 34.11 ns
12 mA 0 0 ns 4 mA 25.66 25.66 ns
16 mA 0.01 0.01 ns 6 mA 24.64 24.64 ns
24 mA 0.01 0.01 ns 8 mA 22.06 22.06 ns
QuietIO 2 mA 25.92 25.92 ns 12 mA 20.64 20.64 ns
4 mA 25.92 25.92 ns LVCMOS12 Slow 2 mA 7.14 7.14 ns
6 mA 25.92 25.92 ns 4 mA 4.87 4.87 ns
8 mA 15.57 15.57 ns 6 mA 5.67 5.67 ns
12 mA 15.59 15.59 ns Fast 2 mA 6.77 6.77 ns
16 mA 14.27 14.27 ns 4 mA 5.02 5.02 ns
24 mA 11.37 11.37 ns 6 mA 4.09 4.09 ns
LVCMOS18 Slow 2 mA 4.48 4.48 ns QuietIO 2 mA 50.76 50.76 ns
4 mA 3.69 3.69 ns 4 mA 43.17 43.17 ns
6 mA 2.91 2.91 ns 6 mA 37.31 37.31 ns
8 mA 1.99 1.99 ns PCI33_3 0.34 0.34 ns
12 mA 1.57 1.57 ns PCI66_3 0.34 0.34 ns
16 mA 1.19 1.19 ns HSTL_I 0.78 0.78 ns
Fast 2 mA 3.96 3.96 ns HSTL_III 1.16 1.16 ns
4 mA 2.57 2.57 ns HSTL_I_18 0.35 0.35 ns
6 mA 1.90 1.90 ns HSTL_II_18 0.30 0.30 ns
8 mA 1.06 1.06 ns HSTL_III_18 0.47 0.47 ns
12 mA 0.83 0.83 ns SSTL18_I 0.40 0.40 ns
16 mA 0.63 0.63 ns SSTL18_II 0.30 0.30 ns
QuietIO 2 mA 24.97 24.97 ns SSTL2_I 0 0 ns
4 mA 24.97 24.97 ns SSTL2_II –0.05 –0.05 ns
6 mA 24.08 24.08 ns SSTL3_I 0 0 ns
8 mA 16.43 16.43 ns SSTL3_II 0.17 0.17 ns
12 mA 14.52 14.52 ns
16 mA 13.41 13.41 ns

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 DC and Switching Characteristics

Table 26: Output Timing Adjustments for IOB(Continued)

Add the
Adjustment
Convert Output Time from Below
LVCMOS25 with 12mA Drive and Speed Grade
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD) -5 -4 Units
Differential Standards
LVDS_25 1.16 1.16 ns
LVDS_33 0.46 0.46 ns
BLVDS_25 0.11 0.11 ns
MINI_LVDS_25 0.75 0.75 ns
MINI_LVDS_33 0.40 0.40 ns
LVPECL_25
Input Only
LVPECL_33
RSDS_25 1.42 1.42 ns
RSDS_33 0.58 0.58 ns
TMDS_33 0.46 0.46 ns
PPDS_25 1.07 1.07 ns
PPDS_33 0.63 0.63 ns
DIFF_HSTL_I_18 0.43 0.43 ns
DIFF_HSTL_II_18 0.41 0.41 ns
DIFF_HSTL_III_18 0.36 0.36 ns
DIFF_HSTL_I 1.01 1.01 ns
DIFF_HSTL_III 0.54 0.54 ns
DIFF_SSTL18_I 0.49 0.49 ns
DIFF_SSTL18_II 0.41 0.41 ns
DIFF_SSTL2_I 0.82 0.82 ns
DIFF_SSTL2_II 0.09 0.09 ns
DIFF_SSTL3_I 1.16 1.16 ns
DIFF_SSTL3_II 0.28 0.28 ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating conditions
set forth in Table 8, Table 11, and Table 13.
2. These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
3. Note that 16 mA drive is faster than 24 mA drive for the Slow
slew rate.

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DC and Switching Characteristics

Timing Measurement Methodology

When measuring timing parameters at the programmable LVCMOS, LVTTL), then RT is set to 1MΩ to indicate an open
I/Os, different signal standards call for different test connection, and VT is set to zero. The same measurement
conditions. Table 27 lists the conditions to use for each point (VM) that was used at the Input is also used at the
standard. Output.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of VL and a VT (VREF)
High logic level of VH is applied to the Input under test.
Some standards also require the application of a bias FPGA Output
RT (RREF)
voltage to the VREF pins of a given bank to properly set the
input-switching threshold. The measurement point of the VM (VMEAS)
Input signal (VM) is commonly located halfway between VL
and VH. CL (CREF)
The Output test setup is shown in Figure 9. A termination
DS312-3_04_102406
voltage VT is applied to the termination resistor RT, the other
end of which is connected to the Output. For each standard, Notes:
RT and VT generally take on the standard values 1. The names shown in parentheses are
used in the IBIS file.
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example, Figure 9: Output Test Setup

Table 27: Test Methods for Timing Measurement at I/Os

Inputs and
Inputs Outputs Outputs
Signal Standard
(IOSTANDARD) VREF (V) VL (V) VH (V) RT (Ω) VT (V) VM (V)
Single-Ended
LVTTL - 0 3.3 1M 0 1.4
LVCMOS33 - 0 3.3 1M 0 1.65
LVCMOS25 - 0 2.5 1M 0 1.25
LVCMOS18 - 0 1.8 1M 0 0.9
LVCMOS15 - 0 1.5 1M 0 0.75
LVCMOS12 - 0 1.2 1M 0 0.6
PCI33_3 Rising - Note 3 Note 3 25 0 0.94
Falling 25 3.3 2.03
PCI66_3 Rising - Note 3 Note 3 25 0 0.94
Falling 25 3.3 2.03
HSTL_I 0.75 VREF – 0.5 VREF + 0.5 50 0.75 VREF
HSTL_III 0.9 VREF – 0.5 VREF + 0.5 50 1.5 VREF
HSTL_I_18 0.9 VREF – 0.5 VREF + 0.5 50 0.9 VREF
HSTL_II_18 0.9 VREF – 0.5 VREF + 0.5 25 0.9 VREF
HSTL_III_18 1.1 VREF – 0.5 VREF + 0.5 50 1.8 VREF
SSTL18_I 0.9 VREF – 0.5 VREF + 0.5 50 0.9 VREF
SSTL18_II 0.9 VREF – 0.5 VREF + 0.5 25 0.9 VREF
SSTL2_I 1.25 VREF – 0.75 VREF + 0.75 50 1.25 VREF
SSTL2_II 1.25 VREF – 0.75 VREF + 0.75 25 1.25 VREF
SSTL3_I 1.5 VREF – 0.75 VREF + 0.75 50 1.5 VREF
SSTL3_II 1.5 VREF – 0.75 VREF + 0.75 25 1.5 VREF

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 DC and Switching Characteristics

Table 27: Test Methods for Timing Measurement at I/Os(Continued)

Inputs and
Inputs Outputs Outputs
Signal Standard
(IOSTANDARD) VREF (V) VL (V) VH (V) RT (Ω) VT (V) VM (V)
Differential
LVDS_25 - VICM – 0.125 VICM + 0.125 50 1.2 VICM
LVDS_33 - VICM – 0.125 VICM + 0.125 50 1.2 VICM
BLVDS_25 - VICM – 0.125 VICM + 0.125 1M 0 VICM
MINI_LVDS_25 - VICM – 0.125 VICM + 0.125 50 1.2 VICM
MINI_LVDS_33 - VICM – 0.125 VICM + 0.125 50 1.2 VICM
LVPECL_25 - VICM – 0.3 VICM + 0.3 N/A N/A VICM
LVPECL_33 - VICM – 0.3 VICM + 0.3 N/A N/A VICM
RSDS_25 - VICM – 0.1 VICM + 0.1 50 1.2 VICM
RSDS_33 - VICM – 0.1 VICM + 0.1 50 1.2 VICM
TMDS_33 - VICM – 0.1 VICM + 0.1 50 3.3 VICM
PPDS_25 - VICM – 0.1 VICM + 0.1 50 0.8 VICM
PPDS_33 - VICM – 0.1 VICM + 0.1 50 0.8 VICM
DIFF_HSTL_I - VICM – 0.5 VICM + 0.5 50 0.75 VICM
DIFF_HSTL_III - VICM – 0.5 VICM + 0.5 50 1.5 VICM
DIFF_HSTL_I_18 - VICM – 0.5 VICM + 0.5 50 0.9 VICM
DIFF_HSTL_II_18 - VICM – 0.5 VICM + 0.5 50 0.9 VICM
DIFF_HSTL_III_18 - VICM – 0.5 VICM + 0.5 50 1.8 VICM
DIFF_SSTL18_I - VICM – 0.5 VICM + 0.5 50 0.9 VICM
DIFF_SSTL18_II - VICM – 0.5 VICM + 0.5 50 0.9 VICM
DIFF_SSTL2_I - VICM – 0.5 VICM + 0.5 50 1.25 VICM
DIFF_SSTL2_II - VICM – 0.5 VICM + 0.5 50 1.25 VICM
DIFF_SSTL3_I - VICM – 0.5 VICM + 0.5 50 1.5 VICM
DIFF_SSTL3_II - VICM – 0.5 VICM + 0.5 50 1.5 VICM

Notes:
1. Descriptions of the relevant symbols are as follows:
VREF – The reference voltage for setting the input switching threshold
VICM – The common mode input voltage
VM – Voltage of measurement point on signal transition
VL – Low-level test voltage at Input pin
VH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required
VT – Termination voltage
2. The load capacitance (CL) at the Output pin is 0 pF for all signal standards.
3. According to the PCI specification.

The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the
speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for
all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those
measurements to produce the final timing numbers as published in the speed files and data sheet.

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DC and Switching Characteristics

Using IBIS Models to Simulate Load Conditions in Application

IBIS models permit the most accurate prediction of timing 1. Simulate the desired signal standard with the output
delays for a given application. The parameters found in the driver connected to the test setup shown in Figure 9.
IBIS model (VREF, RREF, and VMEAS) correspond directly Use parameter values VT, RT, and VM from Table 27.
with the parameters used in Table 27 (VT, RT, and VM). Do CREF is zero.
not confuse VREF (the termination voltage) from the IBIS 2. Record the time to VM.
model with VREF (the input-switching threshold) from the
table. A fourth parameter, CREF, is always zero. The four 3. Simulate the same signal standard with the output driver
parameters describe all relevant output test conditions. IBIS connected to the PCB trace with load. Use the
models are found in the Xilinx development software as well appropriate IBIS model (including VREF, RREF, CREF,
as at the following link: and VMEAS values) or capacitive value to represent the
load.
www.xilinx.com/support/download/index.htm
4. Record the time to VMEAS.
Delays for a given application are simulated according to its 5. Compare the results of steps 2 and 4. Add (or subtract)
specific load conditions as follows: the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 26) to
yield the worst-case delay of the PCB trace.

Simultaneously Switching Output Guidelines

This section provides guidelines for the recommended Table 28 and Table 29 provide the essential SSO guidelines.
maximum allowable number of Simultaneous Switching For each device/package combination, Table 28 provides
Outputs (SSOs). These guidelines describe the maximum the number of equivalent VCCO/GND pairs. The equivalent
number of user I/O pins of a given output signal standard number of pairs is based on characterization and may not
that should simultaneously switch in the same direction, match the physical number of pairs. For each output signal
while maintaining a safe level of switching noise. Meeting standard and drive strength, Table 29 recommends the
these guidelines for the stated test conditions ensures that maximum number of SSOs, switching in the same direction,
the FPGA operates free from the adverse effects of ground allowed per VCCO/GND pair within an I/O bank. The
and power bounce. guidelines in Table 29 are categorized by package style,
slew rate, and output drive current. Furthermore, the
Ground or power bounce occurs when a large number of
number of SSOs is specified by I/O bank. Generally, the left
outputs simultaneously switch in the same direction. The
and right I/O banks (Banks 1 and 3) support higher output
output drive transistors all conduct current to a common
drive current.
voltage rail. Low-to-High transitions conduct to the VCCO
rail; High-to-Low transitions conduct to the GND rail. The Multiply the appropriate numbers from Table 28 and
resulting cumulative current transient induces a voltage Table 29 to calculate the maximum number of SSOs allowed
difference across the inductance that exists between the die within an I/O bank. Exceeding these SSO guidelines might
pad and the power supply or ground return. The inductance result in increased power or ground bounce, degraded
is associated with bonding wires, the package lead frame, signal integrity, or increased system jitter.
and any other signal routing inside the package. Other
SSOMAX/IO Bank = Table 28 x Table 29
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at The recommended maximum SSO values assume that the
receivers. Any SSO-induced voltage consequently affects FPGA is soldered on the printed circuit board and that the
internal switching noise margins and ultimately signal board uses sound design practices. The SSO values do not
quality. apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
The SSO values assume that the VCCAUX is powered at
3.3V. Setting VCCAUX to 2.5V provides better SSO
characteristics.
The number of SSOs allowed for quad-flat packages
(VQ/TQ) is lower than for ball grid array packages (FG) due
to the larger lead inductance of the quad-flat packages. Ball
grid array packages are recommended for applications with
a large number of simultaneously switching outputs.

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 DC and Switching Characteristics

Table 28: Equivalent VCCO/GND Pairs per Bank

Package Style (including Pb-free)
Device VQ100 TQ144 FT256 FG320 FG400 FG484 FG676
XC3S50A 1 2 3 – – – –
XC3S200A 1 – 4 4 – – –
XC3S400A – – 4 4 5 – –
XC3S700A – – 4 – 5 5 –
XC3S1400A – – 4 – – 6 9

Table 29: Recommended Number of Simultaneously Switching Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V) Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued)

Package Type Package Type

FT256, FG320, FT256, FG320,
FG400, FG484, FG400, FG484,
VQ100, TQ144 FG676 VQ100, TQ144 FG676
Top, Left, Top, Left, Top, Left, Top, Left,
Bottom Right Bottom Right Bottom Right Bottom Right
Signal Standard (Banks (Banks (Banks (Banks Signal Standard (Banks (Banks (Banks (Banks
(IOSTANDARD) 0,2) 1,3) 0,2) 1,3) (IOSTANDARD) 0,2) 1,3) 0,2) 1,3)

Single-Ended Standards LVCMOS33 Slow 2 24 24 76 76

LVTTL Slow 2 20 20 60 60 4 14 14 46 46
4 10 10 41 41 6 11 11 27 27
6 10 10 29 29 8 10 10 20 20
8 6 6 22 22 12 9 9 13 13
12 6 6 13 13 16 8 8 10 10
16 5 5 11 11 24 – 8 – 9
24 4 4 9 9 Fast 2 10 10 10 10
Fast 2 10 10 10 10 4 8 8 8 8
4 6 6 6 6 6 5 5 5 5
6 5 5 5 5 8 4 4 4 4
8 3 3 3 3 12 4 4 4 4
12 3 3 3 3 16 2 2 2 2
16 3 3 3 3 24 – 2 – 2
24 2 2 2 2 QuietIO 2 36 36 76 76
QuietIO 2 40 40 80 80 4 32 32 46 46
4 24 24 48 48 6 24 24 32 32
6 20 20 36 36 8 16 16 26 26
8 16 16 27 27 12 16 16 18 18
12 12 12 16 16 16 12 12 14 14
16 9 9 13 13 24 – 10 – 10
24 9 9 12 12

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DC and Switching Characteristics

Table 29: Recommended Number of Simultaneously Switching Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued) Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued)
Package Type Package Type
FT256, FG320, FT256, FG320,
FG400, FG484, FG400, FG484,
VQ100, TQ144 FG676 VQ100, TQ144 FG676
Top, Left, Top, Left, Top, Left, Top, Left,
Bottom Right Bottom Right Bottom Right Bottom Right
Signal Standard (Banks (Banks (Banks (Banks Signal Standard (Banks (Banks (Banks (Banks
(IOSTANDARD) 0,2) 1,3) 0,2) 1,3) (IOSTANDARD) 0,2) 1,3) 0,2) 1,3)
LVCMOS25 Slow 2 16 16 76 76 LVCMOS15 Slow 2 12 12 55 55
4 10 10 46 46 4 7 7 31 31
6 8 8 33 33 6 7 7 18 18
8 7 7 24 24 8 – 6 – 15
12 6 6 18 18 12 – 5 – 10
16 – 6 – 11 Fast 2 10 10 25 25
24 – 5 – 7 4 7 7 10 10
Fast 2 12 12 18 18 6 6 6 6 6
4 10 10 14 14 8 – 4 – 4
6 8 8 6 6 12 – 3 – 3
8 6 6 6 6 QuietIO 2 30 30 70 70
12 3 3 3 3 4 21 21 40 40
16 – 3 – 3 6 18 18 31 31
24 – 2 – 2 8 – 12 – 31
QuietIO 2 36 36 76 76 12 – 12 – 20
4 30 30 60 60 LVCMOS12 Slow 2 17 17 40 40
6 24 24 48 48 4 – 13 – 25
8 20 20 36 36 6 – 10 – 18
12 12 12 36 36 Fast 2 12 9 31 31
16 – 12 – 36 4 – 9 – 13
24 – 8 – 8 6 – 9 – 9
LVCMOS18 Slow 2 13 13 64 64 QuietIO 2 36 36 55 55
4 8 8 34 34 4 – 33 – 36
6 8 8 22 22 6 – 27 – 36
8 7 7 18 18 PCI33_3 9 9 16 16
12 – 5 – 13 PCI66_3 – 9 – 13
16 – 5 – 10 HSTL_I – 11 – 20
Fast 2 13 13 18 18 HSTL_III – 7 – 8
4 8 8 9 9 HSTL_I_18 13 13 17 17
6 7 7 7 7 HSTL_II_18 – 5 – 5
8 4 4 4 4 HSTL_III_18 8 8 10 8
12 – 4 – 4 SSTL18_I 7 13 7 15
16 – 3 – 3 SSTL18_II – 9 – 9
QuietIO 2 30 30 64 64 SSTL2_I 10 10 18 18
4 24 24 64 64 SSTL2_II – 6 – 9
6 20 20 48 48 SSTL3_I 7 8 8 10
8 16 16 36 36 SSTL3_II 5 6 6 7
12 – 12 – 36
16 – 12 – 24

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 DC and Switching Characteristics

Table 29: Recommended Number of Simultaneously Switching

Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued)
Package Type
FT256, FG320,
FG400, FG484,
VQ100, TQ144 FG676
Top, Left, Top, Left,
Bottom Right Bottom Right
Signal Standard (Banks (Banks (Banks (Banks
(IOSTANDARD) 0,2) 1,3) 0,2) 1,3)
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25 8 – 22 –
LVDS_33 8 – 27 –
BLVDS_25 1 1 4 4
MINI_LVDS_25 8 – 22 –
MINI_LVDS_33 8 – 27 –
LVPECL_25 Input Only
LVPECL_33 Input Only
RSDS_25 8 – 22 –
RSDS_33 8 – 27 –
TMDS_33 8 – 27 –
PPDS_25 8 – 22 –
PPDS_33 8 – 27 –
DIFF_HSTL_I – 5 – 10
DIFF_HSTL_III – 3 – 4
DIFF_HSTL_I_18 6 6 8 8
DIFF_HSTL_II_18 – 2 – 2
DIFF_HSTL_III_18 4 4 5 4
DIFF_SSTL18_I 3 6 3 7
DIFF_SSTL18_II – 4 – 4
DIFF_SSTL2_I 5 5 9 9
DIFF_SSTL2_II – 3 – 4
DIFF_SSTL3_I 3 4 4 5
DIFF_SSTL3_II 2 3 3 3
Notes:
1. Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in top
or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
2. The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the VIL/VIH voltage
limits for the respective I/O standard.
3. If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.

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DC and Switching Characteristics

Configurable Logic Block (CLB) Timing

Table 30: CLB (SLICEM) Timing
Speed Grade
-5 -4
Symbol Description Min Max Min Max Units
Clock-to-Output Times
TCKO When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data – 0.60 – 0.68 ns
appearing at the XQ (YQ) output
Setup Times
TAS Time from the setup of data at the F or G input to the 0.18 – 0.36 – ns
active transition at the CLK input of the CLB
TDICK Time from the setup of data at the BX or BY input to 1.58 – 1.88 – ns
the active transition at the CLK input of the CLB
Hold Times
TAH Time from the active transition at the CLK input to the 0 – 0 – ns
point where data is last held at the F or G input
TCKDI Time from the active transition at the CLK input to the 0 – 0 – ns
point where data is last held at the BX or BY input
Clock Timing
TCH The High pulse width of the CLB’s CLK signal 0.63 – 0.75 – ns
TCL The Low pulse width of the CLK signal 0.63 – 0.75 – ns
FTOG Toggle frequency (for export control) 0 770 0 667 MHz
Propagation Times
TILO The time it takes for data to travel from the CLB’s F – 0.62 – 0.71 ns
(G) input to the X (Y) output
Set/Reset Pulse Width
TRPW_CLB The minimum allowable pulse width, High or Low, to 1.33 – 1.61 – ns
the CLB’s SR input

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.

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 DC and Switching Characteristics

Table 31: CLB Distributed RAM Switching Characteristics

-5 -4
Symbol Description Min Max Min Max Units
Clock-to-Output Times
TSHCKO Time from the active edge at the CLK input to data appearing on – 1.69 – 2.01 ns
the distributed RAM output
Setup Times
TDS Setup time of data at the BX or BY input before the active –0.07 – –0.02 – ns
transition at the CLK input of the distributed RAM
TAS Setup time of the F/G address inputs before the active transition 0.18 – 0.36 – ns
at the CLK input of the distributed RAM
TWS Setup time of the write enable input before the active transition at 0.30 – 0.59 – ns
the CLK input of the distributed RAM
Hold Times
TDH Hold time of the BX and BY data inputs after the active transition 0.13 – 0.13 – ns
at the CLK input of the distributed RAM
TAH, TWH Hold time of the F/G address inputs or the write enable input after 0.01 – 0.01 – ns
the active transition at the CLK input of the distributed RAM
Clock Pulse Width
TWPH, TWPL Minimum High or Low pulse width at CLK input 0.88 – 1.01 – ns

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.

Table 32: CLB Shift Register Switching Characteristics

-5 -4
Symbol Description Min Max Min Max Units
Clock-to-Output Times
TREG Time from the active edge at the CLK input to data appearing on – 4.11 – 4.82 ns
the shift register output
Setup Times
TSRLDS Setup time of data at the BX or BY input before the active 0.13 – 0.18 – ns
transition at the CLK input of the shift register
Hold Times
TSRLDH Hold time of the BX or BY data input after the active transition at 0.16 – 0.16 – ns
the CLK input of the shift register
Clock Pulse Width
TWPH, TWPL Minimum High or Low pulse width at CLK input 0.90 – 1.01 – ns

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.

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DC and Switching Characteristics

Clock Buffer/Multiplexer Switching Characteristics

Table 33: Clock Distribution Switching Characteristics
Maximum
Speed Grade
Description Symbol Minimum -5 -4 Units
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to TGIO – 0.22 0.23 ns
O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and TGSI – 0.56 0.63 ns
I1 inputs. Same as BUFGCE enable CE-input
Frequency of signals distributed on global buffers (all sides) FBUFG 0 350 334 MHz

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.

44 www.xilinx.com DS529 (v2.1) December 18, 2018

 DC and Switching Characteristics

18 x 18 Embedded Multiplier Timing

Table 34: 18 x 18 Embedded Multiplier Timing
Speed Grade
-5 -4
Symbol Description Min Max Min Max Units
Combinatorial Delay
TMULT Combinational multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product – 4.36 – 4.88 ns
(AREG, BREG, and PREG registers unused)
Clock-to-Output Times
TMSCKP_P Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG – 0.84 – 1.30 ns
register(2,3)
TMSCKP_A Clock-to-output delay from the active transition of the CLK input to
TMSCKP_B valid data appearing on the P outputs when using either the AREG – 4.44 – 4.97 ns
or BREG register(2,4)
Setup Times
TMSDCK_P Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG 3.56 – 3.98 – ns
registers unused)(3)
TMSDCK_A Data setup time at the A input before the active transition at the CLK 0.00 – 0.00 – ns
when using the AREG input register(4)
TMSDCK_B Data setup time at the B input before the active transition at the CLK 0.00 – 0.00 – ns
when using the BREG input register(4)
Hold Times
TMSCKD_P Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG 0.00 – 0.00 – ns
registers unused)(3)
TMSCKD_A Data hold time at the A input after the active transition at the CLK 0.35 – 0.45 – ns
when using the AREG input register(4)
TMSCKD_B Data hold time at the B input after the active transition at the CLK 0.35 – 0.45 – ns
when using the BREG input register(4)
Clock Frequency
FMULT Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output 0 280 0 250 MHz
register(1)

Notes:
1. Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3. The PREG register is typically used when inferring a single-stage multiplier.
4. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
5. The numbers in this table are based on the operating conditions set forth in Table 8.

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DC and Switching Characteristics

Block RAM Timing

Table 35: Block RAM Timing
Speed Grade
-5 -4
Symbol Description Min Max Min Max Units
Clock-to-Output Times
TRCKO When reading from block RAM, the delay from the active
transition at the CLK input to data appearing at the DOUT – 2.06 – 2.49 ns
output
Setup Times
TRCCK_ADDR Setup time for the ADDR inputs before the active transition at 0.32 – 0.36 – ns
the CLK input of the block RAM
TRDCK_DIB Setup time for data at the DIN inputs before the active 0.28 – 0.31 – ns
transition at the CLK input of the block RAM
TRCCK_ENB Setup time for the EN input before the active transition at the 0.69 – 0.77 – ns
CLK input of the block RAM
TRCCK_WEB Setup time for the WE input before the active transition at the 1.12 – 1.26 – ns
CLK input of the block RAM
Hold Times
TRCKC_ADDR Hold time on the ADDR inputs after the active transition at the 0 – 0 – ns
CLK input
TRCKD_DIB Hold time on the DIN inputs after the active transition at the 0 – 0 – ns
CLK input
TRCKC_ENB Hold time on the EN input after the active transition at the CLK 0 – 0 – ns
input
TRCKC_WEB Hold time on the WE input after the active transition at the CLK 0 – 0 – ns
input
Clock Timing
TBPWH High pulse width of the CLK signal 1.56 – 1.79 – ns
TBPWL Low pulse width of the CLK signal 1.56 – 1.79 – ns
Clock Frequency
FBRAM Block RAM clock frequency 0 320 0 280 MHz

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.

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 DC and Switching Characteristics

Digital Clock Manager (DCM) Timing

For specification purposes, the DCM consists of three key Period jitter is the worst-case deviation from the ideal clock
components: the Delay-Locked Loop (DLL), the Digital period over a collection of millions of samples. In a
Frequency Synthesizer (DFS), and the Phase Shifter (PS). histogram of period jitter, the mean value is the clock period.
Aspects of DLL operation play a role in all DCM applications. Cycle-cycle jitter is the worst-case difference in clock period
All such applications inevitably use the CLKIN and the between adjacent clock cycles in the collection of clock
CLKFB inputs connected to either the CLK0 or the CLK2X periods sampled. In a histogram of cycle-cycle jitter, the
feedback, respectively. Thus, specifications in the DLL mean value is zero.
tables (Table 36 and Table 37) apply to any application that
only employs the DLL component. When the DFS and/or the Spread Spectrum
PS components are used together with the DLL, then the DCMs accept typical spread spectrum clocks as long as
specifications listed in the DFS and PS tables (Table 38 they meet the input requirements. The DLL will track the
through Table 41) supersede any corresponding ones in the frequency changes created by the spread spectrum clock to
DLL tables. DLL specifications that do not change with the drive the global clocks to the FPGA logic. See XAPP469,
addition of DFS or PS functions are presented in Table 36 Spread-Spectrum Clocking Reception for Displays for
and Table 37. details.
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.

Delay-Locked Loop (DLL)

Table 36: Recommended Operating Conditions for the DLL
Speed Grade
-5 -4
Symbol Description Min Max Min Max Units
Input Frequency Ranges
FCLKIN CLKIN_FREQ_DLL Frequency of the CLKIN clock input 5(2) 280(3) 5(2) 250(3) MHz
Input Pulse Requirements
CLKIN_PULSE CLKIN pulse width as a FCLKIN < 150 MHz 40% 60% 40% 60% –
percentage of the CLKIN
period FCLKIN > 150 MHz 45% 55% 45% 55% –

Input Clock Jitter Tolerance and Delay Path Variation(4)

CLKIN_CYC_JITT_DLL_LF Cycle-to-cycle jitter at the FCLKIN < 150 MHz – ±300 – ±300 ps
CLKIN input
CLKIN_CYC_JITT_DLL_HF FCLKIN > 150 MHz – ±150 – ±150 ps
CLKIN_PER_JITT_DLL Period jitter at the CLKIN input – ±1 – ±1 ns
CLKFB_DELAY_VAR_EXT Allowable variation of off-chip feedback delay ±1 ±1 ns
– –
from the DCM output to the CLKFB input

Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 38.
3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
4. CLKIN input jitter beyond these limits might cause the DCM to lose lock.
5. The DCM specifications are guaranteed when both adjacent DCMs are locked.

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DC and Switching Characteristics

Table 37: Switching Characteristics for the DLL

Speed Grade
-5 -4
Symbol Description Device Min Max Min Max Units
Output Frequency Ranges
CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs All 5 280 5 250 MHz
CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs 5 200 5 200 MHz
CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs 10 334 10 334 MHz
CLKOUT_FREQ_DV Frequency for the CLKDV output 0.3125 186 0.3125 166 MHz
Output Clock Jitter(2,3,4)
CLKOUT_PER_JITT_0 Period jitter at the CLK0 output All – ±100 – ±100 ps
CLKOUT_PER_JITT_90 Period jitter at the CLK90 output – ±150 – ±150 ps
CLKOUT_PER_JITT_180 Period jitter at the CLK180 output – ±150 – ±150 ps
CLKOUT_PER_JITT_270 Period jitter at the CLK270 output – ±150 – ±150 ps
CLKOUT_PER_JITT_2X Period jitter at the CLK2X and CLK2X180 outputs ±[0.5% ±[0.5% ps
of CLKIN of CLKIN
– period – period
+ 100] + 100]
CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing integer – ±150 – ±150 ps
division
CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing non-integer ±[0.5% ±[0.5% ps
division of CLKIN of CLKIN
– period – period
+ 100] + 100]
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, All ±[1% of ±[1% of ps
CLK2X, CLK2X180, and CLKDV outputs, including the CLKIN CLKIN
BUFGMUX and clock tree duty-cycle distortion – period – period
+ 350] + 350]
Phase Alignment(4)
CLKIN_CLKFB_PHASE Phase offset between the CLKIN and CLKFB inputs All – ±150 – ±150 ps
CLKOUT_PHASE_DLL Phase offset between DLL outputs CLK0 to CLK2X ±[1% of ±[1% of ps
(not CLK2X180) CLKIN CLKIN
– period – period
+ 100] + 100]
All others ±[1% of ±[1% of ps
CLKIN CLKIN
– period – period
+ 150] + 150]
Lock Time
LOCK_DLL(3) When using the DLL alone: The 5 MHz < FCLKIN < 15 MHz All – 5 – 5 ms
time from deassertion at the DCM’s
Reset input to the rising transition FCLKIN > 15 MHz – 600 – 600 µs
at its LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase
Delay Lines
DCM_DELAY_STEP(5) Finest delay resolution, averaged over all steps All 15 35 15 35 ps

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 36.
2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter of
“±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps.
According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps.
5. The typical delay step size is 23 ps.

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 DC and Switching Characteristics

Digital Frequency Synthesizer (DFS)

Table 38: Recommended Operating Conditions for the DFS
Speed Grade
-5 -4
Symbol Description Min Max Min Max Units
Input Frequency Ranges(2)
FCLKIN CLKIN_FREQ_FX Frequency for the CLKIN input 0.200 333(4) 0.200 333(4) MHz
Input Clock Jitter Tolerance(3)
CLKIN_CYC_JITT_FX_LF Cycle-to-cycle jitter at the CLKIN FCLKFX < 150 MHz – ±300 – ±300 ps
input, based on CLKFX output
CLKIN_CYC_JITT_FX_HF frequency FCLKFX > 150 MHz – ±150 – ±150 ps
CLKIN_PER_JITT_FX Period jitter at the CLKIN input – ±1 – ±1 ns

Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 36.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
4. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.

Table 39: Switching Characteristics for the DFS

Speed Grade

-5 -4

Symbol Description Device Min Max Min Max Units

Output Frequency Ranges
CLKOUT_FREQ_FX(2) Frequency for the CLKFX and CLKFX180 outputs All 5 350 5 320 MHz
Output Clock Jitter(3,4)
CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180 All Typ Max Typ Max
outputs.
CLKIN Use the Spartan-3A Jitter Calculator: ps
≤ 20 MHz www.xilinx.com/support/documentatio
n/data_sheets/s3a_jitter_calc.zip
CLKIN ±[1% of ±[1% of ±[1% of ±[1% of ps
> 20 MHz CLKFX CLKFX CLKFX CLKFX
period period period period
+ 100] + 200] + 100] + 200]
Duty Cycle(5,6)
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs, All ±[1% of ±[1% of ps
including the BUFGMUX and clock tree duty-cycle distortion CLKFX CLKFX
– period – period
+ 350] + 350]
Phase Alignment(6)
CLKOUT_PHASE_FX Phase offset between the DFS CLKFX output and the DLL All ±200 ±200 ps
CLK0 output when both the DFS and DLL are used – –

CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX180 output and the DLL All ±[1% of ±[1% of ps
CLK0 output when both the DFS and DLL are used CLKFX CLKFX
– period – period
+ 200] + 200]

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DC and Switching Characteristics

Table 39: Switching Characteristics for the DFS(Continued)

Speed Grade
-5 -4

Symbol Description Device Min Max Min Max Units

Lock Time
LOCK_FX(2, 3) The time from deassertion at the DCM’s 5 MHz < FCLKIN All 5 5 ms
Reset input to the rising transition at its < 15 MHz – –
LOCKED output. The DFS asserts
LOCKED when the CLKFX and CLKFX180 FCLKIN > 450 450 µs
signals are valid. If using both the DLL and 15 MHz – –
the DFS, use the longer locking time.

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 38.
2. DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching)
on an XC3S1400A FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB
utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the
system application.
5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
6. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.

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 DC and Switching Characteristics

Phase Shifter (PS)

Table 40: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
-5 -4
Symbol Description Min Max Min Max Units
Operating Frequency Ranges
PSCLK_FREQ Frequency for the PSCLK input 1 167 1 167 MHz
(FPSCLK)
Input Pulse Requirements
PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period 40% 60% 40% 60% -

Table 41: Switching Characteristics for the PS in Variable Phase Mode

Symbol Description Phase Shift Amount Units

Phase Shifting Range

MAX_STEPS(2) Maximum allowed number of CLKIN < 60 ±[INTEGER(10 • (TCLKIN – 3 ns))] steps
DCM_DELAY_STEP steps for a MHz
given CLKIN clock period, where
T = CLKIN clock period in ns. If using CLKIN ≥ 60 ±[INTEGER(15 • (TCLKIN – 3 ns))]
CLKIN_DIVIDE_BY_2 = TRUE, MHz
double the clock effective clock
period.
FINE_SHIFT_RANGE_MIN Minimum guaranteed delay for variable phase shifting ±[MAX_STEPS • ns
DCM_DELAY_STEP_MIN]
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting ±[MAX_STEPS • ns
DCM_DELAY_STEP_MAX]

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 40.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 37.

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DC and Switching Characteristics

Miscellaneous DCM Timing

Table 42: Miscellaneous DCM Timing
Symbol Description Min Max Units
DCM_RST_PW_MIN Minimum duration of a RST pulse width 3 CLKIN
– cycles
DCM_RST_PW_MAX(2) Maximum duration of a RST pulse width N/A N/A seconds
N/A N/A seconds
DCM_CONFIG_LAG_TIME(3) Maximum duration from VCCINT applied to FPGA configuration N/A N/A minutes
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL N/A N/A minutes

Notes:
1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
2. This specification is equivalent to the Virtex®-4 DCM_RESET specification. This specification does not apply for Spartan-3A FPGAs.
3. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3A FPGAs.

DNA Port Timing

Table 43: DNA_PORT Interface Timing
Symbol Description Min Max Units
TDNASSU Setup time on SHIFT before the rising edge of CLK 1.0 – ns
TDNASH Hold time on SHIFT after the rising edge of CLK 0.5 – ns
TDNADSU Setup time on DIN before the rising edge of CLK 1.0 – ns
TDNADH Hold time on DIN after the rising edge of CLK 0.5 – ns
TDNARSU Setup time on READ before the rising edge of CLK 5.0 10,000 ns
TDNARH Hold time on READ after the rising edge of CLK 0 – ns
TDNADCKO Clock-to-output delay on DOUT after rising edge of CLK 0.5 1.5 ns
TDNACLKF CLK frequency 0 100 MHz
TDNACLKH CLK High time 1.0 ∞ ns
TDNACLKL CLK Low time 1.0 ∞ ns

Notes:
1. The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 µs.
2. The numbers in this table are based on the operating conditions set forth in Table 8.

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 DC and Switching Characteristics

Suspend Mode Timing

Entering Suspend Mode Exiting Suspend Mode

sw_gwe_cycle
sw_gts_cycle
SUSPEND Input

tSUSPENDHIGH_AWAKE tSUSPENDLOW_AWAKE

AWAKE Output
tSUSPEND_GWE tAWAKE_GWE

Flip-Flops, Block RAM, Write Protected

Distributed RAM
tSUSPEND_GTS tAWAKE_GTS

FPGA Outputs Defined by SUSPEND constraint

tSUSPEND_DISABLE tSUSPEND_ENABLE
FPGA Inputs,
Blocked
Interconnect
DS610-3_08_061207

Figure 10: Suspend Mode Timing

Table 44: Suspend Mode Timing Parameters

Symbol Description Min Typ Max Units
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter – 7 – ns
(suspend_filter:No)
TSUSPENDFILTER Adjustment to SUSPEND pin rising edge parameters when glitch filter +160 +300 +600 ns
enabled (suspend_filter:Yes)
TSUSPEND_GTS Rising edge of SUSPEND pin until FPGA output pins drive their defined – 10 – ns
SUSPEND constraint behavior
TSUSPEND_GWE Rising edge of SUSPEND pin to write-protect lock on all writable clocked – <5 – ns
elements
TSUSPEND_DISABLE Rising edge of the SUSPEND pin to FPGA input pins and interconnect – 340 – ns
disabled
Exiting Suspend Mode
TSUSPENDLOW_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not – 4 to 108 – µs
include DCM lock time.
TSUSPEND_ENABLE Falling edge of the SUSPEND pin to FPGA input pins and interconnect – 3.7 to 109 – µs
re-enabled
TAWAKE_GWE1 Rising edge of the AWAKE pin until write-protect lock released on all writable – 67 – ns
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
TAWAKE_GWE512 Rising edge of the AWAKE pin until write-protect lock released on all writable – 14 – µs
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
TAWAKE_GTS1 Rising edge of the AWAKE pin until outputs return to the behavior described – 57 – ns
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
TAWAKE_GTS512 Rising edge of the AWAKE pin until outputs return to the behavior described – 14 – µs
in the FPGA application, using sw_clk:InternalClock and
sw_gts_cycle:512.

Notes:
1. These parameters based on characterization.
2. For information on using the Spartan-3A Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.

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DC and Switching Characteristics

Configuration and JTAG Timing

General Configuration Power-On/Reconfigure Timing

VCCINT 1.2V
(Supply) 1.0V

VCCAUX 2.5V
2.0V or
(Supply) 3.3V
VCCO Bank 2 2.5V
(Supply) 2.0V or
3.3V
TPOR
PROG_B
(Input)
TPROG TPL
INIT_B
(Open-Drain)
TICCK
CCLK
(Output)
DS529-3_01_052708

Notes:
1. The VCCINT, VCCAUX, and VCCO supplies can be applied in any order.
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).

Figure 11: Waveforms for Power-On and the Beginning of Configuration

Table 45: Power-On Timing and the Beginning of Configuration

All Speed Grades
Symbol Description Device Min Max Units
TPOR(2) The time from the application of VCCINT, VCCAUX, and VCCO All – 18 ms
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
TPROG The width of the low-going pulse on the PROG_B pin All 0.5 - µs
TPL(2) The time from the rising edge of the PROG_B pin to the XC3S50A – 0.5 ms
rising transition on the INIT_B pin
XC3S200A – 0.5 ms
XC3S400A – 1 ms
XC3S700A – 2 ms
XC3S1400A – 2 ms
TINIT Minimum Low pulse width on INIT_B output All 250 – ns
TICCK(3) The time from the rising edge of the INIT_B pin to the All 0.5 4 µs
generation of the configuration clock signal at the CCLK
output pin

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8. This means power must be applied to all VCCINT, VCCO,
and VCCAUX lines.
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the Master Serial, SPI, and BPI modes.
4. For details on configuration, see UG332 Spartan-3 Generation Configuration User Guide.

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 DC and Switching Characteristics

Configuration Clock (CCLK) Characteristics

Table 46: Master Mode CCLK Output Period by ConfigRate Opti0on Setting
ConfigRate Temperature
Symbol Description Setting Range Minimum Maximum Units
CCLK clock period by 1 Commercial 1,254 ns
TCCLK1 ConfigRate setting (power-on value) 2,500
Industrial 1,180 ns
Commercial 413 ns
TCCLK3 3 833
Industrial 390 ns
Commercial 207 ns
TCCLK6 6 (default) 417
Industrial 195 ns
Commercial 178 ns
TCCLK7 7 357
Industrial 168 ns
Commercial 156 ns
TCCLK8 8 313
Industrial 147 ns
Commercial 123 ns
TCCLK10 10 250
Industrial 116 ns
Commercial 103 ns
TCCLK12 12 208
Industrial 97 ns
Commercial 93 ns
TCCLK13 13 192
Industrial 88 ns
Commercial 72 ns
TCCLK17 17 147
Industrial 68 ns
Commercial 54 ns
TCCLK22 22 114
Industrial 51 ns
Commercial 47 ns
TCCLK25 25 100
Industrial 45 ns
Commercial 44 ns
TCCLK27 27 93
Industrial 42 ns
Commercial 36 ns
TCCLK33 33 76
Industrial 34 ns
Commercial 26 ns
TCCLK44 44 57
Industrial 25 ns
Commercial 22 ns
TCCLK50 50 50
Industrial 21 ns
Commercial 11.2 ns
TCCLK100 100 25
Industrial 10.6 ns

Notes:
1. Set the ConfigRate option value when generating a configuration bitstream.

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DC and Switching Characteristics

Table 47: Master Mode CCLK Output Frequency by ConfigRate Option Setting
ConfigRate Temperature
Symbol Description Setting Range Minimum Maximum Units
Equivalent CCLK clock frequency 1 Commercial 0.797 MHz
FCCLK1 by ConfigRate setting 0.400
(power-on value) Industrial 0.847 MHz
Commercial 2.42 MHz
FCCLK3 3 1.20
Industrial 2.57 MHz

6 Commercial 4.83 MHz

FCCLK6 (default) 2.40
Industrial 5.13 MHz
Commercial 5.61 MHz
FCCLK7 7 2.80
Industrial 5.96 MHz
Commercial 6.41 MHz
FCCLK8 8 3.20
Industrial 6.81 MHz
Commercial 8.12 MHz
FCCLK10 10 4.00
Industrial 8.63 MHz
Commercial 9.70 MHz
FCCLK12 12 4.80
Industrial 10.31 MHz
Commercial 10.69 MHz
FCCLK13 13 5.20
Industrial 11.37 MHz
Commercial 13.74 MHz
FCCLK17 17 6.80
Industrial 14.61 MHz
Commercial 18.44 MHz
FCCLK22 22 8.80
Industrial 19.61 MHz
Commercial 20.90 MHz
FCCLK25 25 10.00
Industrial 22.23 MHz
Commercial 22.39 MHz
FCCLK27 27 10.80
Industrial 23.81 MHz
Commercial 27.48 MHz
FCCLK33 33 13.20
Industrial 29.23 MHz
Commercial 37.60 MHz
FCCLK44 44 17.60
Industrial 40.00 MHz
Commercial 44.80 MHz
FCCLK50 50 20.00
Industrial 47.66 MHz
Commercial 88.68 MHz
FCCLK100 100 40.00
Industrial 94.34 MHz

Table 48: Master Mode CCLK Output Minimum Low and High Time
ConfigRate Setting

Symbol Description 1 3 6 7 8 10 12 13 17 22 25 27 33 44 50 100 Units

Master Mode Commercial 595 196 98.3 84.5 74.1 58.4 48.9 44.1 34.2 25.6 22.3 20.9 17.1 12.3 10.4 5.3 ns
TMCCL, CCLK
TMCCH Minimum Low Industrial 560 185 92.6 79.8 69.8 55.0 46.0 41.8 32.3 24.2 21.4 20.0 16.2 11.9 10.0 5.0 ns
and High Time

Table 49: Slave Mode CCLK Input Low and High Time
Symbol Description Min Max Units
TSCCL, CCLK Low and High time 5 ∞ ns
TSCCH

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 DC and Switching Characteristics

Master Serial and Slave Serial Mode Timing

PROG_B
(Input)

INIT_B
(Open-Drain) TMCCH
TMCCL
TSCCL TSCCH

CCLK
(Input/Output)
TDCC TCCD 1/FCCSER

DIN
(Input) Bit 0 Bit 1 Bit n Bit n+1

TCCO

DOUT
Bit n-64 Bit n-63
(Output)

DS312-3_05_103105

Figure 12: Waveforms for Master Serial and Slave Serial Configuration

Table 50: Timing for the Master Serial and Slave Serial Configuration Modes
All Speed Grades
Slave/
Symbol Description Master Min Max Units
Clock-to-Output Times
TCCO The time from the falling transition on the CCLK pin to data appearing at the Both 1.5 10 ns
DOUT pin
Setup Times
TDCC The time from the setup of data at the DIN pin to the rising transition at the Both 7 – ns
CCLK pin
Hold Times
TCCD The time from the rising transition at the CCLK pin to the point when data is Master 0 ns
last held at the DIN pin –
Slave 1.0
Clock Timing
TCCH High pulse width at the CCLK input pin Master See Table 48
Slave See Table 49
TCCL Low pulse width at the CCLK input pin Master See Table 48
Slave See Table 49
FCCSER Frequency of the clock signal at the No bitstream compression Slave 0 100 MHz
CCLK input pin
With bitstream compression 0 100 MHz

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.

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DC and Switching Characteristics

Slave Parallel Mode Timing

PROG_B
(Input)

INIT_B
(Open-Drain)
TSMCSCC TSMCCCS

CSI_B
(Input)
TSMCCW
TSMWCC

RDWR_B
(Input)
TMCCH TMCCL
TSCCH TSCCL
CCLK
(Input)
TSMDCC TSMCCD 1/FCCPAR

D0 - D7 Byte 0 Byte 1 Byte n Byte n+1

(Inputs)
DS529-3_02_051607
Notes:
1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
2. To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332 Chapter 7 section “Non-Continuous SelectMAP Data
Loading” for more details.
Figure 13: Waveforms for Slave Parallel Configuration

Table 51: Timing for the Slave Parallel Configuration Mode

All Speed Grades
Symbol Description Min Max Units
Setup Times
TSMDCC(2) The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin 7 – ns
TSMCSCC Setup time on the CSI_B pin before the rising transition at the CCLK pin 7 – ns
TSMCCW Setup time on the RDWR_B pin before the rising transition at the CCLK pin 15 – ns
Hold Times
TSMCCD The time from the rising transition at the CCLK pin to the point when data is last held at 1.0 – ns
the D0-D7 pins
TSMCCCS The time from the rising transition at the CCLK pin to the point when a logic level is last 0 – ns
held at the CSO_B pin
TSMWCC The time from the rising transition at the CCLK pin to the point when a logic level is last 0 – ns
held at the RDWR_B pin
Clock Timing
TCCH The High pulse width at the CCLK input pin 5 – ns
TCCL The Low pulse width at the CCLK input pin 5 – ns
FCCPAR Frequency of the clock signal No bitstream compression 0 80 MHz
at the CCLK input pin
With bitstream compression 0 80 MHz

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.

58 www.xilinx.com DS529 (v2.1) December 18, 2018

 DC and Switching Characteristics

Serial Peripheral Interface (SPI) Configuration Timing

PROG_B
(Input)

PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
(Input)

VS[2:0] <1:1:1>
(Input) Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
M[2:0] <0:0:1>
(Input)
TMINIT TINITM
INIT_B
(Open-Drain) New ConfigRate active

TMCCLn TCCLKn
TMCCL1 TMCCH1 TCCLK1 TMCCHn
T CCLK1

CCLK

TV

DIN Data Data Data Data

(Input)
TCSS
TDCC
TCCD
CSO_B
TCCO
Command Command
MOSI (msb) (msb-1)
TDSU T DH

Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.

Shaded values indicate specifications on attached SPI Flash PROM. DS529-3_06_102506

Figure 14: Waveforms for Serial Peripheral Interface (SPI) Configuration

Table 52: Timing for Serial Peripheral Interface (SPI) Configuration Mode
Symbol Description Minimum Maximum Units
TCCLK1 Initial CCLK clock period See Table 46
TCCLKn CCLK clock period after FPGA loads ConfigRate bitstream option setting See Table 46
TMINIT Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the 50 – ns
rising edge of INIT_B
TINITM Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the 0 – ns
rising edge of INIT_B
TCCO MOSI output valid delay after CCLK falling clock edge See Table 50
TDCC Setup time on the DIN data input before CCLK rising clock edge See Table 50
TCCD Hold time on the DIN data input after CCLK rising clock edge See Table 50

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DC and Switching Characteristics

Table 53: Configuration Timing Requirements for Attached SPI Serial Flash
Symbol Description Requirement Units
TCCS SPI serial Flash PROM chip-select time T CCS ≤ T MCCL1 – T CCO ns

TDSU SPI serial Flash PROM data input setup time ns

T DSU ≤ T MCCL1 – T CCO

TDH SPI serial Flash PROM data input hold time ns

T DH ≤ T MCCH1

TV SPI serial Flash PROM data clock-to-output time ns

T V ≤ T MCCLn – T DCC

fC or fR Maximum SPI serial Flash PROM clock frequency (also depends on 1 MHz
specific read command used) f C ≥ ---------------------------------
T CCLKn ( min )

Notes:
1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
2. Subtract additional printed circuit board routing delay as required by the application.

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 DC and Switching Characteristics

Byte Peripheral Interface (BPI) Configuration Timing

PROG_B
(Input)

PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
(Input)

M[2:0] Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
<0:1:0> input values do not matter until DONE goes High, at which point the mode pins
(Input) become user-I/O pins.
TMINIT TINITM
INIT_B
Open-Drain)
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
LDC[2:0]

HDC

CSO_B New ConfigRate active

T INITADDR TCCLK1 TCCLKn

TCCLK1
CCLK

TCCO

A[25:0] 000_0000 000_0001 Address Address Address

TAVQV TDCC TCCD
D[7:0]
Byte 0 Byte 1 Data Data Data Data
(Input)

Shaded values indicate specifications on attached parallel NOR Flash PROM.

DS529-3_05_021009

Figure 15: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration

Table 54: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
Symbol Description Minimum Maximum Units
TCCLK1 Initial CCLK clock period See Table 46
TCCLKn CCLK clock period after FPGA loads ConfigRate setting See Table 46
TMINIT Setup time on M[2:0] mode pins before the rising edge of INIT_B 50 – ns
TINITM Hold time on M[2:0] mode pins after the rising edge of INIT_B 0 – ns
TINITADDR Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted 5 5 TCCLK1
and valid cycles
TCCO Address A[25:0] outputs valid after CCLK falling edge See Table 50
TDCC Setup time on D[7:0] data inputs before CCLK rising edge See TSMDCC in Table 51
TCCD Hold time on D[7:0] data inputs after CCLK rising edge 0 – ns

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DC and Switching Characteristics

Table 55: Configuration Timing Requirements for Attached Parallel NOR BPI Flash
Symbol Description Requirement Units
TCE Parallel NOR Flash PROM chip-select time ns
T CE ≤ T INITADDR
(tELQV)
TOE Parallel NOR Flash PROM output-enable time ns
T OE ≤ T INITADDR
(tGLQV)
TACC Parallel NOR Flash PROM read access time ns
T ACC ≤ 50%T CCLKn ( min ) – T CCO – T DCC – PCB
(tAVQV)
TBYTE For x8/x16 PROMs only: BYTE# to output valid time(3) ns
T BYTE ≤ T INITADDR
(tFLQV, tFHQV)

Notes:
1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
2. Subtract additional printed circuit board routing delay as required by the application.
3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s PUDC_B pin is High or Low.

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 DC and Switching Characteristics

IEEE 1149.1/1532 JTAG Test Access Port Timing

TCCH TCCL
TCK
(Input)
1/FTCK
TTMSTCK TTCKTMS

TMS
(Input)
TTDITCK TTCKTDI

TDI
(Input)
TTCKTDO

TDO
(Output)
DS099_06_020709

Figure 16: JTAG Waveforms

Table 56: Timing for the JTAG Test Access Port

All Speed
Grades
Symbol Description Min Max Units
Clock-to-Output Times
TTCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin 1.0 11.0 ns
Setup Times
TTDITCK The time from the setup of data at the All devices and functions except those shown below 7.0 – ns
TDI pin to the rising transition at the
TCK pin Boundary scan commands (INTEST, EXTEST, 11.0
SAMPLE) on XC3S700A and XC3S1400A FPGAs
TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin 7.0 – ns
Hold Times
TTCKTDI The time from the rising transition at All functions except those shown below 0 – ns
the TCK pin to the point when data is
last held at the TDI pin Configuration commands (CFG_IN, ISC_PROGRAM) 2.0

TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the 0 – ns
TMS pin
Clock Timing
TCCH The High pulse width at the TCK pin All functions except ISC_DNA command 5 – ns
TCCL The Low pulse width at the TCK pin 5 – ns
TCCHDNA The High pulse width at the TCK pin During ISC_DNA command 10 10,000 ns
TCCLDNA The Low pulse width at the TCK pin 10 10,000 ns
FTCK Frequency of the TCK signal All operations on XC3S50A, XC3S200A, and 0 33 MHz
XC3S400A FPGAs and for BYPASS or HIGHZ
instructions on all FPGAs
All operations on XC3S700A and XC3S1400A FPGAs, 20
except for BYPASS or HIGHZ instructions

Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. For details on JTAG see Chapter 9 “JTAG Configuration Mode and Boundary-Scan” in UG332 Spartan-3 Generation Configuration User
Guide.

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DC and Switching Characteristics

Revision History
The following table shows the revision history for this document.

Date Version Revision

12/05/06 1.0 Initial release.
02/02/07 1.1 Promoted to Preliminary status. Moved Table 15 to under "DC Electrical Characteristics" section. Updated all
timing specifications for the v1.32 speed files. Added recommended Simultaneous Switching Output (SSO)
limits in Table 29. Set a 10 µs maximum pulse width for the DNA_PORT READ signal and the JTAG clock
input during the ISC_DNA command, affecting both Table 43 and Table 56. Described "External Termination
Requirements for Differential I/O." Added separate DIN hold time for Slave mode in Table 50. Corrected
wording in Table 52 and Table 54; no specifications affected.
03/16/07 1.2 Updated all AC timing specifications to the v1.34 speeds file. Promoted the XC3S700A and XC3S1400A
FPGAs offered in the -4 speed grade to Production status, as shown in Table 16. Added Note 2 to Table 39
regarding the extra logic (one LUT) automatically added by ISE 9.1i and later software revisions for any DCM
application that leverages the Digital Frequency Synthesizer (DFS). Separated some JTAG specifications by
array size or function, as shown in Table 56. Updated quiescent current limits in Table 10.
04/23/07 1.3 Updated all AC timing specifications to the v1.35 speeds file. Promoted all devices except the XC3S400A to
Production status, as shown in Table 16.
05/08/07 1.4 Updated XC3S400A to Production and v1.36 speeds file. Added banking rules and other explanatory
footnotes to Table 12 and Table 13. Corrected DIFF_SSTL3_II VOL Max in Table 14. Improved XC3S400A
Pin-to-Pin Clock-to-Output times in Table 18. Updated XC3S400A Pin-to-Pin Setup Times in Table 19.
Updated TIOICKPD for -5 in Table 20. Added SSO numbers to Table 28 and Table 29. Removed invalid
Embedded Multiplier Hold Times in Table 34. Improved CLKOUT_FREQ_CLK90 in Table 37. Improved
TTDITCK and FTCK performance for XC3S400A in Table 56.
07/10/07 1.5 Added DIFF_HSTL_I and DIFF_HSTL_III to Table 13, Table 14, Table 27, and Table 29. Updated TMDS DC
characteristics in Table 14. Updated for speed file v1.37 in ISE 9.2.01i as shown in Table 17. Updated
pin-to-pin setup and hold times in Table 19. Updated TMDS output adjustment in Table 26. Updated I/O Test
Method values in Table 27. Added BLVDS SSO numbers inTable 29. For Multiplier block, updated setup times
and added hold times to Table 34. Updated block RAM clock width in Table 35. Updated
CLKOUT_PER_JITT_2X and CLKOUT_PER_JITT_DV2 in Table 37. Added CCLK specifications for
Commercial in Table 46 through Table 48.
04/15/08 1.6 Added VIN to Recommended Operating Conditions in Table 8 and added reference to XAPP459, “Eliminating
I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.” Reduced typical
ICCINTQ and ICCAUXQ quiescent current values by 12%-58% in Table 10. Increased VIL max to 0.4V for
LVCMOS12/15/18 and improved VIH min to 0.7V for LVCMOS12 in Table 11. Changed VOL max to 0.4V and
VOH min to VCCO-0.4V for LVCMOS15/18 in Table 12. Noted latest speed file v1.39 in ISE 10.1 software in
Table 16. Added new packages to SSO limits in Table 28 and Table 29. Improved SSTL18_II SSO limit for
FG packages in Table 29. Improved FBUFG for -4 to 334 MHz in Table 33. Added references to 375 MHz
performance via SCD 4103 in Table 33,Table 38, Table 39, and Table 40. Restored Units column to Table 44.
Updated CCLK output maximum period in Table 46 to match minimum frequency in Table 47. Corrected BPI
active clock edge in Figure 15 and Table 54.
05/28/08 1.7 Improved VCCAUXT and VCCO2T POR minimum in Table 5 and updated VCCO POR levels in Figure 11.
Clarified recommended VIN in Table 8. Added reference to VCCAUX in "Simultaneously Switching Output
Guidelines". Added reference to Sample Window in Table 21. Removed DNA_RETENTION limit of 10 years
in Table 15 since number of Read cycles is the only unique limit. Added references to UG332.
03/06/09 1.8 Changed typical quiescent current temperature from ambient to junction. Updated BPI configuration
waveforms in Figure 15 and updated Table 55. Updated selected I/O standard DC characteristics. Added
TIOPI and TIOPID in Table 22.
Removed references to SCD 4103.
08/19/10 2.0 Added IIK to Table 4. Updated VIN in Table 8 and footnoted IL in Table 9 to note potential leakage between
pins of a differential pair. Clarified LVPECL notes to Table 13. Corrected symbols for TSUSPEND_GTS and
TSUSPEND_GWE in Table 44.
12/18/18 2.1 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).

64 www.xilinx.com DS529 (v2.1) December 18, 2018

 132
Spartan-3A FPGA Family:
Pinout Descriptions
DS529 (v2.1) December 18, 2018 0 Product Specification

Introduction
This section describes how the various pins on a Except for the thermal characteristics, all information for the
Spartan®-3A FPGA connect within the supported standard package applies equally to the Pb-free package.
component packages, and provides device-specific thermal
characteristics. For general information on the pin functions
and the package characteristics, see the Packaging section Pin Types
of UG331: Spartan-3 Generation FPGA User Guide.
Most pins on a Spartan-3A FPGA are general-purpose,
• UG331: Spartan-3 Generation FPGA User Guide user-defined I/O pins. There are, however, up to 12 different
www.xilinx.com/support/documentation functional types of pins on Spartan-3A FPGA packages, as
/user_guides/ug331.pdf outlined in Table 57. In the package footprint drawings that
follow, the individual pins are color-coded according to pin
Spartan-3A FPGAs are available in both standard and
type as in the table.
Pb-free, RoHS versions of each package, with the Pb-free
version adding a “G” to the middle of the package code.

Table 57: Types of Pins on Spartan-3A FPGAs

Type / Color Description Pin Name(s) in Type
Code
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form IO_#
I/O differential I/Os. IO_Lxxy_#
Unrestricted, general-purpose input-only pin. This pin does not have an output structure, IP_#
INPUT differential termination resistor, or PCI clamp diode. IP_Lxxy_#
Dual-purpose pin used in some configuration modes during the configuration process and M[2:0]
then usually available as a user I/O after configuration. If the pin is not used during PUDC_B
configuration, this pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation CCLK
Configuration User Guide for additional information on these signals. MOSI/CSI_B
D[7:1]
D0/DIN
DOUT
DUAL CSO_B
RDWR_B
INIT_B
A[25:0]
VS[2:0]
LDC[2:0]
HDC
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other IP/VREF_#
VREF pins in the same bank, provides a reference voltage input for certain I/O standards. IP_Lxxy_#/VREF_#
VREF If used for a reference voltage within a bank, all VREF pins within the bank must be IO/VREF_#
connected. IO_Lxxy_#/VREF_#
Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16 IO_Lxxy_#/GCLK[15:0],
global clock inputs that optionally clock the entire device. The exceptions are the TQ144 IO_Lxxy_#/LHCLK[7:0],
and the XC3S50A in the FT256 package). The RHCLK inputs optionally clock the right half IO_Lxxy_#/RHCLK[7:0]
CLK of the device. The LHCLK inputs optionally clock the left half of the device. See the Using
Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for
additional information on these signals.
Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every DONE, PROG_B
package has two dedicated configuration pins. These pins are powered by VCCAUX. See
CONFIG the UG332: Spartan-3 Generation Configuration User Guide for additional information on
the DONE and PROG_B signals.

© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.

DS529 (v2.1) December 18, 2018 www.xilinx.com 65

Pinout Descriptions

Table 57: Types of Pins on Spartan-3A FPGAs(Continued)

Type / Color
Code Description Pin Name(s) in Type

Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated SUSPEND, AWAKE
PWR pin and is powered by VCCAUX. AWAKE is a dual-purpose pin. Unless Suspend mode is
MGMT enabled in the application, AWAKE is available as a user-I/O pin.
Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has TDI, TMS, TCK, TDO
JTAG four dedicated JTAG pins. These pins are powered by VCCAUX.
Dedicated ground pin. The number of GND pins depends on the package used. All must GND
GND be connected.
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the VCCAUX
VCCAUX package used. All must be connected. VCCAUX can be either 2.5V or 3.3V. Set on board
and using CONFIG VCCAUX constraint.
Dedicated internal core logic power supply pin. The number of VCCINT pins depends on VCCINT
VCCINT the package used. All must be connected to +1.2V.
Along with all the other VCCO pins in the same bank, this pin supplies power to the output VCCO_#
VCCO buffers within the I/O bank and sets the input threshold voltage for some I/O standards. All
must be connected.
This package pin is not connected in this specific device/package combination but may be N.C.
N.C. connected in larger devices in the same package.

Notes:
1. # = I/O bank number, an integer between 0 and 3.

Package Pins by Type

Each package has three separate voltage supply inputs— A majority of package pins are user-defined I/O or input
VCCINT, VCCAUX, and VCCO—and a common ground pins. However, the numbers and characteristics of these I/O
return, GND. The numbers of pins dedicated to these depend on the device type and the package in which it is
functions vary by package, as shown in Table 58. available, as shown in Table 59. The table shows the
maximum number of single-ended I/O pins available,
Table 58: Power and Ground Supply Pins by Package assuming that all I/O-, INPUT-, DUAL-, VREF-, and
Package VCCINT VCCAUX VCCO GND CLK-type pins are used as general-purpose I/O. AWAKE is
counted here as a dual-purpose I/O pin. Likewise, the table
VQ100 4 3 6 13
shows the maximum number of differential pin-pairs
TQ144 4 4 8 13 available on the package. Finally, the table shows how the
FT256 (50A/200A/400A) 6 4 16 28 total maximum user-I/Os are distributed by pin type,
including the number of unconnected—N.C.—pins on the
FT256 (700A/1400A) 15 10 13 50
device.
FG320 6 8 16 32
Not all I/O standards are supported on all I/O banks. The left
FG400 9 8 22 43
and right banks (I/O banks 1 and 3) support higher output
FG484 15 10 24 53 drive current than the top and bottom banks (I/O banks 0
FG676 23 14 36 77 and 2). Similarly, true differential output standards, such as
LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only
supported in the top or bottom banks (I/O banks 0 and 2).
Inputs are unrestricted. For more details, see the chapter
“Using I/O Resources” in UG331.

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 Pinout Descriptions

Table 59: Maximum User I/O by Package

Maximum All Possible I/Os by Type
Maximum Maximum
Device Package User I/Os Input- Differential
and I/O INPUT DUAL VREF CLK N.C.
Input-Only Only Pairs

XC3S50A 68 6 60 17 2 20 6 23 0
VQ100
XC3S200A 68 6 60 17 2 20 6 23 0
XC3S50A TQ144 108 7 50 42 2 26 8 30 0
XC3S50A 144 32 64 53 20 26 15 30 51
XC3S200A 195 35 90 69 21 52 21 32 0
XC3S400A FT256 195 35 90 69 21 52 21 32 0
XC3S700A 161 13 60 59 2 52 18 30 0
XC3S1400A 161 13 60 59 2 52 18 30 0
XC3S200A 248 56 112 101 40 52 23 32 3
FG320
XC3S400A 251 59 112 101 42 52 24 32 0
XC3S400A 311 63 142 155 46 52 26 32 0
FG400
XC3S700A 311 63 142 155 46 52 26 32 0
XC3S700A 372 84 165 194 61 52 33 32 3
FG484
XC3S1400A 375 87 165 195 62 52 34 32 0
XC3S1400A FG676 502 94 227 313 67 52 38 32 17

Notes:
1. Some VREFs are on INPUT pins. See pinout tables for details.

Electronic versions of the package pinout tables and foot-

prints are available for download from the Xilinx website.
Using a spreadsheet program, the data can be sorted and
reformatted according to any specific needs. Similarly, the
ASCII-text file is easily parsed by most scripting programs.
http://www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip

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Pinout Descriptions

Package Overview
Table 60 shows the six low-cost, space-saving production package styles for the Spartan-3A family.

Table 60: Spartan-3A Family Package Options(1)

Maximum Lead Pitch Body Area Height
Package Leads Type
I/O (mm) (mm) (mm)
VQ100 / VQG100 100 Very Thin Quad Flat Pack (VQFP) 68 0.5 14 x 14 1.20
TQ144 / TQG144 144 Thin Quad Flat Pack (TQFP) 108 0.5 20 x 20 1.60
FT256 / FTG256 256 Fine-pitch Thin Ball Grid Array (FBGA) 195 1.0 17 x 17 1.55
FG320 / FGG320 320 Fine-pitch Ball Grid Array (FBGA) 251 1.0 19 x 19 2.00
FG400 / FGG400 400 Fine-pitch Ball Grid Array (FBGA) 311 1.0 21 x 21 2.43
FG484 / FGG484 484 Fine-pitch Ball Grid Array (FBGA) 375 1.0 23 x 23 2.60
FG676 / FGG676 676 Fine-pitch Ball Grid Array (FBGA) 502 1.0 27 x 27 2.60

Notes:
1. See the package material declaration data sheet for package mass.

Each package style is available in an environmentally Mechanical Drawings

friendly lead-free (Pb-free) option. The Pb-free packages
Material Declaration Data Sheets (MDDS) are also available
include an extra ‘G’ in the package style name. For on the www.xilinx.com for each package.
example, the standard “CS484” package becomes
“CSG484” when ordered as the Pb-free option. The
mechanical dimensions of the standard and Pb-free
packages are similar. Package drawings and package
material declaration data sheets (MDDS) are available on
www.xilinx.com.
For additional package information, see UG112: Device
Package User Guide.

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 Pinout Descriptions

Package Thermal Characteristics

The power dissipated by an FPGA application has The junction-to-case thermal resistance (θJC) indicates the
implications on package selection and system design. The difference between the temperature measured on the
power consumed by a Spartan-3A FPGA is reported using package body (case) and the die junction temperature per
either the XPower Power Estimator or the XPower Analyzer watt of power consumption. The junction-to-board (θJB)
calculator integrated in the Xilinx® ISE® development value similarly reports the difference between the board and
software. Table 61 provides the thermal characteristics for junction temperature. The junction-to-ambient (θJA) value
the various Spartan-3A FPGA package offerings. This reports the temperature difference between the ambient
information is also available using the Thermal Query tool environment and the junction temperature. The θJA value is
on xilinx.com (www.xilinx.com/cgi-bin/thermal/thermal.pl). reported at different air velocities, measured in linear feet
per minute (LFM). The “Still Air (0 LFM)” column shows the
θJA value in a system without a fan. The thermal resistance
drops with increasing air flow.

Table 61: Spartan-3A Package Thermal Characteristics

Junction-to-Ambient (θJA)
at Different Air Flows
Junction-to-Case Junction-to- Still Air
Package Device (θJC) Board (θJB) (0 LFM) 250 LFM 500 LFM 750 LFM Units

VQ100 XC3S50A 12.9 30.1 48.5 40.4 37.6 36.6 °C/Watt

VQG100 XC3S200A 10.9 25.7 42.9 35.7 33.2 32.4 °C/Watt
TQ144 XC3S50A 16.5 32.0 42.4 36.3 35.8 34.9 °C/Watt
TQG144
XC3S50A 16.0 33.5 42.3 35.6 35.5 34.5 °C/Watt
XC3S200A 10.3 23.8 32.7 26.6 26.1 25.2 °C/Watt
FT256 XC3S400A 8.4 19.3 29.9 24.9 23.0 22.3 °C/Watt
FTG256
XC3S700A 7.8 18.6 28.1 22.3 21.2 20.7 °C/Watt
XC3S1400A 5.4 14.1 24.2 18.7 17.5 17.0 °C/Watt

FG320 XC3S200A 11.7 18.5 27.8 22.3 21.1 20.3 °C/Watt

FGG320 XC3S400A 9.9 15.4 25.2 19.8 18.6 17.8 °C/Watt

FG400 XC3S400A 9.8 15.5 25.6 19.2 18.0 17.3 °C/Watt

FGG400 XC3S700A 8.2 13.0 23.1 17.9 16.7 16.0 °C/Watt

FG484 XC3S700A 7.9 12.8 22.3 17.4 16.2 15.5 °C/Watt

FGG484 XC3S1400A 6.0 9.9 19.5 14.7 13.5 12.8 °C/Watt
FG676 XC3S1400A 5.8 9.4 17.8 13.5 12.4 11.8 °C/Watt
FGG676

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Pinout Descriptions

VQ100: 100-lead Very Thin Quad Flat Package

The XC3S50A and XC3S200 are available in the 100-lead Table 62: Spartan-3A VQ100 Pinout(Continued)
very thin quad flat package, VQ100. 1 IO_L02P_1/RHCLK0 P59 CLK
Table 62 lists all the package pins. They are sorted by bank 1 IO_L03N_1/TRDY1/RHCLK3 P62 CLK
number and then by pin name. Pins that form a differential
1 IO_L03P_1/RHCLK2 P61 CLK
I/O pair appear together in the table. The table also shows
the pin number for each pin and the pin type, as defined 1 IO_L04N_1/RHCLK7 P65 CLK
earlier. 1 IO_L04P_1/IRDY1/RHCLK6 P64 CLK
The VQ100 does not support Suspend mode (SUSPEND 1 IO_L05N_1 P71 IO
and AWAKE are not connected), the address output pins for 1 IO_L05P_1 P70 IO
the Byte-wide Peripheral Interface (BPI) configuration mode,
or daisy chain configuration (DOUT is not connected). 1 IO_L06N_1 P73 IO
1 IO_L06P_1 P72 IO
Table 62 also indicates that some differential I/O pairs have
different assignments between the XC3S50A and the 1 IP_1/VREF_1 P68 VREF
XC3S200A, highlighted in light blue. See "Footprint 1 VCCO_1 P67 VCCO
Migration Differences," page 72 for additional information.
2 IO_2/MOSI/CSI_B P46 DUAL
An electronic version of this package pinout table and 2 IO_L01N_2/M0 P25 DUAL
footprint diagram is available for download from the Xilinx
website at 2 IO_L01P_2/M1 P23 DUAL
2 IO_L02N_2/CSO_B P27 DUAL
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip. 2 IO_L02P_2/M2 P24 DUAL
IO_L03N_2/VS1 (3S50A)
2 P30 DUAL
Pinout Table IO_L04P_2/VS1 (3S200A)

Table 62: Spartan-3A VQ100 Pinout 2 IO_L03P_2/RDWR_B P28 DUAL

2 IO_L04N_2/VS0 P31 DUAL
Bank Pin Name Pin Type
IO_L04P_2/VS2 (3S50A)
0 IO_0/GCLK11 P90 CLK 2 P29 DUAL
IO_L03N_2/VS2 (3S200A)
0 IO_L01N_0 P78 IO
IO_L05N_2/D7 (3S50A)
0 IO_L01P_0/VREF_0 P77 VREF 2 P34 DUAL
IO_L06P_2/D7 (3S200A)
0 IO_L02N_0/GCLK5 P84 CLK 2 IO_L05P_2 P32 IO
0 IO_L02P_0/GCLK4 P83 CLK 2 IO_L06N_2/D6 P35 DUAL
0 IO_L03N_0/GCLK7 P86 CLK IO_L06P_2 (3S50A)
2 P33 IO
0 IO_L03P_0/GCLK6 P85 CLK IO_L05N_2 (3S200A)

0 IO_L04N_0/GCLK9 P89 CLK 2 IO_L07N_2/D4 P37 DUAL

0 IO_L04P_0/GCLK8 P88 CLK 2 IO_L07P_2/D5 P36 DUAL

0 IO_L05N_0 P94 IO 2 IO_L08N_2/GCLK15 P41 CLK

0 IO_L05P_0 P93 IO 2 IO_L08P_2/GCLK14 P40 CLK

0 IO_L06N_0/PUDC_B P99 DUAL 2 IO_L09N_2/GCLK1 P44 CLK

0 IO_L06P_0/VREF_0 P98 VREF 2 IO_L09P_2/GCLK0 P43 CLK

0 IP_0 P97 IP 2 IO_L10N_2/D3 P49 DUAL

0 IP_0/VREF_0 P82 VREF 2 IO_L10P_2/INIT_B P48 DUAL

0 VCCO_0 P79 VCCO IO_L11N_2/D0/DIN/MISO

(3S50A)
2 P51 DUAL
0 VCCO_0 P96 VCCO IO_L12P_2/D0/DIN/MISO
(3S200A)
1 IO_L01N_1 P57 IO
2 IO_L11P_2/D2 P50 DUAL
1 IO_L01P_1 P56 IO
2 IO_L12N_2/CCLK P53 DUAL
1 IO_L02N_1/RHCLK1 P60 CLK

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 Pinout Descriptions

Table 62: Spartan-3A VQ100 Pinout(Continued) Table 62: Spartan-3A VQ100 Pinout(Continued)
IO_L12P_2/D1 (3S50A) VCCINT VCCINT P17 VCCINT
2 P52 DUAL
IO_L11N_2/D1 (3S200A)
VCCINT VCCINT P38 VCCINT
2 IP_2/VREF_2 P39 VREF
VCCINT VCCINT P66 VCCINT
2 VCCO_2 P26 VCCO
VCCINT VCCINT P81 VCCINT
2 VCCO_2 P45 VCCO
3 IO_L01N_3 P4 IO
3 IO_L01P_3 P3 IO
3 IO_L02N_3 P6 IO
3 IO_L02P_3 P5 IO
3 IO_L03N_3/LHCLK1 P10 CLK
3 IO_L03P_3/LHCLK0 P9 CLK
3 IO_L04N_3/IRDY2/LHCLK3 P13 CLK
3 IO_L04P_3/LHCLK2 P12 CLK
3 IO_L05N_3/LHCLK7 P16 CLK
3 IO_L05P_3/TRDY2/LHCLK6 P15 CLK
3 IO_L06N_3 P20 IO
3 IO_L06P_3 P19 IO
3 IP_3 P21 IP
3 IP_3/VREF_3 P7 VREF
3 VCCO_3 P11 VCCO
GND GND P14 GND
GND GND P18 GND
GND GND P42 GND
GND GND P47 GND
GND GND P58 GND
GND GND P63 GND
GND GND P69 GND
GND GND P74 GND
GND GND P8 GND
GND GND P80 GND
GND GND P87 GND
GND GND P91 GND
GND GND P95 GND
VCCAUX DONE P54 CONFIG
VCCAUX PROG_B P100 CONFIG
VCCAUX TCK P76 JTAG
VCCAUX TDI P2 JTAG
VCCAUX TDO P75 JTAG
VCCAUX TMS P1 JTAG
VCCAUX VCCAUX P22 VCCAUX
VCCAUX VCCAUX P55 VCCAUX
VCCAUX VCCAUX P92 VCCAUX

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Pinout Descriptions

User I/Os by Bank

Table 63 indicates how the 68 available user-I/O pins are
distributed between the four I/O banks on the VQ100
package.

Table 63: User I/Os Per Bank for the XC3S50A and XC3S200A in the VQ100 Package

Package All Possible I/O Pins by Type

Edge I/O Bank Maximum I/O
I/O INPUT DUAL VREF CLK
Top 0 15 3 1 1 3 7
Right 1 13 6 0 0 1 6
Bottom 2 26 2 0 19 1 4
Left 3 14 6 1 0 1 6
TOTAL 68 17 2 20 6 23

Footprint Migration Differences

The XC3S50A and XC3S200 have common VQ100 pinouts
except for some differences in alignment of differential I/O
pairs.

Differential I/O Alignment Differences

Some differential I/O pairs in the VQ100 on the XC3S50A
FPGA are aligned differently than the corresponding pairs
on the XC3S200A FPGAs, as shown in Table 64. All the
mismatched pairs are in I/O Bank 2. These differences are
indicated with the black diamond character () in the
footprint diagrams Figure 17 and Figure 18.

Table 64: Differential I/O Differences in VQ100

VQ100 Pin Bank XC3S50A XC3S200A
P29 IIO_L04P_2/VS2 IO_L03N_2/VS2
P30 IO_L03N_2/VS1 IO_L04P_2/VS1
P33 IO_L06P_2 IO_L05N_2
P34 2 IO_L05N_2/D7 IO_L06P_2/D7
IO_L11N_2/D0/DIN/ IO_L12P_2/D0/DIN/
P51 MISO MISO
P52 IO_L12P_2/D1 IO_L11N_2/D1

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 Pinout Descriptions

VQ100 Footprint (XC3S50A)

Note pin 1 indicator in top-left corner and logo orientation.

99 IO_L06N_0/PUDC_B
98 IO_L06P_0/VREF_0

77 IO_L01P_0/VREF_0
89 IO_L04N_0/GCLK9

86 IO_L03N_0/GCLK7

84 IO_L02N_0/GCLK5
88 IO_L04P_0/GCLK8

85 IO_L03P_0/GCLK6

83 IO_L02P_0/GCLK4
90 IO_0/GCLK11

82 IP_0/VREF_0
94 IO_L05N_0

78 IO_L01N_0
93 IO_L05P_0
100 PROG_B

92 VCCAUX
96 VCCO_0

79 VCCO_0
81 VCCINT
95 GND

91 GND

87 GND

80 GND
97 IP_0

76 TCK
TMS 1 Bank 0 75 TDO
TDI 2 74 GND
IO_L01P_3 3 73 IO_L06N_1
IO_L01N_3 4 72 IO_L06P_1
IO_L02P_3 5 71 IO_L05N_1
6 70 IO_L05P_1
IO_L02N_3
IP_3/VREF_3 7 69 GND
GND 8 68 IP_1/VREF_1
IO_L03P_3/LHCLK0 9 67 VCCO_1
IO_L03N_3/LHCLK1 10 66 VCCINT

Bank 1
Bank 3

VCCO_3 11 65 IO_L04N_1/RHCLK7
IO_L04P_3/LHCLK2 12 64 IO_L04P_1/IRDY1/RHCLK6
IO_L04N_3/IRDY2/LHCLK3 13 63 GND
GND 14 62 IO_L03N_1/TRDY1/RHCLK3
IO_L05P_3/TRDY2/LHCLK6 15 61 IO_L03P_1/RHCLK2
IO_L05N_3/LHCLK7 16 60 IO_L02N_1/RHCLK1
VCCINT 17 59 IO_L02P_1/RHCLK0
GND 18 58 GND
IO_L06P_3 19 57 IO_L01N_1
IO_L06N_3 20 56 IO_L01P_1
IP_3 21 55 VCCAUX
VCCAUX 22 54 DONE
IO_L01P_2/M1 23 53 IO_L12N_2/CCLK
IO_L02P_2/M2 24 52 IO_L12P_2/D1(◆)
IO_L01N_2/M0 25 Bank 2 51 IO_L11N_2/D0/DIN/MISO (◆)
VCCO_2 26
IO_L02N_2/CSO_B 27
IO_L03P_2/RDWR_B 28
IO_L04P_2/VS2 (◆) 29
IO_L03N_2/VS1 (◆) 30
IO_L04N_2/VS0 31
IO_L05P_2 32
IO_L06P_2 (◆) 33
IO_L05N_2/D7 (◆) 34
IO_L06N_2/D6 35
IO_L07P_2/D5 36
IO_L07N_2/D4 37
VCCINT 38
IP_2/VREF_2 39
IO_L08P_2/GCLK14 40
IO_L08N_2/GCLK15 41
GND 42
IO_L09P_2/GCLK0 43
IO_L09N_2/GCLK1 44
VCCO_2 45
IO_2/MOSI/CSI_B 46
GND 47
IO_L10P_2/INIT_B 48
IO_L10N_2/D3 49
IO_L11P_2/D2 50

Figure 17: VQ100 Package Footprint - XC3S50A (Top View)

I/O: Unrestricted, general-purpose DUAL: Configuration pins, then VREF: User I/O or input voltage
17 user I/O 20 possible user I/O 6 reference for bank

INPUT: Unrestricted, CLK: User I/O, input, or global VCCO: Output voltage supply for
2 general-purpose input pin 23 buffer input 6 bank

CONFIG: Dedicated configuration JTAG: Dedicated JTAG port pins VCCINT: Internal core supply
2 pins 4 4 voltage (+1.2V)

0 N.C.: Not connected 13 GND: Ground 3 VCCAUX: Auxiliary supply voltage

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Pinout Descriptions

VQ100 Footprint (XC3S200A)

Note pin 1 indicator in top-left corner and logo orientation.

99 IO_L06N_0/PUDC_B
98 IO_L06P_0/VREF_0

77 IO_L01P_0/VREF_0
89 IO_L04N_0/GCLK9

86 IO_L03N_0/GCLK7

84 IO_L02N_0/GCLK5
83 IO_L02P_0/GCLK4
88 IO_L04P_0/GCLK8

85 IO_L03P_0/GCLK6
90 IO_0/GCLK11

82 IP_0/VREF_0
94 IO_L05N_0

78 IO_L01N_0
93 IO_L05P_0
100 PROG_B

92 VCCAUX
96 VCCO_0

79 VCCO_0
81 VCCINT
95 GND

91 GND

87 GND

80 GND
97 IP_0

76 TCK
TMS 1 Bank 0 75 TDO
TDI 2 74 GND
IO_L01P_3 3 73 IO_L06N_1
IO_L01N_3 4 72 IO_L06P_1
IO_L02P_3 5 71 IO_L05N_1
6 70 IO_L05P_1
IO_L02N_3
IP_3/VREF_3 7 69 GND
GND 8 68 IP_1/VREF_1
IO_L03P_3/LHCLK0 9 67 VCCO_1
IO_L03N_3/LHCLK1 10 66 VCCINT

Bank 1
Bank 3

VCCO_3 11 65 IO_L04N_1/RHCLK7
IO_L04P_3/LHCLK2 12 64 IO_L04P_1/IRDY1/RHCLK6
IO_L04N_3/IRDY2/LHCLK3 13 63 GND
GND 14 62 IO_L03N_1/TRDY1/RHCLK3
IO_L05P_3/TRDY2/LHCLK6 15 61 IO_L03P_1/RHCLK2
IO_L05N_3/LHCLK7 16 60 IO_L02N_1/RHCLK1
VCCINT 17 59 IO_L02P_1/RHCLK0
GND 18 58 GND
IO_L06P_3 19 57 IO_L01N_1
IO_L06N_3 20 56 IO_L01P_1
IP_3 21 55 VCCAUX
VCCAUX 22 54 DONE
IO_L01P_2/M1 23 53 IO_L12N_2/CCLK
IO_L02P_2/M2 24 52 IO_L11N_2/D1(◆)
IO_L01N_2/M0 25 Bank 2 51 IO_L12P_2/D0/DIN/MISO (◆)
200A
VCCO_2 26
IO_L02N_2/CSO_B 27
IO_L03P_2/RDWR_B 28
IO_L03N_2/VS2 (◆) 29
IO_L04P_2/VS1(◆) 30
IO_L04N_2/VS0 31
IO_L05P_2 32
IO_L05N_2 (◆) 33
IO_L06P_2/D7 (◆) 34
IO_L06N_2/D6 35
IO_L07P_2/D5 36
IO_L07N_2/D4 37
VCCINT 38
IP_2/VREF_2 39
IO_L08P_2/GCLK14 40
IO_L08N_2/GCLK15 41
GND 42
IO_L09P_2/GCLK0 43
IO_L09N_2/GCLK1 44
VCCO_2 45
IO_2/MOSI/CSI_B 46
GND 47
IO_L10P_2/INIT_B 48
IO_L10N_2/D3 49
IO_L11P_2/D2 50

Figure 18: VQ100 Package Footprint - XC3S200A (Top View)

I/O: Unrestricted, general-purpose DUAL: Configuration pins, then VREF: User I/O or input voltage
17 user I/O 20 possible user I/O 6 reference for bank

INPUT: Unrestricted, CLK: User I/O, input, or global VCCO: Output voltage supply for
2 general-purpose input pin 23 buffer input 6 bank

CONFIG: Dedicated configuration JTAG: Dedicated JTAG port pins VCCINT: Internal core supply
2 pins 4 4 voltage (+1.2V)

0 N.C.: Not connected 13 GND: Ground 3 VCCAUX: Auxiliary supply voltage

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 Pinout Descriptions

TQ144: 144-lead Thin Quad Flat Package

The XC3S50A is available in the 144-lead thin quad flat Table 65: Spartan-3A TQ144 Pinout(Continued)
package, TQ144. Bank Pin Name Pin Type
Table 65 lists all the package pins. They are sorted by bank 0 IP_0/VREF_0 P123 VREF
number and then by pin name. Pins that form a differential 0 VCCO_0 P119 VCCO
I/O pair appear together in the table. The table also shows
the pin number for each pin and the pin type, as defined 0 VCCO_0 P136 VCCO
earlier. 1 IO_1 P79 I/O

The XC3S50A does not support the address output pins for 1 IO_L01N_1/LDC2 P78 DUAL
the Byte-wide Peripheral Interface (BPI) configuration mode. 1 IO_L01P_1/HDC P76 DUAL
An electronic version of this package pinout table and 1 IO_L02N_1/LDC0 P77 DUAL
footprint diagram is available for download from the Xilinx 1 IO_L02P_1/LDC1 P75 DUAL
website at
1 IO_L03N_1 P84 I/O
www.xilinx.com/support/documentation/data_sheets/ 1 IO_L03P_1 P82 I/O
s3a_pin.zip.
1 IO_L04N_1/RHCLK1 P85 RHCLK

Pinout Table 1 IO_L04P_1/RHCLK0 P83 RHCLK

1 IO_L05N_1/TRDY1/RHCLK3 P88 RHCLK
Table 65: Spartan-3A TQ144 Pinout
1 IO_L05P_1/RHCLK2 P87 RHCLK
Bank Pin Name Pin Type
1 IO_L06N_1/RHCLK5 P92 RHCLK
0 IO_0 P142 I/O
1 IO_L06P_1/RHCLK4 P90 RHCLK
0 IO_L01N_0 P111 I/O
1 IO_L07N_1/RHCLK7 P93 RHCLK
0 IO_L01P_0 P110 I/O
1 IO_L07P_1/IRDY1/RHCLK6 P91 RHCLK
0 IO_L02N_0 P113 I/O
1 IO_L08N_1 P98 I/O
0 IO_L02P_0/VREF_0 P112 VREF
1 IO_L08P_1 P96 I/O
0 IO_L03N_0 P117 I/O
1 IO_L09N_1 P101 I/O
0 IO_L03P_0 P115 I/O
1 IO_L09P_1 P99 I/O
0 IO_L04N_0 P116 I/O
1 IO_L10N_1 P104 I/O
0 IO_L04P_0 P114 I/O
1 IO_L10P_1 P102 I/O
0 IO_L05N_0 P121 I/O
1 IO_L11N_1 P105 I/O
0 IO_L05P_0 P120 I/O
1 IO_L11P_1 P103 I/O
0 IO_L06N_0/GCLK5 P126 GCLK
1 IP_1/VREF_1 P80 VREF
0 IO_L06P_0/GCLK4 P124 GCLK
1 IP_1/VREF_1 P97 VREF
0 IO_L07N_0/GCLK7 P127 GCLK
1 VCCO_1 P86 VCCO
0 IO_L07P_0/GCLK6 P125 GCLK
1 VCCO_1 P95 VCCO
0 IO_L08N_0/GCLK9 P131 GCLK
2 IO_2/MOSI/CSI_B P62 DUAL
0 IO_L08P_0/GCLK8 P129 GCLK
2 IO_L01N_2/M0 P38 DUAL
0 IO_L09N_0/GCLK11 P132 GCLK
2 IO_L01P_2/M1 P37 DUAL
0 IO_L09P_0/GCLK10 P130 GCLK
2 IO_L02N_2/CSO_B P41 DUAL
0 IO_L10N_0 P135 I/O
2 IO_L02P_2/M2 P39 DUAL
0 IO_L10P_0 P134 I/O
2 IO_L03N_2/VS1 P44 DUAL
0 IO_L11N_0 P139 I/O
2 IO_L03P_2/RDWR_B P42 DUAL
0 IO_L11P_0 P138 I/O
2 IO_L04N_2/VS0 P45 DUAL
0 IO_L12N_0/PUDC_B P143 DUAL
2 IO_L04P_2/VS2 P43 DUAL
0 IO_L12P_0/VREF_0 P141 VREF
2 IO_L05N_2/D7 P48 DUAL
0 IP_0 P140 INPUT

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Pinout Descriptions

Table 65: Spartan-3A TQ144 Pinout(Continued) Table 65: Spartan-3A TQ144 Pinout(Continued)
Bank Pin Name Pin Type Bank Pin Name Pin Type
2 IO_L05P_2 P46 I/O 3 IO_L10P_3 P27 I/O
2 IO_L06N_2/D6 P49 DUAL 3 IO_L11N_3 P30 I/O
2 IO_L06P_2 P47 I/O 3 IO_L11P_3 P28 I/O
2 IO_L07N_2/D4 P51 DUAL 3 IO_L12N_3 P32 I/O
2 IO_L07P_2/D5 P50 DUAL 3 IO_L12P_3 P31 I/O
2 IO_L08N_2/GCLK15 P55 GCLK 3 IP_L13N_3/VREF_3 P35 VREF
2 IO_L08P_2/GCLK14 P54 GCLK 3 IP_L13P_3 P33 INPUT
2 IO_L09N_2/GCLK1 P59 GCLK 3 VCCO_3 P14 VCCO
2 IO_L09P_2/GCLK0 P57 GCLK 3 VCCO_3 P23 VCCO
2 IO_L10N_2/GCLK3 P60 GCLK GND GND P9 GND
2 IO_L10P_2/GCLK2 P58 GCLK GND GND P17 GND
2 IO_L11N_2/DOUT P64 DUAL GND GND P26 GND
PWR GND GND P34 GND
2 IO_L11P_2/AWAKE P63 MGMT
GND GND P56 GND
2 IO_L12N_2/D3 P68 DUAL
GND GND P65 GND
2 IO_L12P_2/INIT_B P67 DUAL
GND GND P81 GND
2 IO_L13N_2/D0/DIN/MISO P71 DUAL
GND GND P89 GND
2 IO_L13P_2/D2 P69 DUAL
GND GND P100 GND
2 IO_L14N_2/CCLK P72 DUAL
GND GND P106 GND
2 IO_L14P_2/D1 P70 DUAL
GND GND P118 GND
2 IP_2/VREF_2 P53 VREF
GND GND P128 GND
2 VCCO_2 P40 VCCO
GND GND P137 GND
2 VCCO_2 P61 VCCO
PWR
3 IO_L01N_3 P6 I/O VCCAUX SUSPEND P74 MGMT
3 IO_L01P_3 P4 I/O VCCAUX DONE P73 CONFIG
3 IO_L02N_3 P5 I/O VCCAUX PROG_B P144 CONFIG
3 IO_L02P_3 P3 I/O VCCAUX TCK P109 JTAG
3 IO_L03N_3 P8 I/O VCCAUX TDI P2 JTAG
3 IO_L03P_3 P7 I/O VCCAUX TDO P107 JTAG
3 IO_L04N_3/VREF_3 P11 VREF VCCAUX TMS P1 JTAG
3 IO_L04P_3 P10 I/O VCCAUX VCCAUX P36 VCCAUX
3 IO_L05N_3/LHCLK1 P13 LHCLK VCCAUX VCCAUX P66 VCCAUX
3 IO_L05P_3/LHCLK0 P12 LHCLK VCCAUX VCCAUX P108 VCCAUX
3 IO_L06N_3/IRDY2/LHCLK3 P16 LHCLK VCCAUX VCCAUX P133 VCCAUX
3 IO_L06P_3/LHCLK2 P15 LHCLK VCCINT VCCINT P22 VCCINT
3 IO_L07N_3/LHCLK5 P20 LHCLK VCCINT VCCINT P52 VCCINT
3 IO_L07P_3/LHCLK4 P18 LHCLK VCCINT VCCINT P94 VCCINT
3 IO_L08N_3/LHCLK7 P21 LHCLK VCCINT VCCINT P122 VCCINT
3 IO_L08P_3/TRDY2/LHCLK6 P19 LHCLK
3 IO_L09N_3 P25 I/O
3 IO_L09P_3 P24 I/O
3 IO_L10N_3 P29 I/O

76 www.xilinx.com DS529 (v2.1) December 18, 2018

 Pinout Descriptions

User I/Os by Bank

Table 66 indicates how the 108 available user-I/O pins are
distributed between the four I/O banks on the TQ144
package. The AWAKE pin is counted as a dual-purpose I/O.

Table 66: User I/Os Per Bank for the XC3S50A in the TQ144 Package

Package All Possible I/O Pins by Type

Edge I/O Bank Maximum I/O
I/O INPUT DUAL VREF CLK
Top 0 27 14 1 1 3 8
Right 1 25 11 0 4 2 8
Bottom 2 30 2 0 21 1 6
Left 3 26 15 1 0 2 8
TOTAL 108 42 2 26 8 30

Footprint Migration Differences

The XC3S50A FPGA is the only Spartan-3A device offered
in the TQ144 package.

DS529 (v2.1) December 18, 2018 www.xilinx.com 77

Pinout Descriptions

TQ144 Footprint
Note pin 1 indicator in top-left corner and logo orientation.

143 IO_L12N_0/PUDC_B

132 IO_L09N_0/GCLK11

130 IO_L09P_0/GCLK10

112 IO_L02P_0/VREF_0
141 IO_L12P_0/VREF_0

131 IO_L08N_0/GCLK9

127 IO_L07N_0/GCLK7
126 IO_L06N_0/GCLK5
129 IO_L08P_0/GCLK8

125 IO_L07P_0/GCLK6
124 IO_L06P_0/GCLK4
123 IP_0/VREF_0
139 IO_L11N_0

135 IO_L10N_0

121 IO_L05N_0

117 IO_L03N_0
116 IO_L04N_0

113 IO_L02N_0

111 IO_L01N_0
138 IO_L11P_0

134 IO_L10P_0

120 IO_L05P_0

115 IO_L03P_0
114 IO_L04P_0

110 IO_L01P_0
144 PROG_B

133 VCCAUX
136 VCCO_0

119 VCCO_0
122 VCCINT
137 GND

128 GND

118 GND
142 IO_0

140 IP_0

109 TCK
TMS 1 108 VCCAUX
TDI 2 Bank 0 107 TDO
IO_L02P_3
IO_L01P_3
3
4 X 106
105
GND
IO_L11N_1
IO_L02N_3 5 104 IO_L10N_1
IO_L01N_3 6 103 IO_L11P_1
IO_L03P_3 7 102 IO_L10P_1
IO_L03N_3 8 101 IO_L09N_1
GND 9 100 GND
IO_L04P_3 10 99 IO_L09P_1
IO_L04N_3/VREF_3 11 98 IO_L08N_1
IO_L05P_3/LHCLK0 12 97 IP_1/VREF_1
IO_L05N_3/LHCLK1 13 96 IO_L08P_1
VCCO_3 14 95 VCCO_1
IO_L06P_3/LHCLK2 15 94 VCCINT
IO_L06N_3/LHCLK3 16 93 IO_L07N_1/RHCLK7
Bank 3

GND 17 92 IO_L06N_1/RHCLK5

Bank 1
IO_L07P_3/LHCLK4 18 91 IO_L07P_1/RHCLK6
IO_L08P_3/LHCLK6 19 90 IO_L06P_1/RHCLK4
IO_L07N_3/LHCLK5 20 89 GND
IO_L08N_3/LHCLK7 21 88 IO_L05N_1/RHCLK3
VCCINT 22 87 IO_L05P_1/RHCLK2
VCCO_3 23 86 VCCO_1
IO_L09P_3 24 85 IO_L04N_1/RHCLK1
IO_L09N_3 25 84 IO_L03N_1
GND 26 83 IO_L04P_1/RHCLK0
IO_L10P_3 27 82 IO_L03P_1
IO_L11P_3 28 81 GND
IO_L10N_3 29 80 IP_1/VREF_1
IO_L11N_3 30 79 IO_1
IO_L12P_3 31 78 IO_L01N_1/LDC2
IO_L12N_3 32 77 IO_L02N_1/LDC0
IP_L13P_3 33 76 IO_L01P_1/HDC
GND 34 75 IO_L02P_1/LDC1
IP_L13N_3/VREF_3 35 74 SUSPEND
VCCAUX 36 Bank 2 73 DONE
IO_L01P_2/M1 37
IO_L01N_2/M0 38
IO_L02P_2/M2 39
VCCO_2 40
IO_L02N_2/CSO_B 41
IO_L03P_2/RDWR_B 42
IO_L04P_2/VS2 43
IO_L03N_2/VS1 44
IO_L04N_2/VS0 45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IO_L13N_2/D0/DIN/MISO
IO_L05N_2/D7
IO_L06N_2/D6
IO_L07P_2/D5
IO_L07N_2/D4

IO_L12N_2/D3
IO_L13P_2/D2
IO_L14P_2/D1
IP_2/VREF_2
IO_L08P_2/GCLK14
IO_L08N_2/GCLK15

IO_L09P_2/GCLK0
IO_L10P_2/GCLK2

IO_L10N_2/GCLK3
IO_L05P_2
IO_L06P_2

IO_L09N_2/GCLK1
GND

VCCO_2

GND

IO_L14N_2/CCLK
IO_2/MOSI/CSI_B
IO_L11P_2/AWAKE

VCCAUX
IO_L12P_2/INIT_B
IO_L11N_2/DOUT
VCCINT

DS529-4_10_031207

Figure 19: TQ144 Package Footprint (Top View)

I/O: Unrestricted, general-purpose DUAL: Configuration pins, then VREF: User I/O or input voltage
42 user I/O 25 possible user I/O 8 reference for bank
INPUT: Unrestricted, CLK: User I/O, input, or global VCCO: Output voltage supply for
2 general-purpose input pin 30 buffer input 8 bank

CONFIG: Dedicated configuration JTAG: Dedicated JTAG port pins VCCINT: Internal core supply
2 pins 4 4 voltage (+1.2V)

0 N.C.: Not connected 13 GND: Ground 4 VCCAUX: Auxiliary supply voltage

SUSPEND: Dedicated SUSPEND

2 and dual-purpose AWAKE Power
Management pins

78 www.xilinx.com DS529 (v2.1) December 18, 2018

 Pinout Descriptions

FT256: 256-ball Fine-pitch, Thin Ball Grid Array

The 256-ball fine-pitch, thin ball grid array package, FT256, Pinout Table
supports all five Spartan-3A FPGAs. The XC3S200A and
XC3S400A have identical footprints, and the XC3S700A Table 67: Spartan-3A FT256 Pinout (XC3S50A,
and XC3S1400A have identical footprints. The XC3S50A is XC3S200A, XC3S400)
compatible with the XC3S200A/XC3S400A but has 51 XC3S200A FT256
unconnected balls. The XC3S200A/XC3S400A is similar to Bank XC3S50A XC3S400A Ball Type
the XC3S700A/XC3S1400A, but the XC3S700A/ 0 IO_L01N_0 IO_L01N_0 C13 I/O
XC3S1400A adds more power and ground pins and 0 IO_L01P_0 IO_L01P_0 D13 I/O
therefore is not compatible.
0 IO_L02N_0 IO_L02N_0 B14 I/O
Table 67 lists all the package pins for the XC3S50A, IO_L02P_0/ IO_L02P_0/
XC3S200A, and XC3S400A. They are sorted by bank 0
VREF_0 VREF_0 B15 VREF
number and then by pin name of the largest device. Pins 0 IO_L03N_0 IO_L03N_0 D11 I/O
that form a differential I/O pair appear together in the table.
0 IO_L03P_0 IO_L03P_0 C12 I/O
The table also shows the pin number for each pin and the
pin type, as defined earlier. 0 IO_L04N_0 IO_L04N_0 A13 I/O
0 IO_L04P_0 IO_L04P_0 A14 I/O
The highlighted rows indicate pinout differences between
the XC3S50A, the XC3S200A, and the XC3S400A FPGAs. 0 N.C. (◆) IO_L05N_0 A12 I/O
The XC3S50A has 51 unconnected balls, indicated as N.C. 0 IP_0 IO_L05P_0 B12 I/O
(No Connection) in Table 67 and Figure 20 and with the IO_L06N_0/
0 N.C. (◆) E10 VREF
black diamond character () in Table 67. Figure 21 VREF_0
provides the common footprint for the XC3S200A and 0 N.C. (◆) IO_L06P_0 D10 I/O
XC3S400A.
0 IO_L07N_0 IO_L07N_0 A11 I/O
Table 67 also indicates that some differential I/O pairs have 0 IO_L07P_0 IO_L07P_0 C11 I/O
different assignments between the XC3S50A and the
0 IO_L08N_0 IO_L08N_0 A10 I/O
XC3S200A/XC3S400A, highlighted in light blue. See
"Footprint Migration Differences," page 99 for additional 0 IO_L08P_0 IO_L08P_0 B10 I/O
information. 0
IO_L09N_0/ IO_L09N_0/
D9 GCLK
GCLK5 GCLK5
All other balls have nearly identical functionality on all three IO_L09P_0/ IO_L09P_0/
devices. Table 72 summarizes the XC3S50A FPGA footprint 0 GCLK4 GCLK4 C10 GCLK
migration differences for the FT256 package. IO_L10N_0/ IO_L10N_0/
0
GCLK7 GCLK7 A9 GCLK
The XC3S50A does not support the address output pins for
the Byte-wide Peripheral Interface (BPI) configuration mode. IO_L10P_0/ IO_L10P_0/
0
GCLK6 GCLK6 C9 GCLK

Table 68 lists all the package pins for the XC3S700A and IO_L11N_0/ IO_L11N_0/
0
GCLK9 GCLK9 D8 GCLK
XC3S1400A. They are sorted by bank number and then by
pin name. Pins that form a differential I/O pair appear 0
IO_L11P_0/ IO_L11P_0/
C8 GCLK
together in the table. The table also shows the pin number GCLK8 GCLK8
for each pin and the pin type, as defined earlier. Figure 22 0 IO_L12N_0/ IO_L12N_0/
B8 GCLK
GCLK11 GCLK11
provides the common footprint for the XC3S200A and
XC3S400A. IO_L12P_0/ IO_L12P_0/
0
GCLK10 GCLK10 A8 GCLK
An electronic version of this package pinout table and 0 N.C. (◆) IO_L13N_0 C7 I/O
footprint diagram is available for download from the Xilinx
0 N.C. (◆) IO_L13P_0 A7 I/O
website at
IO_L14N_0/
0 N.C. (◆) E7 VREF
www.xilinx.com/support/documentation/data_sheets/ VREF_0
s3a_pin.zip. 0 N.C. (◆) IO_L14P_0 F8 I/O
0 IO_L15N_0 IO_L15N_0 B6 I/O
0 IO_L15P_0 IO_L15P_0 A6 I/O
0 IO_L16N_0 IO_L16N_0 C6 I/O
0 IO_L16P_0 IO_L16P_0 D7 I/O
0 IO_L17N_0 IO_L17N_0 C5 I/O

DS529 (v2.1) December 18, 2018 www.xilinx.com 79

Pinout Descriptions

Table 67: Spartan-3A FT256 Pinout (XC3S50A, Table 67: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400) (Continued) XC3S200A, XC3S400) (Continued)
XC3S200A FT256 XC3S200A FT256
Bank XC3S50A XC3S400A Ball Type Bank XC3S50A XC3S400A Ball Type
0 IO_L17P_0 IO_L17P_0 A5 I/O 1 IO_L12N_1/ IO_L12N_1/
J16 RHCLK
TRDY1/RHCLK3 TRDY1/RHCLK3
0 IO_L18N_0 IO_L18N_0 B4 I/O
IO_L12P_1/ IO_L12P_1/
0 IO_L18P_0 IO_L18P_0 A4 I/O 1
RHCLK2 RHCLK2 K16 RHCLK

0 IO_L19N_0 IO_L19N_0 B3 I/O IO_L14N_1/ IO_L14N_1/

1
RHCLK5 RHCLK5 H14 RHCLK
0 IO_L19P_0 IO_L19P_0 A3 I/O
IO_L14P_1/ IO_L14P_1/
IO_L20N_0/ IO_L20N_0/ 1
RHCLK4 RHCLK4 J14 RHCLK
0
PUDC_B PUDC_B D5 DUAL
IO_L15N_1/ IO_L15N_1/
IO_L20P_0/ IO_L20P_0/ 1
RHCLK7 RHCLK7 H16 RHCLK
0
VREF_0 VREF_0 C4 VREF
IO_L15P_1/ IO_L15P_1/
0 IP_0 IP_0 D6 INPUT 1
IRDY1/RHCLK6 IRDY1/RHCLK6 H15 RHCLK

0 IP_0 IP_0 D12 INPUT 1 N.C. (◆) IO_L16N_1/A11 F16 DUAL

0 IP_0 IP_0 E6 INPUT 1 N.C. (◆) IO_L16P_1/A10 G16 DUAL
0 IP_0 IP_0 F7 INPUT 1 N.C. (◆) IO_L17N_1/A13 G14 DUAL
0 IP_0 IP_0 F9 INPUT 1 N.C. (◆) IO_L17P_1/A12 H13 DUAL
0 IP_0 IP_0 F10 INPUT 1 N.C. (◆) IO_L18N_1/A15 F15 DUAL
0 IP_0/VREF_0 IP_0/VREF_0 E9 VREF 1 N.C. (◆) IO_L18P_1/A14 E16 DUAL
0 VCCO_0 VCCO_0 B5 VCCO 1 N.C. (◆) IO_L19N_1/A17 F14 DUAL
0 VCCO_0 VCCO_0 B9 VCCO 1 N.C. (◆) IO_L19P_1/A16 G13 DUAL
0 VCCO_0 VCCO_0 B13 VCCO 1 IO_L20N_1 IO_L20N_1/A19 F13 DUAL
0 VCCO_0 VCCO_0 E8 VCCO 1 IO_L20P_1 IO_L20P_1/A18 E14 DUAL
IO_L01N_1/ IO_L01N_1/ 1 IO_L22N_1 IO_L22N_1/A21 D15 DUAL
1
LDC2 LDC2 N14 DUAL
1 IO_L22P_1 IO_L22P_1/A20 D16 DUAL
IO_L01P_1/ IO_L01P_1/
1 HDC HDC N13 DUAL
1 IO_L23N_1 IO_L23N_1/A23 D14 DUAL
IO_L02N_1/ IO_L02N_1/ 1 IO_L23P_1 IO_L23P_1/A22 E13 DUAL
1
LDC0 LDC0 P15 DUAL
1 IO_L24N_1 IO_L24N_1/A25 C15 DUAL
IO_L02P_1/ IO_L02P_1/
1
LDC1 LDC1 R15 DUAL 1 IO_L24P_1 IO_L24P_1/A24 C16 DUAL
1 IO_L03N_1 IO_L03N_1/A1 N16 DUAL 1
IP_L04N_1/ IP_L04N_1/
K12 VREF
VREF_1 VREF_1
1 IO_L03P_1 IO_L03P_1/A0 P16 DUAL
1 IP_L04P_1 IP_L04P_1 K11 INPUT
IO_L05N_1/
1 N.C. (◆)
VREF_1 M14 VREF 1 N.C. (◆) IP_L09N_1 J11 INPUT
1 N.C. (◆) IO_L05P_1 M13 I/O 1 N.C. (◆)
IP_L09P_1/
J10 VREF
VREF_1
1 N.C. (◆) IO_L06N_1/A3 K13 DUAL
1 IP_L13N_1 IP_L13N_1 H11 INPUT
1 N.C. (◆) IO_L06P_1/A2 L13 DUAL
1 IP_L13P_1 IP_L13P_1 H10 INPUT
1 N.C. (◆) IO_L07N_1/A5 M16 DUAL
1 IP_L21N_1 IP_L21N_1 G11 INPUT
1 N.C. (◆) IO_L07P_1/A4 M15 DUAL
IP_L21P_1/ IP_L21P_1/
1 N.C. (◆) IO_L08N_1/A7 L16 DUAL 1
VREF_1 VREF_1 G12 VREF

1 N.C. (◆) IO_L08P_1/A6 L14 DUAL 1 IP_L25N_1 IP_L25N_1 F11 INPUT

1 IO_L10N_1 IO_L10N_1/A9 J13 DUAL IP_L25P_1/ IP_L25P_1/
1
VREF_1 VREF_1 F12 VREF
1 IO_L10P_1 IO_L10P_1/A8 J12 DUAL
1 VCCO_1 VCCO_1 E15 VCCO
IO_L11N_1/ IO_L11N_1/
1
RHCLK1 RHCLK1 K14 RHCLK
1 VCCO_1 VCCO_1 H12 VCCO
IO_L11P_1/ IO_L11P_1/ 1 VCCO_1 VCCO_1 J15 VCCO
1
RHCLK0 RHCLK0 K15 RHCLK
1 VCCO_1 VCCO_1 N15 VCCO

80 www.xilinx.com DS529 (v2.1) December 18, 2018

 Pinout Descriptions

Table 67: Spartan-3A FT256 Pinout (XC3S50A, Table 67: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400) (Continued) XC3S200A, XC3S400) (Continued)
XC3S200A FT256 XC3S200A FT256
Bank XC3S50A XC3S400A Ball Type Bank XC3S50A XC3S400A Ball Type
2 IO_L01N_2/M0 IO_L01N_2/M0 P4 DUAL 2 IO_L20P_2/D1 IO_L18N_2/D1 R13 DUAL
2 IO_L01P_2/M1 IO_L01P_2/M1 N4 DUAL 2 IO_L18P_2/D2 IO_L18P_2/D2 T13 DUAL

2 IO_L02N_2/ IO_L02N_2/
T2 DUAL 2 N.C. (◆) IO_L19N_2 P13 I/O
CSO_B CSO_B
2 N.C. (◆) IO_L19P_2 N12 I/O
2 IO_L02P_2/M2 IO_L02P_2/M2 R2 DUAL
IO_L20N_2/ IO_L20N_2/
2 IO_L04P_2/VS2 IO_L03N_2/VS2 T3 DUAL 2
CCLK CCLK R14 DUAL

IO_L03P_2/ IO_L03P_2/ IO_L18N_2/D0/ IO_L20P_2/D0/

2
RDWR_B RDWR_B R3 DUAL 2
DIN/MISO DIN/MISO T14 DUAL

2 IO_L04N_2/VS0 IO_L04N_2/VS0 P5 DUAL 2 IP_2 IP_2 L7 INPUT

2 IO_L03N_2/VS1 IO_L04P_2/VS1 N6 DUAL 2 IP_2 IP_2 L8 INPUT
2 IO_L06P_2 IO_L05N_2 R5 I/O 2 IP_2/VREF_2 IP_2/VREF_2 L9 VREF
2 IO_L05P_2 IO_L05P_2 T4 I/O 2 IP_2/VREF_2 IP_2/VREF_2 L10 VREF
2 IO_L06N_2/D6 IO_L06N_2/D6 T6 DUAL 2 IP_2/VREF_2 IP_2/VREF_2 M7 VREF
2 IO_L05N_2/D7 IO_L06P_2/D7 T5 DUAL 2 IP_2/VREF_2 IP_2/VREF_2 M8 VREF
2 N.C. (◆) IO_L07N_2 P6 I/O 2 IP_2/VREF_2 IP_2/VREF_2 M11 VREF
2 N.C. (◆) IO_L07P_2 N7 I/O 2 IP_2/VREF_2 IP_2/VREF_2 N5 VREF
2 IO_L08N_2/D4 IO_L08N_2/D4 N8 DUAL 2 VCCO_2 VCCO_2 M9 VCCO
2 IO_L08P_2/D5 IO_L08P_2/D5 P7 DUAL 2 VCCO_2 VCCO_2 R4 VCCO

2 N.C. (◆)
IO_L09N_2/
T7 GCLK 2 VCCO_2 VCCO_2 R8 VCCO
GCLK13
2 VCCO_2 VCCO_2 R12 VCCO
IO_L09P_2/
2 N.C. (◆) GCLK12 R7 GCLK 3 IO_L01N_3 IO_L01N_3 C1 I/O
IO_L10N_2/ IO_L10N_2/ 3 IO_L01P_3 IO_L01P_3 C2 I/O
2
GCLK15 GCLK15 T8 GCLK
3 IO_L02N_3 IO_L02N_3 D3 I/O
IO_L10P_2/ IO_L10P_2/
2
GCLK14 GCLK14 P8 GCLK 3 IO_L02P_3 IO_L02P_3 D4 I/O
IO_L11N_2/ IO_L11N_2/ 3 IO_L03N_3 IO_L03N_3 E1 I/O
2 GCLK1 GCLK1 P9 GCLK
3 IO_L03P_3 IO_L03P_3 D1 I/O
IO_L11P_2/ IO_L11P_2/
2
GCLK0 GCLK0 N9 GCLK 3 N.C. (◆) IO_L05N_3 E2 I/O

IO_L12N_2/ IO_L12N_2/ 3 N.C. (◆) IO_L05P_3 E3 I/O

2
GCLK3 GCLK3 T9 GCLK
3 N.C. (◆) IO_L07N_3 G4 I/O
IO_L12P_2/ IO_L12P_2/
2
GCLK2 GCLK2 R9 GCLK 3 N.C. (◆) IO_L07P_3 F3 I/O
IO_L08N_3/ IO_L08N_3/
2 N.C. (◆) IO_L13N_2 M10 I/O 3
VREF_3 VREF_3 G1 VREF
2 N.C. (◆) IO_L13P_2 N10 I/O 3 IO_L08P_3 IO_L08P_3 F1 I/O
IO_L14P_2/ IO_L14N_2/
2
MOSI/CSI_B MOSI/CSI_B P10 DUAL 3 N.C. (◆) IO_L09N_3 H4 I/O

2 IO_L14N_2 IO_L14P_2 T10 I/O 3 N.C. (◆) IO_L09P_3 G3 I/O

IO_L15N_2/ IO_L15N_2/ 3 N.C. (◆) IO_L10N_3 H5 I/O

2
DOUT DOUT R11 DUAL
3 N.C. (◆) IO_L10P_3 H6 I/O
IO_L15P_2/ IO_L15P_2/ PWR IO_L11N_3/ IO_L11N_3/
2
AWAKE AWAKE T11 MGMT 3 H1 LHCLK
LHCLK1 LHCLK1
2 IO_L16N_2 IO_L16N_2 N11 I/O IO_L11P_3/ IO_L11P_3/
3
LHCLK0 LHCLK0 G2 LHCLK
2 IO_L16P_2 IO_L16P_2 P11 I/O
IO_L12N_3/ IO_L12N_3/
2 IO_L17N_2/D3 IO_L17N_2/D3 P12 DUAL 3
IRDY2/LHCLK3 IRDY2/LHCLK3 J3 LHCLK
IO_L17P_2/ IO_L17P_2/
2
INIT_B INIT_B T12 DUAL 3
IO_L12P_3/ IO_L12P_3/
H3 LHCLK
LHCLK2 LHCLK2

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Table 67: Spartan-3A FT256 Pinout (XC3S50A, Table 67: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400) (Continued) XC3S200A, XC3S400) (Continued)
XC3S200A FT256 XC3S200A FT256
Bank XC3S50A XC3S400A Ball Type Bank XC3S50A XC3S400A Ball Type

3 IO_L14N_3/ IO_L14N_3/
J1 LHCLK GND GND GND B11 GND
LHCLK5 LHCLK5
GND GND GND C3 GND
IO_L14P_3/ IO_L14P_3/
3
LHCLK4 LHCLK4 J2 LHCLK GND GND GND C14 GND
IO_L15N_3/ IO_L15N_3/ GND GND GND E5 GND
3
LHCLK7 LHCLK7 K1 LHCLK
GND GND GND E12 GND
IO_L15P_3/ IO_L15P_3/
3
TRDY2/LHCLK6 TRDY2/LHCLK6 K3 LHCLK GND GND GND F2 GND

3 N.C. (◆) IO_L16N_3 L2 I/O GND GND GND F6 GND

IO_L16P_3/ GND GND GND G8 GND
3 N.C. (◆)
VREF_3 L1 VREF
GND GND GND G10 GND
3 N.C. (◆) IO_L17N_3 J6 I/O
GND GND GND G15 GND
3 N.C. (◆) IO_L17P_3 J4 I/O
GND GND GND H9 GND
3 N.C. (◆) IO_L18N_3 L3 I/O
GND GND GND J8 GND
3 N.C. (◆) IO_L18P_3 K4 I/O
GND GND GND K2 GND
3 N.C. (◆) IO_L19N_3 L4 I/O
GND GND GND K7 GND
3 N.C. (◆) IO_L19P_3 M3 I/O
GND GND GND K9 GND
3 IO_L20N_3 IO_L20N_3 N1 I/O
GND GND GND L11 GND
3 IO_L20P_3 IO_L20P_3 M1 I/O
GND GND GND L15 GND
3 IO_L22N_3 IO_L22N_3 P1 I/O
GND GND GND M5 GND
3 IO_L22P_3 IO_L22P_3 N2 I/O
GND GND GND M12 GND
3 IO_L23N_3 IO_L23N_3 P2 I/O
GND GND GND P3 GND
3 IO_L23P_3 IO_L23P_3 R1 I/O
GND GND GND P14 GND
3 IO_L24N_3 IO_L24N_3 M4 I/O
GND GND GND R6 GND
3 IO_L24P_3 IO_L24P_3 N3 I/O
GND GND GND R10 GND
IP_L04N_3/ IP_L04N_3/
3
VREF_3 VREF_3 F4 VREF GND GND GND T1 GND

3 IP_L04P_3 IP_L04P_3 E4 INPUT GND GND GND T16 GND

IP_L06N_3/ PWR
3 N.C. (◆) G5 VREF VCCAUX SUSPEND SUSPEND R16 MGMT
VREF_3
3 N.C. (◆) IP_L06P_3 G6 INPUT VCCAUX DONE DONE T15 CONFIG

3 IP_L13N_3 IP_L13N_3 J7 INPUT VCCAUX PROG_B PROG_B A2 CONFIG

3 IP_L13P_3 IP_L13P_3 H7 INPUT VCCAUX TCK TCK A15 JTAG

3 IP_L21N_3 IP_L21N_3 K6 INPUT VCCAUX TDI TDI B1 JTAG

3 IP_L21P_3 IP_L21P_3 K5 INPUT VCCAUX TDO TDO B16 JTAG

IP_L25N_3/ IP_L25N_3/ VCCAUX TMS TMS B2 JTAG

3
VREF_3 VREF_3 L6 VREF
VCCAUX VCCAUX VCCAUX E11 VCCAUX
3 IP_L25P_3 IP_L25P_3 L5 INPUT VCCAUX VCCAUX VCCAUX F5 VCCAUX
3 VCCO_3 VCCO_3 D2 VCCO VCCAUX VCCAUX VCCAUX L12 VCCAUX
3 VCCO_3 VCCO_3 H2 VCCO VCCAUX VCCAUX VCCAUX M6 VCCAUX
3 VCCO_3 VCCO_3 J5 VCCO VCCINT VCCINT VCCINT G7 VCCINT
3 VCCO_3 VCCO_3 M2 VCCO VCCINT VCCINT VCCINT G9 VCCINT
GND GND GND A1 GND VCCINT VCCINT VCCINT H8 VCCINT
GND GND GND A16 GND VCCINT VCCINT VCCINT J9 VCCINT
GND GND GND B7 GND

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Table 67: Spartan-3A FT256 Pinout (XC3S50A, Table 68: Spartan-3A FT256 Pinout (XC3S700A,
XC3S200A, XC3S400) (Continued) XC3S700A FT256
Bank Type
XC3S200A FT256 XC3S1400A Ball
Bank XC3S50A XC3S400A Ball Type 0 IO_L18N_0 B4 I/O
VCCINT VCCINT VCCINT K8 VCCINT
0 IO_L18P_0 A4 I/O
VCCINT VCCINT VCCINT K10 VCCINT
0 IO_L19N_0 B3 I/O

Table 68: Spartan-3A FT256 Pinout (XC3S700A, XC3S1400A) 0 IO_L19P_0 A3 I/O

XC3S700A FT256 0 IO_L20N_0/PUDC_B D5 DUAL

Bank Type
XC3S1400A Ball 0 IO_L20P_0/VREF_0 C4 VREF
0 IO_L01N_0 C13 I/O 0 IP_0 E6 INPUT
0 IO_L01P_0 D13 I/O 0 VCCO_0 B13 VCCO
0 IO_L02N_0 B14 I/O 0 VCCO_0 B5 VCCO
0 IO_L02P_0/VREF_0 B15 VREF 0 VCCO_0 B9 VCCO
0 IO_L03N_0 D12 I/O 0 VCCO_0 E8 VCCO
0 IO_L03P_0 C12 I/O 1 IO_L01N_1/LDC2 N14 DUAL
0 IO_L04N_0 A13 I/O 1 IO_L01P_1/HDC N13 DUAL
0 IO_L04P_0 A14 I/O 1 IO_L02N_1/LDC0 P15 DUAL
0 IO_L05N_0 A12 I/O 1 IO_L02P_1/LDC1 R15 DUAL
0 IO_L05P_0 B12 I/O 1 IO_L03N_1/A1 N16 DUAL
0 IO_L06N_0/VREF_0 D10 VREF 1 IO_L03P_1/A0 P16 DUAL
0 IO_L06P_0 D11 I/O 1 IO_L06N_1/A3 K13 DUAL
0 IO_L07N_0 A11 I/O 1 IO_L06P_1/A2 L13 DUAL
0 IO_L07P_0 C11 I/O 1 IO_L07N_1/A5 M16 DUAL
0 IO_L08N_0 A10 I/O 1 IO_L07P_1/A4 M15 DUAL
0 IO_L08P_0 B10 I/O 1 IO_L08N_1/A7 L16 DUAL
0 IO_L09N_0/GCLK5 D9 GCLK 1 IO_L08P_1/A6 L14 DUAL
0 IO_L09P_0/GCLK4 C10 GCLK 1 IO_L10N_1/A9 J13 DUAL
0 IO_L10N_0/GCLK7 A9 GCLK 1 IO_L10P_1/A8 J12 DUAL
0 IO_L10P_0/GCLK6 C9 GCLK 1 IO_L11N_1/RHCLK1 K14 RHCLK
0 IO_L11N_0/GCLK9 D8 GCLK 1 IO_L11P_1/RHCLK0 K15 RHCLK
0 IO_L11P_0/GCLK8 C8 GCLK 1 IO_L12N_1/TRDY1/RHCLK3 J16 RHCLK
0 IO_L12N_0/GCLK11 B8 GCLK 1 IO_L12P_1/RHCLK2 K16 RHCLK
0 IO_L12P_0/GCLK10 A8 GCLK 1 IO_L15N_1/RHCLK7 H16 RHCLK
0 IO_L13N_0 C7 I/O 1 IO_L15P_1/IRDY1/RHCLK6 H15 RHCLK
0 IO_L13P_0 A7 I/O 1 IO_L16N_1/A11 F16 DUAL
0 IO_L14N_0/VREF_0 E7 VREF 1 IO_L16P_1/A10 G16 DUAL
0 IO_L14P_0 E9 I/O 1 IO_L17N_1/A13 G14 DUAL
0 IO_L15N_0 B6 I/O 1 IO_L17P_1/A12 H13 DUAL
0 IO_L15P_0 A6 I/O 1 IO_L18N_1/A15 F15 DUAL
0 IO_L16N_0 C6 I/O 1 IO_L18P_1/A14 E16 DUAL
0 IO_L16P_0 D7 I/O 1 IO_L19N_1/A17 F14 DUAL
0 IO_L17N_0 C5 I/O 1 IO_L19P_1/A16 G13 DUAL
0 IO_L17P_0 A5 I/O 1 IO_L20N_1/A19 F13 DUAL

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Table 68: Spartan-3A FT256 Pinout (XC3S700A, Table 68: Spartan-3A FT256 Pinout (XC3S700A,
XC3S700A FT256 XC3S700A FT256
Bank Type Bank Type
XC3S1400A Ball XC3S1400A Ball
1 IO_L20P_1/A18 E14 DUAL 2 IO_L16N_2 N11 I/O
1 IO_L22N_1/A21 D15 DUAL 2 IO_L16P_2 P11 I/O
1 IO_L22P_1/A20 D16 DUAL 2 IO_L17N_2/D3 P12 DUAL
1 IO_L23N_1/A23 D14 DUAL 2 IO_L17P_2/INIT_B T12 DUAL
1 IO_L23P_1/A22 E13 DUAL 2 IO_L18N_2/D1 R13 DUAL
1 IO_L24N_1/A25 C15 DUAL 2 IO_L18P_2/D2 T13 DUAL
1 IO_L24P_1/A24 C16 DUAL 2 IO_L19N_2 P13 I/O
1 IP_1/VREF_1 H12 VREF 2 IO_L19P_2 N12 I/O
1 IP_1/VREF_1 J14 VREF 2 IO_L20N_2/CCLK R14 DUAL
1 IP_1/VREF_1 M13 VREF 2 IO_L20P_2/D0/DIN/MISO T14 DUAL
1 IP_1/VREF_1 M14 VREF 2 IP_2/VREF_2 M11 VREF
1 VCCO_1 E15 VCCO 2 IP_2/VREF_2 M7 VREF
1 VCCO_1 J15 VCCO 2 IP_2/VREF_2 M9 VREF
1 VCCO_1 N15 VCCO 2 IP_2/VREF_2 N5 VREF
2 IO_L01N_2/M0 P4 DUAL 2 IP_2/VREF_2 P6 VREF
2 IO_L01P_2/M1 N4 DUAL 2 VCCO_2 R12 VCCO
2 IO_L02N_2/CSO_B T2 DUAL 2 VCCO_2 R4 VCCO
2 IO_L02P_2/M2 R2 DUAL 2 VCCO_2 R8 VCCO
2 IO_L03N_2/VS2 T3 DUAL 3 IO_L01N_3 C1 I/O
2 IO_L03P_2/RDWR_B R3 DUAL 3 IO_L01P_3 C2 I/O
2 IO_L04N_2/VS0 P5 DUAL 3 IO_L02N_3 D3 I/O
2 IO_L04P_2/VS1 N6 DUAL 3 IO_L02P_3 D4 I/O
2 IO_L05N_2 R5 I/O 3 IO_L03N_3 E1 I/O
2 IO_L05P_2 T4 I/O 3 IO_L03P_3 D1 I/O
2 IO_L06N_2/D6 T6 DUAL 3 IO_L04N_3 F4 I/O
2 IO_L06P_2/D7 T5 DUAL 3 IO_L04P_3 E4 I/O
2 IO_L08N_2/D4 N8 DUAL 3 IO_L05N_3 E2 I/O
2 IO_L08P_2/D5 P7 DUAL 3 IO_L05P_3 E3 I/O
2 IO_L09N_2/GCLK13 T7 GCLK 3 IO_L07N_3 G3 I/O
2 IO_L09P_2/GCLK12 R7 GCLK 3 IO_L07P_3 F3 I/O
2 IO_L10N_2/GCLK15 T8 GCLK 3 IO_L08N_3/VREF_3 G1 VREF
2 IO_L10P_2/GCLK14 P8 GCLK 3 IO_L08P_3 F1 I/O
2 IO_L11N_2/GCLK1 P9 GCLK 3 IO_L11N_3/LHCLK1 H1 LHCLK
2 IO_L11P_2/GCLK0 N9 GCLK 3 IO_L11P_3/LHCLK0 G2 LHCLK
2 IO_L12N_2/GCLK3 T9 GCLK 3 IO_L12N_3/IRDY2/LHCLK3 J3 LHCLK
2 IO_L12P_2/GCLK2 R9 GCLK 3 IO_L12P_3/LHCLK2 H3 LHCLK
2 IO_L14N_2/MOSI/CSI_B P10 DUAL 3 IO_L14N_3/LHCLK5 J1 LHCLK
2 IO_L14P_2 T10 I/O 3 IO_L14P_3/LHCLK4 J2 LHCLK
2 IO_L15N_2/DOUT R11 DUAL 3 IO_L15N_3/LHCLK7 K1 LHCLK
2 IO_L15P_2/AWAKE T11 PWRMGT 3 IO_L15P_3/TRDY2/LHCLK6 K3 LHCLK

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Table 68: Spartan-3A FT256 Pinout (XC3S700A, Table 68: Spartan-3A FT256 Pinout (XC3S700A,
XC3S700A FT256 XC3S700A FT256
Bank Type Bank Type
XC3S1400A Ball XC3S1400A Ball
3 IO_L16N_3 L2 I/O GND GND G8 GND
3 IO_L16P_3/VREF_3 L1 VREF GND GND H11 GND
3 IO_L18N_3 L3 I/O GND GND H5 GND
3 IO_L18P_3 K4 I/O GND GND H7 GND
3 IO_L19N_3 L4 I/O GND GND H9 GND
3 IO_L19P_3 M3 I/O GND GND J10 GND
3 IO_L20N_3 N1 I/O GND GND J6 GND
3 IO_L20P_3 M1 I/O GND GND J8 GND
3 IO_L22N_3 P1 I/O GND GND K11 GND
3 IO_L22P_3/VREF_3 N2 VREF GND GND K12 GND
3 IO_L23N_3 P2 I/O GND GND K2 GND
3 IO_L23P_3 R1 I/O GND GND K5 GND
3 IO_L24N_3 M4 I/O GND GND K7 GND
3 IO_L24P_3 N3 I/O GND GND K9 GND
3 IP_3 J4 INPUT GND GND L10 GND
3 IP_3/VREF_3 G4 VREF GND GND L11 GND
3 IP_3/VREF_3 J5 VREF GND GND L15 GND
3 VCCO_3 D2 VCCO GND GND L6 GND
3 VCCO_3 H2 VCCO GND GND L8 GND
3 VCCO_3 M2 VCCO GND GND M12 GND
GND GND A1 GND GND GND M5 GND
GND GND A16 GND GND GND M8 GND
GND GND B11 GND GND GND N10 GND
GND GND B7 GND GND GND N7 GND
GND GND C14 GND GND GND P14 GND
GND GND C3 GND GND GND P3 GND
GND GND E10 GND GND GND R10 GND
GND GND E12 GND GND GND R6 GND
GND GND E5 GND GND GND T1 GND
GND GND F11 GND GND GND T16 GND
GND GND F2 GND VCCAUX SUSPEND R16 PWRMGT
GND GND F6 GND VCCAUX DONE T15 CONFIG
GND GND F7 GND VCCAUX PROG_B A2 CONFIG
GND GND F8 GND VCCAUX TCK A15 JTAG
GND GND F9 GND VCCAUX TDI B1 JTAG
GND GND G10 GND VCCAUX TDO B16 JTAG
GND GND G12 GND VCCAUX TMS B2 JTAG
GND GND G15 GND VCCAUX VCCAUX D6 VCCAUX
GND GND G5 GND VCCAUX VCCAUX E11 VCCAUX
GND GND G6 GND VCCAUX VCCAUX F12 VCCAUX

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Pinout Descriptions

Table 68: Spartan-3A FT256 Pinout (XC3S700A,

XC3S700A FT256
Bank Type
XC3S1400A Ball
VCCAUX VCCAUX F5 VCCAUX
VCCAUX VCCAUX H14 VCCAUX
VCCAUX VCCAUX H4 VCCAUX
VCCAUX VCCAUX L12 VCCAUX
VCCAUX VCCAUX L5 VCCAUX
VCCAUX VCCAUX M10 VCCAUX
VCCAUX VCCAUX M6 VCCAUX
VCCINT VCCINT F10 VCCINT
VCCINT VCCINT G11 VCCINT
VCCINT VCCINT G7 VCCINT
VCCINT VCCINT G9 VCCINT
VCCINT VCCINT H10 VCCINT
VCCINT VCCINT H6 VCCINT
VCCINT VCCINT H8 VCCINT
VCCINT VCCINT J11 VCCINT
VCCINT VCCINT J7 VCCINT
VCCINT VCCINT J9 VCCINT
VCCINT VCCINT K10 VCCINT
VCCINT VCCINT K6 VCCINT
VCCINT VCCINT K8 VCCINT
VCCINT VCCINT L7 VCCINT
VCCINT VCCINT L9 VCCINT

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 Pinout Descriptions

User I/Os by Bank

Table 69, Table 70, and Table 71 indicate how the available The XC3S50A FPGA in the FT256 package has 51
user-I/O pins are distributed between the four I/O banks on unconnected balls, labeled with an “N.C.” type. These pins
the FT256 package. The AWAKE pin is counted as a are also indicated in Figure 20.
dual-purpose I/O.

Table 69: User I/Os Per Bank on XC3S50A in the FT256 Package

Package All Possible I/O Pins by Type

Edge I/O Bank Maximum I/O
I/O INPUT DUAL VREF CLK
Top 0 40 21 7 1 3 8
Right 1 32 12 5 4 3 8
Bottom 2 40 5 2 21 6 6
Left 3 32 15 6 0 3 8
TOTAL 144 53 20 26 15 30
.

Table 70: User I/Os Per Bank on XC3S200A and XC3S400A in the FT256 Package

Package All Possible I/O Pins by Type

Edge I/O Bank Maximum I/O
I/O INPUT DUAL VREF CLK
Top 0 47 27 6 1 5 8
Right 1 50 1 6 30 5 8
Bottom 2 48 11 2 21 6 8
Left 3 50 30 7 0 5 8
TOTAL 195 69 21 52 21 32

Table 71: User I/Os Per Bank on XC3S700A and XC3S1400A in the FT256 Package

Package All Possible I/O Pins by Type

I/O Bank Maximum I/O
Edge I/O INPUT DUAL VREF CLK
Top 0 41 27 1 1 4 8
Right 1 40 0 0 30 4 6
Bottom 2 41 7 0 21 5 8
Left 3 39 25 1 0 5 8
TOTAL 161 59 2 52 18 30

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Pinout Descriptions

Footprint Migration Differences

Unconnected Balls on XC3S50A
Table 72 summarizes any footprint and functionality Table 72: FT256 XC3S50A Footprint Migration
differences between the XC3S50A and the XC3S200A or XC3S200A/
XC3S400A FPGAs that might affect easy migration between FT256 XC3S50A XC3S400A
these devices in the FT256 package. The XC3S200A and Ball Bank Type Migration Type
XC3S400A have identical pinouts. The XC3S50A pinout is K4 3 N.C.  I/O
compatible, but there are 52 balls that are different. K13 1 N.C.  I/O
Generally, designs easily migrate upward from the
L1 3 N.C.  I/O
XC3S50A to either the XC3S200A or XC3S400A. If using
differential I/O, see Table 73. If using the BPI configuration L2 3 N.C.  I/O
mode (parallel Flash), see Table 74. L3 3 N.C.  I/O

Table 72: FT256 XC3S50A Footprint Migration Difference L4 3 N.C.  I/O

XC3S200A/ L13 1 N.C.  I/O

FT256 XC3S50A XC3S400A
Ball Bank Type Migration Type L14 1 N.C.  I/O

A7 0 N.C.  I/O L16 1 N.C.  I/O

A12 0 N.C.  I/O M3 3 N.C.  I/O

B12 0 INPUT  I/O M10 2 N.C.  I/O

C7 0 N.C.  I/O M13 1 N.C.  I/O

D10 0 N.C.  I/O M14 1 N.C.  I/O

E2 3 N.C.  I/O M15 1 N.C.  I/O

E3 3 N.C.  I/O M16 1 N.C.  I/O

E7 0 N.C.  I/O N7 2 N.C.  I/O

E10 0 N.C.  I/O N10 2 N.C.  I/O

E16 1 N.C.  I/O N12 2 N.C.  I/O

F3 3 N.C.  I/O P6 2 N.C.  I/O

F8 0 N.C.  I/O P13 2 N.C.  I/O

F14 1 N.C.  I/O R7 2 N.C.  I/O

F15 1 N.C.  I/O T7 2 N.C.  I/O

F16 1 N.C.  I/O DIFFERENCES 52

Legend:
G3 3 N.C.  I/O
 This pin can unconditionally migrate from the device
G4 3 N.C.  I/O on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
G5 3 N.C.  INPUT configured for the device on the right.
G6 3 N.C.  INPUT
G13 1 N.C.  I/O
G14 1 N.C.  I/O
G16 1 N.C.  I/O
H4 3 N.C.  I/O
H5 3 N.C.  I/O
H6 3 N.C.  I/O
H13 1 N.C.  I/O
J4 3 N.C.  I/O
J6 3 N.C.  I/O
J10 1 N.C.  INPUT
J11 1 N.C.  INPUT

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XC3S50A Differential I/O Alignment Differences

Also, some differential I/O pairs on the XC3S50A FPGA are Table 73: Differential I/O Differences in FT256
aligned differently than the corresponding pairs on the
FT256 XC3S200A
XC3S200A or XC3S400A FPGAs, as shown in Table 73. All Ball Bank XC3S50A XC3S400A
the mismatched pairs are in I/O Bank 2. The shading
highlights the N side of each pair. T3 IO_L04P_2/VS2 IO_L03N_2/VS2
N6 IO_L03N_2/VS1 IO_L04P_2/VS1
R5 IO_L06P_2 IO_L05N_2
T5 IO_L05N_2/D7 IO_L06P_2/D7
2 IO_L14P_2/MOSI IO_L14N_2/MOSI
P10 /CSI_B /CSI_B
T10 IO_L14N_2 IO_L14P_2
R13 IO_L20P_2 IO_L18N_2
T14 IO_L18N_2 IO_L20P_2

XC3S50A Does Not Have BPI Mode Address Outputs

The XC3S50A FPGA does not generate the BPI-mode
address pins during configuration. Table 74 summarizes
these differences.

Table 74: XC3S50A BPI Functional Differences

FT256 Bank XC3S50A XC3S200A
Ball XC3S400A
N16 IO_L03N_1 IO_L03N_1/A1
P16 IO_L03P_1 IO_L03P_1/A0
J13 IO_L10N_1 IO_L10N_1/A9
J12 IO_L10P_1 IO_L10P_1/A8
F13 IO_L20N_1 IO_L20N_1/A19
E14 IO_L20P_1 IO_L20P_1/A18
1
D15 IO_L22N_1 IO_L22N_1/A21
D16 IO_L22P_1 IO_L22P_1/A20
D14 IO_L23N_1 IO_L23N_1/A23
E13 IO_L23P_1 IO_L23P_1/A22
C15 IO_L24N_1 IO_L24N_1/A25
C16 IO_L24P_1 IO_L24P_1/A24

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Differences Between XC3S200A/XC3S400A and XC3S700A/XC3S1400A

The XC3S700A and XC3S1400A FPGAs have several Table 75: Differences Between XC3S200A/XC3S400A
additional power and ground pins as compared to the and XC3S700A/XC3S1400A (Continued)
XC3S200A and XC3S400A. Table 75 summarizes all the XC3S200A XC3S700A
differences. All dedicated and dual-purpose configuration FT256 Bank XC3S400A XC3S1400A
pins are in the same location. Ball
Pin Name Type Pin Name Type
Table 75: Differences Between XC3S200A/XC3S400A N10 2 IO_L13P_2 I/O GND GND
and XC3S700A/XC3S1400A
M10 2 IO_L13N_2 I/O VCCAUX VCCAUX
XC3S200A XC3S700A
FT256 XC3S400A XC3S1400A IP_2/
P6 2 IO_L07N_2 I/O VREF
Ball Bank VREF_2
Pin Name Type Pin Name Type
L8 2 IP_2 INPUT GND GND
F8 0 IO_L14P_0 I/O GND GND
L7 2 IP_2 INPUT VCCINT VCCINT
D11 0 IO_L03N_0 I/O IO_L06P_0 I/O
IP_2/
M9 2 VCCO_2 VCCO VREF
IO_L06N_0/ VREF_2
D10 0 IO_L06P_0 I/O VREF
VREF_0
IP_2/
L10 2 VREF GND GND
F7 0 IP_0 INPUT GND GND VREF_2

F9 0 IP_0 INPUT GND GND IP_2/

M8 2 VREF GND GND
VREF_2
D12 0 IP_0 INPUT IO_L03N_0 I/O
IP_2/
L9 2 VREF VCCINT VCCINT
IP_0/ VREF_2
E9 0 INPUT IO_L14P_0 I/O
VREF_0
H5 3 IO_L10N_3 I/O GND GND
D6 0 IP_0 INPUT VCCAUX VCCAUX
J6 3 IO_L17N_3 I/O GND GND
F10 0 IP_0 INPUT VCCINT VCCINT
G3 3 IO_L09P_3 I/O IO_L07N_3 I/O
IO_L06N_0/
E10 0 VREF GND GND J4 3 IO_L17P_3 I/O IP_3 IP
VREF_0
IP_1/ H4 3 IO_L09N_3 I/O VCCAUX VCCAUX
M13 1 IO_L05P_1 I/O VREF
VREF_1
H6 3 IO_L10P_3 I/O VCCINT VCCINT
F11 1 IP_L25N_1 INPUT GND GND
IO_L22P_3/
N2 3 IO_L22P_3 I/O VREF
H11 1 IP_L13N_1 INPUT GND GND VREF_3

K11 1 IP_L04P_1 INPUT GND GND IP_3/

G4 3 IO_L07N_3 I/O VREF
VREF_3
G11 1 IP_L21N_1 INPUT VCCINT VCCINT
G6 3 IP_L06P_3 INPUT GND GND
H10 1 IP_L13P_1 INPUT VCCINT VCCINT
H7 3 IP_L13P_3 INPUT GND GND
J11 1 IP_L09N_1 INPUT VCCINT VCCINT
K5 3 IP_L21P_3 INPUT GND GND
IO_L14N_1/ RHCLK VCCAUX
H14 1 VCCAUX E4 3 IP_L04P_3 INPUT IO_L04P_3 I/O
RHCLK5
IO_L14P_1/ RHCLK IP_1/ L5 3 IP_L25P_3 INPUT VCCAUX VCCAUX
J14 1 VREF
RHCLK4 VREF_1
J7 3 IP_L13N_3 INPUT VCCINT VCCINT
IP_1/
H12 1 VCCO_1 VCCO VREF K6 3 IP_L21N_3 INPUT VCCINT VCCINT
VREF_1
IP_L21P_1/ IP_3/
G12 1 VREF GND GND J5 3 VCCO_3 VCCO VREF
VREF_1 VREF_3

IP_L09P_1/ IP_L06N_3/
J10 1 VREF GND GND G5 3 VREF GND GND
VREF_1 VREF_3

IP_L04N_1/ IP_L25N_3/
K12 1 VREF GND GND L6 3 VREF GND GND
VREF_1 VREF_3

IP_L25P_1/ IP_L04N_3/
F12 1 VREF VCCAUX VCCAUX F4 3 VREF IO_L04N_3 I/O
VREF_1 VREF_3

IO_L05N_1/ IP_1/
M14 1 VREF VREF
VREF_1 VREF_1
N7 2 IO_L07P_2 I/O GND GND

90 www.xilinx.com DS529 (v2.1) December 18, 2018

 Pinout Descriptions

FT256 Footprint (XC3S50A)

(Differential Outputs) Bank 0 (Differential Outputs)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I/O I/O

_B
I/O I/O I/O I/O I/O I/O I/O I/O
A

G
GND N.C. L12P_0 L10N_0 N.C. TCK GND

O
L19P_0 L18P_0 L17P_0 L15P_0 L08N_0 L07N_0 L04N_0 L04P_0
PR GCLK10 GCLK7

I/O I/O
I/O I/O I/O I/O I/O
B TDI TMS
L19N_0 L18N_0
VCCO_0
L15N_0
GND L12N_0 VCCO_0
L08P_0
GND INPUT VCCO_0
L02N_0
L02P_0 TDO
GCLK11 VREF_0

I/O I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O I/O I/O
C L01N_3 L01P_3
GND L20P_0
L17N_0 L16N_0
N.C. L11P_0 L10P_0 L09P_0
L07P_0 L03P_0 L01N_0
GND
L24N_1 L24P_1
VREF_0 GCLK8 GCLK6 GCLK4

(High Output Drive)

(High Output Drive)

I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O I/O I/O
D L03P_3
VCCO_3
L02N_3 L02P_3
L20N_0 INPUT
L16P_0
L11N_0 L09N_0 N.C.
L03N_0
INPUT
L01P_0 L23N_1 L22N_1 L22P_1
PUDC_B GCLK9 GCLK5

I/O INPUT INPUT I/O I/O

E L03N_3
N.C. N.C.
L04P_3
GND INPUT N.C. VCCO_0
VREF_0
N.C. VCCAUX GND
L23P_1 L20P_1
VCCO_1 N.C.

INPUT INPUT
I/O INPUT I/O
F L08P_3
GND N.C. L04N_3 VCCAUX GND INPUT N.C. INPUT INPUT
L25N_1
L25P_1
L20N_1
N.C. N.C. N.C.
VREF_3 VREF_1

I/O I/O INPUT

INPUT
G L08N_3 L11P_3 N.C. N.C. N.C. N.C. VCCINT GND VCCINT GND
L21N_1
L21P_1 N.C. N.C. GND N.C.
VREF_3 LHCLK0 VREF_1

I/O I/O I/O I/O I/O

INPUT INPUT INPUT L15P_1
H L11N_3 VCCO_3 L12P_3 N.C. N.C. N.C. VCCINT GND VCCO_1 N.C. L14N_1
IRDY1
L15N_1
Bank 3

Bank 1
L13P_3 L13P_1 L13N_1
LHCLK1 LHCLK2 RHCLK5 RHCLK6 RHCLK7

I/O I/O I/O I/O I/O

L12N_3 INPUT I/O I/O L12N_1
J L14N_3 L14P_3
IRDY2
N.C. VCCO_3 N.C.
L13N_3
GND VCCINT N.C. N.C.
L10P_1 L10N_1
L14P_1 VCCO_1
TRDY1
LHCLK5 LHCLK4 LHCLK3 RHCLK4 RHCLK3

I/O I/O INPUT I/O I/O I/O

L15P_3 INPUT INPUT INPUT
K L15N_3 GND TRDY2
N.C.
L21P_3 L21N_3
GND VCCINT GND VCCINT
L04P_1
L04N_1 N.C. L11N_1 L11P_1 L12P_1
LHCLK7 LHCLK6 VREF_1 RHCLK1 RHCLK0 RHCLK2

INPUT
(High Output Drive)

(High Output Drive)

INPUT INPUT INPUT
L N.C. N.C. N.C. N.C.
L25P_3
L25N_3 INPUT INPUT
VREF_2 VREF_2
GND VCCAUX N.C. N.C. GND N.C.
VREF_3

I/O I/O INPUT INPUT INPUT

M L20P_3
VCCO_3 N.C.
L24N_3
GND VCCAUX
VREF_2 VREF_2
VCCO_2 N.C.
VREF_2
GND N.C. N.C. N.C. N.C.

I/O I/O I/O I/O I/O I/O

I/O I/O I/O INPUT I/O I/O
N L20N_3 L22P_3 L24P_3
L01P_2
VREF_2
L03N_2 N.C. L08N_2 L11P_2 N.C.
L16N_2
N.C. L01P_1 L01N_1 VCCO_1
L03N_1
M1 VS1 D4 GCLK0 HDC LDC2

I/O I/O I/O I/O I/O I/O I/O I/O

I/O I/O L14P_2 I/O I/O
P L22N_3 L23N_3
GND L01N_2 L04N_2 N.C. L08P_2 L10P_2 L11N_2
MOSI L16P_2
L17N_2 N.C. GND L02N_1
L03P_1
M0 VS0 D5 GCLK14 GCLK1 CSI_B D3 LDC0

D
I/O I/O I/O I/O I/O I/O I/O

EN
I/O I/O
R L23P_3
L02P_2 L03P_2 VCCO_2
L06P_2
GND N.C. VCCO_2 L12P_2 GND L15N_2 VCCO_2 L20P_2 L20N_2 L02P_1 SP
SU

M2 RDWR_B GCLK2 DOUT D1 CCLK LDC1

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O L18N_2
T GND L02N_2 L04P_2
L05P_2
L05N_2 L06N_2 N.C. L10N_2 L12N_2
L14N_2
L15P_2 L17P_2 L18P_2
D0
DONE GND
CSO_B VS2 D7 D6 GCLK15 GCLK3 AWAKE INIT_B D2 DIN/MISO

(Differential Outputs) Bank 2 (Differential Outputs) DS529-4_09_012009

Figure 20: XC3S50A FT256 Package Footprint (Top View)

I/O: Unrestricted, DUAL: Configuration pins, VREF: User I/O or input SUSPEND: Dedicated
53 general-purpose user I/O 25 then possible user I/O 15 voltage reference for bank 2 SUSPEND and
dual-purpose AWAKE
INPUT: Unrestricted, CLK: User I/O, input, or VCCO: Output voltage Power Management pins
20 general-purpose input pin 30 global buffer input 16 supply for bank

CONFIG: Dedicated JTAG: Dedicated JTAG VCCINT: Internal core

2 configuration pins 4 port pins 6 supply voltage (+1.2V)

N.C.: Not connected GND: Ground VCCAUX: Auxiliary supply

51 (XC3S50A only) 28 4 voltage

DS529 (v2.1) December 18, 2018 www.xilinx.com 91

Pinout Descriptions

FT256 Footprint (XC3S200A, XC3S400A)

Bank 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I/O I/O

_B
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
A

G
GND L12P_0 L10N_0 TCK GND

O
L19P_0 L18P_0 L17P_0 L15P_0 L13P_0 L08N_0 L07N_0 L05N_0 L04N_0 L04P_0
PR
GCLK10 GCLK7

I/O I/O
I/O I/O I/O I/O I/O I/O
B TDI TMS
L19N_0 L18N_0
VCCO_0
L15N_0
GND L12N_0 VCCO_0
L08P_0
GND
L05P_0
VCCO_0
L02N_0
L02P_0 TDO
GCLK11 VREF_0

I/O I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O I/O
C L01N_3 L01P_3
GND L20P_0
L17N_0 L16N_0 L13N_0
L11P_0 L10P_0 L09P_0
L07P_0 L03P_0 L01N_0
GND L24N_1 L24P_1
VREF_0 GCLK8 GCLK6 GCLK4 A25 A24

I/O I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O
D L03P_3
VCCO_3
L02N_3 L02P_3
L20N_0 INPUT
L16P_0
L11N_0 L09N_0
L06P_0 L03N_0
INPUT
L01P_0
L23N_1 L22N_1 L22P_1
PUDC_B GCLK9 GCLK5 A23 A21 A20

I/O I/O I/O I/O I/O

I/O I/O I/O INPUT INPUT
E L03N_3 L05N_3 L05P_3 L04P_3
GND INPUT L14N_0 VCCO_0
VREF_0
L06N_0 VCCAUX GND L23P_1 L20P_1 VCCO_1 L18P_1
VREF_0 VREF_0 A22 A18 A14

INPUT INPUT I/O I/O I/O I/O

I/O I/O I/O INPUT
F L08P_3
GND
L07P_3
L04N_3 VCCAUX GND INPUT
L14P_0
INPUT INPUT
L25N_1
L25P_1 L20N_1 L19N_1 L18N_1 L16N_1
VREF_3 VREF_1 A19 A17 A15 A11

I/O I/O INPUT INPUT I/O I/O I/O

I/O I/O INPUT INPUT
G L08N_3 L11P_3
L09P_3 L07N_3
L06N_3
L06P_3
VCCINT GND VCCINT GND
L21N_1
L21P_1 L19P_1 L17N_1 GND L16P_1
VREF_3 LHCLK0 VREF_3 VREF_1 A16 A13 A10

I/O I/O I/O I/O I/O I/O

I/O I/O I/O INPUT INPUT INPUT L15P_1
H L11N_3 VCCO_3 L12P_3 VCCINT GND VCCO_1 L17P_1 L14N_1
IRDY1
L15N_1
Bank 3

Bank 1
L09N_3 L10N_3 L10P_3 L13P_3 L13P_1 L13N_1
LHCLK1 LHCLK2 A12 RHCLK5 RHCLK6 RHCLK7

I/O I/O I/O INPUT I/O I/O I/O I/O

L12N_3 I/O I/O INPUT INPUT L12N_1
J L14N_3 L14P_3
IRDY2 L17P_3
VCCO_3
L17N_3 L13N_3
GND VCCINT L09P_1
L09N_1
L10P_1 L10N_1 L14P_1 VCCO_1
TRDY1
LHCLK5 LHCLK4 LHCLK3 VREF_1 A8 A9 RHCLK4 RHCLK3

I/O I/O INPUT I/O I/O I/O I/O

L15P_3 I/O INPUT INPUT INPUT
K L15N_3 GND TRDY2 L18P_3 L21P_3 L21N_3
GND VCCINT GND VCCINT
L04P_1
L04N_1 L06N_1 L11N_1 L11P_1 L12P_1
LHCLK7 LHCLK6 VREF_1 A3 RHCLK1 RHCLK0 RHCLK2

I/O INPUT I/O I/O I/O

I/O I/O I/O INPUT INPUT INPUT
L L16P_3
L16N_3 L18N_3 L19N_3 L25P_3
L25N_3 INPUT INPUT
VREF_2 VREF_2
GND VCCAUX L06P_1 L08P_1 GND L08N_1
VREF_3 VREF_3 A2 A6 A7

I/O I/O I/O

I/O I/O I/O INPUT INPUT I/O INPUT I/O
M L20P_3
VCCO_3
L19P_3 L24N_3
GND VCCAUX
VREF_2 VREF_2
VCCO_2
L13N_2 VREF_2
GND
L05P_1
L05N_1 L07P_1 L07N_1
VREF_1 A4 A5

I/O I/O I/O I/O I/O I/O I/O

I/O I/O I/O INPUT I/O I/O I/O I/O
N L20N_3 L22P_3 L24P_3
L01P_2
VREF_2
L04P_2
L07P_2
L08N_2 L11P_2
L13P_2 L16N_2 L19P_2
L01P_1 L01N_1 VCCO_1 L03N_1
M1 VS1 D4 GCLK0 HDC LDC2 A1

I/O I/O I/O I/O I/O I/O I/O I/O I/O

I/O I/O I/O L14N_2 I/O I/O
P L22N_3 L23N_3
GND L01N_2 L04N_2
L07N_2
L08P_2 L10P_2 L11N_2
MOSI L16P_2
L17N_2
L19N_2
GND L02N_1 L03P_1
M0 VS0 D5 GCLK14 GCLK1 CSI_B D3 LDC0 A0

I/O I/O I/O I/O I/O I/O I/O I/O

D
N
I/O I/O
E
R L23P_3
L02P_2 L03P_2 VCCO_2
L05N_2
GND L09P_2 VCCO_2 L12P_2 GND L15N_2 VCCO_2 L18N_2 L20N_2 L02P_1 SU
SP
M2 RDWR_B GCLK12 GCLK2 DOUT D1 CCLK LDC1

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O L20P_2
T GND L02N_2 L03N_2
L05P_2
L06P_2 L06N_2 L09N_2 L10N_2 L12N_2
L14P_2
L15P_2 L17P_2 L18P_2
D0
DONE GND
CSO_B VS2 D7 D6 GCLK13 GCLK15 GCLK3 AWAKE INIT_B D2 DIN/MISO

Bank 2 DS529-4_06_012009

Figure 21: XC3S200A and XC3S400A FT256 Package Footprint (Top View)

I/O: Unrestricted, DUAL: Configuration pins, VREF: User I/O or input SUSPEND: Dedicated
69 general-purpose user I/O 51 then possible user I/O 21 voltage reference for bank 2 SUSPEND and
dual-purpose AWAKE
INPUT: Unrestricted, CLK: User I/O, input, or VCCO: Output voltage Power Management pins
21 general-purpose input pin 32 global buffer input 16 supply for bank

CONFIG: Dedicated JTAG: Dedicated JTAG VCCINT: Internal core

2 configuration pins 4 port pins 6 supply voltage (+1.2V)

N.C.: Not connected GND: Ground VCCAUX: Auxiliary supply

0 28 4 voltage

92 www.xilinx.com DS529 (v2.1) December 18, 2018

 Pinout Descriptions

FT256 Footprint (XC3S700A, XC3S1400A)

Bank 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
A GND PROG_B L19P_0 L18P_0 L17P_0 L15P_0 L13P_0 L12P_0 L10N_0 TCK GND
L08N_0 L07N_0 L05N_0 L04N_0 L04P_0
GCLK10 GCLK7

I/O I/O I/O I/O I/O I/O I/O I/O

B TDI TMS L19N_0 L18N_0 VCCO_0 L15N_0 GND L12N_0 VCCO_0 L08P_0 GND L05P_0 VCCO_0 L02N_0 L02P_0 TDO
GCLK11 VREF_0

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
C L01N_3 L01P_3 GND L20P_0 L17N_0 L16N_0 L13N_0 L11P_0 L10P_0 L09P_0 L07P_0 L03P_0 L01N_0 GND L24N_1 L24P_1
VREF_0 GCLK8 GCLK6 GCLK4 A25 A24

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
D L03P_3 VCCO_3 L02N_3 L02P_3 L20N_0 VCCAUX L16P_0 L11N_0 L09N_0 L06N_0 L06P_0 L03N_0 L01P_0 L23N_1 L22N_1 L22P_1
PUDC_B GCLK9 GCLK5 VREF_0 A23 A21 A20

I/O I/O I/O I/O I/O I/O I/O I/O I/O

E L03N_3 L05N_3 L05P_3 L04P_3 GND INPUT L14N_0 VCCO_0 L14P_0 GND VCCAUX GND L23P_1 L20P_1 VCCO_1 L18P_1
VREF_0 A22 A18 A14

I/O I/O I/O I/O I/O I/O I/O

F L08P_3 GND L07P_3 L04N_3 VCCAUX GND GND GND GND VCCINT GND VCCAUX L20N_1 L19N_1 L18N_1 L16N_1
A19 A17 A15 A11

I/O I/O I/O I/O I/O I/O

INPUT
G L08N_3 L11P_3 L07N_3 GND GND VCCINT GND VCCINT GND VCCINT GND L19P_1 L17N_1 GND L16P_1
VREF_3
VREF_3 LHCLK0 A16 A13 A10
I/O
I/O I/O INPUT I/O I/O
L15P_1
H L11N_3 VCCO_3 L12P_3 VCCAUX GND VCCINT GND VCCINT GND VCCINT GND VREF_1 L17P_1 VCCAUX IRDY1 L15N_1
Bank 3

Bank 1
LHCLK1 LHCLK2 A12 RHCLK7
RHCLK6
I/O I/O
I/O I/O INPUT I/O I/O INPUT
L12N_3
J L14N_3 L14P_3 INPUT VREF_3 GND VCCINT GND VCCINT GND VCCINT L10P_1 L10N_1 VREF_1 VCCO_1 L12N_1
IRDY2 TRDY1
LHCLK5 LHCLK4 A8 A9
LHCLK3 RHCLK3
I/O I/O I/O I/O I/O I/O
L15P_3 I/O
K L15N_3 GND GND VCCINT GND VCCINT GND VCCINT GND GND L06N_1 L11N_1 L11P_1 L12P_1
TRDY2 L18P_3
LHCLK7 A3 RHCLK1 RHCLK0 RHCLK2
LHCLK6
I/O I/O I/O I/O I/O I/O I/O
L L16P_3 L16N_3 L18N_3 L19N_3 VCCAUX GND VCCINT GND VCCINT GND GND VCCAUX L06P_1 L08P_1 GND L08N_1
VREF_3 A2 A6 A7

I/O I/O I/O INPUT INPUT INPUT INPUT INPUT I/O I/O
M L20P_3 VCCO_3 L19P_3 L24N_3 GND VCCAUX VREF_2 GND VREF_2 VCCAUX VREF_2 GND VREF_1 VREF_1 L07P_1 L07N_1
A4 A5

I/O I/O I/O I/O INPUT I/O I/O I/O I/O I/O I/O I/O I/O
N L20N_3 L22P_3 L24P_3 L01P_2 VREF_2 L04P_2 GND L08N_2 L11P_2 GND L16N_2 L19P_2 L01P_1 L01N_1 VCCO_1 L03N_1
VREF_3 M1 VS1 D4 GCLK0 HDC LDC2 A1

I/O I/O I/O I/O I/O I/O I/O I/O I/O

I/O I/O INPUT I/O I/O
P L22N_3 L23N_3 GND L01N_2 L04N_2 VREF_2 L08P_2 L10P_2 L11N_2 L14N_2 L16P_2 L17N_2 L19N_2 GND L02N_1 L03P_1
MOSI
M0 VS0 D5 GCLK14 GCLK1 CSI_B D3 LDC0 A0

I/O I/O I/O I/O I/O I/O I/O I/O

D
I/O I/O EN
R L23P_3 L02P_2 L03P_2 VCCO_2 L05N_2 GND L09P_2 VCCO_2 L12P_2 GND L15N_2 VCCO_2 L18N_2 L20N_2 L02P_1
SP

M2 RDWR_B GCLK12 GCLK2 DOUT D1 CCLK LDC1

SU

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O
T GND L02N_2 L03N_2 L06P_2 L06N_2 L09N_2 L10N_2 L12N_2 L14P_2 L15P_2 L17P_2 L18P_2 L20P_2 DONE GND
L05P_2 D0/DIN
CSO_B VS2 D7 D6 GCLK13 GCLK15 GCLK3 AWAKE INIT_B D2 MISO

Bank 2
DS529-4_012009

Figure 22: XC3S700A and XC3S1400A FT256 Package Footprint (Top View)

I/O: Unrestricted, DUAL: Configuration, then VREF: User I/O or input SUSPEND: Dedicated
59 general-purpose user I/O 51 possible user I/O 18 voltage reference for bank 2 SUSPEND and
dual-purpose AWAKE
INPUT: Unrestricted, CLK: User I/O, input, or VCCO: Output voltage Power Management pins
2 general-purpose input pin 30 global buffer input 13 supply for bank

CONFIG: Dedicated JTAG: Dedicated JTAG VCCINT: Internal core

2 configuration pins 4 port pins 15 supply voltage (+1.2V)

N.C.: Not connected GND: Ground VCCAUX: Auxiliary supply

0 50 10 voltage

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Pinout Descriptions

FG320: 320-ball Fine-pitch Ball Grid Array

The 320-ball fine-pitch ball grid array package, FG320, Table 76: Spartan-3A FG320 Pinout(Continued)
supports two Spartan-3A FPGAs, the XC3S200A and the FG320
XC3S400A, as shown in Table 76 and Figure 23. Bank Pin Name Ball Type
The FG320 package is an 18 x 18 array of solder balls 0 IO_L09P_0 B11 I/O
minus the four center balls. 0 IO_L10N_0 D10 I/O
Table 76 lists all the package pins. They are sorted by bank 0 IO_L10P_0 C11 I/O
number and then by pin name of the largest device. Pins
0 IO_L11N_0/GCLK5 C9 GCLK
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the 0 IO_L11P_0/GCLK4 B10 GCLK
pin type, as defined earlier. 0 IO_L12N_0/GCLK7 B9 GCLK
The shaded rows indicate pinout differences between the 0 IO_L12P_0/GCLK6 A10 GCLK
XC3S200A and the XC3S400A FPGAs. The XC3S200A 0 IO_L13N_0/GCLK9 B7 GCLK
has three unconnected balls, indicated as N.C. (No
Connection) in Table 76 and with the black diamond 0 IO_L13P_0/GCLK8 A8 GCLK
character () in Table 76 and Figure 23. 0 IO_L14N_0/GCLK11 C8 GCLK

All other balls have nearly identical functionality on all three 0 IO_L14P_0/GCLK10 B8 GCLK
devices. Table 79 summarizes the Spartan-3A FPGA 0 IO_L15N_0 C7 I/O
footprint migration differences for the FG320 package.
0 IO_L15P_0 D8 I/O
An electronic version of this package pinout table and 0 IO_L16N_0 E9 I/O
footprint diagram is available for download from the Xilinx
website at 0 IO_L16P_0 D9 I/O
0 IO_L17N_0 B6 I/O
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip. 0 IO_L17P_0 A6 I/O
0 IO_L18N_0/VREF_0 A4 VREF
Pinout Table 0 IO_L18P_0 A5 I/O
Table 76: Spartan-3A FG320 Pinout 0 IO_L19N_0 E7 I/O
FG320 0 IO_L19P_0 F8 I/O
Bank Pin Name Ball Type
0 IO_L20N_0 D6 I/O
0 IO_L01N_0 C15 I/O
0 IO_L20P_0 C6 I/O
0 IO_L01P_0 C16 I/O
0 IO_L21N_0 A3 I/O
0 IO_L02N_0 A16 I/O
0 IO_L21P_0 B4 I/O
0 IO_L02P_0/VREF_0 B16 VREF
0 IO_L22N_0 D5 I/O
0 IO_L03N_0 A14 I/O
0 IO_L22P_0 C5 I/O
0 IO_L03P_0 A15 I/O
0 IO_L23N_0 A2 I/O
0 IO_L04N_0 C14 I/O
0 IO_L23P_0 B3 I/O
0 IO_L04P_0 B15 I/O
0 IO_L24N_0/PUDC_B E5 DUAL
0 IO_L05N_0 D12 I/O
0 IO_L24P_0/VREF_0 E6 VREF
0 IO_L05P_0 C13 I/O
0 IP_0 D13 INPUT
0 IO_L06N_0/VREF_0 A13 VREF
0 IP_0 D14 INPUT
0 IO_L06P_0 B13 I/O
0 IP_0 E12 INPUT
0 IO_L07N_0 B12 I/O
XC3S400A: IP_0
0 E13 INPUT
0 IO_L07P_0 C12 I/O XC3S200A: N.C. (◆)
0 IO_L08N_0 F11 I/O 0 IP_0 F7 INPUT
0 IO_L08P_0 E11 I/O 0 IP_0 F9 INPUT
0 IO_L09N_0 A11 I/O 0 IP_0 F10 INPUT

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 Pinout Descriptions

Table 76: Spartan-3A FG320 Pinout(Continued) Table 76: Spartan-3A FG320 Pinout(Continued)
FG320 FG320
Bank Pin Name Ball Type Bank Pin Name Ball Type
0 IP_0 F12 INPUT 1 IO_L21N_1 F17 I/O
0 IP_0 G7 INPUT 1 IO_L21P_1 G17 I/O
0 IP_0 G8 INPUT 1 IO_L22N_1/A13 E18 DUAL
0 IP_0 G9 INPUT 1 IO_L22P_1/A12 F18 DUAL
0 IP_0 G11 INPUT 1 IO_L23N_1/A15 H15 DUAL
0 IP_0/VREF_0 E10 VREF 1 IO_L23P_1/A14 J14 DUAL
0 VCCO_0 B5 VCCO 1 IO_L25N_1 D17 I/O
0 VCCO_0 B14 VCCO 1 IO_L25P_1 D18 I/O
0 VCCO_0 D11 VCCO 1 IO_L26N_1/A17 E16 DUAL
0 VCCO_0 E8 VCCO 1 IO_L26P_1/A16 F16 DUAL
1 IO_L01N_1/LDC2 T17 DUAL 1 IO_L27N_1/A19 F15 DUAL
1 IO_L01P_1/HDC R16 DUAL 1 IO_L27P_1/A18 G15 DUAL
1 IO_L02N_1/LDC0 U18 DUAL 1 IO_L29N_1/A21 E15 DUAL
1 IO_L02P_1/LDC1 U17 DUAL 1 IO_L29P_1/A20 D16 DUAL
1 IO_L03N_1/A1 R17 DUAL 1 IO_L30N_1/A23 B18 DUAL
1 IO_L03P_1/A0 T18 DUAL 1 IO_L30P_1/A22 C18 DUAL
1 IO_L05N_1 N16 I/O 1 IO_L31N_1/A25 B17 DUAL
1 IO_L05P_1 P16 I/O 1 IO_L31P_1/A24 C17 DUAL
1 IO_L06N_1 M14 I/O 1 IP_L04N_1/VREF_1 N14 VREF
1 IO_L06P_1 N15 I/O 1 IP_L04P_1 P15 INPUT
1 IO_L07N_1/VREF_1 P18 VREF 1 IP_L08N_1/VREF_1 L14 VREF
1 IO_L07P_1 R18 I/O 1 IP_L08P_1 M13 INPUT
1 IO_L09N_1/A3 M17 DUAL 1 IP_L12N_1 L16 INPUT
1 IO_L09P_1/A2 M16 DUAL 1 IP_L12P_1/VREF_1 M15 VREF
1 IO_L10N_1/A5 N18 DUAL 1 IP_L16N_1 K14 INPUT
1 IO_L10P_1/A4 N17 DUAL 1 IP_L16P_1 K13 INPUT
1 IO_L11N_1/A7 L12 DUAL 1 IP_L20N_1 J13 INPUT
1 IO_L11P_1/A6 L13 DUAL 1 IP_L20P_1/VREF_1 K12 VREF
1 IO_L13N_1/A9 K16 DUAL 1 IP_L24N_1 G14 INPUT
1 IO_L13P_1/A8 L17 DUAL 1 IP_L24P_1 H13 INPUT
1 IO_L14N_1/RHCLK1 K17 RHCLK 1 IP_L28N_1 G13 INPUT
1 IO_L14P_1/RHCLK0 L18 RHCLK 1 IP_L28P_1/VREF_1 H12 VREF
1 IO_L15N_1/TRDY1/RHCLK3 J17 RHCLK 1 IP_L32N_1 F13 INPUT
1 IO_L15P_1/RHCLK2 K18 RHCLK 1 IP_L32P_1/VREF_1 F14 VREF
1 IO_L17N_1/RHCLK5 K15 RHCLK 1 VCCO_1 E17 VCCO
1 IO_L17P_1/RHCLK4 J16 RHCLK 1 VCCO_1 H14 VCCO
1 IO_L18N_1/RHCLK7 H17 RHCLK 1 VCCO_1 L15 VCCO
1 IO_L18P_1/IRDY1/RHCLK6 H18 RHCLK 1 VCCO_1 P17 VCCO
1 IO_L19N_1/A11 G16 DUAL 2 IO_L01N_2/M0 U3 DUAL
1 IO_L19P_1/A10 H16 DUAL 2 IO_L01P_2/M1 T3 DUAL

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Table 76: Spartan-3A FG320 Pinout(Continued) Table 76: Spartan-3A FG320 Pinout(Continued)
FG320 FG320
Bank Pin Name Ball Type Bank Pin Name Ball Type
2 IO_L02N_2/CSO_B V3 DUAL 2 IO_L21P_2 V14 I/O
2 IO_L02P_2/M2 V2 DUAL 2 IO_L22N_2/D1 U15 DUAL
2 IO_L03N_2/VS2 U4 DUAL 2 IO_L22P_2/D2 V15 DUAL
2 IO_L03P_2/RDWR_B T4 DUAL 2 IO_L23N_2 T15 I/O
2 IO_L04N_2 T5 I/O 2 IO_L23P_2 R14 I/O
2 IO_L04P_2 R5 I/O 2 IO_L24N_2/CCLK U16 DUAL
2 IO_L05N_2/VS0 V5 DUAL 2 IO_L24P_2/D0/DIN/MISO V16 DUAL
2 IO_L05P_2/VS1 V4 DUAL 2 IP_2 M8 INPUT
2 IO_L06N_2 U6 I/O 2 IP_2 M9 INPUT
2 IO_L06P_2 T6 I/O 2 IP_2 M12 INPUT
2 IO_L07N_2 P8 I/O XC3S400A: IP_2
2 N7 INPUT
XC3S200A: N.C. (◆)
2 IO_L07P_2 N8 I/O
2 IP_2 N9 INPUT
2 IO_L08N_2/D6 T7 DUAL
2 IP_2 N11 INPUT
2 IO_L08P_2/D7 R7 DUAL
2 IP_2 R6 INPUT
2 IO_L09N_2 R9 I/O
2 IP_2/VREF_2 M11 VREF
2 IO_L09P_2 T8 I/O
2 IP_2/VREF_2 N10 VREF
2 IO_L10N_2/D4 V6 DUAL
2 IP_2/VREF_2 P6 VREF
2 IO_L10P_2/D5 U7 DUAL
2 IP_2/VREF_2 P7 VREF
2 IO_L11N_2/GCLK13 V8 GCLK
2 IP_2/VREF_2 P9 VREF
2 IO_L11P_2/GCLK12 U8 GCLK
2 IP_2/VREF_2 P13 VREF
2 IO_L12N_2/GCLK15 V9 GCLK
XC3S400A: IP_2/VREF_2
2 IO_L12P_2/GCLK14 U9 GCLK 2 P14 VREF
XC3S200A: N.C. (◆)
2 IO_L13N_2/GCLK1 T10 GCLK 2 VCCO_2 P11 VCCO
2 IO_L13P_2/GCLK0 U10 GCLK 2 VCCO_2 R8 VCCO
2 IO_L14N_2/GCLK3 U11 GCLK 2 VCCO_2 U5 VCCO
2 IO_L14P_2/GCLK2 V11 GCLK 2 VCCO_2 U14 VCCO
2 IO_L15N_2 R10 I/O 3 IO_L01N_3 C1 I/O
2 IO_L15P_2 P10 I/O 3 IO_L01P_3 C2 I/O
2 IO_L16N_2/MOSI/CSI_B T11 DUAL 3 IO_L02N_3 B1 I/O
2 IO_L16P_2 R11 I/O 3 IO_L02P_3 B2 I/O
2 IO_L17N_2 V13 I/O 3 IO_L03N_3 D2 I/O
2 IO_L17P_2 U12 I/O 3 IO_L03P_3 D3 I/O
2 IO_L18N_2/DOUT U13 DUAL 3 IO_L05N_3 G5 I/O
PWR 3 IO_L05P_3 F5 I/O
2 IO_L18P_2/AWAKE T12 MGMT
3 IO_L06N_3 E3 I/O
2 IO_L19N_2 P12 I/O
3 IO_L06P_3 F4 I/O
2 IO_L19P_2 N12 I/O
3 IO_L07N_3 E1 I/O
2 IO_L20N_2/D3 R13 DUAL
3 IO_L07P_3 D1 I/O
2 IO_L20P_2/INIT_B T13 DUAL
3 IO_L09N_3 G4 I/O
2 IO_L21N_2 T14 I/O
3 IO_L09P_3 F3 I/O

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Table 76: Spartan-3A FG320 Pinout(Continued) Table 76: Spartan-3A FG320 Pinout(Continued)
FG320 FG320
Bank Pin Name Ball Type Bank Pin Name Ball Type
3 IO_L10N_3/VREF_3 F1 VREF 3 IP_L16N_3 K6 INPUT
3 IO_L10P_3 F2 I/O 3 IP_L16P_3 J5 INPUT
3 IO_L11N_3 J6 I/O 3 IP_L20N_3 L6 INPUT
3 IO_L11P_3 J7 I/O 3 IP_L20P_3 L7 INPUT
3 IO_L13N_3 H1 I/O 3 IP_L24N_3 M4 INPUT
3 IO_L13P_3 H2 I/O 3 IP_L24P_3 M3 INPUT
3 IO_L14N_3/LHCLK1 J3 LHCLK 3 IP_L28N_3 M5 INPUT
3 IO_L14P_3/LHCLK0 H3 LHCLK 3 IP_L28P_3 M6 INPUT
3 IO_L15N_3/IRDY2/LHCLK3 J1 LHCLK 3 IP_L32N_3/VREF_3 P4 VREF
3 IO_L15P_3/LHCLK2 J2 LHCLK 3 IP_L32P_3 P5 INPUT
3 IO_L17N_3/LHCLK5 K5 LHCLK 3 VCCO_3 E2 VCCO
3 IO_L17P_3/LHCLK4 J4 LHCLK 3 VCCO_3 H4 VCCO
3 IO_L18N_3/LHCLK7 K3 LHCLK 3 VCCO_3 L5 VCCO
3 IO_L18P_3/TRDY2/LHCLK6 K2 LHCLK 3 VCCO_3 P2 VCCO
3 IO_L19N_3 L2 I/O GND GND A1 GND
3 IO_L19P_3/VREF_3 L1 VREF GND GND A7 GND
3 IO_L21N_3 M2 I/O GND GND A12 GND
3 IO_L21P_3 N1 I/O GND GND A18 GND
3 IO_L22N_3 N2 I/O GND GND C10 GND
3 IO_L22P_3 P1 I/O GND GND D4 GND
3 IO_L23N_3 L4 I/O GND GND D7 GND
3 IO_L23P_3 L3 I/O GND GND D15 GND
3 IO_L25N_3 R2 I/O GND GND F6 GND
3 IO_L25P_3 R1 I/O GND GND G1 GND
3 IO_L26N_3 N4 I/O GND GND G12 GND
3 IO_L26P_3 N3 I/O GND GND G18 GND
3 IO_L27N_3 T2 I/O GND GND H8 GND
3 IO_L27P_3 T1 I/O GND GND H10 GND
3 IO_L29N_3 N6 I/O GND GND J11 GND
3 IO_L29P_3 N5 I/O GND GND J15 GND
3 IO_L30N_3 R3 I/O GND GND K4 GND
3 IO_L30P_3 P3 I/O GND GND K8 GND
3 IO_L31N_3 U2 I/O GND GND L9 GND
3 IO_L31P_3 U1 I/O GND GND L11 GND
3 IP_L04N_3/VREF_3 H7 VREF GND GND M1 GND
3 IP_L04P_3 G6 INPUT GND GND M7 GND
3 IP_L08N_3/VREF_3 H5 VREF GND GND M18 GND
3 IP_L08P_3 H6 INPUT GND GND N13 GND
3 IP_L12N_3 G2 INPUT GND GND R4 GND
3 IP_L12P_3 G3 INPUT GND GND R12 GND

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Pinout Descriptions

Table 76: Spartan-3A FG320 Pinout(Continued)

FG320
Bank Pin Name Ball Type
GND GND R15 GND
GND GND T9 GND
GND GND V1 GND
GND GND V7 GND
GND GND V12 GND
GND GND V18 GND
PWR
VCCAUX SUSPEND T16 MGMT
VCCAUX DONE V17 CONFIG
VCCAUX PROG_B C4 CONFIG
VCCAUX TCK A17 JTAG
VCCAUX TDI E4 JTAG
VCCAUX TDO E14 JTAG
VCCAUX TMS C3 JTAG
VCCAUX VCCAUX A9 VCCAUX
VCCAUX VCCAUX G10 VCCAUX
VCCAUX VCCAUX J12 VCCAUX
VCCAUX VCCAUX J18 VCCAUX
VCCAUX VCCAUX K1 VCCAUX
VCCAUX VCCAUX K7 VCCAUX
VCCAUX VCCAUX M10 VCCAUX
VCCAUX VCCAUX V10 VCCAUX
VCCINT VCCINT H9 VCCINT
VCCINT VCCINT H11 VCCINT
VCCINT VCCINT J8 VCCINT
VCCINT VCCINT K11 VCCINT
VCCINT VCCINT L8 VCCINT
VCCINT VCCINT L10 VCCINT

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 Pinout Descriptions

User I/Os by Bank

Table 77 and Table 78 indicate how the available user-I/O
pins are distributed between the four I/O banks on the
FG320 package. The AWAKE pin is counted as a
dual-purpose I/O.

Table 77: User I/Os Per Bank for XC3S200A in the FG320 Package

Package All Possible I/O Pins by Type

Edge I/O Bank Maximum I/O
I/O INPUT DUAL VREF CLK
Top 0 60 35 11 1 5 8
Right 1 64 9 10 30 7 8
Bottom 2 60 19 6 21 6 8
Left 3 64 38 13 0 5 8
TOTAL 248 101 40 52 23 32

Table 78: User I/Os Per Bank for XC3S400A in the FG320 Package

Package All Possible I/O Pins by Type

I/O Bank Maximum I/O
Edge I/O INPUT DUAL VREF CLK
Top 0 61 35 12 1 5 8
Right 1 64 9 10 30 7 8
Bottom 2 62 19 7 21 7 8
Left 3 64 38 13 0 5 8
TOTAL 251 101 42 52 24 32

Footprint Migration Differences

Table 79 summarizes any footprint and functionality
differences between the XC3S200A and the XC3S400A
FPGAs that might affect easy migration between devices
available in the FG320 package. There are three such balls.
All other pins not listed in Table 79 unconditionally migrate
between Spartan-3A devices available in the FG320
package.
The arrows indicate the direction for easy migration.

Table 79: FG320 Footprint Migration Differences

Pin Bank XC3S200A Migration XC3S400A
E13 0 N.C.  INPUT
N7 2 N.C.  INPUT
P14 2 N.C.  INPUT/VREF
DIFFERENCES 3
Legend:
 This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.

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Pinout Descriptions

FG320 Footprint

Bank 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
A GND
L23N_0 L21N_0
L18N_0
L18P_0 L17P_0
GND L13P_0 VCCAUX L12P_0
L09N_0
GND L06N_0
L03N_0 L03P_0 L02N_0
TCK GND
VREF_0 GCLK8 GCLK6 VREF_0

I/O I/O I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O I/O I/O
B L02N_3 L02P_3 L23P_0 L21P_0
VCCO_0
L17N_0
L13N_0 L14P_0 L12N_0 L11P_0
L09P_0 L07N_0 L06P_0
VCCO_0
L04P_0
L02P_0 L31N_1 L30N_1
GCLK9 GCLK10 GCLK7 GCLK4 VREF_0 A25 A23

I/O I/O I/O I/O

_B
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
C TMS GND
G
L14N_0 L11N_0 L31P_1 L30P_1
O
L01N_3 L01P_3 PR L22P_0 L20P_0 L15N_0 L10P_0 L07P_0 L05P_0 L04N_0 L01N_0 L01P_0
GCLK11 GCLK5 A24 A22

I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
D L07P_3 L03N_3 L03P_3
GND
L22N_0 L20N_0
GND
L15P_0 L16P_0 L10N_0
VCCO_0
L05N_0
INPUT INPUT GND L29P_1
L25N_1 L25P_1
A20

I/O I/O INPUT I/O I/O I/O

I/O I/O I/O I/O INPUT I/O
E VCCO_3 TDI VCCO_0 INPUT TDO VCCO_1
◆
L24N_0 L24P_0 L29N_1 L26N_1 L22N_1
L07N_3 L06N_3 L19N_0 L16N_0 VREF_0 L08P_0
PUDC_B VREF_0 A21 A17 A13

I/O INPUT I/O I/O I/O

I/O I/O I/O I/O I/O I/O INPUT I/O
F L10N_3
L10P_3 L09P_3 L06P_3 L05P_3
GND INPUT
L19P_0
INPUT INPUT
L08N_0
INPUT
L32N_1
L32P_1 L27N_1 L26P_1
L21N_1
L22P_1
VREF_3 VREF_1 A19 A16 A12

I/O I/O
INPUT INPUT I/O I/O INPUT INPUT INPUT I/O
G GND
L12N_3 L12P_3 L09N_3 L05N_3 L04P_3
INPUT INPUT INPUT VCCAUX INPUT GND
L28N_1 L24N_1
L27P_1 L19N_1
L21P_1
GND
A18 A11

I/O INPUT INPUT INPUT I/O I/O I/O I/O

I/O I/O INPUT INPUT L18P_1
H L13N_3 L13P_3
L14P_3 VCCO_3 L08N_3
L08P_3
L04N_3 GND VCCINT GND VCCINT L28P_1
L24P_1
VCCO_1 L23N_1 L19P_1 L18N_1 IRDY1
LHCLK0 VREF_3 VREF_3 VREF_1 A15 A10 RHCLK7 RHCLK6
I/O I/O I/O I/O I/O I/O I/O
L15N_3 INPUT I/O I/O INPUT L15N_1
J VCCINT GND GND
Bank 3

Bank 1
L15P_3 L14N_3 L17P_3 VCCAUX L23P_1 L17P_1 VCCAUX
IRDY2 L16P_3 L11N_3 L11P_3 L20N_1 TRDY1
LHCLK3 LHCLK2 LHCLK1 LHCLK4 A14 RHCLK4 RHCLK3
I/O I/O I/O INPUT I/O I/O I/O I/O
L18P_3 INPUT INPUT INPUT
K VCCAUX
TRDY2 L18N_3 GND L17N_3
L16N_3
VCCAUX GND VCCINT L20P_1
L16P_1 L16N_1
L17N_1 L13N_1 L14N_1 L15P_1
LHCLK6 LHCLK7 LHCLK5 VREF_1 RHCLK5 A9 RHCLK1 RHCLK2

I/O I/O I/O INPUT I/O I/O

I/O I/O I/O INPUT INPUT INPUT
L L19P_3
L19N_3 L23P_3 L23N_3
VCCO_3
L20N_3 L20P_3
VCCINT GND VCCINT GND L11N_1 L11P_1 L08N_1 VCCO_1
L12N_1
L13P_1 L14P_1
VREF_3 A7 A6 VREF_1 A8 RHCLK0

INPUT I/O I/O

I/O INPUT INPUT INPUT INPUT INPUT INPUT I/O
M GND
L21N_3 L24P_3 L24N_3 L28N_3 L28P_3
GND INPUT INPUT VCCAUX
VREF_2
INPUT
L08P_1 L06N_1
L12P_1 L09P_1 L09N_1 GND
VREF_1 A2 A3

INPUT INPUT I/O I/O

I/O I/O I/O I/O I/O I/O I/O INPUT I/O I/O I/O
N INPUT INPUT GND
◆
L04N_1 L10P_1 L10N_1
L21P_3 L22N_3 L26P_3 L26N_3 L29P_3 L29N_3 L07P_2 VREF_2 L19P_2 L06P_1 L05N_1
VREF_1 A4 A5

INPUT INPUT I/O

I/O I/O INPUT INPUT INPUT I/O INPUT I/O I/O INPUT VREF_2 INPUT I/O
P VCCO_3 L32N_3 VCCO_2 VCCO_1 L07N_1
◆
L22P_3 L30P_3 L32P_3 VREF_2 VREF_2 L07N_2 VREF_2 L15P_2 L19N_2 VREF_2 L04P_1 L05P_1
VREF_3 VREF_1

I/O I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O I/O I/O
R L25P_3 L25N_3 L30N_3
GND
L04P_2
INPUT L08P_2 VCCO_2
L09N_2 L15N_2 L16P_2
GND L20N_2
L23P_2
GND L01P_1 L03N_1
L07P_1
D7 D3 HDC A1

I/O I/O I/O I/O I/O I/O I/O D I/O I/O

EN
I/O I/O I/O I/O I/O L16N_2 I/O I/O
T L01P_2 L03P_2 L08N_2 GND L13N_2 L18P_2 L20P_2 L01N_1 L03P_1
SP

L27P_3 L27N_3 L04N_2 L06P_2 L09P_2 MOSI L21N_2 L23N_2

M1 RDWR_B D6 GCLK1 AWAKE INIT_B LDC2 A0
SU

CSI_B

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O
U L31P_3 L31N_3
L01N_2 L03N_2 VCCO_2
L06N_2
L10P_2 L11P_2 L12P_2 L13P_2 L14N_2
L17P_2
L18N_2 VCCO_2 L22N_2 L24N_2 L02P_1 L02N_1
M0 VS2 D5 GCLK12 GCLK14 GCLK0 GCLK3 DOUT D1 CCLK LDC1 LDC0
I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O L24P_2
V GND L02P_2 L02N_2 L05P_2 L05N_2 L10N_2 GND L11N_2 L12N_2 VCCAUX L14P_2 GND
L17N_2 L21P_2
L22P_2
D0
DONE GND
M2 CSO_B VS1 VS0 D4 GCLK13 GCLK15 GCLK2 D2
DIN/MISO

Bank 2 DS529-4_05_012009

Figure 23: FG320 Package Footprint (Top View)

I/O: Unrestricted, DUAL: Configuration 23 - VREF: User I/O or input SUSPEND: Dedicated
101 general-purpose user I/O 51 pins, then possible voltage reference for 2 SUSPEND and
user-I/O 24 bank dual-purpose AWAKE
Power Management pins
40 - INPUT: Unrestricted, CLK: User I/O, input, or VCCO: Output voltage
general-purpose input 32 global buffer input 16 supply for bank
42 pin

CONFIG: Dedicated JTAG: Dedicated JTAG VCCINT: Internal core

2 configuration pins 4 port pins 6 supply voltage (+1.2V)

N.C.: Not connected. GND: Ground VCCAUX: Auxiliary

3 Only the XC3S200A has 32 8 supply voltage
these pins ().

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 Pinout Descriptions

FG400: 400-ball Fine-pitch Ball Grid Array

The 400-ball fine-pitch ball grid array, FG400, supports two Table 80: Spartan-3A FG400 Pinout(Continued)
different Spartan-3A FPGAs, the XC3S400A and the
FG400
XC3S700A. Both devices share a common footprint for this Bank Pin Name Ball Type
package as shown in Table 80 and Figure 24.
0 IO_L13P_0 B12 I/O
Table 80 lists all the FG400 package pins. They are sorted 0 IO_L14N_0 C11 I/O
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The 0 IO_L14P_0 B11 I/O
table also shows the pin number for each pin and the pin 0 IO_L15N_0/GCLK5 E11 GCLK
type, as defined earlier. 0 IO_L15P_0/GCLK4 D11 GCLK
An electronic version of this package pinout table and 0 IO_L16N_0/GCLK7 C10 GCLK
footprint diagram is available for download from the Xilinx
0 IO_L16P_0/GCLK6 A10 GCLK
website at
0 IO_L17N_0/GCLK9 E10 GCLK
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip. 0 IO_L17P_0/GCLK8 D10 GCLK
0 IO_L18N_0/GCLK11 A8 GCLK
Pinout Table 0 IO_L18P_0/GCLK10 A9 GCLK
Table 80: Spartan-3A FG400 Pinout 0 IO_L19N_0 C9 I/O

FG400 0 IO_L19P_0 B9 I/O

Bank Pin Name Ball Type 0 IO_L20N_0 C8 I/O
0 IO_L01N_0 A18 I/O 0 IO_L20P_0 B8 I/O
0 IO_L01P_0 B18 I/O 0 IO_L21N_0 D8 I/O
0 IO_L02N_0 C17 I/O 0 IO_L21P_0 C7 I/O
0 IO_L02P_0/VREF_0 D17 VREF 0 IO_L22N_0/VREF_0 F9 VREF
0 IO_L03N_0 E15 I/O 0 IO_L22P_0 E9 I/O
0 IO_L03P_0 D16 I/O 0 IO_L23N_0 F8 I/O
0 IO_L04N_0 A17 I/O 0 IO_L23P_0 E8 I/O
0 IO_L04P_0/VREF_0 B17 VREF 0 IO_L24N_0 A7 I/O
0 IO_L05N_0 A16 I/O 0 IO_L24P_0 B7 I/O
0 IO_L05P_0 C16 I/O 0 IO_L25N_0 C6 I/O
0 IO_L06N_0 C15 I/O 0 IO_L25P_0 A6 I/O
0 IO_L06P_0 D15 I/O 0 IO_L26N_0 B5 I/O
0 IO_L07N_0 A14 I/O 0 IO_L26P_0 A5 I/O
0 IO_L07P_0 C14 I/O 0 IO_L27N_0 F7 I/O
0 IO_L08N_0 A15 I/O 0 IO_L27P_0 E7 I/O
0 IO_L08P_0 B15 I/O 0 IO_L28N_0 D6 I/O
0 IO_L09N_0 F13 I/O 0 IO_L28P_0 C5 I/O
0 IO_L09P_0 E13 I/O 0 IO_L29N_0 C4 I/O
0 IO_L10N_0/VREF_0 C13 VREF 0 IO_L29P_0 A4 I/O
0 IO_L10P_0 D14 I/O 0 IO_L30N_0 B3 I/O
0 IO_L11N_0 C12 I/O 0 IO_L30P_0 A3 I/O
0 IO_L11P_0 B13 I/O 0 IO_L31N_0 F6 I/O
0 IO_L12N_0 F12 I/O 0 IO_L31P_0 E6 I/O
0 IO_L12P_0 D12 I/O 0 IO_L32N_0/PUDC_B B2 DUAL
0 IO_L13N_0 A12 I/O

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Pinout Descriptions

Table 80: Spartan-3A FG400 Pinout(Continued) Table 80: Spartan-3A FG400 Pinout(Continued)
FG400 FG400
Bank Pin Name Ball Type Bank Pin Name Ball Type
0 IO_L32P_0/VREF_0 A2 VREF 1 IO_L13N_1/A5 N19 DUAL
0 IP_0 E14 INPUT 1 IO_L13P_1/A4 N18 DUAL
0 IP_0 F11 INPUT 1 IO_L14N_1/A7 M18 DUAL
0 IP_0 F14 INPUT 1 IO_L14P_1/A6 M17 DUAL
0 IP_0 G8 INPUT 1 IO_L16N_1/A9 L16 DUAL
0 IP_0 G9 INPUT 1 IO_L16P_1/A8 L15 DUAL
0 IP_0 G10 INPUT 1 IO_L17N_1/RHCLK1 M20 RHCLK
0 IP_0 G12 INPUT 1 IO_L17P_1/RHCLK0 M19 RHCLK
0 IP_0 G13 INPUT 1 IO_L18N_1/TRDY1/RHCLK3 L18 RHCLK
0 IP_0 H9 INPUT 1 IO_L18P_1/RHCLK2 L19 RHCLK
0 IP_0 H10 INPUT 1 IO_L20N_1/RHCLK5 L17 RHCLK
0 IP_0 H11 INPUT 1 IO_L20P_1/RHCLK4 K18 RHCLK
0 IP_0 H12 INPUT 1 IO_L21N_1/RHCLK7 J20 RHCLK
0 IP_0/VREF_0 G11 VREF 1 IO_L21P_1/IRDY1/RHCLK6 K20 RHCLK
0 VCCO_0 B4 VCCO 1 IO_L22N_1/A11 J18 DUAL
0 VCCO_0 B10 VCCO 1 IO_L22P_1/A10 J19 DUAL
0 VCCO_0 B16 VCCO 1 IO_L24N_1 K16 I/O
0 VCCO_0 D7 VCCO 1 IO_L24P_1 J17 I/O
0 VCCO_0 D13 VCCO 1 IO_L25N_1/A13 H18 DUAL
0 VCCO_0 F10 VCCO 1 IO_L25P_1/A12 H19 DUAL
1 IO_L01N_1/LDC2 V20 DUAL 1 IO_L26N_1/A15 G20 DUAL
1 IO_L01P_1/HDC W20 DUAL 1 IO_L26P_1/A14 H20 DUAL
1 IO_L02N_1/LDC0 U18 DUAL 1 IO_L28N_1 H17 I/O
1 IO_L02P_1/LDC1 V19 DUAL 1 IO_L28P_1 G18 I/O
1 IO_L03N_1/A1 R16 DUAL 1 IO_L29N_1/A17 F19 DUAL
1 IO_L03P_1/A0 T17 DUAL 1 IO_L29P_1/A16 F20 DUAL
1 IO_L05N_1 T20 I/O 1 IO_L30N_1/A19 F18 DUAL
1 IO_L05P_1 T18 I/O 1 IO_L30P_1/A18 G17 DUAL
1 IO_L06N_1 U20 I/O 1 IO_L32N_1 E19 I/O
1 IO_L06P_1 U19 I/O 1 IO_L32P_1 E20 I/O
1 IO_L07N_1 P17 I/O 1 IO_L33N_1 F17 I/O
1 IO_L07P_1 P16 I/O 1 IO_L33P_1 E18 I/O
1 IO_L08N_1 R17 I/O 1 IO_L34N_1 D18 I/O
1 IO_L08P_1 R18 I/O 1 IO_L34P_1 D20 I/O
1 IO_L09N_1 R20 I/O 1 IO_L36N_1/A21 F16 DUAL
1 IO_L09P_1 R19 I/O 1 IO_L36P_1/A20 G16 DUAL
1 IO_L10N_1/VREF_1 P20 VREF 1 IO_L37N_1/A23 C19 DUAL
1 IO_L10P_1 P18 I/O 1 IO_L37P_1/A22 C20 DUAL
1 IO_L12N_1/A3 N17 DUAL 1 IO_L38N_1/A25 B19 DUAL
1 IO_L12P_1/A2 N15 DUAL 1 IO_L38P_1/A24 B20 DUAL

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 Pinout Descriptions

Table 80: Spartan-3A FG400 Pinout(Continued) Table 80: Spartan-3A FG400 Pinout(Continued)
FG400 FG400
Bank Pin Name Ball Type Bank Pin Name Ball Type
1 IP_1/VREF_1 N14 VREF 2 IO_L09N_2/VS0 W6 DUAL
1 IP_L04N_1/VREF_1 P15 VREF 2 IO_L09P_2/VS1 V6 DUAL
1 IP_L04P_1 P14 INPUT 2 IO_L10N_2 Y7 I/O
1 IP_L11N_1/VREF_1 M15 VREF 2 IO_L10P_2 Y6 I/O
1 IP_L11P_1 M16 INPUT 2 IO_L11N_2 U9 I/O
1 IP_L15N_1 M13 INPUT 2 IO_L11P_2 T9 I/O
1 IP_L15P_1/VREF_1 M14 VREF 2 IO_L12N_2/D6 W8 DUAL
1 IP_L19N_1 L13 INPUT 2 IO_L12P_2/D7 V7 DUAL
1 IP_L19P_1 L14 INPUT 2 IO_L13N_2 V9 I/O
1 IP_L23N_1 K14 INPUT 2 IO_L13P_2 V8 I/O
1 IP_L23P_1/VREF_1 K15 VREF 2 IO_L14N_2/D4 T10 DUAL
1 IP_L27N_1 J15 INPUT 2 IO_L14P_2/D5 U10 DUAL
1 IP_L27P_1 J16 INPUT 2 IO_L15N_2/GCLK13 Y9 GCLK
1 IP_L31N_1 J13 INPUT 2 IO_L15P_2/GCLK12 W9 GCLK
1 IP_L31P_1/VREF_1 J14 VREF 2 IO_L16N_2/GCLK15 W10 GCLK
1 IP_L35N_1 H14 INPUT 2 IO_L16P_2/GCLK14 V10 GCLK
1 IP_L35P_1 H15 INPUT 2 IO_L17N_2/GCLK1 V11 GCLK
1 IP_L39N_1 G14 INPUT 2 IO_L17P_2/GCLK0 Y11 GCLK
1 IP_L39P_1/VREF_1 G15 VREF 2 IO_L18N_2/GCLK3 V12 GCLK
1 VCCO_1 D19 VCCO 2 IO_L18P_2/GCLK2 U11 GCLK
1 VCCO_1 H16 VCCO 2 IO_L19N_2 R12 I/O
1 VCCO_1 K19 VCCO 2 IO_L19P_2 T12 I/O
1 VCCO_1 N16 VCCO 2 IO_L20N_2/MOSI/CSI_B W12 DUAL
1 VCCO_1 T19 VCCO 2 IO_L20P_2 Y12 I/O
2 IO_L01N_2/M0 V4 DUAL 2 IO_L21N_2 W13 I/O
2 IO_L01P_2/M1 U4 DUAL 2 IO_L21P_2 Y13 I/O
2 IO_L02N_2/CSO_B Y2 DUAL 2 IO_L22N_2/DOUT V13 DUAL
2 IO_L02P_2/M2 W3 DUAL IO_L22P_2/AWAKE U13 PWR
2 MGMT
2 IO_L03N_2 W4 I/O
2 IO_L23N_2 R13 I/O
2 IO_L03P_2 Y3 I/O
2 IO_L23P_2 T13 I/O
2 IO_L04N_2 R7 I/O
2 IO_L24N_2/D3 W14 DUAL
2 IO_L04P_2 T6 I/O
2 IO_L24P_2/INIT_B Y14 DUAL
2 IO_L05N_2 U5 I/O
2 IO_L25N_2 T14 I/O
2 IO_L05P_2 V5 I/O
2 IO_L25P_2 V14 I/O
2 IO_L06N_2 U6 I/O
2 IO_L26N_2/D1 V15 DUAL
2 IO_L06P_2 T7 I/O
2 IO_L26P_2/D2 Y15 DUAL
2 IO_L07N_2/VS2 U7 DUAL
2 IO_L27N_2 T15 I/O
2 IO_L07P_2/RDWR_B T8 DUAL
2 IO_L27P_2 U15 I/O
2 IO_L08N_2 Y5 I/O
2 IO_L28N_2 W16 I/O
2 IO_L08P_2 Y4 I/O

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Pinout Descriptions

Table 80: Spartan-3A FG400 Pinout(Continued) Table 80: Spartan-3A FG400 Pinout(Continued)
FG400 FG400
Bank Pin Name Ball Type Bank Pin Name Ball Type
2 IO_L28P_2 Y16 I/O 3 IO_L08P_3 H6 I/O
2 IO_L29N_2 U16 I/O 3 IO_L09N_3 G4 I/O
2 IO_L29P_2 V16 I/O 3 IO_L09P_3 F3 I/O
2 IO_L30N_2 Y18 I/O 3 IO_L10N_3 F2 I/O
2 IO_L30P_2 Y17 I/O 3 IO_L10P_3 E3 I/O
2 IO_L31N_2 U17 I/O 3 IO_L12N_3 H2 I/O
2 IO_L31P_2 V17 I/O 3 IO_L12P_3 G3 I/O
2 IO_L32N_2/CCLK Y19 DUAL 3 IO_L13N_3/VREF_3 G1 VREF
2 IO_L32P_2/D0/DIN/MISO W18 DUAL 3 IO_L13P_3 F1 I/O
2 IP_2 P9 INPUT 3 IO_L14N_3 H3 I/O
2 IP_2 P12 INPUT 3 IO_L14P_3 J4 I/O
2 IP_2 P13 INPUT 3 IO_L16N_3 J2 I/O
2 IP_2 R8 INPUT 3 IO_L16P_3 J3 I/O
2 IP_2 R10 INPUT 3 IO_L17N_3/LHCLK1 K2 LHCLK
2 IP_2 T11 INPUT 3 IO_L17P_3/LHCLK0 J1 LHCLK
2 IP_2/VREF_2 N9 VREF 3 IO_L18N_3/IRDY2/LHCLK3 L3 LHCLK
2 IP_2/VREF_2 N12 VREF 3 IO_L18P_3/LHCLK2 K3 LHCLK
2 IP_2/VREF_2 P8 VREF 3 IO_L20N_3/LHCLK5 L5 LHCLK
2 IP_2/VREF_2 P10 VREF 3 IO_L20P_3/LHCLK4 K4 LHCLK
2 IP_2/VREF_2 P11 VREF 3 IO_L21N_3/LHCLK7 M1 LHCLK
2 IP_2/VREF_2 R14 VREF 3 IO_L21P_3/TRDY2/LHCLK6 L1 LHCLK
2 VCCO_2 R11 VCCO 3 IO_L22N_3 M3 I/O
2 VCCO_2 U8 VCCO 3 IO_L22P_3/VREF_3 M2 VREF
2 VCCO_2 U14 VCCO 3 IO_L24N_3 M5 I/O
2 VCCO_2 W5 VCCO 3 IO_L24P_3 M4 I/O
2 VCCO_2 W11 VCCO 3 IO_L25N_3 N2 I/O
2 VCCO_2 W17 VCCO 3 IO_L25P_3 N1 I/O
3 IO_L01N_3 D3 I/O 3 IO_L26N_3 N4 I/O
3 IO_L01P_3 D4 I/O 3 IO_L26P_3 N3 I/O
3 IO_L02N_3 C2 I/O 3 IO_L28N_3 R1 I/O
3 IO_L02P_3 B1 I/O 3 IO_L28P_3 P1 I/O
3 IO_L03N_3 D2 I/O 3 IO_L29N_3 P4 I/O
3 IO_L03P_3 C1 I/O 3 IO_L29P_3 P3 I/O
3 IO_L05N_3 E1 I/O 3 IO_L30N_3 R3 I/O
3 IO_L05P_3 D1 I/O 3 IO_L30P_3 R2 I/O
3 IO_L06N_3 G5 I/O 3 IO_L32N_3 T2 I/O
3 IO_L06P_3 F4 I/O 3 IO_L32P_3/VREF_3 T1 VREF
3 IO_L07N_3 J5 I/O 3 IO_L33N_3 R4 I/O
3 IO_L07P_3 J6 I/O 3 IO_L33P_3 T3 I/O
3 IO_L08N_3 H4 I/O 3 IO_L34N_3 U3 I/O

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 Pinout Descriptions

Table 80: Spartan-3A FG400 Pinout(Continued) Table 80: Spartan-3A FG400 Pinout(Continued)
FG400 FG400
Bank Pin Name Ball Type Bank Pin Name Ball Type
3 IO_L34P_3 U1 I/O GND GND E12 GND
3 IO_L36N_3 T4 I/O GND GND F15 GND
3 IO_L36P_3 R5 I/O GND GND G2 GND
3 IO_L37N_3 V2 I/O GND GND G19 GND
3 IO_L37P_3 V1 I/O GND GND H8 GND
3 IO_L38N_3 W2 I/O GND GND H13 GND
3 IO_L38P_3 W1 I/O GND GND J9 GND
3 IP_3 H7 INPUT GND GND J11 GND
3 IP_L04N_3/VREF_3 G6 VREF GND GND K1 GND
3 IP_L04P_3 G7 INPUT GND GND K10 GND
3 IP_L11N_3/VREF_3 J7 VREF GND GND K12 GND
3 IP_L11P_3 J8 INPUT GND GND K17 GND
3 IP_L15N_3 K7 INPUT GND GND L4 GND
3 IP_L15P_3 K8 INPUT GND GND L9 GND
3 IP_L19N_3 K5 INPUT GND GND L11 GND
3 IP_L19P_3 K6 INPUT GND GND L20 GND
3 IP_L23N_3 L6 INPUT GND GND M10 GND
3 IP_L23P_3 L7 INPUT GND GND M12 GND
3 IP_L27N_3 M7 INPUT GND GND N8 GND
3 IP_L27P_3 M8 INPUT GND GND N11 GND
3 IP_L31N_3 N7 INPUT GND GND N13 GND
3 IP_L31P_3 M6 INPUT GND GND P2 GND
3 IP_L35N_3 N6 INPUT GND GND P19 GND
3 IP_L35P_3 P5 INPUT GND GND R6 GND
3 IP_L39N_3/VREF_3 P7 VREF GND GND R9 GND
3 IP_L39P_3 P6 INPUT GND GND T16 GND
3 VCCO_3 E2 VCCO GND GND U12 GND
3 VCCO_3 H5 VCCO GND GND V3 GND
3 VCCO_3 L2 VCCO GND GND V18 GND
3 VCCO_3 N5 VCCO GND GND W7 GND
3 VCCO_3 U2 VCCO GND GND W15 GND
GND GND A1 GND GND GND Y1 GND
GND GND A11 GND GND GND Y10 GND
GND GND A20 GND GND GND Y20 GND
GND GND B6 GND PWR
VCCAUX SUSPEND R15 MGMT
GND GND B14 GND
VCCAUX DONE W19 CONFIG
GND GND C3 GND
VCCAUX PROG_B D5 CONFIG
GND GND C18 GND
VCCAUX TCK A19 JTAG
GND GND D9 GND
VCCAUX TDI F5 JTAG
GND GND E5 GND

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Pinout Descriptions

Table 80: Spartan-3A FG400 Pinout(Continued)

FG400
Bank Pin Name Ball Type
VCCAUX TDO E17 JTAG
VCCAUX TMS E4 JTAG
VCCAUX VCCAUX A13 VCCAUX
VCCAUX VCCAUX E16 VCCAUX
VCCAUX VCCAUX H1 VCCAUX
VCCAUX VCCAUX K13 VCCAUX
VCCAUX VCCAUX L8 VCCAUX
VCCAUX VCCAUX N20 VCCAUX
VCCAUX VCCAUX T5 VCCAUX
VCCAUX VCCAUX Y8 VCCAUX
VCCINT VCCINT J10 VCCINT
VCCINT VCCINT J12 VCCINT
VCCINT VCCINT K9 VCCINT
VCCINT VCCINT K11 VCCINT
VCCINT VCCINT L10 VCCINT
VCCINT VCCINT L12 VCCINT
VCCINT VCCINT M9 VCCINT
VCCINT VCCINT M11 VCCINT
VCCINT VCCINT N10 VCCINT

User I/Os by Bank

Table 81 indicates how the 311 available user-I/O pins are
distributed between the four I/O banks on the FG400
package. The AWAKE pin is counted as a dual-purpose I/O.

Table 81: User I/Os Per Bank for the XC3S400A and XC3S700A in the FG400 Package

Package All Possible I/O Pins by Type

Edge I/O Bank Maximum I/O
I/O INPUT DUAL VREF CLK
Top 0 77 50 12 1 6 8
Right 1 79 21 12 30 8 8
Bottom 2 76 35 6 21 6 8
Left 3 79 49 16 0 6 8
TOTAL 311 155 46 52 26 32

Footprint Migration Differences

The XC3S400A and XC3S700A FPGAs have identical
footprints in the FG400 package. Designs can migrate
between the XC3S400A and XC3S700A FPGAs without
further consideration.

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 Pinout Descriptions

FG400 Footprint Bank 0

1 2 3 4 5 6 7 8 9 10
Left Half of FG400 I/O I/O I/O I/O
I/O I/O I/O I/O I/O
Package (Top View) A GND L32P_0
L30P_0 L29P_0 L26P_0 L25P_0 L24N_0
L18N_0 L18P_0 L16P_0
VREF_0 GCLK11 GCLK10 GCLK6

I/O
I/O I/O I/O I/O I/O I/O
B L02P_3
L32N_0
L30N_0
VCCO_0
L26N_0
GND
L24P_0 L20P_0 L19P_0
VCCO_0
I/O: Unrestricted, PUDC_B
155 general-purpose user I/O
I/O
I/O I/O I/O I/O I/O I/O I/O I/O
C L03P_3 L02N_3
GND
L29N_0 L28P_0 L25N_0 L21P_0 L20N_0 L19N_0
L16N_0
GCLK7
INPUT: Unrestricted,
46 general-purpose input pin I/O

_B
I/O I/O I/O I/O I/O I/O

G
D VCCO_0 GND L17P_0

O
L05P_3 L03N_3 L01N_3 L01P_3 L28N_0 L21N_0

PR
GCLK8

51 DUAL: Configuration pins,

then possible user I/O E
I/O VCCO_3
I/O
TMS GND
I/O I/O I/O I/O
I/O
L17N_0
L05N_3 L10P_3 L31P_0 L27P_0 L23P_0 L22P_0
GCLK9

VREF: User I/O or input I/O

26 voltage reference for bank I/O I/O I/O I/O I/O I/O I/O
F L13P_3 L10N_3 L09P_3 L06P_3
TDI
L31N_0 L27N_0 L23N_0
L22N_0 VCCO_0
VREF_0

I/O INPUT
CLK: User I/O, input, or I/O I/O I/O INPUT
G L13N_3 GND L04N_3 INPUT INPUT INPUT
32 clock buffer input VREF_3
L12P_3 L09N_3 L06N_3
VREF_3
L04P_3

I/O I/O I/O I/O

H VCCAUX VCCO_3 INPUT GND INPUT INPUT
2 CONFIG: Dedicated
configuration pins
L12N_3 L14N_3 L08N_3 L08P_3

I/O INPUT
I/O I/O I/O I/O I/O INPUT
JTAG: Dedicated JTAG J L17P_3 L11N_3 GND VCCINT
L16N_3 L16P_3 L14P_3 L07N_3 L07P_3 L11P_3
4 port pins LHCLK0 VREF_3

I/O I/O I/O

INPUT INPUT INPUT INPUT
K GND VCCINT GND
Bank 3

L17N_3 L18P_3 L20P_3

SUSPEND: Dedicated L19N_3 L19P_3 L15N_3 L15P_3
LHCLK1 LHCLK2 LHCLK4
SUSPEND and
2 dual-purpose AWAKE I/O I/O I/O
L21P_3 L18N_3 INPUT INPUT VCCAUX
Power Management pins L TRDY2
VCCO_3
IRDY2
GND L20N_3 GND VCCINT
L23N_3 L23P_3
LHCLK6 LHCLK3 LHCLK5

GND: Ground I/O I/O

43 I/O I/O I/O INPUT INPUT INPUT
M L21N_3 L22P_3
L22N_3 L24P_3 L24N_3 L31P_3 L27N_3 L27P_3
VCCINT GND
LHCLK7 VREF_3

VCCO: Output voltage I/O I/O I/O I/O INPUT INPUT INPUT
N VCCO_3 GND VCCINT
22 supply for bank L25P_3 L25N_3 L26P_3 L26N_3 L35N_3 L31N_3 VREF_2

INPUT
I/O I/O I/O INPUT INPUT INPUT INPUT
VCCINT: Internal core P L28P_3
GND
L29P_3 L29N_3 L35P_3 L39P_3
L39N_3
VREF_2
INPUT
VREF_2
VREF_3
9 supply voltage (+1.2V)
I/O I/O I/O I/O I/O I/O
R L28N_3 L30P_3 L30N_3 L33N_3 L36P_3
GND
L04N_2
INPUT GND INPUT
VCCAUX: Auxiliary supply
8 voltage
I/O I/O I/O
I/O I/O I/O I/O I/O I/O
T L32P_3
L32N_3 L33P_3 L36N_3
VCCAUX
L04P_2 L06P_2
L07P_2
L11P_2
L14N_2
VREF_3 RDWR_B D4

I/O I/O I/O

I/O I/O I/O I/O I/O
U L34P_3
VCCO_3
L34N_3
L01P_2
L05N_2 L06N_2
L07N_2 VCCO_2
L11N_2
L14P_2
M1 VS2 D5

I/O I/O I/O I/O

I/O I/O I/O I/O I/O
V L37P_3 L37N_3
GND L01N_2
L05P_2
L09P_2 L12P_2
L13P_2 L13N_2
L16P_2
M0 VS1 D7 GCLK14

I/O I/O I/O I/O I/O

I/O I/O I/O
W L38P_3 L38N_3
L02P_2
L03N_2
VCCO_2 L09N_2 GND L12N_2 L15P_2 L16N_2
M2 VS0 D6 GCLK12 GCLK15

I/O I/O
I/O I/O I/O I/O I/O
Y GND L02N_2
L03P_2 L08P_2 L08N_2 L10P_2 L10N_2
VCCAUX L15N_2 GND
CSO_B GCLK13

Bank 2 DS529-4_03_011608

Figure 24: FG400 Package Footprint (Top View)

DS529 (v2.1) December 18, 2018 www.xilinx.com 107

Pinout Descriptions

Bank 0
11 12 13 14 15 16 17 18 19 20
Right Half of FG400
GND
I/O VCCAUX
I/O I/O I/O I/O I/O
TCK GND A Package (Top View)
L13N_0 L07N_0 L08N_0 L05N_0 L04N_0 L01N_0

I/O I/O I/O

I/O I/O I/O I/O I/O
L14P_0 L13P_0 L11P_0
GND
L08P_0
VCCO_0 L04P_0
L01P_0
L38N_1 L38P_1 B
VREF_0 A25 A24

I/O I/O I/O

I/O I/O I/O I/O I/O I/O
L14N_0 L11N_0
L10N_0
L07P_0 L06N_0 L05P_0 L02N_0
GND L37N_1 L37P_1 C
VREF_0 A23 A22

I/O I/O
I/O I/O I/O I/O I/O I/O
L15P_0
L12P_0
VCCO_0
L10P_0 L06P_0 L03P_0
L02P_0
L34N_1
VCCO_1
L34P_1
D
GCLK4 VREF_0

I/O
I/O I/O I/O I/O I/O
L15N_0 GND
L09P_0
INPUT
L03N_0
VCCAUX TDO
L33P_1 L32N_1 L32P_1
E
GCLK5

I/O I/O I/O I/O

I/O I/O I/O
INPUT
L12N_0 L09N_0
INPUT GND L36N_1
L33N_1
L30N_1 L29N_1 L29P_1 F
A21 A19 A17 A16

INPUT I/O I/O I/O

INPUT INPUT I/O
VREF_0
INPUT INPUT
L39N_1
L39P_1 L36P_1 L30P_1
L28P_1
GND L26N_1 G
VREF_1 A20 A18 A15

I/O I/O I/O

INPUT INPUT I/O
INPUT INPUT GND
L35N_1 L35P_1
VCCO_1
L28N_1
L25N_1 L25P_1 L26P_1 H
A13 A12 A14

INPUT I/O I/O I/O

INPUT INPUT INPUT I/O
GND VCCINT
L31N_1
L31P_1
L27N_1 L27P_1 L24P_1
L22N_1 L22P_1 L21N_1 J
VREF_1 A11 A10 RHCLK7

INPUT I/O I/O

INPUT I/O L21P_1
VCCINT GND GND K
Bank 1

VCCAUX L23P_1 L20P_1 VCCO_1

L23N_1 L24N_1 IRDY1
VREF_1 RHCLK4 RHCLK6

I/O I/O I/O I/O I/O

INPUT INPUT L18N_1
GND VCCINT
L19N_1 L19P_1
L16P_1 L16N_1 L20N_1
TRDY1
L18P_1 GND L
A8 A9 RHCLK5 RHCLK3 RHCLK2

INPUT INPUT I/O I/O I/O I/O

INPUT INPUT
VCCINT GND
L15N_1
L15P_1 L11N_1
L11P_1
L14P_1 L14N_1 L17P_1 L17N_1 M
VREF_1 VREF_1 A6 A7 RHCLK0 RHCLK1

I/O I/O I/O I/O

INPUT INPUT
GND
VREF_2
GND
VREF_1
L12P_1 VCCO_1 L12N_1 L13P_1 L13N_1 VCCAUX N
A2 A3 A4 A5

INPUT I/O
INPUT INPUT I/O I/O I/O
VREF_2
INPUT INPUT
L04P_1
L04N_1
L07P_1 L07N_1 L10P_1
GND L10N_1 P
VREF_1 VREF_1
D

I/O
EN

I/O I/O INPUT I/O I/O I/O I/O

VCCO_2 L03N_1 R
SP

L19N_2 L23N_2 VREF_2 L08N_1 L08P_1 L09P_1 L09N_1

SU

A1

I/O
I/O I/O I/O I/O I/O I/O
INPUT
L19P_2 L23P_2 L25N_2 L27N_2
GND L03P_1
L05P_1
VCCO_1
L05N_1
T
A0

I/O I/O I/O

I/O I/O I/O I/O I/O
L18P_2 GND L22P_2 VCCO_2
L27P_2 L29N_2 L31N_2
L02N_1
L06P_1 L06N_1
U
GCLK2 AWAKE LDC0

I/O I/O I/O I/O I/O I/O

I/O I/O I/O
L17N_2 L18N_2 L22N_2
L25P_2
L26N_2
L29P_2 L31P_2
GND L02P_1 L01N_1 V
GCLK1 GCLK3 DOUT D1 LDC1 LDC2

I/O I/O I/O I/O

L20N_2 I/O I/O L32P_2
VCCO_2
MOSI L21N_2
L24N_2 GND
L28N_2
VCCO_2
D0
DONE L01P_1 W
CSI_B D3 DIN/MISO HDC

I/O I/O I/O I/O

I/O I/O I/O I/O I/O
L17P_2
L20P_2 L21P_2
L24P_2 L26P_2
L28P_2 L30P_2 L30N_2
L32N_2 GND Y
GCLK0 INIT_B D2 CCLK

Bank 2 DS529-4_04_012009

108 www.xilinx.com DS529 (v2.1) December 18, 2018

 Pinout Descriptions

FG484: 484-ball Fine-pitch Ball Grid Array

The 484-ball fine-pitch ball grid array, FG484, supports both Table 82: Spartan-3A FG484 Pinout(Continued)
the XC3S700A and the XC3S1400A FPGAs. There are FG484
three pinout differences, as described in Table 85. Bank Pin Name Ball Type
Table 82 lists all the FG484 package pins. They are sorted 0 IO_L11P_0 D15 I/O
by bank number and then by pin name. Pairs of pins that 0 IO_L12N_0/VREF_0 A15 VREF
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin 0 IO_L12P_0 A16 I/O
type, as defined earlier. 0 IO_L13N_0 A14 I/O

The shaded rows indicate pinout differences between the 0 IO_L13P_0 B15 I/O
XC3S700A and the XC3S1400A FPGAs. The XC3S700A 0 IO_L14N_0 E13 I/O
has three unconnected balls, indicated as N.C. (No
0 IO_L14P_0 F13 I/O
Connection) in Table 82 and with the black diamond
character () in Table 82 and Figure 25. 0 IO_L15N_0 C13 I/O

An electronic version of this package pinout table and 0 IO_L15P_0 D13 I/O
footprint diagram is available for download from the Xilinx 0 IO_L16N_0 A13 I/O
website at 0 IO_L16P_0 B13 I/O
www.xilinx.com/support/documentation/data_sheets/ 0 IO_L17N_0/GCLK5 E12 GCLK
s3a_pin.zip.
0 IO_L17P_0/GCLK4 C12 GCLK

Pinout Table 0 IO_L18N_0/GCLK7 A11 GCLK

0 IO_L18P_0/GCLK6 A12 GCLK
Table 82: Spartan-3A FG484 Pinout
0 IO_L19N_0/GCLK9 C11 GCLK
FG484
Bank Pin Name Ball Type 0 IO_L19P_0/GCLK8 B11 GCLK
0 IO_L01N_0 D18 I/O 0 IO_L20N_0/GCLK11 E11 GCLK
0 IO_L01P_0 E17 I/O 0 IO_L20P_0/GCLK10 D11 GCLK
0 IO_L02N_0 C19 I/O 0 IO_L21N_0 C10 I/O
0 IO_L02P_0/VREF_0 D19 VREF 0 IO_L21P_0 A10 I/O
0 IO_L03N_0 A20 I/O 0 IO_L22N_0 A8 I/O
0 IO_L03P_0 B20 I/O 0 IO_L22P_0 A9 I/O
0 IO_L04N_0 F15 I/O 0 IO_L23N_0 E10 I/O
0 IO_L04P_0 E15 I/O 0 IO_L23P_0 D10 I/O
0 IO_L05N_0 A18 I/O 0 IO_L24N_0/VREF_0 C9 VREF
0 IO_L05P_0 C18 I/O 0 IO_L24P_0 B9 I/O
0 IO_L06N_0 A19 I/O 0 IO_L25N_0 C8 I/O
0 IO_L06P_0/VREF_0 B19 VREF 0 IO_L25P_0 B8 I/O
0 IO_L07N_0 C17 I/O 0 IO_L26N_0 A6 I/O
0 IO_L07P_0 D17 I/O 0 IO_L26P_0 A7 I/O
0 IO_L08N_0 C16 I/O 0 IO_L27N_0 C7 I/O
0 IO_L08P_0 D16 I/O 0 IO_L27P_0 D7 I/O
0 IO_L09N_0 E14 I/O 0 IO_L28N_0 A5 I/O
0 IO_L09P_0 C14 I/O 0 IO_L28P_0 B6 I/O
0 IO_L10N_0 A17 I/O 0 IO_L29N_0 D6 I/O
0 IO_L10P_0 B17 I/O 0 IO_L29P_0 C6 I/O
0 IO_L11N_0 C15 I/O 0 IO_L30N_0 D8 I/O

DS529 (v2.1) December 18, 2018 www.xilinx.com 109

Pinout Descriptions

Table 82: Spartan-3A FG484 Pinout(Continued) Table 82: Spartan-3A FG484 Pinout(Continued)
FG484 FG484
Bank Pin Name Ball Type Bank Pin Name Ball Type
0 IO_L30P_0 E9 I/O 1 IO_L01P_1/HDC AA22 DUAL
0 IO_L31N_0 B4 I/O 1 IO_L02N_1/LDC0 W20 DUAL
0 IO_L31P_0 A4 I/O 1 IO_L02P_1/LDC1 W19 DUAL
0 IO_L32N_0 D5 I/O 1 IO_L03N_1/A1 T18 DUAL
0 IO_L32P_0 C5 I/O 1 IO_L03P_1/A0 T17 DUAL
0 IO_L33N_0 B3 I/O 1 IO_L05N_1 W21 I/O
0 IO_L33P_0 A3 I/O 1 IO_L05P_1 Y22 I/O
0 IO_L34N_0 F8 I/O 1 IO_L06N_1 V20 I/O
0 IO_L34P_0 E7 I/O 1 IO_L06P_1 V19 I/O
0 IO_L35N_0 E6 I/O 1 IO_L07N_1 V22 I/O
0 IO_L35P_0 F7 I/O 1 IO_L07P_1 W22 I/O
0 IO_L36N_0/PUDC_B A2 DUAL 1 IO_L09N_1 U21 I/O
0 IO_L36P_0/VREF_0 B2 VREF 1 IO_L09P_1 U22 I/O
0 IP_0 E16 INPUT 1 IO_L10N_1 U19 I/O
0 IP_0 E8 INPUT 1 IO_L10P_1 U20 I/O
0 IP_0 F10 INPUT 1 IO_L11N_1 T22 I/O
0 IP_0 F12 INPUT 1 IO_L11P_1 T20 I/O
0 IP_0 F16 INPUT 1 IO_L13N_1 T19 I/O
0 IP_0 G10 INPUT 1 IO_L13P_1 R20 I/O
0 IP_0 G11 INPUT 1 IO_L14N_1 R22 I/O
0 IP_0 G12 INPUT 1 IO_L14P_1 R21 I/O
0 IP_0 G13 INPUT 1 IO_L15N_1/VREF_1 P22 VREF
0 IP_0 G14 INPUT 1 IO_L15P_1 P20 I/O
0 IP_0 G15 INPUT 1 IO_L17N_1/A3 P18 DUAL
0 IP_0 G16 INPUT 1 IO_L17P_1/A2 R19 DUAL
0 IP_0 G7 INPUT 1 IO_L18N_1/A5 N21 DUAL
0 IP_0 G9 INPUT 1 IO_L18P_1/A4 N22 DUAL
0 IP_0 H10 INPUT 1 IO_L19N_1/A7 N19 DUAL
0 IP_0 H13 INPUT 1 IO_L19P_1/A6 N20 DUAL
0 IP_0 H14 INPUT 1 IO_L20N_1/A9 N17 DUAL
0 IP_0/VREF_0 G8 VREF 1 IO_L20P_1/A8 N18 DUAL
0 IP_0/VREF_0 H12 VREF 1 IO_L21N_1/RHCLK1 L22 RHCLK
0 IP_0/VREF_0 H9 VREF 1 IO_L21P_1/RHCLK0 M22 RHCLK
0 VCCO_0 B10 VCCO 1 IO_L22N_1/TRDY1/RHCLK3 L20 RHCLK
0 VCCO_0 B14 VCCO 1 IO_L22P_1/RHCLK2 L21 RHCLK
0 VCCO_0 B18 VCCO 1 IO_L24N_1/RHCLK5 M20 RHCLK
0 VCCO_0 B5 VCCO 1 IO_L24P_1/RHCLK4 M18 RHCLK
0 VCCO_0 F14 VCCO 1 IO_L25N_1/RHCLK7 K19 RHCLK
0 VCCO_0 F9 VCCO 1 IO_L25P_1/IRDY1/RHCLK6 K20 RHCLK
1 IO_L01N_1/LDC2 Y21 DUAL 1 IO_L26N_1/A11 J22 DUAL

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 Pinout Descriptions

Table 82: Spartan-3A FG484 Pinout(Continued) Table 82: Spartan-3A FG484 Pinout(Continued)
FG484 FG484
Bank Pin Name Ball Type Bank Pin Name Ball Type
1 IO_L26P_1/A10 K22 DUAL 1 IP_L23P_1 M17 INPUT
1 IO_L28N_1 L19 I/O 1 IP_L27N_1 L16 INPUT
1 IO_L28P_1 L18 I/O 1 IP_L27P_1/VREF_1 M15 VREF
1 IO_L29N_1/A13 J20 DUAL 1 IP_L31N_1 K16 INPUT
1 IO_L29P_1/A12 J21 DUAL 1 IP_L31P_1 L15 INPUT
1 IO_L30N_1/A15 G22 DUAL 1 IP_L35N_1 K15 INPUT
1 IO_L30P_1/A14 H22 DUAL 1 IP_L35P_1/VREF_1 K14 VREF
1 IO_L32N_1 K18 I/O 1 IP_L39N_1 H18 INPUT
1 IO_L32P_1 K17 I/O 1 IP_L39P_1 H17 INPUT
1 IO_L33N_1/A17 H20 DUAL 1 IP_L43N_1/VREF_1 J15 VREF
1 IO_L33P_1/A16 H21 DUAL 1 IP_L43P_1 J16 INPUT
1 IO_L34N_1/A19 F21 DUAL 1 IP_L47N_1 H15 INPUT
1 IO_L34P_1/A18 F22 DUAL 1 IP_L47P_1/VREF_1 H16 VREF
1 IO_L36N_1 G20 I/O PWR
VCCAUX SUSPEND U18 MGMT
1 IO_L36P_1 G19 I/O
1 VCCO_1 E21 VCCO
1 IO_L37N_1 H19 I/O
1 VCCO_1 J17 VCCO
1 IO_L37P_1 J18 I/O
1 VCCO_1 K21 VCCO
1 IO_L38N_1 F20 I/O
1 VCCO_1 P17 VCCO
1 IO_L38P_1 E20 I/O
1 VCCO_1 P21 VCCO
1 IO_L40N_1 F18 I/O
1 VCCO_1 V21 VCCO
1 IO_L40P_1 F19 I/O
2 IO_L01N_2/M0 W5 DUAL
1 IO_L41N_1 D22 I/O
2 IO_L01P_2/M1 V6 DUAL
1 IO_L41P_1 E22 I/O
2 IO_L02N_2/CSO_B Y4 DUAL
1 IO_L42N_1 D20 I/O
2 IO_L02P_2/M2 W4 DUAL
1 IO_L42P_1 D21 I/O
2 IO_L03N_2 AA3 I/O
1 IO_L44N_1/A21 C21 DUAL
2 IO_L03P_2 AB2 I/O
1 IO_L44P_1/A20 C22 DUAL
2 IO_L04N_2 AA4 I/O
1 IO_L45N_1/A23 B21 DUAL
2 IO_L04P_2 AB3 I/O
1 IO_L45P_1/A22 B22 DUAL
2 IO_L05N_2 Y5 I/O
1 IO_L46N_1/A25 G17 DUAL
2 IO_L05P_2 W6 I/O
1 IO_L46P_1/A24 G18 DUAL
2 IO_L06N_2 AB5 I/O
1 IP_L04N_1/VREF_1 R16 VREF
2 IO_L06P_2 AB4 I/O
1 IP_L04P_1 R15 INPUT
2 IO_L07N_2 Y6 I/O
1 IP_L08N_1 P16 INPUT
2 IO_L07P_2 W7 I/O
1 IP_L08P_1 P15 INPUT
2 IO_L08N_2 AB6 I/O
1 IP_L12N_1/VREF_1 R18 VREF
2 IO_L08P_2 AA6 I/O
1 IP_L12P_1 R17 INPUT
2 IO_L09N_2/VS2 W9 DUAL
1 IP_L16N_1/VREF_1 N16 VREF
2 IO_L09P_2/RDWR_B V9 DUAL
1 IP_L16P_1 N15 INPUT
2 IO_L10N_2 AB7 I/O
1 IP_L23N_1 M16 INPUT

DS529 (v2.1) December 18, 2018 www.xilinx.com 111

Pinout Descriptions

Table 82: Spartan-3A FG484 Pinout(Continued) Table 82: Spartan-3A FG484 Pinout(Continued)
FG484 FG484
Bank Pin Name Ball Type Bank Pin Name Ball Type
2 IO_L10P_2 Y7 I/O 2 IO_L30N_2 V15 I/O
2 IO_L11N_2/VS0 Y8 DUAL 2 IO_L30P_2 V14 I/O
2 IO_L11P_2/VS1 W8 DUAL 2 IO_L31N_2 V16 I/O
2 IO_L12N_2 AB8 I/O 2 IO_L31P_2 W16 I/O
2 IO_L12P_2 AA8 I/O 2 IO_L32N_2 AA19 I/O
2 IO_L13N_2 Y10 I/O 2 IO_L32P_2 AB19 I/O
2 IO_L13P_2 V10 I/O 2 IO_L33N_2 V17 I/O
2 IO_L14N_2/D6 AB9 DUAL 2 IO_L33P_2 W18 I/O
2 IO_L14P_2/D7 Y9 DUAL 2 IO_L34N_2 W17 I/O
2 IO_L15N_2 AB10 I/O 2 IO_L34P_2 Y18 I/O
2 IO_L15P_2 AA10 I/O 2 IO_L35N_2 AA21 I/O
2 IO_L16N_2/D4 AB11 DUAL 2 IO_L35P_2 AB21 I/O
2 IO_L16P_2/D5 Y11 DUAL 2 IO_L36N_2/CCLK AA20 DUAL
2 IO_L17N_2/GCLK13 V11 GCLK 2 IO_L36P_2/D0/DIN/MISO AB20 DUAL
2 IO_L17P_2/GCLK12 U11 GCLK 2 IP_2 P12 INPUT
2 IO_L18N_2/GCLK15 Y12 GCLK 2 IP_2 R10 INPUT
2 IO_L18P_2/GCLK14 W12 GCLK 2 IP_2 R11 INPUT
2 IO_L19N_2/GCLK1 AB12 GCLK 2 IP_2 R9 INPUT
2 IO_L19P_2/GCLK0 AA12 GCLK 2 IP_2 T13 INPUT
2 IO_L20N_2/GCLK3 U12 GCLK 2 IP_2 T14 INPUT
2 IO_L20P_2/GCLK2 V12 GCLK 2 IP_2 T9 INPUT
2 IO_L21N_2 Y13 I/O 2 IP_2 U10 INPUT
2 IO_L21P_2 AB13 I/O 2 IP_2 U15 INPUT
2 IO_L22N_2/MOSI/CSI_B AB14 DUAL XC3S1400A: IP_2
2 U16 INPUT
2 IO_L22P_2 AA14 I/O XC3S700A: N.C. (◆)

2 IO_L23N_2 Y14 I/O XC3S1400A: IP_2

2 U7 INPUT
XC3S700A: N.C. (◆)
2 IO_L23P_2 W13 I/O
2 IP_2 U8 INPUT
IO_L24N_2/
2 AA15 DUAL 2 IP_2 V7 INPUT
DOUT
PWR 2 IP_2/VREF_2 R12 VREF
2 IO_L24P_2/AWAKE AB15 MGMT
2 IP_2/VREF_2 R13 VREF
2 IO_L25N_2 Y15 I/O
2 IP_2/VREF_2 R14 VREF
2 IO_L25P_2 W15 I/O
2 IP_2/VREF_2 T10 VREF
2 IO_L26N_2/D3 U13 DUAL
2 IP_2/VREF_2 T11 VREF
2 IO_L26P_2/INIT_B V13 DUAL
2 IP_2/VREF_2 T15 VREF
2 IO_L27N_2 Y16 I/O
2 IP_2/VREF_2 T16 VREF
2 IO_L27P_2 AB16 I/O
2 IP_2/VREF_2 T7 VREF
2 IO_L28N_2/D1 Y17 DUAL
XC3S1400A: IP_2/VREF_2
2 IO_L28P_2/D2 AA17 DUAL 2 T8 VREF
XC3S700A: N.C. (◆)
2 IO_L29N_2 AB18 I/O 2 IP_2/VREF_2 V8 VREF
2 IO_L29P_2 AB17 I/O 2 VCCO_2 AA13 VCCO

112 www.xilinx.com DS529 (v2.1) December 18, 2018

 Pinout Descriptions

Table 82: Spartan-3A FG484 Pinout(Continued) Table 82: Spartan-3A FG484 Pinout(Continued)
FG484 FG484
Bank Pin Name Ball Type Bank Pin Name Ball Type
2 VCCO_2 AA18 VCCO 3 IO_L22P_3/LHCLK2 K1 LHCLK
2 VCCO_2 AA5 VCCO 3 IO_L24N_3/LHCLK5 M2 LHCLK
2 VCCO_2 AA9 VCCO 3 IO_L24P_3/LHCLK4 M1 LHCLK
2 VCCO_2 U14 VCCO 3 IO_L25N_3/LHCLK7 M4 LHCLK
2 VCCO_2 U9 VCCO 3 IO_L25P_3/TRDY2/LHCLK6 M3 LHCLK
3 IO_L01N_3 D2 I/O 3 IO_L26N_3 N3 I/O
3 IO_L01P_3 C1 I/O 3 IO_L26P_3/VREF_3 N1 VREF
3 IO_L02N_3 C2 I/O 3 IO_L28N_3 P2 I/O
3 IO_L02P_3 B1 I/O 3 IO_L28P_3 P1 I/O
3 IO_L03N_3 E4 I/O 3 IO_L29N_3 P5 I/O
3 IO_L03P_3 D3 I/O 3 IO_L29P_3 P3 I/O
3 IO_L05N_3 G5 I/O 3 IO_L30N_3 N4 I/O
3 IO_L05P_3 G6 I/O 3 IO_L30P_3 M5 I/O
3 IO_L06N_3 E1 I/O 3 IO_L32N_3 R2 I/O
3 IO_L06P_3 D1 I/O 3 IO_L32P_3 R1 I/O
3 IO_L07N_3 E3 I/O 3 IO_L33N_3 R4 I/O
3 IO_L07P_3 F4 I/O 3 IO_L33P_3 R3 I/O
3 IO_L08N_3 G4 I/O 3 IO_L34N_3 T4 I/O
3 IO_L08P_3 F3 I/O 3 IO_L34P_3 R5 I/O
3 IO_L09N_3 H6 I/O 3 IO_L36N_3 T3 I/O
3 IO_L09P_3 H5 I/O 3 IO_L36P_3/VREF_3 T1 VREF
3 IO_L10N_3 J5 I/O 3 IO_L37N_3 U2 I/O
3 IO_L10P_3 K6 I/O 3 IO_L37P_3 U1 I/O
3 IO_L12N_3 F1 I/O 3 IO_L38N_3 V3 I/O
3 IO_L12P_3 F2 I/O 3 IO_L38P_3 V1 I/O
3 IO_L13N_3 G1 I/O 3 IO_L40N_3 U5 I/O
3 IO_L13P_3 G3 I/O 3 IO_L40P_3 T5 I/O
3 IO_L14N_3 H3 I/O 3 IO_L41N_3 U4 I/O
3 IO_L14P_3 H4 I/O 3 IO_L41P_3 U3 I/O
3 IO_L16N_3 H1 I/O 3 IO_L42N_3 W2 I/O
3 IO_L16P_3 H2 I/O 3 IO_L42P_3 W1 I/O
3 IO_L17N_3/VREF_3 J1 VREF 3 IO_L43N_3 W3 I/O
3 IO_L17P_3 J3 I/O 3 IO_L43P_3 V4 I/O
3 IO_L18N_3 K4 I/O 3 IO_L44N_3 Y2 I/O
3 IO_L18P_3 K5 I/O 3 IO_L44P_3 Y1 I/O
3 IO_L20N_3 K2 I/O 3 IO_L45N_3 AA2 I/O
3 IO_L20P_3 K3 I/O 3 IO_L45P_3 AA1 I/O
3 IO_L21N_3/LHCLK1 L3 LHCLK 3 IP_3/VREF_3 J8 VREF
3 IO_L21P_3/LHCLK0 L5 LHCLK 3 IP_3/VREF_3 R6 VREF
3 IO_L22N_3/IRDY2/LHCLK3 L1 LHCLK 3 IP_L04N_3/VREF_3 H7 VREF

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Pinout Descriptions

Table 82: Spartan-3A FG484 Pinout(Continued) Table 82: Spartan-3A FG484 Pinout(Continued)
FG484 FG484
Bank Pin Name Ball Type Bank Pin Name Ball Type
3 IP_L04P_3 H8 INPUT GND GND F17 GND
3 IP_L11N_3 K8 INPUT GND GND F6 GND
3 IP_L11P_3 J7 INPUT GND GND G2 GND
3 IP_L15N_3/VREF_3 L8 VREF GND GND G21 GND
3 IP_L15P_3 K7 INPUT GND GND J11 GND
3 IP_L19N_3 M8 INPUT GND GND J13 GND
3 IP_L19P_3 L7 INPUT GND GND J14 GND
3 IP_L23N_3 M6 INPUT GND GND J19 GND
3 IP_L23P_3 M7 INPUT GND GND J4 GND
3 IP_L27N_3 N9 INPUT GND GND J9 GND
3 IP_L27P_3 N8 INPUT GND GND K10 GND
3 IP_L31N_3 N5 INPUT GND GND K12 GND
3 IP_L31P_3 N6 INPUT GND GND L11 GND
3 IP_L35N_3 P8 INPUT GND GND L13 GND
3 IP_L35P_3 N7 INPUT GND GND L17 GND
3 IP_L39N_3 R8 INPUT GND GND L2 GND
3 IP_L39P_3 P7 INPUT GND GND L6 GND
3 IP_L46N_3/VREF_3 T6 VREF GND GND L9 GND
3 IP_L46P_3 R7 INPUT GND GND M10 GND
3 VCCO_3 E2 VCCO GND GND M12 GND
3 VCCO_3 J2 VCCO GND GND M14 GND
3 VCCO_3 J6 VCCO GND GND M21 GND
3 VCCO_3 N2 VCCO GND GND N11 GND
3 VCCO_3 P6 VCCO GND GND N13 GND
3 VCCO_3 V2 VCCO GND GND P10 GND
GND GND A1 GND GND GND P14 GND
GND GND A22 GND GND GND P19 GND
GND GND AA11 GND GND GND P4 GND
GND GND AA16 GND GND GND P9 GND
GND GND AA7 GND GND GND T12 GND
GND GND AB1 GND GND GND T2 GND
GND GND AB22 GND GND GND T21 GND
GND GND B12 GND GND GND U17 GND
GND GND B16 GND GND GND U6 GND
GND GND B7 GND GND GND W10 GND
GND GND C20 GND GND GND W14 GND
GND GND C3 GND GND GND Y20 GND
GND GND D14 GND GND GND Y3 GND
GND GND D9 GND PWR
VCCAUX SUSPEND U18 MGMT
GND GND F11 GND

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 Pinout Descriptions

Table 82: Spartan-3A FG484 Pinout(Continued)

FG484
Bank Pin Name Ball Type
VCCAUX DONE Y19 CONFIG
VCCAUX PROG_B C4 CONFIG
VCCAUX TCK A21 JTAG
VCCAUX TDI F5 JTAG
VCCAUX TDO E19 JTAG
VCCAUX TMS D4 JTAG
VCCAUX VCCAUX D12 VCCAUX
VCCAUX VCCAUX E18 VCCAUX
VCCAUX VCCAUX E5 VCCAUX
VCCAUX VCCAUX H11 VCCAUX
VCCAUX VCCAUX L4 VCCAUX
VCCAUX VCCAUX M19 VCCAUX
VCCAUX VCCAUX P11 VCCAUX
VCCAUX VCCAUX V18 VCCAUX
VCCAUX VCCAUX V5 VCCAUX
VCCAUX VCCAUX W11 VCCAUX
VCCINT VCCINT J10 VCCINT
VCCINT VCCINT J12 VCCINT
VCCINT VCCINT K11 VCCINT
VCCINT VCCINT K13 VCCINT
VCCINT VCCINT K9 VCCINT
VCCINT VCCINT L10 VCCINT
VCCINT VCCINT L12 VCCINT
VCCINT VCCINT L14 VCCINT
VCCINT VCCINT M11 VCCINT
VCCINT VCCINT M13 VCCINT
VCCINT VCCINT M9 VCCINT
VCCINT VCCINT N10 VCCINT
VCCINT VCCINT N12 VCCINT
VCCINT VCCINT N14 VCCINT
VCCINT VCCINT P13 VCCINT

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Pinout Descriptions

User I/Os by Bank

Table 83 and Table 84 indicate how the user-I/O pins are
distributed between the four I/O banks on the FG484
package. The AWAKE pin is counted as a dual-purpose I/O.

Table 83: User I/Os Per Bank for the XC3S700A in the FG484 Package
All Possible I/O Pins by Type
Package
Edge I/O Bank Maximum I/O I/O INPUT DUAL VREF CLK
Top 0 92 58 17 1 8 8
Right 1 94 33 15 30 8 8
Bottom 2 92 43 11 21 9 8
Left 3 94 61 17 0 8 8
TOTAL 372 195 60 52 33 32

Table 84: User I/Os Per Bank for the XC3S1400A in the FG484 Package
All Possible I/O Pins by Type
Package
Edge I/O Bank Maximum I/O I/O INPUT DUAL VREF CLK
Top 0 92 58 17 1 8 8
Right 1 94 33 15 30 8 8
Bottom 2 95 43 13 21 10 8
Left 3 94 61 17 0 8 8
TOTAL 375 195 62 52 34 32

Footprint Migration Differences

Table 85 summarizes any footprint and functionality
differences between the XC3S700A and the XC3S1400A
FPGAs that might affect easy migration between devices
available in the FG484 package. There are three such balls.
All other pins not listed in Table 85 unconditionally migrate
between Spartan-3A devices available in the FG484
package.
The arrows indicate the direction for easy migration.

Table 85: FG484 Footprint Migration Differences

Pin Bank XC3S700A Migration XC3S1400A
T8 2 N.C.  INPUT/VREF
U7 2 N.C.  INPUT
U16 2 N.C.  INPUT
DIFFERENCES 3
Legend:
 This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.

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 Pinout Descriptions

FG484 Footprint Bank 0

1 2 3 4 5 6 7 8 9 10 11
Left Half of FG484 I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
Package (Top View) A GND L36N_0
PUDC_B
L33P_0 L31P_0 L28N_0 L26N_0 L26P_0 L22N_0 L22P_0 L21P_0
L18N_0
GCLK7

I/O I/O
I/O I/O I/O I/O I/O I/O
B L02P_3
L36P_0
L33N_0 L31N_0
VCCO_0
L28P_0
GND
L25P_0 L24P_0
VCCO_0 L19P_0
VREF_0 GCLK8
I/O: Unrestricted,
195 general-purpose user I/O I/O I/O

_B
I/O I/O I/O I/O I/O I/O I/O
C

G
GND L24N_0 L19N_0

O
L01P_3 L02N_3 L32P_0 L29P_0 L27N_0 L25N_0 L21N_0

PR
VREF_0 GCLK9

INPUT: Unrestricted, I/O

60- general-purpose input pin I/O I/O I/O I/O I/O I/O I/O I/O
D L06P_3 L01N_3 L03P_3
TMS
L32N_0 L29N_0 L27P_0 L30N_0
GND
L23P_0
L20P_0
62 GCLK10

I/O
I/O I/O I/O I/O I/O I/O I/O
E VCCO_3 VCCAUX INPUT L20N_0
51 DUAL: Configuration pins,
L06N_3 L07N_3 L03N_3 L35N_0 L34P_0 L30P_0 L23N_0
GCLK11
then possible user I/O
I/O I/O I/O I/O I/O I/O
F TDI GND VCCO_0 INPUT GND
VREF: User I/O or input L12N_3 L12P_3 L08P_3 L07P_3 L35P_0 L34N_0
33- voltage reference for bank
34
I/O I/O I/O I/O I/O INPUT
G L13N_3
GND
L13P_3 L08N_3 L05N_3 L05P_3
INPUT
VREF_0
INPUT INPUT INPUT

CLK: User I/O, input, or

32 clock buffer input INPUT
I/O I/O I/O I/O I/O I/O INPUT INPUT
H L16N_3 L16P_3 L14N_3 L14P_3 L09P_3 L09N_3
L04N_3
L04P_3 VREF_0
INPUT VCCAUX
VREF_3

SUSPEND: Dedicated I/O

I/O I/O INPUT INPUT
SUSPEND and J L17N_3 VCCO_3
L17P_3
GND
L10N_3
VCCO_3
L11P_3 VREF_3
GND VCCINT GND
2 VREF_3
dual-purpose AWAKE
Power Management pins I/O
I/O I/O I/O I/O I/O INPUT INPUT
K L22P_3
L20N_3 L20P_3 L18N_3 L18P_3 L10P_3 L15P_3 L11N_3
VCCINT GND VCCINT
LHCLK2
2 CONFIG: Dedicated
configuration pins I/O I/O I/O INPUT
L22N_3 INPUT
L GND GND GND VCCINT GND
Bank 3

L21N_3 VCCAUX L21P_3 L15N_3

IRDY2 L19P_3
LHCLK3 LHCLK1 LHCLK0 VREF_3
JTAG: Dedicated JTAG port
4 pins I/O I/O I/O I/O
L25P_3 I/O INPUT INPUT INPUT
M L24P_3 L24N_3 TRDY2 L25N_3
L30P_3 L23N_3 L23P_3 L19N_3
VCCINT GND VCCINT
LHCLK4 LHCLK5 LHCLK6 LHCLK7

GND: Ground I/O

I/O I/O INPUT INPUT INPUT INPUT INPUT
53 N L26P_3 VCCO_3
L26N_3 L30N_3 L31N_3 L31P_3 L35P_3 L27P_3 L27N_3
VCCINT GND
VREF_3

I/O I/O I/O I/O INPUT INPUT

VCCO: Output voltage P L28P_3 L28N_3 L29P_3
GND
L29N_3
VCCO_3
L39P_3 L35N_3
GND GND VCCAUX

24 supply for bank

I/O I/O I/O I/O I/O INPUT INPUT INPUT
R L32P_3 L32N_3 L33P_3 L33N_3 L34P_3 VREF_3 L46P_3 L39N_3
INPUT INPUT INPUT
VCCINT: Internal core
15 supply voltage (+1.2V) I/O
I/O I/O I/O
INPUT
INPUT
INPUT
VREF_2 INPUT INPUT
T L36P_3 GND L46N_3 INPUT
◆
L36N_3 L34N_3 L40P_3 VREF_2 VREF_2 VREF_2
VREF_3 VREF_3

VCCAUX: Auxiliary supply INPUT I/O

I/O I/O I/O I/O I/O
U GND INPUT VCCO_2 INPUT
◆
L17P_2
10 voltage L37P_3 L37N_3 L41P_3 L41N_3 L40N_3
GCLK12

I/O I/O I/O

I/O I/O I/O INPUT I/O
V VCCO_3 VCCAUX L01P_2 INPUT L09P_2 L17N_2
N.C.: Not connected L38P_3 L38N_3 L43P_3 VREF_2 L13P_2
3 (XC3S700A only)
M1 RDWR_B GCLK13
◆ I/O I/O I/O I/O
I/O I/O I/O I/O I/O
W L42P_3 L42N_3 L43N_3
L02P_2 L01N_2
L05P_2 L07P_2
L11P_2 L09N_2 GND VCCAUX
M2 M0 VS1 VS2

I/O I/O I/O I/O

I/O I/O I/O I/O I/O I/O
Y L44P_3 L44N_3
GND L02N_2
L05N_2 L07N_2 L10P_2
L11N_2 L14P_2
L13N_2
L16P_2
CSO_B VS0 D7 D5

A I/O I/O I/O I/O I/O I/O I/O

VCCO_2 GND VCCO_2 GND
A L45P_3 L45N_3 L03N_2 L04N_2 L08P_2 L12P_2 L15P_2

A I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
GND L14N_2 L16N_2
B L03P_2 L04P_2 L06P_2 L06N_2 L08N_2 L10N_2 L12N_2
D6
L15N_2
D4

Bank 2 DS529-4 01 101106

Figure 25: FG484 Package Footprint (Top View)

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Pinout Descriptions

Bank 0
12 13 14 15 16 17 18 19 20 21 22
I/O I/O
Right Half of FG484
I/O I/O I/O I/O I/O I/O I/O
L18P_0
GCLK6
L16N_0 L13N_0
L12N_0
VREF_0
L12P_0 L10N_0 L05N_0 L06N_0 L03N_0
TCK GND A Package (Top View)
I/O I/O I/O
I/O I/O I/O I/O
GND
L16P_0
VCCO_0
L13P_0
GND
L10P_0
VCCO_0 L06P_0
L03P_0
L45N_1 L45P_1 B
VREF_0 A23 A22

I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O
L17P_0
L15N_0 L09P_0 L11N_0 L08N_0 L07N_0 L05P_0 L02N_0
GND L44N_1 L44P_1 C
GCLK4 A21 A20

I/O
I/O I/O I/O I/O I/O I/O I/O I/O
VCCAUX
L15P_0
GND
L11P_0 L08P_0 L07P_0 L01N_0
L02P_0
L42N_1 L42P_1 L41N_1
D
VREF_0

I/O
I/O I/O I/O I/O I/O I/O
L17N_0
L14N_0 L09N_0 L04P_0
INPUT
L01P_0
VCCAUX TDO
L38P_1
VCCO_1
L41P_1
E
GCLK5

I/O I/O
I/O I/O I/O I/O I/O
INPUT
L14P_0
VCCO_0
L04N_0
INPUT GND
L40N_1 L40P_1 L38N_1
L34N_1 L34P_1 F
A19 A18

I/O I/O I/O

I/O I/O
INPUT INPUT INPUT INPUT INPUT L46N_1 L46P_1
L36P_1 L36N_1
GND L30N_1 G
A25 A24 A15

INPUT I/O I/O I/O

INPUT INPUT INPUT INPUT I/O
VREF_0
INPUT INPUT
L47N_1
L47P_1
L39P_1 L39N_1 L37N_1
L33N_1 L33P_1 L30P_1 H
VREF_1 A17 A16 A14

INPUT I/O I/O I/O

INPUT I/O
VCCINT GND GND L43N_1
L43P_1
VCCO_1
L37P_1
GND L29N_1 L29P_1 L26N_1 J
VREF_1 A13 A12 A11

INPUT I/O I/O I/O

INPUT INPUT I/O I/O L25P_1
GND VCCINT L35P_1
L35N_1 L31N_1 L32P_1 L32N_1
L25N_1 IRDY1
VCCO_1 L26P_1 K
VREF_1 RHCLK7 RHCLK6 A10

I/O I/O I/O

INPUT INPUT I/O I/O L22N_1
VCCINT GND VCCINT GND L
Bank 1

TRDY1 L22P_1 L21N_1

L31P_1 L27N_1 L28P_1 L28N_1
RHCLK3 RHCLK2 RHCLK1

INPUT I/O I/O I/O

INPUT INPUT
GND VCCINT GND L27P_1
L23N_1 L23P_1
L24P_1 VCCAUX L24N_1 GND L21P_1 M
VREF_1 RHCLK4 RHCLK5 RHCLK0

INPUT I/O I/O I/O I/O I/O I/O

INPUT
VCCINT GND VCCINT
L16P_1
L16N_1 L20N_1 L20P_1 L19N_1 L19P_1 L18N_1 L18P_1 N
VREF_1 A9 A8 A7 A6 A5 A4

I/O I/O
INPUT INPUT I/O
INPUT VCCINT GND
L08P_1 L08N_1
VCCO_1 L17N_1 GND
L15P_1
VCCO_1 L15N_1 P
A3 VREF_1

INPUT INPUT I/O

INPUT INPUT INPUT INPUT INPUT I/O I/O I/O
VREF_2 VREF_2 VREF_2 L04P_1
L04N_1
L12P_1
L12N_1 L17P_1
L13P_1 L14P_1 L14N_1
R
VREF_1 VREF_1 A2

I/O I/O
INPUT INPUT I/O I/O I/O
GND INPUT INPUT
VREF_2 VREF_2
L03P_1 L03N_1
L13N_1 L11P_1
GND
L11N_1
T
A0 A1

I/O I/O
D

INPUT
EN

I/O I/O I/O I/O

VCCO_2 INPUT GND U
◆
L20N_2 L26N_2
SP

L10N_1 L10P_1 L09N_1 L09P_1

SU

GCLK3 D3

I/O I/O
I/O I/O I/O I/O I/O I/O I/O
L20P_2 L26P_2
L30P_2 L30N_2 L31N_2 L33N_2
VCCAUX
L06P_1 L06N_1
VCCO_1
L07N_1
V
GCLK2 INIT_B

I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O
L18P_2
L23P_2
GND
L25P_2 L31P_2 L34N_2 L33P_2
L02P_1 L02N_1
L05N_1 L07P_1
W
GCLK14 LDC1 LDC0

I/O I/O I/O

I/O I/O I/O I/O I/O I/O
L18N_2
L21N_2 L23N_2 L25N_2 L27N_2
L28N_2
L34P_2
DONE GND L01N_1
L05P_1
Y
GCLK15 D1 LDC2

I/O I/O I/O I/O I/O A

I/O I/O I/O
L19P_2 VCCO_2 L24N_2 GND L28P_2 VCCO_2 L36N_2 L01P_1
GCLK0
L22P_2
DOUT D2
L32N_2
CCLK
L35N_2
HDC A

I/O I/O I/O I/O

I/O L22N_2 I/O I/O I/O I/O L36P_2 I/O A
L19N_2 MOSI L24P_2 D0
GND
GCLK1
L21P_2
CSI_B AWAKE
L27P_2 L29P_2 L29N_2 L32P_2
DIN/MISO
L35P_2 B

Bank 2 DS529-4_02_012009

Figure 26:

118 www.xilinx.com DS529 (v2.1) December 18, 2018

 Pinout Descriptions

FG676: 676-ball Fine-pitch Ball Grid Array

The 676-ball fine-pitch ball grid array, FG676, supports the Table 86: Spartan-3A FG676 Pinout(Continued)
XC3S1400A FPGA. FG676
Table 86 lists all the FG676 package pins. They are sorted Bank Pin Name Ball Type
by bank number and then by pin name. Pairs of pins that 0 IO_L15N_0 A19 I/O
form a differential I/O pair appear together in the table. The 0 IO_L15P_0 B19 I/O
table also shows the pin number for each pin and the pin
type, as defined earlier. 0 IO_L16N_0 H15 I/O
0 IO_L16P_0 G15 I/O
The XC3S1400A has 17 unconnected balls, indicated as
N.C. (No Connection) in Table 86 and with the black 0 IO_L17N_0 C18 I/O
diamond character () in Table 86 and Figure 27. 0 IO_L17P_0 D18 I/O
An electronic version of this package pinout table and 0 IO_L18N_0 A18 I/O
footprint diagram is available for download from the Xilinx 0 IO_L18P_0 B18 I/O
website at:
0 IO_L19N_0 B17 I/O
www.xilinx.com/support/documentation/data_sheets/
0 IO_L19P_0 C17 I/O
s3a_pin.zip.
0 IO_L20N_0/VREF_0 E15 VREF
Pinout Table 0 IO_L20P_0 F15 I/O

Table 86: Spartan-3A FG676 Pinout 0 IO_L21N_0 C16 I/O

0 IO_L21P_0 D17 I/O
FG676
Bank Pin Name Ball Type 0 IO_L22N_0 C15 I/O
0 IO_L01N_0 F20 I/O 0 IO_L22P_0 D16 I/O
0 IO_L01P_0 G20 I/O 0 IO_L23N_0 A15 I/O
0 IO_L02N_0 F19 I/O 0 IO_L23P_0 B15 I/O
0 IO_L02P_0/VREF_0 G19 VREF 0 IO_L24N_0 F14 I/O
0 IO_L05N_0 C22 I/O 0 IO_L24P_0 E14 I/O
0 IO_L05P_0 D22 I/O 0 IO_L25N_0/GCLK5 J14 GCLK
0 IO_L06N_0 C23 I/O 0 IO_L25P_0/GCLK4 K14 GCLK
0 IO_L06P_0 D23 I/O 0 IO_L26N_0/GCLK7 A14 GCLK
0 IO_L07N_0 A22 I/O 0 IO_L26P_0/GCLK6 B14 GCLK
0 IO_L07P_0 B23 I/O 0 IO_L27N_0/GCLK9 G13 GCLK
0 IO_L08N_0 G17 I/O 0 IO_L27P_0/GCLK8 F13 GCLK
0 IO_L08P_0 H17 I/O 0 IO_L28N_0/GCLK11 C13 GCLK
0 IO_L09N_0 B21 I/O 0 IO_L28P_0/GCLK10 B13 GCLK
0 IO_L09P_0 C21 I/O 0 IO_L29N_0 B12 I/O
0 IO_L10N_0 D21 I/O 0 IO_L29P_0 A12 I/O
0 IO_L10P_0 E21 I/O 0 IO_L30N_0 C12 I/O
0 IO_L11N_0 C20 I/O 0 IO_L30P_0 D13 I/O
0 IO_L11P_0 D20 I/O 0 IO_L31N_0 F12 I/O
0 IO_L12N_0 K16 I/O 0 IO_L31P_0 E12 I/O
0 IO_L12P_0 J16 I/O 0 IO_L32N_0/VREF_0 D11 VREF
0 IO_L13N_0 E17 I/O 0 IO_L32P_0 C11 I/O
0 IO_L13P_0 F17 I/O 0 IO_L33N_0 B10 I/O
0 IO_L14N_0 A20 I/O 0 IO_L33P_0 A10 I/O
0 IO_L14P_0/VREF_0 B20 VREF

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Table 86: Spartan-3A FG676 Pinout(Continued) Table 86: Spartan-3A FG676 Pinout(Continued)
FG676 FG676
Bank Pin Name Ball Type Bank Pin Name Ball Type
0 IO_L34N_0 D10 I/O 0 IP_0 D12 INPUT
0 IO_L34P_0 C10 I/O 0 IP_0 D15 INPUT
0 IO_L35N_0 H12 I/O 0 IP_0 D19 INPUT
0 IO_L35P_0 G12 I/O 0 IP_0 E11 INPUT
0 IO_L36N_0 B9 I/O 0 IP_0 E18 INPUT
0 IO_L36P_0 A9 I/O 0 IP_0 E20 INPUT
0 IO_L37N_0 D9 I/O 0 IP_0 F10 INPUT
0 IO_L37P_0 E10 I/O 0 IP_0 G14 INPUT
0 IO_L38N_0 B8 I/O 0 IP_0 G16 INPUT
0 IO_L38P_0 A8 I/O 0 IP_0 H13 INPUT
0 IO_L39N_0 K12 I/O 0 IP_0 H18 INPUT
0 IO_L39P_0 J12 I/O 0 IP_0 J10 INPUT
0 IO_L40N_0 D8 I/O 0 IP_0 J13 INPUT
0 IO_L40P_0 C8 I/O 0 IP_0 J15 INPUT
0 IO_L41N_0 C6 I/O 0 IP_0/VREF_0 D7 VREF
0 IO_L41P_0 B6 I/O 0 IP_0/VREF_0 D14 VREF
0 IO_L42N_0 C7 I/O 0 IP_0/VREF_0 G11 VREF
0 IO_L42P_0 B7 I/O 0 IP_0/VREF_0 J17 VREF
0 IO_L43N_0 K11 I/O 0 N.C. (◆) A24 N.C.
0 IO_L43P_0 J11 I/O 0 N.C. (◆) B24 N.C.
0 IO_L44N_0 D6 I/O 0 N.C. (◆) D5 N.C.
0 IO_L44P_0 C5 I/O 0 N.C. (◆) E9 N.C.
0 IO_L45N_0 B4 I/O 0 N.C. (◆) F18 N.C.
0 IO_L45P_0 A4 I/O 0 N.C. (◆) E6 N.C.
0 IO_L46N_0 H10 I/O 0 N.C. (◆) F9 N.C.
0 IO_L46P_0 G10 I/O 0 N.C. (◆) G18 N.C.
0 IO_L47N_0 H9 I/O 0 VCCO_0 B5 VCCO
0 IO_L47P_0 G9 I/O 0 VCCO_0 B11 VCCO
0 IO_L48N_0 E7 I/O 0 VCCO_0 B16 VCCO
0 IO_L48P_0 F7 I/O 0 VCCO_0 B22 VCCO
0 IO_L51N_0 B3 I/O 0 VCCO_0 E8 VCCO
0 IO_L51P_0 A3 I/O 0 VCCO_0 E13 VCCO
0 IO_L52N_0/PUDC_B G8 DUAL 0 VCCO_0 E19 VCCO
0 IO_L52P_0/VREF_0 F8 VREF 0 VCCO_0 H11 VCCO
0 IP_0 A5 INPUT 0 VCCO_0 H16 VCCO
0 IP_0 A7 INPUT 1 IO_L01N_1/LDC2 Y21 DUAL
0 IP_0 A13 INPUT 1 IO_L01P_1/HDC Y20 DUAL
0 IP_0 A17 INPUT 1 IO_L02N_1/LDC0 AD25 DUAL
0 IP_0 A23 INPUT 1 IO_L02P_1/LDC1 AE26 DUAL
0 IP_0 C4 INPUT 1 IO_L03N_1/A1 AC24 DUAL

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 Pinout Descriptions

Table 86: Spartan-3A FG676 Pinout(Continued) Table 86: Spartan-3A FG676 Pinout(Continued)
FG676 FG676
Bank Pin Name Ball Type Bank Pin Name Ball Type
1 IO_L03P_1/A0 AC23 DUAL 1 IO_L26P_1/A4 T23 DUAL
1 IO_L04N_1 W21 I/O 1 IO_L27N_1/A7 R17 DUAL
1 IO_L04P_1 W20 I/O 1 IO_L27P_1/A6 R18 DUAL
1 IO_L05N_1 AC25 I/O 1 IO_L29N_1/A9 R26 DUAL
1 IO_L05P_1 AD26 I/O 1 IO_L29P_1/A8 R25 DUAL
1 IO_L06N_1 AB26 I/O 1 IO_L30N_1/RHCLK1 P20 RHCLK
1 IO_L06P_1 AC26 I/O 1 IO_L30P_1/RHCLK0 P21 RHCLK
1 IO_L07N_1/VREF_1 AB24 VREF 1 IO_L31N_1/TRDY1/RHCLK3 P25 RHCLK
1 IO_L07P_1 AB23 I/O 1 IO_L31P_1/RHCLK2 P26 RHCLK
1 IO_L08N_1 V19 I/O 1 IO_L33N_1/RHCLK5 N24 RHCLK
1 IO_L08P_1 V18 I/O 1 IO_L33P_1/RHCLK4 P23 RHCLK
1 IO_L09N_1 AA23 I/O 1 IO_L34N_1/RHCLK7 N19 RHCLK
1 IO_L09P_1 AA22 I/O 1 IO_L34P_1/IRDY1/RHCLK6 P18 RHCLK
1 IO_L10N_1 U20 I/O 1 IO_L35N_1/A11 M25 DUAL
1 IO_L10P_1 V21 I/O 1 IO_L35P_1/A10 M26 DUAL
1 IO_L11N_1 AA25 I/O 1 IO_L37N_1 N21 I/O
1 IO_L11P_1 AA24 I/O 1 IO_L37P_1 P22 I/O
1 IO_L12N_1 U18 I/O 1 IO_L38N_1/A13 M23 DUAL
1 IO_L12P_1 U19 I/O 1 IO_L38P_1/A12 L24 DUAL
1 IO_L13N_1 Y23 I/O 1 IO_L39N_1/A15 N17 DUAL
1 IO_L13P_1 Y22 I/O 1 IO_L39P_1/A14 N18 DUAL
1 IO_L14N_1 T20 I/O 1 IO_L41N_1 K26 I/O
1 IO_L14P_1 U21 I/O 1 IO_L41P_1 K25 I/O
1 IO_L15N_1 Y25 I/O 1 IO_L42N_1/A17 M20 DUAL
1 IO_L15P_1 Y24 I/O 1 IO_L42P_1/A16 N20 DUAL
1 IO_L17N_1 T17 I/O 1 IO_L43N_1/A19 J25 DUAL
1 IO_L17P_1 T18 I/O 1 IO_L43P_1/A18 J26 DUAL
1 IO_L18N_1 V22 I/O 1 IO_L45N_1 M22 I/O
1 IO_L18P_1 W23 I/O 1 IO_L45P_1 M21 I/O
1 IO_L19N_1 V25 I/O 1 IO_L46N_1 K22 I/O
1 IO_L19P_1 V24 I/O 1 IO_L46P_1 K23 I/O
1 IO_L21N_1 U22 I/O 1 IO_L47N_1 M18 I/O
1 IO_L21P_1 V23 I/O 1 IO_L47P_1 M19 I/O
1 IO_L22N_1 R20 I/O 1 IO_L49N_1 J22 I/O
1 IO_L22P_1 R19 I/O 1 IO_L49P_1 J23 I/O
1 IO_L23N_1/VREF_1 U24 VREF 1 IO_L50N_1 K21 I/O
1 IO_L23P_1 U23 I/O 1 IO_L50P_1 L22 I/O
1 IO_L25N_1/A3 R22 DUAL 1 IO_L51N_1 G24 I/O
1 IO_L25P_1/A2 R21 DUAL 1 IO_L51P_1 G23 I/O
1 IO_L26N_1/A5 T24 DUAL 1 IO_L53N_1 K20 I/O

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Table 86: Spartan-3A FG676 Pinout(Continued) Table 86: Spartan-3A FG676 Pinout(Continued)
FG676 FG676
Bank Pin Name Ball Type Bank Pin Name Ball Type
1 IO_L53P_1 L20 I/O 1 IP_L48P_1 H23 INPUT
1 IO_L54N_1 F24 I/O 1 IP_L52N_1/VREF_1 G25 VREF
1 IO_L54P_1 F25 I/O 1 IP_L52P_1 G26 INPUT
1 IO_L55N_1 L17 I/O 1 IP_L65N_1 B25 INPUT
1 IO_L55P_1 L18 I/O 1 IP_L65P_1/VREF_1 B26 VREF
1 IO_L56N_1 F23 I/O 1 VCCO_1 AB25 VCCO
1 IO_L56P_1 E24 I/O 1 VCCO_1 E25 VCCO
1 IO_L57N_1 K18 I/O 1 VCCO_1 H22 VCCO
1 IO_L57P_1 K19 I/O 1 VCCO_1 L19 VCCO
1 IO_L58N_1 G22 I/O 1 VCCO_1 L25 VCCO
1 IO_L58P_1/VREF_1 F22 VREF 1 VCCO_1 N22 VCCO
1 IO_L59N_1 J20 I/O 1 VCCO_1 T19 VCCO
1 IO_L59P_1 J19 I/O 1 VCCO_1 T25 VCCO
1 IO_L60N_1 D26 I/O 1 VCCO_1 W22 VCCO
1 IO_L60P_1 E26 I/O 2 IO_L01N_2/M0 AD4 DUAL
1 IO_L61N_1 D24 I/O 2 IO_L01P_2/M1 AC4 DUAL
1 IO_L61P_1 D25 I/O 2 IO_L02N_2/CSO_B AA7 DUAL
1 IO_L62N_1/A21 H21 DUAL 2 IO_L02P_2/M2 Y7 DUAL
1 IO_L62P_1/A20 J21 DUAL 2 IO_L05N_2 Y9 I/O
1 IO_L63N_1/A23 C25 DUAL 2 IO_L05P_2 W9 I/O
1 IO_L63P_1/A22 C26 DUAL 2 IO_L06N_2 AF3 I/O
1 IO_L64N_1/A25 G21 DUAL 2 IO_L06P_2 AE3 I/O
1 IO_L64P_1/A24 H20 DUAL 2 IO_L07N_2 AF4 I/O
1 IP_L16N_1 Y26 INPUT 2 IO_L07P_2 AE4 I/O
1 IP_L16P_1 W25 INPUT 2 IO_L08N_2 AD6 I/O
1 IP_L20N_1/VREF_1 V26 VREF 2 IO_L08P_2 AC6 I/O
1 IP_L20P_1 W26 INPUT 2 IO_L09N_2 W10 I/O
1 IP_L24N_1/VREF_1 U26 VREF 2 IO_L09P_2 V10 I/O
1 IP_L24P_1 U25 INPUT 2 IO_L10N_2 AE6 I/O
1 IP_L28N_1 R24 INPUT 2 IO_L10P_2 AF5 I/O
1 IP_L28P_1/VREF_1 R23 VREF 2 IO_L11N_2 AE7 I/O
1 IP_L32N_1 N25 INPUT 2 IO_L11P_2 AD7 I/O
1 IP_L32P_1 N26 INPUT 2 IO_L12N_2 AA10 I/O
1 IP_L36N_1 N23 INPUT 2 IO_L12P_2 Y10 I/O
1 IP_L36P_1/VREF_1 M24 VREF 2 IO_L13N_2 U11 I/O
1 IP_L40N_1 L23 INPUT 2 IO_L13P_2 V11 I/O
1 IP_L40P_1 K24 INPUT 2 IO_L14N_2 AB7 I/O
1 IP_L44N_1 H25 INPUT 2 IO_L14P_2 AC8 I/O
1 IP_L44P_1/VREF_1 H26 VREF 2 IO_L15N_2 AC9 I/O
1 IP_L48N_1 H24 INPUT 2 IO_L15P_2 AB9 I/O

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 Pinout Descriptions

Table 86: Spartan-3A FG676 Pinout(Continued) Table 86: Spartan-3A FG676 Pinout(Continued)
FG676 FG676
Bank Pin Name Ball Type Bank Pin Name Ball Type
2 IO_L16N_2 W12 I/O 2 IO_L35P_2 V15 I/O
2 IO_L16P_2 V12 I/O 2 IO_L36N_2/D1 AE18 DUAL
2 IO_L17N_2/VS2 AA12 DUAL 2 IO_L36P_2/D2 AF18 DUAL
2 IO_L17P_2/RDWR_B Y12 DUAL 2 IO_L37N_2 AE19 I/O
2 IO_L18N_2 AF8 I/O 2 IO_L37P_2 AF19 I/O
2 IO_L18P_2 AE8 I/O 2 IO_L38N_2 AB16 I/O
2 IO_L19N_2/VS0 AF9 DUAL 2 IO_L38P_2 AC16 I/O
2 IO_L19P_2/VS1 AE9 DUAL 2 IO_L39N_2 AE20 I/O
2 IO_L20N_2 W13 I/O 2 IO_L39P_2 AF20 I/O
2 IO_L20P_2 V13 I/O 2 IO_L40N_2 AC19 I/O
2 IO_L21N_2 AC12 I/O 2 IO_L40P_2 AD19 I/O
2 IO_L21P_2 AB12 I/O 2 IO_L41N_2 AC20 I/O
2 IO_L22N_2/D6 AF10 DUAL 2 IO_L41P_2 AD20 I/O
2 IO_L22P_2/D7 AE10 DUAL 2 IO_L42N_2 U16 I/O
2 IO_L23N_2 AC11 I/O 2 IO_L42P_2 V16 I/O
2 IO_L23P_2 AD11 I/O 2 IO_L43N_2 Y17 I/O
2 IO_L24N_2/D4 AE12 DUAL 2 IO_L43P_2 AA17 I/O
2 IO_L24P_2/D5 AF12 DUAL 2 IO_L44N_2 AD21 I/O
2 IO_L25N_2/GCLK13 Y13 GCLK 2 IO_L44P_2 AE21 I/O
2 IO_L25P_2/GCLK12 AA13 GCLK 2 IO_L45N_2 AC21 I/O
2 IO_L26N_2/GCLK15 AE13 GCLK 2 IO_L45P_2 AD22 I/O
2 IO_L26P_2/GCLK14 AF13 GCLK 2 IO_L46N_2 V17 I/O
2 IO_L27N_2/GCLK1 AA14 GCLK 2 IO_L46P_2 W17 I/O
2 IO_L27P_2/GCLK0 Y14 GCLK 2 IO_L47N_2 AA18 I/O
2 IO_L28N_2/GCLK3 AE14 GCLK 2 IO_L47P_2 AB18 I/O
2 IO_L28P_2/GCLK2 AF14 GCLK 2 IO_L48N_2 AE23 I/O
2 IO_L29N_2 AC14 I/O 2 IO_L48P_2 AF23 I/O
2 IO_L29P_2 AD14 I/O 2 IO_L51N_2 AE25 I/O
2 IO_L30N_2/MOSI/CSI_B AB15 DUAL 2 IO_L51P_2 AF25 I/O
2 IO_L30P_2 AC15 I/O 2 IO_L52N_2/CCLK AE24 DUAL
2 IO_L31N_2 W15 I/O 2 IO_L52P_2/D0/DIN/MISO AF24 DUAL
2 IO_L31P_2 V14 I/O 2 IP_2 AA19 INPUT
2 IO_L32N_2/DOUT AE15 DUAL 2 IP_2 AB13 INPUT
PWR 2 IP_2 AB17 INPUT
2 IO_L32P_2/AWAKE AD15 MGMT
2 IP_2 AB20 INPUT
2 IO_L33N_2 AD17 I/O
2 IP_2 AC7 INPUT
2 IO_L33P_2 AE17 I/O
2 IP_2 AC13 INPUT
2 IO_L34N_2/D3 Y15 DUAL
2 IP_2 AC17 INPUT
2 IO_L34P_2/INIT_B AA15 DUAL
2 IP_2 AC18 INPUT
2 IO_L35N_2 U15 I/O
2 IP_2 AD9 INPUT

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Pinout Descriptions

Table 86: Spartan-3A FG676 Pinout(Continued) Table 86: Spartan-3A FG676 Pinout(Continued)
FG676 FG676
Bank Pin Name Ball Type Bank Pin Name Ball Type
2 IP_2 AD10 INPUT 3 IO_L05P_3 K9 I/O
2 IP_2 AD16 INPUT 3 IO_L06N_3 E4 I/O
2 IP_2 AF2 INPUT 3 IO_L06P_3 D3 I/O
2 IP_2 AF7 INPUT 3 IO_L07N_3 F4 I/O
2 IP_2 Y11 INPUT 3 IO_L07P_3 E3 I/O
2 IP_2/VREF_2 AA9 VREF 3 IO_L09N_3 G4 I/O
2 IP_2/VREF_2 AA20 VREF 3 IO_L09P_3 F5 I/O
2 IP_2/VREF_2 AB6 VREF 3 IO_L10N_3 H6 I/O
2 IP_2/VREF_2 AB10 VREF 3 IO_L10P_3 J7 I/O
2 IP_2/VREF_2 AC10 VREF 3 IO_L11N_3 F2 I/O
2 IP_2/VREF_2 AD12 VREF 3 IO_L11P_3 E1 I/O
2 IP_2/VREF_2 AF15 VREF 3 IO_L13N_3 J6 I/O
2 IP_2/VREF_2 AF17 VREF 3 IO_L13P_3 K7 I/O
2 IP_2/VREF_2 AF22 VREF 3 IO_L14N_3 F3 I/O
2 IP_2/VREF_2 Y16 VREF 3 IO_L14P_3 G3 I/O
2 N.C. (◆) AA8 N.C. 3 IO_L15N_3 L9 I/O
2 N.C. (◆) AC5 N.C. 3 IO_L15P_3 L10 I/O
2 N.C. (◆) AC22 N.C. 3 IO_L17N_3 H1 I/O
2 N.C. (◆) AD5 N.C. 3 IO_L17P_3 H2 I/O
2 N.C. (◆) Y18 N.C. 3 IO_L18N_3 L7 I/O
2 N.C. (◆) Y19 N.C. 3 IO_L18P_3 K6 I/O
2 N.C. (◆) AD23 N.C. 3 IO_L19N_3 J4 I/O
2 N.C. (◆) W18 N.C. 3 IO_L19P_3 J5 I/O
2 N.C. (◆) Y8 N.C. 3 IO_L21N_3 M9 I/O
2 VCCO_2 AB8 VCCO 3 IO_L21P_3 M10 I/O
2 VCCO_2 AB14 VCCO 3 IO_L22N_3 K4 I/O
2 VCCO_2 AB19 VCCO 3 IO_L22P_3 K5 I/O
2 VCCO_2 AE5 VCCO 3 IO_L23N_3 K2 I/O
2 VCCO_2 AE11 VCCO 3 IO_L23P_3 K3 I/O
2 VCCO_2 AE16 VCCO 3 IO_L25N_3 L3 I/O
2 VCCO_2 AE22 VCCO 3 IO_L25P_3 L4 I/O
2 VCCO_2 W11 VCCO 3 IO_L26N_3 M7 I/O
2 VCCO_2 W16 VCCO 3 IO_L26P_3 M8 I/O
3 IO_L01N_3 J9 I/O 3 IO_L27N_3 M3 I/O
3 IO_L01P_3 J8 I/O 3 IO_L27P_3 M4 I/O
3 IO_L02N_3 B1 I/O 3 IO_L28N_3 M6 I/O
3 IO_L02P_3 B2 I/O 3 IO_L28P_3 M5 I/O
3 IO_L03N_3 H7 I/O 3 IO_L29N_3/VREF_3 M1 VREF
3 IO_L03P_3 G6 I/O 3 IO_L29P_3 M2 I/O
3 IO_L05N_3 K8 I/O 3 IO_L30N_3 N4 I/O

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 Pinout Descriptions

Table 86: Spartan-3A FG676 Pinout(Continued) Table 86: Spartan-3A FG676 Pinout(Continued)
FG676 FG676
Bank Pin Name Ball Type Bank Pin Name Ball Type
3 IO_L30P_3 N5 I/O 3 IO_L52P_3 W3 I/O
3 IO_L31N_3 N2 I/O 3 IO_L53N_3 Y2 I/O
3 IO_L31P_3 N1 I/O 3 IO_L53P_3 Y1 I/O
3 IO_L32N_3/LHCLK1 N7 LHCLK 3 IO_L55N_3 AA3 I/O
3 IO_L32P_3/LHCLK0 N6 LHCLK 3 IO_L55P_3 AA2 I/O
3 IO_L33N_3/IRDY2/LHCLK3 P2 LHCLK 3 IO_L56N_3 U8 I/O
3 IO_L33P_3/LHCLK2 P1 LHCLK 3 IO_L56P_3 U7 I/O
3 IO_L34N_3/LHCLK5 P3 LHCLK 3 IO_L57N_3 Y6 I/O
3 IO_L34P_3/LHCLK4 P4 LHCLK 3 IO_L57P_3 Y5 I/O
3 IO_L35N_3/LHCLK7 P10 LHCLK 3 IO_L59N_3 V6 I/O
3 IO_L35P_3/TRDY2/LHCLK6 N9 LHCLK 3 IO_L59P_3 V7 I/O
3 IO_L36N_3 R2 I/O 3 IO_L60N_3 AC1 I/O
3 IO_L36P_3/VREF_3 R1 VREF 3 IO_L60P_3 AB1 I/O
3 IO_L37N_3 R4 I/O 3 IO_L61N_3 V8 I/O
3 IO_L37P_3 R3 I/O 3 IO_L61P_3 U9 I/O
3 IO_L38N_3 T4 I/O 3 IO_L63N_3 W6 I/O
3 IO_L38P_3 T3 I/O 3 IO_L63P_3 W7 I/O
3 IO_L39N_3 P6 I/O 3 IO_L64N_3 AC3 I/O
3 IO_L39P_3 P7 I/O 3 IO_L64P_3 AC2 I/O
3 IO_L40N_3 R6 I/O 3 IO_L65N_3 AD2 I/O
3 IO_L40P_3 R5 I/O 3 IO_L65P_3 AD1 I/O
3 IO_L41N_3 P9 I/O 3 IP_L04N_3/VREF_3 C1 VREF
3 IO_L41P_3 P8 I/O 3 IP_L04P_3 C2 INPUT
3 IO_L42N_3 U4 I/O 3 IP_L08N_3 D1 INPUT
3 IO_L42P_3 T5 I/O 3 IP_L08P_3 D2 INPUT
3 IO_L43N_3 R9 I/O 3 IP_L12N_3/VREF_3 H4 VREF
3 IO_L43P_3/VREF_3 R10 VREF 3 IP_L12P_3 G5 INPUT
3 IO_L44N_3 U2 I/O 3 IP_L16N_3 G1 INPUT
3 IO_L44P_3 U1 I/O 3 IP_L16P_3 G2 INPUT
3 IO_L45N_3 R7 I/O 3 IP_L20N_3/VREF_3 J2 VREF
3 IO_L45P_3 R8 I/O 3 IP_L20P_3 J3 INPUT
3 IO_L47N_3 V2 I/O 3 IP_L24N_3 K1 INPUT
3 IO_L47P_3 V1 I/O 3 IP_L24P_3 J1 INPUT
3 IO_L48N_3 T9 I/O 3 IP_L46N_3 V4 INPUT
3 IO_L48P_3 T10 I/O 3 IP_L46P_3 U3 INPUT
3 IO_L49N_3 V5 I/O 3 IP_L50N_3/VREF_3 W2 VREF
3 IO_L49P_3 U5 I/O 3 IP_L50P_3 W1 INPUT
3 IO_L51N_3 U6 I/O 3 IP_L54N_3 Y4 INPUT
3 IO_L51P_3 T7 I/O 3 IP_L54P_3 Y3 INPUT
3 IO_L52N_3 W4 I/O 3 IP_L58N_3/VREF_3 AA5 VREF

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Table 86: Spartan-3A FG676 Pinout(Continued) Table 86: Spartan-3A FG676 Pinout(Continued)
FG676 FG676
Bank Pin Name Ball Type Bank Pin Name Ball Type
3 IP_L58P_3 AA4 INPUT GND GND C19 GND
3 IP_L62N_3 AB4 INPUT GND GND C24 GND
3 IP_L62P_3 AB3 INPUT GND GND F1 GND
3 IP_L66N_3/VREF_3 AE2 VREF GND GND F6 GND
3 IP_L66P_3 AE1 INPUT GND GND F11 GND
3 VCCO_3 AB2 VCCO GND GND F16 GND
3 VCCO_3 E2 VCCO GND GND F21 GND
3 VCCO_3 H5 VCCO GND GND F26 GND
3 VCCO_3 L2 VCCO GND GND H3 GND
3 VCCO_3 L8 VCCO GND GND H8 GND
3 VCCO_3 P5 VCCO GND GND H14 GND
3 VCCO_3 T2 VCCO GND GND H19 GND
3 VCCO_3 T8 VCCO GND GND J24 GND
3 VCCO_3 W5 VCCO GND GND K10 GND
GND GND A1 GND GND GND K17 GND
GND GND A6 GND GND GND L1 GND
GND GND A11 GND GND GND L6 GND
GND GND A16 GND GND GND L11 GND
GND GND A21 GND GND GND L13 GND
GND GND A26 GND GND GND L15 GND
GND GND AA1 GND GND GND L21 GND
GND GND AA6 GND GND GND L26 GND
GND GND AA11 GND GND GND M12 GND
GND GND AA16 GND GND GND M14 GND
GND GND AA21 GND GND GND M16 GND
GND GND AA26 GND GND GND N3 GND
GND GND AD3 GND GND GND N8 GND
GND GND AD8 GND GND GND N11 GND
GND GND AD13 GND GND GND N15 GND
GND GND AD18 GND GND GND P12 GND
GND GND AD24 GND GND GND P16 GND
GND GND AF1 GND GND GND P19 GND
GND GND AF6 GND GND GND P24 GND
GND GND AF11 GND GND GND R11 GND
GND GND AF16 GND GND GND R13 GND
GND GND AF21 GND GND GND R15 GND
GND GND AF26 GND GND GND T1 GND
GND GND C3 GND GND GND T6 GND
GND GND C9 GND GND GND T12 GND
GND GND C14 GND GND GND T14 GND

126 www.xilinx.com DS529 (v2.1) December 18, 2018

 Pinout Descriptions

Table 86: Spartan-3A FG676 Pinout(Continued) Table 86: Spartan-3A FG676 Pinout(Continued)
FG676 FG676
Bank Pin Name Ball Type Bank Pin Name Ball Type
GND GND T16 GND VCCINT VCCINT M17 VCCINT
GND GND T21 GND VCCINT VCCINT N12 VCCINT
GND GND T26 GND VCCINT VCCINT N13 VCCINT
GND GND U10 GND VCCINT VCCINT N14 VCCINT
GND GND U13 GND VCCINT VCCINT N16 VCCINT
GND GND U17 GND VCCINT VCCINT P11 VCCINT
GND GND V3 GND VCCINT VCCINT P13 VCCINT
GND GND W8 GND VCCINT VCCINT P14 VCCINT
GND GND W14 GND VCCINT VCCINT P15 VCCINT
GND GND W19 GND VCCINT VCCINT R12 VCCINT
GND GND W24 GND VCCINT VCCINT R14 VCCINT
PWR VCCINT VCCINT R16 VCCINT
VCCAUX SUSPEND V20 MGMT
VCCINT VCCINT T11 VCCINT
VCCAUX DONE AB21 CONFIG
VCCINT VCCINT T13 VCCINT
VCCAUX PROG_B A2 CONFIG
VCCINT VCCINT T15 VCCINT
VCCAUX TCK A25 JTAG
VCCINT VCCINT U12 VCCINT
VCCAUX TDI G7 JTAG
VCCAUX TDO E23 JTAG
VCCAUX TMS D4 JTAG
VCCAUX VCCAUX AB5 VCCAUX
VCCAUX VCCAUX AB11 VCCAUX
VCCAUX VCCAUX AB22 VCCAUX
VCCAUX VCCAUX E5 VCCAUX
VCCAUX VCCAUX E16 VCCAUX
VCCAUX VCCAUX E22 VCCAUX
VCCAUX VCCAUX J18 VCCAUX
VCCAUX VCCAUX K13 VCCAUX
VCCAUX VCCAUX L5 VCCAUX
VCCAUX VCCAUX N10 VCCAUX
VCCAUX VCCAUX P17 VCCAUX
VCCAUX VCCAUX T22 VCCAUX
VCCAUX VCCAUX U14 VCCAUX
VCCAUX VCCAUX V9 VCCAUX
VCCINT VCCINT K15 VCCINT
VCCINT VCCINT L12 VCCINT
VCCINT VCCINT L14 VCCINT
VCCINT VCCINT L16 VCCINT
VCCINT VCCINT M11 VCCINT
VCCINT VCCINT M13 VCCINT
VCCINT VCCINT M15 VCCINT

DS529 (v2.1) December 18, 2018 www.xilinx.com 127

Pinout Descriptions

User I/Os by Bank

Table 87 indicates how the 502 available user-I/O pins are
distributed between the four I/O banks on the FG676
package. The AWAKE pin is counted as a dual-purpose I/O.

Table 87: User I/Os Per Bank for the XC3S1400A in the FG676 Package
All Possible I/O Pins by Type
Package
Edge I/O Bank Maximum I/O I/O INPUT DUAL VREF CLK
Top 0 120 82 20 1 9 8
Right 1 130 67 15 30 10 8
Bottom 2 120 67 14 21 10 8
Left 3 132 97 18 0 9 8
TOTAL 502 313 67 52 38 32

Footprint Migration Differences

The XC3S1400A FPGA is the only Spartan-3A device Table 88: FG676 Footprint Differences
offered in the FG676 package. However, Table 88
Pin Bank XC3S1400A Migration XC3SD1800A
summarizes footprint and functionality differences between
the XC3S1400A and the XC3SD1800A in the Spartan-3A A24 0 N.C.  INPUT
DSP family. There are 17 unconnected balls in the B24 0 N.C.  INPUT
XC3S1400A that become 16 input-only pins and one I/O pin
D5 0 N.C.  INPUT
in the XC3SD1800A. All other pins not listed in Table 88
unconditionally migrate between the Spartan-3A devices E6 0 N.C.  VREF (INPUT)
and the Spartan-3A DSP devices available in the FG676 E9 0 N.C.  INPUT
package. The arrows indicate the direction for easy
F9 0 N.C.  VREF (INPUT)
migration. For more details on the Spartan-3A DSP family
and pinouts, and additional differences in the FG676 pinout F18 0 N.C.  INPUT
for the XC3SD3400A device, see DS610. G18 0 N.C.  VREF (INPUT)
W18 2 N.C.  VREF (INPUT)
Y8 2 N.C.  VREF (INPUT)
Y18 2 N.C.  INPUT
Y19 2 N.C.  INPUT
AA8 2 N.C.  INPUT
AC5 2 N.C.  INPUT
AC22 2 N.C.  I/O
AD5 2 N.C.  INPUT
AD23 2 N.C.  VREF(INPUT)
DIFFERENCES 17
Legend:
 This pin can unconditionally migrate from the device on
the left to the device on the right. Migration in the other
direction is possible depending on how the pin is
configured for the device on the right.

128 www.xilinx.com DS529 (v2.1) December 18, 2018

 Pinout Descriptions

FG676 Footprint Bank 0

1 2 3 4 5 6 7 8 9 10 11 12 13
Left Half of FG676

_B
I/O I/O I/O I/O I/O I/O

G
A GND INPUT GND INPUT GND INPUT

O
L51P_0 L45P_0 L38P_0 L36P_0 L33P_0 L29P_0
Package (Top View)

PR
I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
B L02N_3 L02P_3 L51N_0 L45N_0
VCCO_0
L41P_0 L42P_0 L38N_0 L36N_0 L33N_0
VCCO_0
L29N_0
L28P_0
GCLK10

INPUT I/O
INPUT I/O I/O I/O I/O I/O I/O I/O
313 I/O: Unrestricted,
general-purpose user I/O
C L04N_3
VREF_3
L04P_3
GND INPUT
L44P_0 L41N_0 L42N_0 L40P_0
GND
L34P_0 L32P_0 L30N_0
L28N_0
GCLK11

N.C. I/O
INPUT INPUT I/O I/O INPUT I/O I/O I/O I/O
D TMS L32N_0 INPUT
67 INPUT: Unrestricted,
general-purpose input pin
L08N_3 L08P_3 L06P_3 L44N_0 VREF_0 L40N_0 L37N_0 L34N_0
VREF_0
L30P_0

I/O I/O I/O N.C. I/O N.C. I/O I/O

E L11P_3
VCCO_3
L07P_3 L06N_3
VCCAUX
L48N_0
VCCO_0
L37P_0
INPUT
L31P_0
VCCO_0

51 DUAL: Configuration pins,

then possible user I/O I/O N.C. I/O
I/O I/O I/O I/O I/O I/O
F GND
L11N_3 L14N_3 L07N_3 L09P_3
GND
L48P_0
L52P_0 INPUT GND
L31N_0
L27P_0
VREF_0 GCLK8
SUSPEND: Dedicated
SUSPEND and I/O I/O
2 dual-purpose AWAKE G
INPUT INPUT I/O I/O INPUT I/O
TDI L52N_0
I/O I/O INPUT I/O
L27N_0
L16N_3 L16P_3 L14P_3 L09N_3 L12P_3 L03P_3 L47P_0 L46P_0 VREF_0 L35P_0
PUDC_B GCLK9
Power Management pins
INPUT
I/O I/O I/O I/O I/O I/O I/O
H L17N_3 L17P_3
GND L12N_3 VCCO_3
L10N_3 L03N_3
GND
L47N_0 L46N_0
VCCO_0
L35N_0
INPUT

38 VREF: User I/O or input VREF_3

voltage reference for bank INPUT
INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O
J L24P_3
L20N_3
L20P_3 L19N_3 L19P_3 L13N_3 L10P_3 L01P_3 L01N_3
INPUT
L43P_0 L39P_0
INPUT
VREF_3
32 CLK: User I/O, input, or
clock buffer input INPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
K L24N_3 L23N_3 L23P_3 L22N_3 L22P_3 L18P_3 L13P_3 L05N_3 L05P_3
GND
L43N_0 L39N_0
VCCAUX

CONFIG: Dedicated
2 configuration pins I/O I/O I/O I/O I/O
L GND VCCO_3
L25N_3 L25P_3
VCCAUX GND
L18N_3
VCCO_3
L15N_3 L15P_3
GND VCCINT GND

JTAG: Dedicated JTAG I/O

4 port pins M L29N_3
I/O I/O I/O I/O I/O I/O I/O I/O I/O
VCCINT GND VCCINT
L29P_3 L27N_3 L27P_3 L28P_3 L28N_3 L26N_3 L26P_3 L21N_3 L21P_3
VREF_3

I/O I/O I/O

GND: Ground I/O I/O I/O I/O L35P_3
Bank 3

77 N L31P_3 L31N_3
GND
L30N_3 L30P_3
L32P_3 L32N_3 GND TRDY2
VCCAUX GND VCCINT VCCINT
LHCLK0 LHCLK1 LHCLK6

I/O I/O I/O I/O I/O

L33N_3 I/O I/O I/O I/O
P L33P_3 L34N_3 L34P_3 VCCO_3 L35N_3 VCCINT GND VCCINT
36 VCCO: Output voltage IRDY2 L39N_3 L39P_3 L41P_3 L41N_3
LHCLK2 LHCLK3 LHCLK5 LHCLK4 LHCLK7
supply for bank
I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
R L36P_3
L36N_3 L37P_3 L37N_3 L40P_3 L40N_3 L45N_3 L45P_3 L43N_3
L43P_3 GND VCCINT GND

23 VCCINT: Internal core VREF_3 VREF_3

supply voltage (+1.2V)

I/O I/O I/O I/O I/O I/O
T GND VCCO_3
L38P_3 L38N_3 L42P_3
GND
L51P_3
VCCO_3
L48N_3 L48P_3
VCCINT GND VCCINT

14 VCCAUX:
voltage
Auxiliary supply
I/O I/O INPUT I/O I/O I/O I/O I/O I/O I/O
U L44P_3 L44N_3 L46P_3 L42N_3 L49P_3 L51N_3 L56P_3 L56N_3 L61P_3
GND
L13N_2
VCCINT GND

17 N.C.: Not connected

◆
I/O I/O INPUT I/O I/O I/O I/O I/O I/O I/O I/O
V L47P_3 L47N_3
GND
L46N_3 L49N_3 L59N_3 L59P_3 L61N_3
VCCAUX
L09P_2 L13P_2 L16P_2 L20P_2

INPUT
INPUT I/O I/O I/O I/O I/O I/O I/O I/O
W L50P_3
L50N_3
L52P_3 L52N_3
VCCO_3
L63N_3 L63P_3
GND
L05P_2 L09N_2
VCCO_2
L16N_2 L20N_2
VREF_3

I/O N.C. I/O I/O

I/O I/O INPUT INPUT I/O I/O I/O I/O
Y L53P_3 L53N_3 L54P_3 L54N_3 L57P_3 L57N_3
L02P_2
L05N_2 L12P_2
INPUT L17P_2 L25N_2
M2 RDWR_B GCLK13

A INPUT I/O N.C. I/O I/O

I/O I/O INPUT INPUT I/O
GND L58N_3 GND L02N_2 GND L17N_2 L25P_2
A L55P_3 L55N_3 L58P_3 VREF_2 L12N_2
VREF_3 CSO_B VS2 GCLK12

A I/O INPUT INPUT INPUT I/O I/O INPUT I/O

VCCO_3 VCCAUX VCCO_2 VCCAUX INPUT
B L60P_3 L62P_3 L62N_3 VREF_2 L14N_2 L15P_2 VREF_2 L21P_2

A I/O N.C.
I/O I/O I/O I/O I/O I/O INPUT I/O I/O
L01P_2 INPUT INPUT
C L60N_3 L64P_3 L64N_3 L08P_2 L14P_2 L15N_2 VREF_2 L23N_2 L21N_2
M1

A I/O N.C.
I/O I/O I/O I/O I/O INPUT
GND L01N_2 GND INPUT INPUT GND
D L65P_3 L65N_3 L08N_2 L11P_2 L23P_2 VREF_2
M0

A INPUT I/O I/O I/O I/O

INPUT I/O I/O VCCO_2
I/O I/O I/O VCCO_2
L66N_3 L19P_2 L22P_2 L24N_2 L26N_2
E L66P_3 L06P_2 L07P_2 L10N_2 L11N_2 L18P_2
VREF_3 VS1 D7 D4 GCLK15

A I/O I/O I/O I/O

I/O I/O I/O I/O
GND INPUT GND INPUT L19N_2 L22N_2 GND L24P_2 L26P_2
F L06N_2 L07N_2 L10P_2 L18N_2
VS0 D6 D5 GCLK14

Bank 2 DS529-4_07_102506

Figure 27: FG676 Package Footprint (Top View)

DS529 (v2.1) December 18, 2018 www.xilinx.com 129

Pinout Descriptions

Bank 0
14 15 16 17 18 19 20 21 22 23 24 25 26
I/O
L26N_0
I/O
GND INPUT
I/O I/O I/O
GND
I/O
INPUT
N.C.
TCK GND A
Right Half of FG676
L23N_0 L18N_0 L15N_0 L14N_0 L07N_0
GCLK7 Package (Top View)
I/O I/O N.C. INPUT
I/O I/O I/O I/O I/O I/O INPUT
L26P_0
L23P_0
VCCO_0
L19N_0 L18P_0 L15P_0
L14P_0
L09N_0
VCCO_0
L07P_0 L65N_1
L65P_1 B
GCLK6 VREF_0 VREF_1

I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
GND
L22N_0 L21N_0 L19P_0 L17N_0
GND
L11N_0 L09P_0 L05N_0 L06N_0
GND L63N_1 L63P_1 C
A23 A22

INPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
VREF_0
INPUT
L22P_0 L21P_0 L17P_0
INPUT
L11P_0 L10N_0 L05P_0 L06P_0 L61N_1 L61P_1 L60N_1
D

I/O
I/O I/O I/O I/O I/O
L24P_0
L20N_0 VCCAUX
L13N_0
INPUT VCCO_0 INPUT
L10P_0
VCCAUX TDO
L56P_1
VCCO_1
L60P_1
E
VREF_0

N.C. I/O
I/O I/O I/O I/O I/O I/O I/O I/O
L24N_0 L20P_0
GND
L13P_0 L02N_0 L01N_0
GND L58P_1
L56N_1 L54N_1 L54P_1
GND F
VREF_1

N.C. I/O I/O INPUT

I/O I/O I/O I/O I/O I/O INPUT
INPUT
L16P_0
INPUT
L08N_0
L02P_0
L01P_0
L64N_1
L58N_1 L51P_1 L51N_1
L52N_1
L52P_1
G
VREF_0 A25 VREF_1

I/O I/O INPUT

I/O I/O INPUT INPUT INPUT
GND
L16N_0
VCCO_0
L08P_0
INPUT GND L64P_1 L62N_1 VCCO_1
L48P_1 L48N_1 L44N_1
L44P_1 H
A24 A21 VREF_1

I/O I/O I/O I/O

I/O INPUT I/O I/O I/O I/O
L25N_0 INPUT
L12P_0 VREF_0
VCCAUX
L59P_1 L59N_1
L62P_1
L49N_1 L49P_1
GND L43N_1 L43P_1 J
GCLK5 A20 A19 A18

I/O
I/O I/O I/O I/O I/O I/O I/O INPUT I/O I/O
L25P_0 VCCINT
L12N_0
GND
L57N_1 L57P_1 L53N_1 L50N_1 L46N_1 L46P_1 L40P_1 L41P_1 L41N_1
K
GCLK4

I/O
I/O I/O I/O I/O INPUT
VCCINT GND VCCINT
L55N_1 L55P_1
VCCO_1
L53P_1
GND
L50P_1 L40N_1
L38P_1 VCCO_1 GND L
A12

I/O I/O INPUT I/O I/O

I/O I/O I/O I/O
GND VCCINT GND VCCINT
L47N_1 L47P_1
L42N_1
L45P_1 L45N_1
L38N_1 L36P_1 L35N_1 L35P_1 M
A17 A13 VREF_1 A11 A10

I/O I/O I/O I/O I/O

I/O INPUT INPUT INPUT
Bank 1
VCCINT GND VCCINT L39N_1 L39P_1 L34N_1 L42P_1
L37N_1
VCCO_1
L36N_1
L33N_1
L32N_1 L32P_1
N
A15 A14 RHCLK7 A16 RHCLK5

I/O I/O I/O I/O I/O I/O

L34P_1 I/O L31N_1
VCCINT VCCINT GND VCCAUX
IRDY1 GND L30N_1 L30P_1
L37P_1
L33P_1 GND TRDY1 L31P_1 P
RHCLK6 RHCLK1 RHCLK0 RHCLK4 RHCLK3 RHCLK2

I/O I/O I/O I/O INPUT I/O I/O

I/O I/O INPUT
VCCINT GND VCCINT L27N_1 L27P_1
L22P_1 L22N_1
L25P_1 L25N_1 L28P_1
L28N_1
L29P_1 L29N_1 R
A7 A6 A2 A3 VREF_1 A8 A9

I/O I/O
I/O I/O I/O
GND VCCINT GND
L17N_1 L17P_1
VCCO_1
L14N_1
GND VCCAUX L26P_1 L26N_1 VCCO_1 GND T
A4 A5

I/O INPUT
I/O I/O I/O I/O I/O I/O I/O I/O INPUT
VCCAUX
L35N_2 L42N_2
GND
L12N_1 L12P_1 L10N_1 L14P_1 L21N_1 L23P_1
L23N_1
L24P_1
L24N_1 U
VREF_1 VREF_1
D

INPUT
EN

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
L20N_1 V
SP

L31P_2 L35P_2 L42P_2 L46N_2 L08P_1 L08N_1 L10P_1 L18N_1 L21P_1 L19P_1 L19N_1
VREF_1
SU

I/O I/O N.C. I/O I/O I/O INPUT INPUT

GND
L31N_2
VCCO_2
L46P_2
GND
L04P_1 L04N_1
VCCO_1
L18P_1
GND
L16P_1 L20P_1
W

I/O I/O INPUT N.C. N.C. I/O I/O

I/O I/O I/O I/O I/O INPUT
L27P_2 L34N_2 2
L43N_2
L01P_1 L01N_1
L13P_1 L13N_1 L15P_1 L15N_1 L16N_1
Y
GCLK0 D3 VREF_2 HDC LDC2

I/O I/O A
I/O I/O INPUT I/O I/O I/O I/O
L27N_2 L34P_2 GND INPUT GND GND
L43P_2 L47N_2 VREF_2 L09P_1 L09N_1 L11P_1 L11N_1 A
GCLK1 INIT_B

I/O I/O
L30N_2 I/O I/O I/O I/O A
VCCO_2
MOSI INPUT VCCO_2 INPUT DONE VCCAUX L07N_1 VCCO_1
L38N_2 L47P_2 L07P_1 L06N_1 B
CSI_B VREF_1

N.C. I/O I/O A

I/O I/O I/O I/O I/O I/O I/O I/O
INPUT INPUT L03P_1 L03N_1
L29N_2 L30P_2 L38P_2 L40N_2 L41N_2 L45N_2 L05N_1 L06P_1 C
A0 A1

I/O N.C. I/O A

I/O I/O I/O I/O I/O I/O I/O
L32P_2 INPUT GND GND L02N_1
L29P_2 L33N_2 L40P_2 L41P_2 L44N_2 L45P_2 L05P_1 D
AWAKE LDC0

I/O I/O I/O I/O I/O A

VCCO_2
I/O I/O I/O I/O VCCO_2
I/O I/O
L28N_2 L32N_2 L36N_2 L52N_2 L02P_1
L33P_2 L37N_2 L39N_2 L44P_2 L48N_2 L51N_2 E
GCLK3 DOUT D1 CCLK LDC1

I/O I/O I/O

INPUT INPUT I/O I/O INPUT I/O L52P_2 I/O A
L28P_2 GND L36P_2 GND D0 GND
VREF_2 VREF_2 L37P_2 L39P_2 VREF_2 L48P_2 L51P_2 F
GCLK2 D2 DIN/MISO

Bank 2 DS529-4_08_012009

130 www.xilinx.com DS529 (v2.1) December 18, 2018

 Pinout Descriptions

Revision History
The following table shows the revision history for this document.

Date Version Revision

12/05/06 1.0 Initial release.
02/02/07 1.1 Promoted to Preliminary status. Added DOUT pin to DUAL-type pins in Table 57. Corrected counts for
DUAL pins and differential pairs in Table 59. Corrected minor typographical error on pin names for pin
numbers P24 and P25 in Table 65. Highlighted the differences in differential I/O pairs between the
XC3S50A and XC3S200A in the FT256 package, shown in Table 67 and added Table 73 and Table 74
to summarize the differences.
03/16/07 1.2 Corrected minor typographical error in Figure 19.
04/23/07 1.3 Added reference to compatible Spartan-3A DSP family.
05/08/07 1.4 Added note regarding banking rules.
07/10/07 1.5 Updated Thermal Characteristics in Table 61.
04/15/08 1.6 Added VQ100 for XC3S50A and XC3S200A and added FT256 for XC3S700A and XCS1400A to
Table 58, Table 59, and Table 61. Updated Thermal Characteristics with latest data in Table 61.
Corrected bank for T8 and type for U16 in Table 85. Removed VREF name on 6 unconnected N.C. pins
for XC3S1400A FG676 in Table 86 and Figure 27. These pins are noted as VREF if migrating up to the
XC3SD1800A in Table 88.
05/28/08 1.7 Added "Package Overview" section.
03/06/09 1.8 Corrected bank designation for SUSPEND to VCCAUX. Corrected bank designation for JTAG pins in
XC3S700A and XC3S1400A FT256 to VCCAUX.
08/19/10 2.0 Corrected pin 36 number in Figure 17 and Figure 18. Noted difference in FT256 P10/T10 function
between XC3S50A and larger devices in Table 67 and Table 73.
12/18/18 2.1 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).
Updated Table 60 and Note 1. Removed Table 61.

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