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QP DLD Midtest

This document provides instructions and questions for a mid-term exam on network analysis. It contains 6 questions with multiple parts each. Students are instructed to attempt one question from each pair, and to show diagrams where necessary. Questions cover topics like combinational logic circuits, sequential circuits, flip-flops, counters, and VHDL modeling.

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Vinod Jagdale
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30 views1 page

QP DLD Midtest

This document provides instructions and questions for a mid-term exam on network analysis. It contains 6 questions with multiple parts each. Students are instructed to attempt one question from each pair, and to show diagrams where necessary. Questions cover topics like combinational logic circuits, sequential circuits, flip-flops, counters, and VHDL modeling.

Uploaded by

Vinod Jagdale
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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FRM/ENG/12

Rev. No. 00
Total No. of Questions: 06] [Total No. of Printed Pages: 01

Navsahyadri Education Societies Group of institution’s

Faculty of Engineering

S.E. (E & TC- SEM-I) MID-TEST (2010-2011)

NETWORK ANALYSIS

Time: 2 hours] [Max. Marks: 50


Instructions:
1) ATTEMPT ONE QUESTIONS EACH FROM THE PAIRS .
2) FIGURES TO THE RIGHT INDICATE FULL MARKS .
3) NEAT DIAGRAMS MUST BE DRAWN WHEREVER NECESSARY .
4) USE OF NON-PROGRAMMABLE SCIENTIFIC CALCULATOR IS ALLOWED.
5) ASSUME SUITABLE DATA , IF ANY .

Q.1) (A) Using Tabular Method , obtain the minimal expression for :
[10M]
F =∑ m (6, 7, 8, 9) + d (10, 11, 12, 13, 14, 15).
(B) Design a combinational circuit to produce the 2’s complement of a
[08M]
4-bit binary number as a input.
OR
Q.2) (A) Design a combinational logic circuit to generate an odd parity bit
[06M]
for a 4-bit input.
(B) Use a multiplexer to implement the logic function F= A ʘ B ʘ C [06M]
(C) Design a full adder using 3:8 decoder and NAND gates. [06M]

Q.3) (A) Explain the difference between combinational & sequential


[08M]
circuits. Also convert JK flip-flop into D flip-flop & T flip-flop
(B) Design & implement MOD-10 asynchronous counter using T- flip-
[08M]
flops.
OR
Q.4) (A) Draw & explain the block diagram of sequential logic circuit, also
give the comparison between synchronous & asynchronous [08M]
sequential logic circuits.
(B) What is meant by asynchronous inputs of flip-flop? Explain the
[08M]
operation of J-K flip-flop having preset & clear input.

Q.5) (A) Compare ‘If’ and ‘case’ statements. Write down the VHDL code
[08M]
for 4:1 MUX. (Use behavioral modeling).
(B) Write down the VHDL code for negative edge triggered JK flip-
[08M]
flop having preset & clear input.
OR
Q.6) (A) Write a VHDL code for D- flip-flop using synchronous &
[08M]
asynchronous reset input.
(B) What is difference between sequential & concurrent statements? [04M]
(C) What is VHDL? Write entity & architecture declaration for two
[04M]
input NAND gate.

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