Implementation and Testing of Optimal Design of RTU

Hardware for Wireless SCADA

Muhammad Aamir1, Muhammad Aslam Uqaili2, Javier Poncela3, Nishat Ahmad Khan4,
B.S.Chowdhry2
1
Sir Syed University of Engineering & Technology, Karachi. Pakistan and
Mehran University of Engineering & Technology, Jamshoro, Pakistan
2
Mehran University of Engineering & Technology, Jamshoro, Pakistan
3
ETSI Telecommunication Engineering, University of Malaga, Spain
4
Advanced Engineering & Research Organization, Karachi, Pakistan

{[email protected], [email protected], [email protected],

[email protected], [email protected]}

Abstract--- Design of an optimal Remote Terminal Unit control. In contrast to PLCs, additional hardware features such
(RTU) is a key step in implementation of Wireless SCADA. as integrated power supply with backup battery support;
This paper presents Implementation and Testing of an master control element, process and communication elements,
RTU design which is suitable for wide area operation peripheral elements and diagnostic displays make it more
essential for controlling and monitoring oil and gas sector,
powerful than PLCs. A generalized structural design of an
water and power industries. This particular
implementation is based on FPGA which has resulted in RTU is depicted in Fig.1.
reliable and reconfigurable RTU. It has significant
advantages resulting in a more powerful and optimized
solution for execution of wireless based SCADA. The main CIM
objective of this research work is to implement and verify
(Communication Interface module)
a design considering performance parameters which
assists in optimized development and inexpensive
implementation of an RTU, also featured with wireless
communication.
Command and
Keywords— Supervisory Control and Data Acquisition Data Bus
(SCADA), Remote Terminal Unit (RTU), Field
Programmable Gate Array (FPGA), Communication
Interface Module, hardware description language.
Digital Digital
I. INTRODUCTION Analog
Input Output
Input
(DI) (DO)
(AI)
To understand RTU, a general scenario of SCADA based
energy management is being discussed first. For applications
like energy management (either by means of smart grids or
conventional grids) and mass transit where it used to regulate
electricity to subways, trams and trolley buses. In all cases
described above, the design of SCADA system for significant
applications like energy management systems. This is highly
desired to achieve distribution of electricity in smooth manner Field Sensors Actuators
[1]. SCADA is a short form for Supervisory Control and Data
Acquisition.
Fig. 1. Structural Design of a Remote Terminal Unit (RTU)
SCADA systems generally consist of one or more Remote
Terminal Units (RTUs) which are also termed as field data
interface devices. A communications system (means of Reference to Fig.1, a generalized structure of an RTU includes
telemetry), a central host computer server or collection of Digital and Analog Input modules, Digital output modules and
server termed as Central Monitoring Station (CMS) and a a communication Interface module. The basic functionality of
collection of Human Machine Interface (HMI) software [2]. an RTU can be implemented using above mentioned modules.
Remote Terminal Units (RTUs) are employed as remote These modules are used as reference for intended design
field data interface appliances. However, this sought of approaches of implementing RTUs using FPGAs [5] and PLCs.
appliance may include a Programmable Logic Controller [3, 4] Field sensors can be interfaced with Input modules depending
to function as traditional classification of automated upon their type whereas Actuators can be operated by
programming. Similar to a PLC, the RTU operates at the interfacing them with Digital Output Module. The
desired remote location as a major appliance of a SCADA Communication Interface Module is capable of sending data
system implemented for either equipment monitoring or
from the RTU to the SCADA centre utilizing several means of System Specifications deals with architectural part of the
telemetry. design at highest level possible. The performance of the FPGA
A basic design of an RTU is elaborated in this introductory based RTU is being stated.
section. The same or more powerful RTU in terms of features An electronic system level design involves subdividing the
is being implemented and tested using an FPGA. The system into hardware and software. This subdivision consists
developed RTU can be used in wireless SCADA. of co-design and co-simulation of the hardware and software
components.
II. PHASES OF RTU IMPLEMENTATION USING At the end of the Register Transfer Level Design, the logic
FPGA circuit will be available in terms of gates and memories. The
The hardware implementation and verification of this output of RTL is Gate Level Logic Design.
RTU design is done using a development kit based on XILINX
Floor Planning
Spartan-3 Series FPGA with 500K logic gates. [6]
For simplicity of implementation, a conceptual view of
reduced design containing 8 Digital Inputs and 4 Channel is
presented in Fig.2. The optimized design has significant Placement
advantages over conventional or PLC based RTUs.

Routing

Extraction and
Verification

Fig.3 (b) Typical Physical Design Flow

Physical design then completes technology-specific

Fig.2. A conceptual view of RTU board implemented using
partitioning, floor planning, placement, and routing for the
FPGA
design.
Placement and Routing involves laying of the devices,
The design hierarchy and typical physical design flow are placing them and making interconnection between them
simplified in the form of following figure. 3(a) and 3(b). according to the Design Rules.
Extraction would extract from the layout, the devices
System Specifications/ formed because of junctions of different semiconductor
Requirements and metal layers and the interconnections. As FGPA is
being used as the main processors so this extraction step
has little practical value for our scenario.
System Level Electronic The verification phase verifies the implemented design
Design
view of the chip for performance and functionality.

In this particular implementation, it already determined that

Register Transfer Level
Design functionality of RTU is just limited to 32 I/Os.

The next section will describe implementation of scenario and

Gate Level Logical Design
same will be tested using prototype.

III. PROTOTYPE TESTING USING SELECTED

Transistor Level Physical SCENARIO
Design
As described earlier, hardware implementation and
verification of this RTU design is done using a development
kit based on XILINX Spartan-3 Series FPGA with 500K logic
Fig.3 (a) Design Hierarchy implementing RTU using FPGA
gates.
 Phases described in the previous section implemented and (e) Reasons Why Prototyping is Important
resulted in the following resource utilization statistics which
are being presented in the form of tables and diagrams. • Running a System on Chip (SOC) design on FPGA
prototype is a certain way to ensure that it is
functionally correct. This compares with designers
who rely solely on software simulations to verify that
(a) Device Utilization Summary:
hardware design is sound. Simulation speed and
Device Availability in
Spartan-3E
Utilized in
testing
Percentage
Utilization
modeling accuracy limitation may prevent this
Number of Slices 4656 149 3 development. [7]
Slice Flip Flops 9312 144 1 • FPGA Prototyping allows much more time in the area
4 input LUTs 9312 276 2
Number used as 17 of software development and testing at the integration
logic
Shift registers 36
of software - hardware. This allows many unexpected
RAMs 68 software errors that appear due to the current variety
Inputs/Outputs
Bonded IOBs 158
8
8 5
of operating systems, applications and hardware. [8]
BRAM 20 1 5 • Prototyping also allows the developer to ensure that
GCLKs 24 1 4
all your system IP technologies work well together
offstage simulation and real way.
HDL Synthesis Report • Prototyping has the added advantage as
Macro Statistics: demonstration platforms to customers of SOC, which
Total Counters :3 in early interest. This speeds up the development
9-bit up counter :3
Total Registers : 15 cycle and allows greater overall in the characteristics
1-bit register :9 of chips
4-bit register :3
8-bit register :3
# Multiplexers :3 (f) Proposed Prototype Block Diagram
4 to 1 line multiplexer (8 bit) :1

(b) Advanced HDL Synthesis Report

Macro Statistics
Counters :1
9-bit up counter :1
# Registers : 135
Flip-Flops : 135
# Multiplexers :1
8-bit 4-to-1 multiplexer :1

(c) Final Register Report

Macro Statistics
# Registers : 144
Flip-Flops : 144
Fig.5. Proposed experimental setup for prototype testing
The features of proposed experimental setup for prototype
(d) Placement and Routing testing are being discussed in the next.
It involves laying of the devices, placing them and making
interconnection between them by following the Design Rules. IV. FEATURES OF DEVELOPED RTU
Placement and Routing. Placement and routing diagram for
our scenario is being presented in fig. 4. Hardware
y Xilinx FPGA Spartan 3E
y Temperature and Humidity sensor module (TH01)
y IR Sensor for proximity sensing
y HMTR-3-232 Transceiver for ISM band
y Light Dependant Resistor
y Load devices like Fans and Lights

Software
y Xilinx ISE WebPack Latest Version
y ModelSim for Design Simulation.
Fig.4. Placement, routing and mapping using FPGA
y VHDL/Verilog Language Basics. The FPGA based design provides flexibility in terms of
y Create designs using VHDL/Verilog. I/Os, CPU and radio related configurations. It resulted in
y Create designs using Schematics. focused performance and expansion can be accommodated
quickly if needed.
y Synthesize Designs.
More intelligence is added to the power management aspect
y Using PACE to define Pin Locations. resulting in optimized alarm.
y Using ImPACT to Configure and Download The industrial temperature range of Spartan-3 FPGA is -
40°C to 100°C which is wide to withstand in harsh
environment. The same temperature may be offered by a
(g) Features of Xilinx FPGA Starter Kits high end performance PLC but it will have much higher
cost as compared to any CPU of Siemens S7-200 family
• Spartan-3 FPGA. selected here to make this comparison. It also supports third
generation (Networked Approach) SCADA. [10]
• Complete, Low Cost FPGA Prototyping.
• Xilinx Platform Flash configuration PROM. A view of GUI which is related with functionality of
• Ethernet Interface (requires MAC in FPGA). system described in fig.8. is presented here as an example
which was significantly used in prototype testing.
• Nine-pin RS232 (DTE and DCE-style).
• Miscellaneous: 8xLEDs, 4xswitches, 4xpush-button,
PS/2, Expansion Connectors, auxiliary Clock Socket.

Fig. 6. SPARTAN 3-E

The flow diagram of whole development in fig.7, shows

indigenous development of FPGA based RTU which is Fig.8. A view of GUI developed for Prototype Testing
significantly economical as compared with similar
available hardware in the international market.[9] V. CONCLUSION

The developed RTU is highly reliable and can be

implemented at a relatively low cost as compared with
commercially available RTUs. The commercially
available RTUs with similar configuration are available at
higher prices say starting from 4000 Euros per unit but the
same RTU can be developed as low as 400 Euros per unit
so this low cost RTU design may get considerable
appreciation. With available interfaces for telemetry, the
developed RTU has also become a valuable candidate to
be incorporated in Wireless based SCADA systems.

REFERENCES

[1] Stuart A.Buyer, SCADA: Supervisory Control and

Data Acquisition, 4th Edition, North Carolina: ISA, 2010,
pp. 9-21.
[2] Mahmood, A.; Aamir, M.; Anis, M.I., "Design and
implementation of AMR Smart Grid System," Electric
Fig. 7. Flow Diagram of RTU Development
Power Conference, 2008. EPEC 2008. IEEE Canada ,
vol., no., pp.1,6.
[3] W.Bolton, Programmable Logic Controllers, 5th
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[7] White paper on SCADA produced by Motorola, 2007.
[8] Wayne C. Turner and Steve Doty, “Energy
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[9] Aamir, M.; Mahmood, A., "Performance analysis of
wide area operation, control and protection using high
scale SCADA system," Electric Power Conference, 2008.
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