Introduction to Digital Circuits

Module: SE1EB5 Computer and Internet Technologies

Lecturer: James Grimbleby

URL: http://www.elec.rdg.ac.uk/jbg.html
email: j.b.grimbleby reading.ac.uk

Number of Lectures: 10

Recommended text book:

Alan Clements:
The Principles of Computer Hardware (3rd edition)
Oxford University Press 1999
ISBN 019856453-8

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 1

 Introduction to Digital Circuits

Price: £25 (approx)

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 2
 Engine Management System

Engine Speed Security Device

Crank Angle

λ Sensor

Throttle Injectors

Knock detection Ignition

Air Temperature Valve Timing

Block Temperature Warning Indicators

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 3

 Syllabus

Analogue vs digital; binary codes; error-detecting and

error-correcting codes; Hamming distance

Boolean algebra; operations NOT, AND, OR; truth tables;

Boolean identities and theorems; Boolean functions; Logic
gates; combinational logic systems; analysis of
combinational systems; duality

Karnaugh maps; Boolean simplification using K-maps;

sum-of-products and product-of-sums forms; incompletely-
specified Boolean functions; implementation using logic
gates

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 4

 Syllabus

Universal logic gates; simple implementation method;

formal method for NAND implementation; formal method
for NOR implementation

Hazards in combinational logic systems; static and

dynamic hazards; origin of static hazards in 2-level NAND
systems; origin of dynamic hazards; design of hazard-free
NAND and NOR systems

Other types of logic gate: EXOR gates; MSI combinational

functions: 7-segment, decoders and encoders,
multiplexers; programmable logic

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 5

 Syllabus

Sequential logic systems; RS Flip-flops; D-latch; edge-

triggered flip-flops; edge-triggered D-type flip-flop

Asynchronous counters; synchronous counters; shift

registers; design of synchronous counters using edge-
triggered D-type flip-flops

Edge-triggered JK flip-flops; asynchronous counters, shift

registers

Types of logic gate: TTL + variants, CMOS, ECL;

comparisons of gate types; decoupling.

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 6

 Analogue vs Digital
Analogue signals represent physical quantities by a
simple proportional relationship

The precision of analogue signals is limited by noise/drift

relative to the maximum signal and by non-linearity

Digital signals use numbers to represent physical

quantities

There is in principle no limit to the precision of digital

signals

Digital systems use binary numbers, rather than decimal,

to define digital values

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 7

 Binary Codes

Digital electronics uses binary values: 0 or 1

These are represented in digital circuits by voltages or

currents, for example:

Logic 0: 0 V Æ 0.8 V
Logic 1: 2.0 V Æ 5.0 V

Binary digits are called bits

Bits are normally processed in groups: a group of binary

digits is called a binary word, or more simply, a word

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 8

 Binary Codes
Digital words can be transmitted / processed in serial or
parallel form:

5-bit word - serial data 11010:

1 1 0 1 0

5-bit word - parallel data 11010:

1
1
0
1
0
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 9
 Binary Codes
Words represent information by the use of binary codes

Examples of binary codes:

Natural binary code

Signed binary code
Floating-point codes
Gray code
Alpha-numeric codes

Extra bits can be added to any of these codes to make

them error-detecting or error-correcting

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 10

 Natural Binary Code
An n-bit word:
dn-1, … d2, d1, d0

where dr are the individual bits (value 0 or 1), represents

the positive integer value:

2n-1dn-1 + … + 22d2 + 21d1 + 20d0

So the 6-bit natural binary word 010110 represents the

integer value:

25.0 + 24.1 + 23.0 + 22.1 + 21.1 + 20.0

= 16 + 4 + 2 = 22

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 11

 Natural Binary Code
Natural binary is the most efficient code in the sense that is
uses the minimum number of bits

It is easy to perform arithmetic operations on natural binary

code

8-bit natural binary code represents: 0 Æ 255

16-bit natural binary code represents: 0 Æ 65535

32-bit natural binary code represents: 0 Æ 4295M

In general an n-bit natural binary code represents: 0 Æ (2n-1)

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 12

 4-Bit Natural Binary Code

Natural Natural
Decimal binary Decimal binary
0 0000 8 1000
1 0001 9 1001
2 0010 10 1010
3 0011 11 1011
4 0100 12 1100
5 0101 13 1101
6 0110 14 1110
7 0111 15 1111

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 13

 Signed Binary Code

In many applications it is necessary to represent negative

as well as positive numbers

For example: audio signals, bank account

The most common (and most satisfactory) representation

for signed integers is 2s-complement binary

The operations required to add or subtract 2s-complement

numbers are identical to those for natural binary

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 14

 2s-Complement Binary Code
To obtain the 2s-complement representation of a negative
number:

1. Obtain natural binary representation of its magnitude

2. Complement (0 Æ 1, 1 Æ 0)

3. Add 1

Example: -5
Natural binary 000101 5
Complement 111010
Add 1 111011 -5

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 15

 2s-Complement Binary Code

The sign of a 2s-complement number is determined by the

most-significant (left-most) bit

8-bit signed binary code represents: -128 Æ +127

16-bit signed binary code represents: -32768 Æ +32767

32-bit signed binary code represents: -2147M Æ +2147M

n-bit signed binary code represents: -2n-1 Æ +(2n-1-1)

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 16

 Hamming Distance

The Hamming distance between two code words is the

number of bits that must change to convert one code word
into the other

10110011
Hamming distance = 2
10011011

The minimum distance of a code is the minimum Hamming

distance between any pair of words belonging to the code

An n-distance code is a code sequence where the Hamming

distance between consecutive code words is n

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 17

 Gray Code
Digital position transducer coded using natural binary:

Infra-red detectors (×4)

Infra-red emitters (×4)

Clear
8
4
2
1

Position = 1001 (binary) = 8 + 1 (decimal) = 9

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 18

 Gray Code
This should work in principle, but fails in practice because
the bits do not change simultaneously:

8 0 0 1 1 1
4 1 0 0 0 0
2 1 1 1 1 0
1 1 1 1 0 0
Indicated position: 7 3 11 10 8

Thus spurious positions of 3, 11, and 10 are generated

between 7 and 8

This problem is overcome by using Gray code

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 19

 4-Bit Gray Code

Gray Gray
Decimal code Decimal code
0 0000 8 1100
1 0001 9 1101
2 0011 10 1111
3 0010 11 1110
4 0110 12 1010
5 0111 13 1011
6 0101 14 1001
7 0100 15 1000

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 20

 Gray Code
Digital position transducer coded using Gray code (unit-
distant):
Infra-red detectors (×4)

Infra-red emitters (×4)

Clear

Position = 1101 = 9

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 21

 Alpha-Numeric Codes

ASCII (American Standard Code for Information

Interchange) is a 7-bit code representing alpha-numeric
characters

The code includes control characters, punctuation, symbols,

digits, letters:
0000000: nul 0001101: cr
0011011: esc 0101011: +
0110000: 0 0111001: 9
1000001: A 1011010: Z
1100001: a 1111010: z
1111111: del

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 22

 Error-Detecting Codes

An extra bit added to each binary word allows single errors

to be detected (but not corrected)

This bit is called the parity bit and is chosen to make the
total number of 1s even (even parity) or odd (odd parity)

A single error will lead to the number of 1s changing from

odd to even, or from even to odd; the change in parity then
indicates an error

Parity codes are redundant, and have a minimum Hamming

distance of 2

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 23

 Error-Detecting Codes
Error-detecting codes have a minimum Hamming distance of 2:

Valid codeword Valid codeword

Invalid codeword
(I bit error)

1 bit 2 bits

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 24

 Natural Binary Code / Even Parity

Even Even
Decimal Parity Decimal Parity
0 00000 8 11000
1 10001 9 01001
2 10010 10 01010
3 00011 11 11011
4 10100 12 01100
5 00101 13 11101
6 00110 14 11110
7 10111 15 01111

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 25

 Natural Binary Code / Odd Parity

Odd Odd
Decimal Parity Decimal Parity
0 10000 8 01000
1 00001 9 11001
2 00010 10 11010
3 10011 11 01011
4 00100 12 11100
5 10101 13 01101
6 10110 14 01110
7 00111 15 11111

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 26

 Error-Correcting Codes

Error-detecting codes are of little value in 1-way

communications systems (cannot be corrected)

If a single bit error occurs in a code with a minimum distance

of 3 or greater then the error can be both detected and
corrected

This is because the single error generates a new word which

is distance 1 from the original word; it is still distance 2 from
any other code word

Sometimes called “forward error correction”

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 27

 Error-Correcting Codes
Error-correcting code with minimum Hamming distance of 3:

Valid codeword Valid codeword

Invalid codeword
(I bit error)

1 bit 3 bits
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 28
 Error-Correcting Codes
Error-correcting code with minimum Hamming distance of 5:

Valid codeword Valid codeword

Invalid codeword
(2 bits error)

1 bit 5 bits
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 29
 Error-Correcting Codes

Decimal E-C code Decimal E-C code

0 000000 4 101100
1 011001 5 110101
2 110010 6 011110
3 101011 7 000111

Right-most 3 bits are natural binary, left-most 3 bits are

error-correction

Example: 110110 is not a valid codeword

Nearest valid codeword is 110010 (decimal 2)

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 30

 Error-Correcting Codes

This deliberately-damaged CD can be read without errors

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 31
 Boolean Algebra

Boolean algebra is an algebra of 2-state variables

Boolean variables can have the values 0 or 1

Boolean Algebra is used to describe digital systems

where the binary signals have 2 values

There are three fundamental operations in Boolean

algebra: NOT, AND, OR

These are defined by the use of truth tables

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 32

 Boolean Algebra

NOT A or A or A′ A A
0 1
1 0

A AND B or A.B A B A.B

0 0 0
0 1 0
1 0 0
1 1 1

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 33

 Boolean Algebra

A OR B or A+B A B A+B
0 0 0
0 1 1
1 0 1
1 1 1

There are other Boolean operators such as ⊕ (exclusive

OR) and ⇒ (implies), but these can be written in terms of
the operators NOT, AND, OR:

A ⊕ B ≡ A.B + A.B

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 34

 Boolean Algebra
The operations of AND and OR obey the usual laws of
algebra:

Associative laws: A.(B.C ) ≡ ( A.B).C

A + ( B + C ) ≡ ( A + B) + C

A.B ≡ B.A
Commutative laws:
A+B ≡ B+ A

A.(B + C ) ≡ A.B + A.C

Distributive laws:
A + (B.C ) ≡ ( A + B).( A + C )

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 35

 Proof: A.(B+C) ≡ A.B + A.C

A B C B+C A.(B+C) A.B A.C A.B+A.C

0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1
A.(B+C) = A.B + A.C for all combinations of the variables:
thus A.(B+C) ≡ A.B + A.C

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 36

 Boolean Identities

A number of other identities follow from the definitions of

NOT, AND, OR:

A+0 ≡ A A.0 ≡ 0
A + 1≡ 1 A.1 ≡ A
A+ A≡ A A.A ≡ A
A+ A≡1 A.A ≡ 0

Theorems of DeMorgan: A.B ≡ A + B

A + B ≡ A.B

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 37

 Proof of DeMorgan’s Theorems

A B A.B A.B A B A+B

0 0 0 1 1 1 1
0 1 0 1 1 0 1
1 0 0 1 0 1 1
1 1 1 0 0 0 0

A B A+B A+B A B A. B
0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 38

 Boolean Functions

There is no unique form for a Boolean algebraic

expression. Consider the function:

F = A.(B + C + B.C ) + A.B.(C + D )

By "multiplying out" the brackets and using DeMorgan’s
Theorems:
F = A.B + A.C + A.B.C + A.B.C.D

This is the sum-of-products standard form. An alternative

standard form is the product-of-sums:

F = ( A + B).( A + B + D ).( A + B + C )

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 39

 Algebraic Manipulation of
Boolean Functions
Some simplification can be achieved by multiplying out
brackets and using Boolean identities (including
DeMorgan’s theorems):
F = A + C.D + A.B + ((C.D ) + A)
= A + C.D + A.B + (C + D + A)
= A + C.D + A.B + C.D.A
= A.(1 + B) + C.D.(1 + A)
= A.1 + C.D.1
= A + C.D
This is the simplest sum-of-products form for F
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 40
 Algebraic Manipulation of
Boolean Functions
This process does not guarantee to produce the simplest
sum-of-products form

Consider the function:

F = X .Y + X .Z + Y .Z
There is no obvious way of simplifying this function
algebraically. Nevertheless, the simplest form of the
function is:
F = X .Y + X .Z
Graphical methods for obtaining the simplest form will be
discussed later
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 41
 Switch Logic

F = A.B.C F = A+ B+C

F = A.B.(C + D )

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 42

 Logic Gates
Binary signals are processed in electronic digital systems by
logic gates:
A A
NOT
A A
B A.B.C B A.B.C
C C
AND NAND

A A
B A+ B+C B A+ B+C
C C
OR NOR

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 43

 Logic Gates

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 44

 Logic Gates

Through-hole

Surface-
mount

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 45

 Logic Signals
Binary values are normally represented by voltages. For
example in HCT logic:
Outputs: Inputs:
5.0 V 5.0 V
Logic 1
2.4 V
2.0 V
0.55 V 0.8 V
Logic 0
0.0 V 0.0 V
Noise immunity: Logic 0 = 0.25 V
Logic 1 = 0.4 V

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 46

 Combinational Logic Systems

Systems of logic gates where there is no feedback are

called combinational logic systems

Combinational logic systems have the property that the

output or outputs depend only on the present state of the
inputs

Combinational systems can therefore be specified by a

Boolean expression.

Logic systems with feedback have the property of memory

and cannot be specified by a single Boolean expression.

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 47

 Combinational Logic Systems
A
B A.B.(C + D )
C
D C+D F
B .C A

A.(B + C + B.C )
B + C + B.C

This combinational system implements the Boolean

function:
F = A.(B + C + B.C ) + A.B.(C + D )

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 48

 Duality

A Boolean equation remains valid when converted to its

dual by changing all variables and constants to their
inverses, and replacing AND by OR, and OR by AND

For example if: F = A.(B + C + B.C ) + A.B.(C + D )

or: F = { A.(B + C + {B.C })} + { A.B.(C + D )}

then: F = { A + (B.C.{B + C })}.{ A + B + (C.D)}

or: F = { A + B.C.{B + C }}.{ A + B + C.D }

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 49

 Karnaugh Maps

Karnaugh maps (or K-maps) are graphical representations

of Boolean functions and are used to simplify Boolean
expressions

A K-map has one square for each combination of values

of the variables

1-variable K-Map:

A=0 1
F = A
A=1 0

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 50

 Karnaugh Maps
2-variable K-map:
B=0 B=1
A=0 1 1
F = A+B
A=1 0 1

3-variable K-map:
C=0 C=1
B=0 0 1
A=0
F = C.( A + B) 0 0
B=1
0 1
A=1
B=0 0 1

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 51

 Karnaugh Maps

4-variable K-map:
C=0 C=1
D=0 D=1 D=0
B=0 0 0 0 0
A=0
F = A + B.C.D 0 0 1 0
B=1
1 1 1 1
A=1
B=0 1 1 1 1

Note that adjacent columns and adjacent rows are unit-

distant

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 52

 Karnaugh Maps

A complication of 3- and 4-variable maps is that they must

be regarded as being wrapped around on themselves:

1 1 0 0 0 0 0 0 1 0 0 1
0 0 0 0 1 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 1

F = B .C F = A .B .D F = B .D

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 53

 Boolean Simplification
The preferred method for simplifying Boolean expressions in
4 variables or less uses K-maps

The first stage is to obtain the sum-of-products standard form

using algebraic manipulation

The function is then represented in K-map form

Finally the simplest form for the expression is extracted from

the K-map

To obtain the simplest sum-of-products form the K-map is

inspected for the largest groups first; then for progressively
smaller groups

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 54

 Boolean Simplification
F = A.B + A.C + A.B.C + A.B.C.D

C=0 C=1
D=0 D=1 D=0
B=0 1 1 1 1 Groups of 16: none
A=0 Groups of 8: A
1 1 1 1
B=1 Groups of 4: none
1 0 0 0
A=1 Groups of 2: B .C .D
B=0 0 0 0 0 Groups of 1: none

Simplest sum-of-products form for F is:

F = A + B.C.D

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 55

 Boolean Implementation
The simplest sum-of-products form for F:
F = A + B.C.D
can now be implemented using a combination of AND, OR
and NOT gates:

A
A
B F
C
B.C.D
D

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 56

 Boolean Simplification
To obtain a function F in simplest product-of-sums form, the
first step is to obtain F in simplest sum-of-products form:

C=0 C=1
D=0 D=1 D=0
B=0 1 1 1 1
A=0
1 1 1 1
B=1
1 0 0 0
A=1
B=0 0 0 0 0

Simplest sum-of-products form for F is:

F = A.B + A.D + A.C
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 57
 Boolean Simplification
F = A.B + A.D + A.C
Now use duality to obtain F in simplest product-of-sums form:

F = ( A.B) + ( A.D ) + ( A.C )

F = ( A + B).( A + D ).( A + C )

OR invert and use DeMorgan’s Theorems twice to obtain F in

simplest product-of-sums form:

F = ( A.B) + ( A.D ) + ( A.C )

= ( A.B) . ( A.D ) . ( A.C )
F = ( A + B).( A + D ).( A + C )
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 58
 Boolean Implementation

F = ( A + B).( A + D ).( A + C )

A A+B
B A+C

C F

D A+D

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 59

 Incompletely-Specified Functions

It often happens that the value of a function is not specified

for some combinations of the input variables

In other words the value of the function is "don't-care" and

this is represented by X

K-maps can be used to simplify incompletely-specified

functions, with the don't-care conditions being assigned
either 0 or 1

Incompletely-specified functions cannot be defined by a

Boolean expression; instead a truth table is used

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 60

 Incompletely-Specified Functions
Function F defined by a truth table:

A B C D F A B C D F
0 0 0 0 0 1 0 0 0 0
0 0 0 1 0 1 0 0 1 0
0 0 1 0 0 1 0 1 0 X
0 0 1 1 1 1 0 1 1 X
0 1 0 0 1 1 1 0 0 1
0 1 0 1 1 1 1 0 1 1
0 1 1 0 1 1 1 1 0 1
0 1 1 1 X 1 1 1 1 1

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 61

 Incompletely-Specified Functions
Each row of the truth table corresponds to one square of the
K-map:
C=0 C=1
D=0 D=1 D=0
B=0 0 0 1 0
A=0
1 1 X 1
B=1
1 1 1 1
A=1
B=0 0 0 X X

Simplest sum-of-products form for F is:

F = B + C.D

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 62

 Incompletely-Specified Functions
C=0 C=1
D=0 D=1 D=0
B=0 0 0 1 0
A=0
1 1 X 1
B=1
1 1 1 1
A=1
B=0 0 0 X X

Simplest sum-of-products form for F is:

F = B.C + B.D

Simplest product -of-sums form for F is:

F = (B + C ).(B + D )
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 63
 Boolean Implementation
A Boolean function can be implemented by first obtaining the
simplest sum-of-products form:
F = B + C.D

The overall OR function is then implemented using an OR

gate, each of the terms is implemented using AND gates, and
NOT gates are used where required to invert the inputs:

B B
F
C
D C.D

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 64

 Boolean Implementation
Alternatively implementation can start from the simplest
product-of-sums form:
F = (B + C ).(B + D )
The overall AND function is then implemented using an AND
gate, each of the factors is implemented using OR gates, and
NOT gates are used where required to invert the inputs:

B B+C
C
F

D B+D

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 65

 Universal Logic Gates
NAND gates:
NOT A ( A.A) = A

1
( A.1) = A
NOT A

AND A
( A.B) = A.B
B

A
OR ( A.B) = A + B
B

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 66

 Universal Logic Gates
NOR gates:
NOT A ( A + A) = A

0
( A + 0) = A
NOT A

A
AND ( A + B) = A.B
B

A
OR ( A + B) = A + B
B

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 67

 Implementation in NAND
1. Obtain the function in simplest sum-of-products form:
F = A.B + C.D.E + ...

2. Invert the function twice (thus leaving it unchanged):

F = A.B + C.D.E + ...

3. Use DeMorgan’s theorem on lower inversion:

F = ( A .B ).(C .D .E ). ...

4. The function can now be implemented using only NAND

gates

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 68

 Implementation in NAND
Example: F = A + B.C.D
= A + B.C.D
= A .(B.C.D )
= A .(B.C.D )
A A
B F

C
B.C.D
D

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 69

 Design Example
The days of the week are represented by a 3-bit binary
code:
P Q R
Sunday 0 0 1
Monday 0 1 0
Tuesday 0 1 1 The code 000 will
never occur
Wednesday 1 0 0
Thursday 1 0 1
Friday 1 1 0
Saturday 1 1 1

Design a NAND system to give 1 for the work-days, and 0

for the rest-days

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 70

 Design Example
The first stage is to construct a K-map:

R=0 R=1
Q=0 X 0 Unused Sunday
P=0
1 1 Monday Tuesday
Q=1
1 0 Friday Saturday
P=1
Q=0 1 1 Wednesday Thursday

Note the use of X for the unused code: 000

The simplest sum-of-products form is:

F = R + P.Q + P.Q

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 71

 Design Example
F = R + P.Q + P.Q
= R . (P.Q) . (P.Q)
= R. (P.Q) . (P.Q)

P P

P.Q

F
Q P.Q
Q
R

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 72

 Design Example
The numbers 0 to 15 are represented by the 4-bit natural
binary code ABCD (A is the most-significant bit, D the least-
significant

A function F is required to have a value of 1 for prime

numbers, and to have a value of 0 for composite (non-
prime) numbers.

For the purpose of this design example the numbers 0 and

1 will be taken to be composite.

Design a combinational logic system consisting of NAND

gates to implement the function F of the variables A, B, C
and D.

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 73

 Design Example
C=0 C=1
D=0 D=1 D=0
B=0 0 0 1 1 0 1 3 2
A=0
0 1 1 0 4 5 7 6
B=1
0 1 0 0 12 13 15 14
A=1
B=0 0 0 1 0 8 9 11 10

F = B.C.D + A.B.C + B.C.D + A.B.D

The 1s on the K-map can be grouped in a different way:

F = B.C.D + A.B.C + B.C.D + A.C.D

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 74

 Design Example
F = B.C.D + A.B.C + B.C.D + A.B.D
B.C.D + A.B.C + B.C.D + A.B.D
(B.C.D ) . ( A.B.C ) . (B.C.D ) . ( A.B.D )
B
B.C.D

A A.B.C

C B.C.D

D A.B.D
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 75
 Implementation in NOR
1. Obtain the function in simplest product-of-sums form:

F = ( A + B).(B + C + D ). ...

2. Invert the function twice (thus leaving it unchanged):

F = ( A + B).(B + C + D ). ...
3. Use DeMorgan’s theorem on lower inversion:

F = ( A + B) + (B + C + D ) + ...
4. The function can now be implemented using only NOR
gates

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 76

 Implementation in NOR

Example: F = ( A + B).( A + D ).( A + C )

= ( A + B).( A + D ).( A + C )
= ( A + B) + ( A + D ) + ( A + C )

A ( A + B)
(A + C)
B
F
C

D ( A + D)

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 77

 Design Example
The days of the week are represented by a 3-bit binary
code:
P Q R
Sunday 0 0 1
Monday 0 1 0
Tuesday 0 1 1 The code 000 will
never occur
Wednesday 1 0 0
Thursday 1 0 1
Friday 1 1 0
Saturday 1 1 1

Design a NOR system to give 1 for the work-days, and 0 for

the rest-days

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 78

 Design Example
The first stage is to construct a K-map:
R=0 R=1
Q=0 X 0 Unused Sunday
P=0
1 1 Monday Tuesday
Q=1
1 0 Friday Saturday
P=1
Q=0 1 1 Wednesday Thursday

The simplest sum-of-products form for F is:

F = P.Q + P.Q.R
The simplest product-of-sums form for F is:
F = (P + Q).(P + Q + R )
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 79
 Design Example
F = (P + Q).(P + Q + R )
= (P + Q).(P + Q + R )
= (P + Q ) + (P + Q + R )

P
(P + Q )

P F

Q Q
(P + Q + R )
R
R

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 80

 Hazards in Combinational Logic
Systems
A hazard is a transient change that occurs in a logic
system following a change in an input

Hazards are the result of gate delays

B
A
C

The output C is given by:

C = A+B = A+ A =1
Thus the output should stay at logic 1, and be independent
of the input.
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 81
 Hazards in Combinational Logic
Systems
In fact an output pulse occurs following the 1Æ0 input
transition:

B=A
C=A+B

Delay in NOT Delay in NOT

Hazard exists for a time equal to the gate delay (typically a

few ns)
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 82
 Hazards in Combinational Logic
Systems
There are two types of hazard: static hazards and dynamic
hazards

Static hazard:

Dynamic hazard:

Whether hazards are significant depends on the application

Hazards are always a problem if they occur in logic

providing the input to a system with memory

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 83

 Hazards in NAND Systems
2-level NAND system:

Output gate

Input gates

Suppose that an input Q changes: no input gate can have

both Q and Q for inputs because:
Q.Q. ... = 0 = 1

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 84

 Hazards in NAND Systems

Case 1: (potential dynamic hazard)

Input gate 1
Input gate 2
Output

No Hazard

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 85

 Hazards in NAND Systems

Case 2: (potential static hazard)

Input gate 1
Input gate 2
Output

No Hazard

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 86

 Hazards in NAND Systems

Case 3: (potential static hazard)

Input gate 1
Input gate 2
Output

Dynamic hazards do not occur in 2-level NAND systems

Static hazards can occur if one input gate changes from

0Æ1 whilst another input gate changes from 1Æ0

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 87

 Properties of K-maps

Moving one square horizontally or vertically corresponds to

changing a single input variable

Each input gate corresponds to a group of 1s on the K-map:

moving in or out of a group causes the corresponding input
gate to change state

If 2 groups of 1s on the K-map are adjacent and non-

overlapping (horizontally or vertically) then changing a single
input variable can move out of one group and into the other

This is the condition for a static hazard

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 88

 Example of a Static Hazard
F = A.C + B.C.D + A.B.C
C=0 C=1
D=0 D=1 D=0
B=0 1 1 0 0
A=0
1 1 1 0
B=1
0 0 1 1
A=1
B=0 0 0 0 0

F = A.C + B.C.D + A.B.C

A static hazard may occur if the inputs change from A=0,

B=1, C=0, D=1 to A=0, B=1, C=1, D=1
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 89
 Example of a Static Hazard
F = A.C + B.C.D + A.B.C
= A.C + B.C.D + A.B.C
= A.C . (B.C.D ) . ( A.B.C )
= Q1. Q 2 . Q3

ABCD ABCD
0101 0111
Q1 = ( A.C ) 0 1
Q 2 = (B.C.D ) 1 0
Q3 = ( A.B.C ) 1 1

This is condition for a static hazard

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 90

 Eliminating Static Hazards
Static hazards are eliminated by including extra groups
which overlap the offending transitions:
C=0 C=1
D=0 D=1 D=0
B=0 1 1 0 0
A=0
1 1 1 0
B=1
0 0 1 1
A=1
B=0 0 0 0 0

F = A.C + B.C.D + A.B.C + A.B.D

The input gate corresponding to the new group remains at 0
throughout the transition
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 91
 Eliminating Static Hazards
F = A.C + B.C.D + A.B.C + A.B.D
= A.C + B.C.D + A.B.C + A.B.D
= A.C . (B.C.D ) . ( A.B.C ) . ( A.B.D )
= Q1 . Q 2 . Q3 . Q 4

ABCD ABCD
0101 0111
Q1 = ( A.C ) 0 1
Q 2 = (B.C.D ) 1 0
Q3 = ( A.B.C ) 1 1
Q 4 = ( A.B.D ) 0 0

Static hazard has been eliminated

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 92
 Design Example
Implement the function: F = A.D + B.C + B.D
in hazard-free form using NAND gates
C=0 C=1
D=0 D=1 D=0
B=0 0 0 0 0
A=0
1 0 1 1
B=1
1 1 1 1
A=1
B=0 0 1 1 0

Simplest sum-of-products form:

F = A.D + B.C + B.D
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 93
 Design Example
Include an extra group to overlap the border between the
adjacent groups:
C=0 C=1
D=0 D=1 D=0
B=0 0 0 0 0
A=0
1 0 1 1
B=1
1 1 1 1
A=1
B=0 0 1 1 0

Hazard-free sum-of-products form:

F = A.D + B.C + B.D + A.B

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 94

 Design Example
F = A.D + B.C + B.D + A.B
= A.D + B.C + B.D + A.B
= ( A.D ) . (B.C ) . (B.D ) . ( A.B)

B
C
F

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 95

 Hazards in NOR Systems

Dynamic hazards do not occur in 2-level NOR systems

Static hazards can occur if one input gate changes from

0Æ1 whilst another input gate changes from 1Æ0

If 2 groups of 0s on the K-map are adjacent and non-

overlapping (horizontally or vertically) then changing a single
input variable can move out of one group and into the other

This is the condition for a static hazard

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 96

 Example of a Static Hazard
F = A.B + A.D + A.C + B.C + C.D

C=0 C=1
D=0 D=1 D=0
B=0 1 1 0 0
A=0
1 1 0 0
B=1
1 1 1 1
A=1
B=0 0 1 1 0

F = A.C + A.B.D
A static hazard may occur if the inputs change from A=1,
B=0, C=1, D=0 to A=0, B=0, C=1, D=0
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 97
 Example of a Static Hazard
F = ( A.C ) + ( A.B.D )
F = ( A + C ).( A + B + D )
= ( A + C ).( A + B + D )
= ( A + C ) + ( A + B + D)
= Q1 + Q 2

ABCD ABCD
1010 0010
Q1 = ( A + C ) 0 1
Q2 = ( A + B + D) 1 0

This is condition for a static hazard

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 98
 Eliminating Static Hazards
Static hazards are eliminated by including extra groups
which overlap the offending transitions:
C=0 C=1
D=0 D=1 D=0
B=0 1 1 0 0
A=0
1 1 0 0
B=1
1 1 1 1
A=1
B=0 0 1 1 0

F = A.C + A.B.D + B.C.D

The input gate corresponding to the new group remains at 1
throughout the transition
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 99
 Eliminating Static Hazards
F = ( A.C ) + ( A.B.D ) + (B.C.D )
F = ( A + C ).( A + B + D ).(B + C + D )
= ( A + C ).( A + B + D ).(B + C + D )
= ( A + C ) + ( A + B + D ) + (B + C + D )
= Q1 + Q 2 + Q3

ABCD ABCD
1010 0010
Q1 = ( A + C ) 0 1
Q2 = ( A + B + D) 1 0
Q 3 = (B + C + D ) 1 1
Static hazard has been eliminated
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 100
 Design Example
Implement the function: F = A.C + B.C + A.B.C
in hazard-free form using NOR gates

C=0 C=1
B=0 1 0
A=0
1 0
B=1
1 1
A=1
B=0 0 0

Simplest sum-of-products form for F :

F = A.C + A.B

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 101

 Design Example
Include an extra group to overlap the border between the
adjacent groups:

C=0 C=1
B=0 1 0
A=0
1 0
B=1
1 1
A=1
B=0 0 0

Hazard-free sum-of-products form:

F = A.C + A.B + B.C

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 102

 Design Example
F = ( A.C ) + ( A.B) + (B.C )
F = ( A + C ).( A + B).(B + C )
= ( A + C ).( A + B).(B + C )
= ( A + C ) + ( A + B) + ( B + C )

F
B

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 103

 Dynamic Hazards
There must be at least three paths between the input and
output to give the minimum of three transitions that constitute a
dynamic hazard:
A E
C G
B F
H
D

D =C
E = A.C
F = B.D = B.C
G = E + F = A.C + B.C
H = D.G = C.( A.C + B.C ) = B.C
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 104
 Dynamic Hazards
D =C
Let A=1 E = A.C
B=1 F = B.D = B.C
G = E + F = A.C + B.C
H = D.G = C.( A.C + B.C ) = B.C
C
D
E
F
G
H
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 105
 Exclusive-OR Gates

A XOR B or A⊕B A B A+B

0 0 0
This function is similar to the
0 1 1
normal (inclusive) OR function
except for the case A=1, B=1 1 0 1
1 1 0
Electrical symbol:

A
B A⊕B
Identities:
A⊕B ≡ B⊕ A
( A ⊕ B) ⊕ C ≡ A ⊕ ( B ⊕ C )

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 106

 Exclusive-OR Gates
Exclusive-OR functions of more than 2 variables can be
generated by using several 2-input gates:

A
B A⊕B⊕C
C
A
B A⊕B⊕C⊕D
C
D

Operating between several variables the exclusive-OR

function is 1 if an odd number of the input variables are 1

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 107

 Exclusive-OR Gates
C=0 C=1
B=0 B=1 B=0 0 1
A=0
A=0 0 1 1 0
B=1
A=1 1 0 0 1
A=1
A⊕B B=0 1 0
A⊕B⊕C
C=0 C=1
D=0 D=1 D=0
B=0 0 1 0 1
A=0
1 0 1 0
B=1 A⊕B⊕C⊕D
0 1 0 1
A=1
B=0 1 0 1 0

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 108

 7-Segment Decoder
7-segment display:
a
b a
c f b
d
e g
f e c
g
d
common

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 109

 7-Segment Decoder
To reduce the number of connections the cathodes or anodes
of the LEDs are connected in common:

Common anode Common cathode

a a
b b
c c
d d
e e
f f
g g

common common

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 110

 7-Segment Decoder
Value Binary 7-Segment Display
D C B A a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 111
 7-Segment Decoder
Functions a, b, c, d, e, f of the binary code A, B, C, D can now
be obtained using a K-map:
C=0 C=1
Function a:
D=0 D=1 D=0
B=0 1 1 X 0
A=0
1 X X 1
B=1
1 X X 1
A=1
B=0 0 1 X 1

The simplest sum-of-products form for a is:

a = B + D + A.C + A.C
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 112
 7-Segment Decoder
Medium-Scale Integration (MSI) devices are available which
implement these Boolean functions and also provide current
drive:
A a +5V
Binary B b
inputs C c
D d
e
f
g
74HCT47 200Ω

Devices are also available to drive Liquid-Crystal Displays

(LCD) and multi-digit displays
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 113
 Decoders
A decoder converts the information on n input lines to 2n
output lines

For any input combination one, and only one, output line is
set to logical 1

A Y0
For example, a B Y1
3-to-8 line decoder C Y2
Y3
Y4
74HCT138 Y5
Y6
Y7

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 114

 Decoders
Truth table for a 3-to-8 line decoder:

C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 115

 Encoders
Encoders have 2n input lines, n output lines, and perform
the opposite operation to decoders

If one of the input lines is at logical 1 then the output lines

indicate the code for this input

Y0 A
For example, an Y1 B
8-to-3 line encoder Y2 C
Y3
Y4
74HCT148 Y5
Y6
Y7

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 116

 Priority Encoders
Truth table for an 8-to-3 line priority encoder:

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 C B A
0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0
X 1 0 0 0 0 0 0 0 0 1
X X 1 0 0 0 0 0 0 1 0
X X X 1 0 0 0 0 0 1 1
X X X X 1 0 0 0 1 0 0
X X X X X 1 0 0 1 0 1
X X X X X X 1 0 1 1 0
X X X X X X X 1 1 1 1
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 117
 Multiplexers
A multiplexer (MUX) is a combinational logic device that
selects binary information from one of several input lines

Data inputs D0 W
D1
D2
For example, an D3
8-to-1 line MUX D4
D5
D6
74HCT152 D7
C B A
Select inputs

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 118

 Multiplexers
Truth table for a 1-to-8 line multiplexer:

C B A W
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 119

 Programmable Logic
Programmable logic is increasingly being used instead of
standard gates

Programmable logic often leads to lower cost (both design

costs and hardware costs)

Types of programmable logic include: PROMs, PALs, GALs

and FPGAs

The function of programmable logic is determined by the

state of “fuses” on the integrated circuit

These fuses are programmed in a special-purpose

programmer connected to a PC

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 120

 Programmable Array Logic
Inputs: A B C Fixed OR
matrix

Program-
mable AND
matrix

Outputs: W X Y Z
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 121
 HDL Definition File
Name EX1;
Partno EX0000;
Date 6/10/98;
Rev 01;
Designer J.B.Grimbleby;
Company University of Reading;
Assembly None;
Location None;
Device p16l8;
Boolean Operator Symbols:
/* input pins */
PIN 1 = A; ! Æ NOT
PIN 2 =
PIN 3 =
B;
C;
& Æ AND
PIN 4 = D; # Æ OR
/* output pins */
PIN 19 = F;
/* equations */
F = !A & (B # C # !B & !C) # A & B & !(C # D);

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 122

 HDL Documentation File
Expanded Product Terms:
!F =>
A & !B
# A & C
# A & D

Symbol Table:
Pin Variable Pterms Max Min
Pol Name Ext Pin Type Used Pterms Level
--- -------- --- --- ---- ------ ------ -----
A 1 V - - -
B 2 V - - -
C 3 V - - -
D 4 V - - -
F 19 V 3 7 1

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 123

 JEDEC Output File
CUPL(WM) 4.9a Serial# MW-20007187
Device p16l8 Library DLIB-h-39-8
Created Mon Oct 05 19:23:13 1998
Name EX1
Partno EX0000
Revision 01
Date 6/10/98
Designer J.B.Grimbleby
Company University of Reading
Assembly None
Location None
*QP20
*QF2048
*G0
*F0
*L00000 11111111111111111111111111111111
*L00032 10011111111111111111111111111111
*L00064 11010111111111111111111111111111
*L00096 11011111011111111111111111111111
*C0FD1
* 76D1

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 124

 Sequential Logic Systems

Any logic system that has feedback can have memory

The output is not simply a function of the present value of

the inputs, but also of previous states of the system

Digital circuits with memory are termed sequential

General sequential logic systems are formalised as Finite-

State Machines (FSMs)

This course will only cover counters which are a subset of

FSMs

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 125

 RS Flip-Flops
Logic circuits having two stable states are called flip-flops

The simplest flip-flop consists of two cross-coupled NOT

gates:

A=B

B=A

There are two stable states: A=0, B=1

A=1, B=0

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 126

 RS Flip-Flops
Replacing the inverters by NOR gates:

R
Q = (R + P )

P = (S + Q)
S

R = 0, S = 0 : Q = (0 + P ) = P P = (0 + Q) = Q
R = 1, S = 0 : Q = (1 + P ) = 1 = 0 P = (0 + Q) = 0 = 1
R = 0, S = 1: P = (1 + Q) = 1 = 0 Q = (0 + P ) = 0 = 1

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 127

 RS Flip-Flops
The behaviour of the RS flip-flop can be summarised in the
table:

S R Q
0 0 Q-
1 0 1
0 1 0
1 1 X

where Q- represents the previous value of Q, and X

means that the result is undetermined

RS flip-flops can be used to store 1 bit of data

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 128

 RS Flip-Flops
An alternative RS flip-flop using NAND gates:

S
Q = (S.P )

P = (R.Q)
R

R = 1, S = 1: Q = (1.P ) = P P = (1.Q) = Q
R = 1, S = 0 : Q = (0.P ) = 0 = 1 P = (1.Q) = 1 = 0
R = 0, S = 1: P = (0.Q) = 0 = 1 Q = (1.P ) = 1 = 0

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 129

 RS Flip-Flops
The behaviour of the NAND RS flip-flop can be
summarised in the table:

S R Q
1 1 Q-
0 1 1
1 0 0
0 0 X

Like NOR-based RS flip-flops, NAND RS flip-flops are not

normally used for data storage

A common application is switch de-bouncing

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 130

 Switch De-Bouncer
+5V
47kΩ 47kΩ

Q
Assume break S
before make
R

R
S
Q

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 131

 The D-Latch
With the addition of two AND gates and an inverter the RS
flip-flop becomes a D-latch:

le R
Q

S
D

le = 0 → S = 0, R = 0 : Q =Q− (latch holds data)

le = 1 → S = D,R = D : Q = D (latch accepts data)
NB : S = 1, R = 1 cannot occur
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 132
 The D-Latch
The operation of the D-latch is to accept data when le=1, and
to store the data when le=0

Most D-latches also have an inverted output Q

D Q le Q
Q 0 Q-
1 D
le
Note that the control terminal is level-sensitive: as long as
le=1 the latch remains transparent (the output Q follows the
input D)
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 133
 Edge-Triggered Flip-Flops
Level-sensitive flip-flops are not suitable for use in clocked
sequential systems such as counters

For such applications it is necessary to use a different type of

flip-flop which is edge-sensitive

Edge-sensitive flip-flops respond only to a change in the

value of the control input (clock)

In an edge-sensitive flip-flop the output can only change at

the instant of the clock transition

The output value depends on the data inputs immediately

before the clock transition

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 134

 Edge-Triggered Flip-Flops
The edge-triggered D-type flip-flop has a single data input D,
and a clock input clk

D Q
Q

clk
The output Q changes only on a 0-to-1 transition of clk:
Q+ = D −
where Q+ is the output value after the transition and D- is the
data input value immediately before the transition

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 135

 Synchronous and Asynchronous
Systems
Sequential systems using edge-triggered flip-flops are
classified according to how the clock inputs of the flip-flops
are connected

Synchronous systems:
The clocks of all flip-flops are connected together to a
common source

Asynchronous systems:
The clocks of the flip-flops are derived from different
sources (usually the outputs of other flip-flops)

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 136

 Asynchronous Counters
A divide-by-2 counter can be constructed by connecting the
D input to the inverted output

D Q Output

Q
Input

Input
Q

D =Q

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 137

 Asynchronous Counters
Divide-by-2 stages can be cascaded to construct a natural
binary counter:

D Q Q1 D Q Q2 D Q Q3

Q Q Q
Input

Input
Q1
Q2
Q3

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 138

 Asynchronous Counters
Delays in the flip-flops cause spurious outputs while the flip-
flops are in the process of changing state following an input
transition:

Input
Q1
Q2
Q3
Delays in flip-flops

Q1: 1 0 0 0
Q2: 1 1 0 0
Q3: 0 0 0 1
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 139
 Synchronous Counters
In synchronous counters the clock terminals of all the flip-
flops are connected to the input
Q1 Q2
D2
D Q D Q

Q Q
Input

Input
Q1
Q2
D2
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 140
 Synchronous Counters
Synchronous counters can easily be made to count in any
modulo: Q1 Q2
D2
D Q D Q

Q Q
Input

Input
Q1
Q2
D2
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 141
 Shift Registers
Q1 Q2 Q3 Q4

Input D Q D Q D Q D Q

Q Q Q Q
Clock

Clock
Input
Q1
Q2
Q3
Q4
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 142
 Serial-to-Parallel Conversion
Serial data can be clocked into the shift register until the
complete data word is stored

The data is then available in parallel form at the outputs of

the shift register stages

Parallel-to-serial conversion is more difficult using the

standard D-type flip-flop

Some flip-flops have asynchronous load which allows data

to be forced onto the output

Data loaded in parallel into the flip-flops can be clocked out

in serial form

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 143

 Johnson-Code Counters
Johnson-code counters are shift registers with feedback
from the inverting output.

They are synchronous and count modulo 2n where n is the

number of flip-flops

3-stage Johnson-code counter:

Q1 Q2 Q3

D Q D Q D Q

Q Q Q
Input
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 144
 Johnson-Code Counters
Input
Q1
Q2
Q3
Q3

Precautions must be Input

taken to prevent the Q1
counter getting into one Q2
of the unused states: Q3
Q3
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 145
 Chain-Code Generators
Q1 Q2 Q3 Q4

D Q D Q D Q D Q

Q Q Q Q
Input
Input
Q1
Q2
Q3
Q4
D1
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 146
 Design of Synchronous Counters
Counter is required to count modulo-m: then n flip-flops will
be required where 2n ≥ m

The counter will consist of the n flip-flops connected to a

common clock, each with a combinational logic network
generating its D input from all the outputs:

Q1 Q2 Q3

Q1 D Q Q1 D Q Q1 D Q
Q2 Q2 Q2
Q3 Q Q3 Q Q3 Q

Input

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 147

 Design of Synchronous Counters
Modulo-3 counter with 2 outputs A and B:
State A B
1 0 0
2 1 1
3 1 0
1 0 0 etc.
Y-map shows next state for each present state:
B=0 B=1
A=0 1 1 X X Present state A=1, B=1
A=1 0 0 1 0 Next state A=1, B=0
DA DB
State A=0, B=1 does not occur in the required sequence, and
is termed an unused state
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 148
 Design of Synchronous Counters
Now split Y-map into separate K-maps:

B=0 B=1
A=0 1 1 X X
A=1 0 0 1 0
B=0 B=1 B=0 B=1
A=0 1 X A=0 1 X
A=1 0 1 A=1 0 0
DA DB

Thus: DA = A + B DB = A

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 149

 Design of Synchronous Counters

Check unused states:

DA = A + B DB = A
A=0, B=1 : DA=1+1=1, DB=1 Æ A=1, B=1 9

A B

D Q D Q

Q Q
Input

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 150

 Design of Synchronous Counters
If the counter gets into any unused state it should regain the
correct counting sequence after a limited number of input
clock cycles

If necessary modify K-maps to force the unwanted state (01)

back to a correct sequence state (00):

B=0 B=1 B=0 B=1

A=0 1 0 A=0 1 0
A=1 0 1 A=1 0 0
DA DB
DA = A.B + A.B DB = A.B
These functions are more complex than originals
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 151
 Design Example
Design a modulo-5 synchronous counter, using D-type flip-
flops and NAND gates, that has 3 outputs A, B, C and
counts in the sequence:

State A B C
1 0 1 0
2 1 0 0
3 0 0 1
4 0 1 1
5 1 1 0
1 0 1 0 etc.

The number of flip-flops n required is given by:

2n ≥ 5 Æ n = 3
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 152
 Design Example
State A B C
1 0 1 0
2 1 0 0
3 0 0 1
4 0 1 1
5 1 1 0
1 0 1 0 etc.
Y-map:
C=0 C=1
B=0 XXX 011
A=0 Present state 011
100 110
B=1 Next state 110
010 XXX
A=1
B=0 001 XXX
DA DB DC
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 153
 Design Example
C=0 C=1
B=0 XXX 011
A=0
100 110
B=1
010 XXX
A=1
B=0 001 XXX
C=0 C=1
B=0 X 0 X 1 X 1
A=0
1 1 0 1 0 0
B=1
0 X 1 X 0 X
A=1
B=0 0 X 0 X 1 X

DA = A.B DB = C + A.B DC = B
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 154
 Design Example

DA = A.B DB = C + A.B DC = B

Unwanted states:

A=0, B=0, C=0 : DA=0, DB=0, DC=1 Æ A=0, B=0, C=1 9

A=1, B=0, C=1 : DA=0, DB=1, DC=1 Æ A=0, B=1, C=1 9
A=1, B=1, C=1 : DA=0, DB=1, DC=0 Æ A=0, B=1, C=0 9

Convert to NAND form:

DA = A.B DB = C . ( A.B) DC = B

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 155

 Design Example

DA = A.B DB = C . ( A.B) DC = B

D Q D Q D Q C

Q A Q Q

Input

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 156

 Design Example
Design a modulo-5 synchronous counter, using D-type flip-
flops and NOR gates, that has 3 outputs A, B, C and counts
in the sequence:

State A B C
1 0 1 0
2 1 0 0
3 0 0 1
4 0 1 1
5 1 1 0
1 0 1 0 etc.

The number of flip-flops n required is given by:

2n ≥ 5 Æ n = 3
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 157
 Design Example

C=0 C=1
B=0 X 0 X 1 X 1
A=0
1 1 0 1 0 0
B=1
0 X 1 X 0 X
A=1
B=0 0 X 0 X 1 X

DA = A + B DB = A.B + A.C DC = B

Duality:

DA = A.B DB = ( A + B).( A + C ) DC = B

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 158

 Design Example

DA = A.B DB = ( A + B).( A + C ) DC = B

Unwanted states:

A=0, B=0, C=0 : DA=0, DB=0, DC=1 Æ A=0, B=0, C=1 9

A=1, B=0, C=1 : DA=0, DB=0, DC=1 Æ A=0, B=0, C=1 9
A=1, B=1, C=1 : DA=0, DB=1, DC=0 Æ A=0, B=1, C=0 9

Convert to NOR form:

DA = A + B DB = ( A + B) + ( A + C ) DC = B

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 159

 Design Example

DA = A + B DB = ( A + B) + ( A + C ) DC = B

A B
D Q D Q D Q C
Q Q Q

Input

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 160

 Edge-Triggered JK Flip-Flops
The edge-triggered JK flip-flop has 2 data inputs J, K, and a
clock input clk

J Q
K Q

clk
The output Q changes only on a 0-to-1 transition of clk

The output Q+ immediately after the clock transition depends

on the output Q- and the inputs J-, K- immediately before the
transition
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 161
 Edge-Triggered JK Flip-Flops
J- K- Q+
0 0 Q-
1 0 1
0 1 0
1 1 Q-

A divide-by-2 counter can be constructed by connecting

the J and K inputs to logic 1:

1 J Q Output
K Q

Input
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 162
 Edge-Triggered JK Flip-Flops
Asynchronous natural binary counter:
Q1 Q2 Q3
1 1 1
J Q J Q J Q

K Q K Q K Q
Input

Input
Q1
Q2
Q3
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 163
 Edge-Triggered JK Flip-Flops
Shift register:
Q1 Q2 Q3 Q4

Input J Q J Q J Q J Q

K Q K Q K Q K Q
Clock

JK flip-flops can be used to design synchronous counters.

The design process is more complicated than design with
D-type flip-flops, but the result is often more economical

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 164

 Types of Logic Gate

Electromechanical relays: slow (~ 10 ms), poor reliability,

physically large (~ 5 cm3), high power consumption

Vacuum tubes: faster (~ 10 μs), poor reliability, physically

large (~ 2 cm3), high power consumption

Semiconductor devices: fast, (~ 10 ns), excellent reliability,

very small (~ 10-9 cm3), low power consumption

Three main families of semiconductor logic gates: TTL,

CMOS and ECL

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 165

 Types of Logic Gate
The important parameters of a logic family are:

Power dissipation: this is usually dependent on the

transition frequency at the gate output.

Propagation delay: determines the maximum operating

speed

Noise margin: high value reduces the susceptibility to

interference

Fan-out: the maximum number of gates inputs that can be

connected to a single gate output

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 166

 Transistor-Transistor Logic (TTL)
TTL was the first integrated logic family and is still the most
commonly used

Logic levels: logic 0 0.0 Æ 0.8 V

logic 1 2.0 Æ 5.0 V

Basic TTL logic gate is NAND

Available in a number of variants including 74xxx, 74Sxxx,

74Lxxx, 74LSxxx, 74ASxxx, 74ALSxxx, 74Fxxx

Only the 74ALSxxx and 74Fxxx should be used in new

designs

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 167

 Properties of TTL Logic

(Values apply to the 74ALSxxx logic family)

Supply voltage: 5 V ± 0.25 V
Propagation delay: 4 ns
Speed-power product (10 MHz): 5 pJ
Quiescent power consumption: 1 mW
Noise margin: 0.3 V
Fan-out: 20
Cost: Medium

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 168

 Transistor-Transistor Logic (TTL)
The bipolar transistor:
Collector
IC
IB
Base VCE
VBE
Emitter

When used as a switch the transistor has two states:

OFF: IB = 0 IC = 0
ON: IB » IC/β VBE = 0.6V VCE < 0.2V

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 169

 Transistor-Transistor Logic (TTL)
Resistor-transistor logic gate: 5.0V
Logic 0: 0.0V Æ 0.5V
Logic 1: 3.0V Æ 5.0V 500Ω
F
5kΩ 5kΩ 5kΩ
A B C

C=0 C=1
B=0 1 0 F = A.B.C
A=0
0 0
B=1 = A+B+C
0 0
A=1 NOR gate
B=0 0 0
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 170
 Complementary Metal-Oxide
Semiconductor (CMOS) Logic
CMOS was introduced after TTL and is the technology used
in nearly all LSI devices

It is now replacing TTL in most SSI and MSI applications

because of its speed and lower power consumption

Logic levels: logic 0 0.0 Æ 1.5 V

(Typical) logic 1 3.5 Æ 5.0 V

There are also TTL-compatible CMOS logic families:

74HCTxxx and 74VHCT

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 171

 Properties of CMOS Logic

(Values apply to the 74HCxxx logic family)

Supply voltage: 2V Æ 6V
Propagation delay: 10 ns
Speed-power product (10 MHz): 50 pJ
Quiescent power consumption: 10 μW
Noise margin: 1.25 V
Fan-out: 20
Cost: low

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 172

 CMOS Logic
Metal-oxide semiconductor (MOS) transistors:
n-channel MOSFET p-channel MOSFET
Drain Source
VGS
Gate
Gate
VGS
Source Drain

OFF: VGS = 0.0Æ1.5V OFF: VGS = -1.5Æ0.0V

RDS > 1MΩ RDS > 1MΩ
ON: VGS = 3.5Æ5.0V ON: VGS =-5.0Æ-3.5V
RDS < 10Ω RDS < 10Ω
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 173
 CMOS NOT Gate
VDD = 5.0V

Q2 (p-channel)
VIN VOUT
Q1 (n-channel)

VIN Q1 Q2 VOUT
0.0 Æ 1.5V OFF ON 5.0V
3.5 Æ 5.0V ON OFF 0.0V

Thus when input is low, output is high, and when input is

high, output is low
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 174
 CMOS NOR Gate
VDD = 5.0V
A Q3

B Q4
F
Q2 Q1

A B Q1 Q2 Q3 Q4 F
lo lo OFF OFF ON ON hi
lo hi OFF ON ON OFF lo
hi lo ON OFF OFF ON lo
hi hi ON ON OFF OFF lo
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 175
 CMOS NAND Gate
VDD = 5.0V
Q3 Q4
F
A Q1

B Q2

A B Q1 Q2 Q3 Q4 F
lo lo OFF OFF ON ON hi
lo hi OFF ON ON OFF hi
hi lo ON OFF OFF ON hi
hi hi ON ON OFF OFF lo
J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 176
 Emitter-Coupled Logic (ECL)

ECL is the fastest, and most difficult to use, logic family

Logic levels: logic 0 -1.850 Æ -1.475 V

logic 1 -1.105 Æ -0.810 V

Basic ECL logic gate is OR / NOR

Difficult to interface to other logic families

Extreme switching speed means that length of

interconnections becomes significant

Used only when the fastest switching speed is essential

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 177

 Properties of ECL Logic

(Values apply to the 100K logic family)

Supply voltage: -4.5 V
Propagation delay: 0.75 ns
Speed-power product: 80 pJ
Quiescent power consumption: 40 mW
Noise margin: 0.125 V
Fan-out: 20
Cost: high

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 178

 Decoupling
All logic devices take current pulses from the power supply
when switching output state
This causes negative-going pulse on the power supply
(because of supply impedance)
Thus switching in one device could affect another device
This problem is overcome by decoupling: capacitors are
placed across the supply close to the logic devices
Typically 47 nF ceramic capacitors are used
For high-speed logic a decoupling capacitor is required
close to each device

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 179

 Introduction to Digital Circuits

© J. B. Grimbleby, February 07

J. B. Grimbleby School of Systems Engineering: Electronic Engineering Slide 180