MC33201, MC33202,

MC33204, NCV33201,
NCV33202, NCV33204

Low Voltage, Rail-to-Rail

Operational Amplifiers
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The MC33201/2/4 family of operational amplifiers provide
rail−to−rail operation on both the input and output. The inputs can be
driven as high as 200 mV beyond the supply rails without phase
reversal on the outputs, and the output can swing within 50 mV of each PDIP−8
rail. This rail−to−rail operation enables the user to make full use of the P, VP SUFFIX
CASE 626
supply voltage range available. It is designed to work at very low 8
supply voltages (± 0.9 V) yet can operate with a supply of up to +12 V 1
and ground. Output current boosting techniques provide a high output
current capability while keeping the drain current of the amplifier to a SOIC−8
minimum. Also, the combination of low noise and distortion with a 8 D, VD SUFFIX
high slew rate and drive capability make this an ideal amplifier for CASE 751
1
audio applications.

Features Micro8]
DM SUFFIX
• Low Voltage, Single Supply Operation 8
CASE 846A
1
(+1.8 V and Ground to +12 V and Ground)
• Input Voltage Range Includes both Supply Rails
• Output Voltage Swings within 50 mV of both Rails
• No Phase Reversal on the Output for Over−driven Input Signals PDIP−14
P, VP SUFFIX
• High Output Current (ISC = 80 mA, Typ) CASE 646
• Low Supply Current (ID = 0.9 mA, Typ) 14
1
• 600 W Output Drive Capability
• Extended Operating Temperature Ranges
SOIC−14
(−40° to +105°C and −55° to +125°C) D, VD SUFFIX
• Typical Gain Bandwidth Product = 2.2 MHz 14 CASE 751A
1
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable TSSOP−14
14 DTB SUFFIX
• These Devices are Pb−Free and are RoHS Compliant
1 CASE 948G

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.

DEVICE MARKING INFORMATION

See general marking information in the device marking
section on page 11 of this data sheet.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

July, 2018 − Rev. 18 MC33201/D
 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

PIN CONNECTIONS
MC33201 MC33204
All Case Styles All Case Styles
NC 1 8 NC Output 1 1 14 Output 4

2 7 VCC 2 13
1 4
Inputs 1 Inputs 4
Inputs 3 12
3 6 Output
VCC 4 11 VEE
VEE 4 5 NC
5 10
Inputs 2 2 3 Inputs 3
(Top View) 6 9
Output 2 7 8 Output 3
MC33202
All Case Styles (Top View)

Output 1 1 8 VCC

2 7 Output 2
1
Inputs 1
3 6
Inputs 2
2
VEE 4 5

(Top View)

VCC

VCC VEE

VCC

Vin-
Vout

VCC
Vin+

VEE
This device contains 70 active transistors (each amplifier).

Figure 1. Circuit Schematic

(Each Amplifier)

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 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (VCC to VEE) VS +13 V
Input Differential Voltage Range VIDR Note 1 V
Common Mode Input Voltage Range (Note 2) VCM VCC + 0.5 V to V
VEE − 0.5 V
Output Short Circuit Duration ts Note 3 sec
Maximum Junction Temperature TJ +150 °C
Storage Temperature Tstg − 65 to +150 °C
Maximum Power Dissipation PD Note 3 mW

DC ELECTRICAL CHARACTERISTICS (TA = 25°C)

Characteristic VCC = 2.0 V VCC = 3.3 V VCC = 5.0 V Unit
Input Offset Voltage mV
VIO (max)
MC33201, NCV33201V ± 8.0 ± 8.0 ± 6.0
MC33202, NCV33202, V ±10 ±10 ± 8.0
MC33204, NCV33204, V ±12 ±12 ±10

Output Voltage Swing

VOH (RL = 10 kW) 1.9 3.15 4.85 Vmin
VOL (RL = 10 kW) 0.10 0.15 0.15 Vmax
Power Supply Current mA
per Amplifier (ID) 1.125 1.125 1.125
Specifications at VCC = 3.3 V are guaranteed by the 2.0 V and 5.0 V tests. VEE = GND.

DC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic Figure Symbol Min Typ Max Unit
Input Offset Voltage (VCM 0 V to 0.5 V, VCM 1.0 V to 5.0 V) 3 ⎮VIO⎮ mV
MC33201/NCV33201V: TA = + 25°C − − 6.0
MC33201: TA = − 40° to +105°C − − 9.0
MC33201V/NCV33201V: TA = − 55° to +125°C − − 13
MC33202/NCV33202, V: TA = + 25°C − − 8.0
MC33202/NCV33202: TA = − 40° to +105°C − − 11
MC33202V/NCV33202V: TA = − 55° to +125°C (Note 4) − − 14
MC33204/NCV33204V: TA = + 25°C − − 10
MC33204: TA = − 40° to +105°C − − 13
MC33204V/NCV33204V: TA = − 55° to +125°C (Note 4) − − 17
Input Offset Voltage Temperature Coefficient (RS = 50 W) 4 DVIO/DT mV/°C
TA = − 40° to +105°C − 2.0 −
TA = − 55° to +125°C − 2.0 −
Input Bias Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V) 5, 6 ⎮IIB⎮ nA
TA = + 25°C − 80 200
TA = − 40° to +105°C − 100 250
TA = − 55° to +125°C − − 500
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The differential input voltage of each amplifier is limited by two internal parallel back−to−back diodes. For additional differential input voltage
range, use current limiting resistors in series with the input pins.
2. The input common mode voltage range is limited by internal diodes connected from the inputs to both supply rails. Therefore, the voltage
on either input must not exceed either supply rail by more than 500 mV.
3. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See Figure 2)
4. All NCV devices are qualified for Automotive use.

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3
 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

DC ELECTRICAL CHARACTERISTICS (cont.) (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic Figure Symbol Min Typ Max Unit
Input Offset Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V) − ⎮IIO⎮ nA
TA = + 25°C − 5.0 50
TA = − 40° to +105°C − 10 100
TA = − 55° to +125°C − − 200
Common Mode Input Voltage Range − VICR VEE − VCC V
Large Signal Voltage Gain (VCC = + 5.0 V, VEE = − 5.0 V) 7 AVOL kV/V
RL = 10 kW 50 300 −
RL = 600 W 25 250 −
Output Voltage Swing (VID = ± 0.2 V) 8, 9, 10 V
RL = 10 kW VOH 4.85 4.95 −
RL = 10 kW VOL − 0.05 0.15
RL = 600 W VOH 4.75 4.85 −
RL = 600 W VOL − 0.15 0.25
Common Mode Rejection (Vin = 0 V to 5.0 V) 11 CMR 60 90 − dB
Power Supply Rejection Ratio 12 PSRR mV/V
VCC/VEE = 5.0 V/GND to 3.0 V/GND 500 25 −
Output Short Circuit Current (Source and Sink) 13, 14 ISC 50 80 − mA
Power Supply Current per Amplifier (VO = 0 V) 15 ID mA
TA = − 40° to +105°C − 0.9 1.125
TA = − 55° to +125°C − 0.9 1.125

AC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic Figure Symbol Min Typ Max Unit
Slew Rate 16, 26 SR V/ms
(VS = ± 2.5 V, VO = − 2.0 V to + 2.0 V, RL = 2.0 kW, AV = +1.0) 0.5 1.0 −
Gain Bandwidth Product (f = 100 kHz) 17 GBW − 2.2 − MHz
Gain Margin (RL = 600 W, CL = 0 pF) 20, 21, 22 AM − 12 − dB
Phase Margin (RL = 600 W, CL = 0 pF) 20, 21, 22 OM − 65 − Deg
Channel Separation (f = 1.0 Hz to 20 kHz, AV = 100) 23 CS − 90 − dB
Power Bandwidth (VO = 4.0 Vpp, RL = 600 W, THD ≤ 1 %) BWP − 28 − kHz
Total Harmonic Distortion (RL = 600 W, VO = 1.0 Vpp, AV = 1.0) 24 THD %
f = 1.0 kHz − 0.002 −
f = 10 kHz − 0.008 −
Open Loop Output Impedance ⎮ZO⎮ W
(VO = 0 V, f = 2.0 MHz, AV = 10) − 100 −
Differential Input Resistance (VCM = 0 V) Rin − 200 − kW
Differential Input Capacitance (VCM = 0 V) Cin − 8.0 − pF
Equivalent Input Noise Voltage (RS = 100 W) 25 en
nV/
f = 10 Hz − 25 −
− 20 − Hz
f = 1.0 kHz
Equivalent Input Noise Current 25 in
pA/
f = 10 Hz − 0.8 −
Hz
f = 1.0 kHz − 0.2 −

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 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

PD(max) , MAXIMUM POWER DISSIPATION (mW) 2500 40

360 amplifiers tested from

PERCENTAGE OF AMPLIFIERS (%)

8 and 14 Pin DIP Pkg 35 3 (MC33204) wafer lots
2000 VCC = +5.0 V
30 VEE = Gnd
TSSOP-14 Pkg TA = 25°C
1500 25 DIP Package
SO-14 Pkg
20
1000
15
SOIC-8
10
500 Pkg
5.0
0 0
-55 -40 -25 0 25 50 85 125 -10 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 10
TA, AMBIENT TEMPERATURE (°C) VIO, INPUT OFFSET VOLTAGE (mV)

Figure 2. Maximum Power Dissipation Figure 3. Input Offset Voltage Distribution

versus Temperature

50 200
360 amplifiers tested from VCC = +5.0 V

I IB , INPUT BIAS CURRENT (nA)

3 (MC33204) wafer lots VEE = Gnd
40 VCC = +5.0 V 160
VEE = Gnd
TA = 25°C
PERCENTAGE OF AMPLIFIERS (%)

30 DIP Package 120

VCM = 0 V to 0.5 V

20 80
VCM > 1.0 V
10 40

0 0
-50 -40 -30 -20 -10 0 10 20 30 40 50 -55 -40 -25 0 25 70 85 125
TCV , INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (mV/°C) TA, AMBIENT TEMPERATURE (°C)
IO

Figure 4. Input Offset Voltage Figure 5. Input Bias Current

Temperature Coefficient Distribution versus Temperature

150
A VOL , OPEN LOOP VOLTAGE GAIN (kV/V)

300
100
I IB , INPUT BIAS CURRENT (nA)

260
50

0 220
-50

-100 180
VCC = +5.0 V
-150 VCC = 12 V VEE = Gnd
140
VEE = Gnd RL = 600 W
-200 TA = 25°C DVO = 0.5 V to 4.5 V
-250 100
0 2.0 4.0 6.0 8.0 10 12 -55 -40 -25 0 25 70 85 105 125
VCM, INPUT COMMON MODE VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

Figure 6. Input Bias Current Figure 7. Open Loop Voltage Gain versus
versus Common Mode Voltage Temperature

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 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

12 VCC

VSAT, OUTPUT SATURATION VOLTAGE (V)

RL = 600 W TA = -55°C
10 TA = 25°C TA = 125°C
VCC - 0.2 V
VO, OUTPUT VOLTAGE (Vpp )

TA = 25°C
8.0
VCC - 0.4 V
6.0
VEE + 0.4 V
4.0 VCC = +5.0 V
VEE = -5.0 V TA = 25°C
2.0 VEE + 0.2 V
TA = 125°C
TA = -55°C
0 VEE
±1.0 ±2.0 ±3.0 ±4.0 ±5.0 ±6.0 0 5.0 10 15 20
VCC,⎮VEE⎮ SUPPLY VOLTAGE (V) IL, LOAD CURRENT (mA)

Figure 8. Output Voltage Swing Figure 9. Output Saturation Voltage

versus Supply Voltage versus Load Current

12 100

CMR, COMMON MODE REJECTION (dB)

VO, OUTPUT VOLTAGE (Vpp )

80
9.0

60
6.0
VCC = +6.0 V 40
VEE = -6.0 V VCC = +6.0 V
3.0 RL = 600 W VEE = -6.0 V
AV = +1.0 20 TA = -55° to +125°C
TA = 25°C
0 0
1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)

Figure 10. Output Voltage Figure 11. Common Mode Rejection

versus Frequency versus Frequency
I SC , OUTPUT SHORT CIRCUIT CURRENT (mA)

120 100
PSR, POWER SUPPLY REJECTION (dB)

Source
100
80
PSR+
80
60
60 Sink
PSR- 40
40
VCC = +6.0 V 20 VCC = +6.0 V
20 VEE = -6.0 V VEE = -6.0 V
TA = -55° to +125°C TA = 25°C
0 0
10 100 1.0 k 10 k 100 k 1.0 M 0 1.0 2.0 3.0 4.0 5.0 6.0
f, FREQUENCY (Hz) ⎮Vout⎮, OUTPUT VOLTAGE (V)

Figure 12. Power Supply Rejection Figure 13. Output Short Circuit Current
versus Frequency versus Output Voltage

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6
 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204
I SC , OUTPUT SHORT CIRCUIT CURRENT (mA)

I CC , SUPPLY CURRENT PER AMPLIFIER (mA)

150 2.0
VCC = +5.0 V
125 VEE = Gnd
1.6

100 TA = 125°C
Source 1.2
75 TA = 25°C
Sink
0.8
50 TA = -55°C

25 0.4

0 0
-55 -40 -25 0 25 70 85 105 125 ±0 ±1.0 ±2.0 ±3.0 ±4.0 ±5.0 ±6.0
TA, AMBIENT TEMPERATURE (°C) VCC, ⎮VEE⎮, SUPPLY VOLTAGE (V)

Figure 14. Output Short Circuit Current Figure 15. Supply Current per Amplifier
versus Temperature versus Supply Voltage with No Load

2.0 4.0
GBW, GAIN BANDWIDTH PRODUCT (MHz)
VCC = +2.5 V VCC = +2.5 V
VEE = -2.5 V VEE = -2.5 V
VO = ±2.0 V f = 100 kHz
1.5 3.0
SR, SLEW RATE (V/μ s)

+Slew Rate
1.0 2.0

-Slew Rate

0.5 1.0

0 0
-55 -40 -25 0 25 70 85 105 125 -55 -40 -25 0 25 70 85 105 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 16. Slew Rate Figure 17. Gain Bandwidth Product

versus Temperature versus Temperature

70 40 70 40
, OPEN LOOP VOLTAGE GAIN (dB)

A VOL, OPEN LOOP VOLTAGE GAIN (dB)

VS = ±6.0 V CL = 0 pF
TA = 25°C TA = 25°C
O , EXCESS PHASE (DEGREES)

50 RL = 600 W 80 50 RL = 600 W 80 O , EXCESS PHASE (DEGREES)

30 120 30 1A 120
1A 2A
2A
10 160 10 160
2B 1B
1A - Phase, CL = 0 pF 1A - Phase, VS = ±6.0 V
1B - Gain, CL = 0 pF 1B 2B
-10 200 -10 1B - Gain, VS = ±6.0 V 200
2A - Phase, CL = 300 pF
VOL

2A - Phase, VS = ±1.0 V
2B - Gain, CL = 300 pF 2B - Gain, VS = ±1.0 V
A

-30 240 -30 240

10 k 100 k 1.0 M 10 M 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)

Figure 18. Voltage Gain and Phase Figure 19. Voltage Gain and Phase
versus Frequency versus Frequency

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 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

70 70 75 75
Phase Margin Phase Margin
60 60
O M , PHASE MARGIN (DEGREES)

O M , PHASE MARGIN (DEGREES)

60 60
50 50

A , GAIN MARGIN (dB)

A , GAIN MARGIN (dB)

45 VCC = +6.0 V 45
40 VCC = +6.0 V 40 VEE = -6.0 V
VEE = -6.0 V
TA = 25°C
30 RL = 600 W 30
CL = 100 pF 30 30
20 20

M
15 Gain Margin 15
10 10
Gain Margin
0 0 0 0
-55 -40 -25 0 25 70 85 105 125 10 100 1.0 k 10 k 100 k
TA, AMBIENT TEMPERATURE (°C) RT, DIFFERENTIAL SOURCE RESISTANCE (W)

Figure 20. Gain and Phase Margin Figure 21. Gain and Phase Margin
versus Temperature versus Differential Source Resistance

80 16 150
VCC = +6.0 V
70 VEE = -6.0 V 14
O M , PHASE MARGIN (DEGREES)

Phase Margin AV = 100

CS, CHANNEL SEPARATION (dB)
RL = 600 W 120
60 AV = 100 12
A , GAIN MARGIN (dB)

Gain Margin TA = 25°C

50 10 90
40 8.0
AV = 10
30 6.0 60
VCC = +6.0 V
M

20 4.0 VEE = -6.0 V

30
VO = 8.0 Vpp
10 2.0
TA = 25°C
0 0 0
10 100 1.0 k 100 1.0 k 10 k
CL, CAPACITIVE LOAD (pF) f, FREQUENCY (Hz)

Figure 22. Gain and Phase Margin Figure 23. Channel Separation
versus Capacitive Load versus Frequency
en , EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz)

i n , INPUT REFERRED NOISE CURRENT (pA/ Hz)

10 50 5.0
THD, TOTAL HARMONIC DISTORTION (%)

VCC = +5.0 V VEE = -5.0 V VCC = +6.0 V

TA = 25°C RL = 600 W VEE = -6.0 V
VO = 2.0 Vpp 40 TA = 25°C 4.0
1.0
AV = 1000 30 3.0
0.1 AV = 100
Noise Voltage
20 2.0
AV = 10
0.01
10 1.0
AV = 1.0 Noise Current
0.001 0 0
10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k
f, FREQUENCY (Hz) f, FREQUENCY (Hz)

Figure 24. Total Harmonic Distortion Figure 25. Equivalent Input Noise Voltage
versus Frequency and Current versus Frequency

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 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

DETAILED OPERATING DESCRIPTION

General Information Circuit Information

The MC33201/2/4 family of operational amplifiers are Rail−to−rail performance is achieved at the input of the
unique in their ability to swing rail−to−rail on both the input amplifiers by using parallel NPN−PNP differential input
and the output with a completely bipolar design. This offers stages. When the inputs are within 800 mV of the negative
low noise, high output current capability and a wide rail, the PNP stage is on. When the inputs are more than 800
common mode input voltage range even with low supply mV greater than VEE, the NPN stage is on. This switching of
voltages. Operation is guaranteed over an extended input pairs will cause a reversal of input bias currents (see
temperature range and at supply voltages of 2.0 V, 3.3 V and Figure 6). Also, slight differences in offset voltage may be
5.0 V and ground. noted between the NPN and PNP pairs. Cross−coupling
Since the common mode input voltage range extends from techniques have been used to keep this change to a minimum.
VCC to VEE, it can be operated with either single or split In addition to its rail−to−rail performance, the output stage
voltage supplies. The MC33201/2/4 are guaranteed not to is current boosted to provide 80 mA of output current,
latch or phase reverse over the entire common mode range, enabling the op amp to drive 600 W loads. Because of this
however, the inputs should not be allowed to exceed high output current capability, care should be taken not to
maximum ratings. exceed the 150°C maximum junction temperature.

VCC = +6.0 V VCC = +6.0 V

V , OUTPUT VOLTAGE (2.0 mV/DIV)

VEE = -6.0 V V , OUTPUT VOLTAGE (50 mV/DIV) VEE = -6.0 V

RL = 600 W RL = 600 W
CL = 100 pF CL = 100 pF
TA = 25°C TA = 25°C
O

t, TIME (5.0 ms/DIV) t, TIME (10 ms/DIV)

Figure 26. Noninverting Amplifier Slew Rate Figure 27. Small Signal Transient Response

VCC = +6.0 V
V , OUTPUT VOLTAGE (2.0 V/DIV)

VEE = -6.0 V
RL = 600 W
CL = 100 pF
AV = 1.0
TA = 25°C
O

t, TIME (10 ms/DIV)

Figure 28. Large Signal Transient Response

Surface mount board layout is a critical portion of the total between the board and the package. With the correct pad
design. The footprint for the semiconductor packages must be geometry, the packages will self−align when subjected to a
the correct size to ensure proper solder connection interface solder reflow process.

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 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

ORDERING INFORMATION
Operational Device Operating Package
Shipping†
Amplifier Function Temperature Range
MC33201DG SOIC−8 98 Units / Rail
TA= −40° to +105°C (Pb−Free)
MC33201DR2G 2500 / Tape & Reel

Single MC33201VDG 98 Units / Rail

MC33201VDR2G TA = −55° to 125°C 2500 / Tape & Reel
NCV33201VDR2G 2500 / Tape & Reel
MC33202DG SOIC−8 98 Units / Rail
(Pb−Free)
MC33202DR2G 2500 / Tape & Reel
TA= −40 ° to +105°C
MC33202DMR2G Micro−8
(Pb−Free) 4000 / Tape & Reel
Dual NCV33202DMR2G*
MC33202VDG SOIC−8 98 Units / Rail
(Pb−Free)
MC33202VDR2G TA = −55° to 125°C
2500 / Tape & Reel
NCV33202VDR2G*
MC33204DG SO−14 55 Units / Rail
(Pb−Free)
MC33204DR2G 2500 Units / Tape & Reel
TA= −40 ° to +105°C
MC33204DTBG TSSOP−14 96 Units / Rail
(Pb−Free)
MC33204DTBR2G 2500 Units / Tape & Reel
Quad MC33204VDG SO−14 55 Units / Rail
(Pb−Free)
MC33204VDR2G
2500 Units / Tape & Reel
NCV33204DR2G* TA = −55° to 125°C

NCV33204DTBR2G* TSSOP−14
2500 Units / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

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 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

MARKING DIAGRAMS

SOIC−8 SOIC−8 PDIP−8 PDIP−8 Micro−8 SO−14

D SUFFIX VD SUFFIX P SUFFIX VP SUFFIX DM SUFFIX D SUFFIX
CASE 751 CASE 751 CASE 626 CASE 626 CASE 846A CASE 751A
8 8 8 8 8 14
3320x 320xV * **
MC3320xP MC33202VP 3202
ALYW ALYW AWL AWL MC33204DG
G G AYWG
YYWWG YYWWG AWLYWW
1 1 G
1 1 1
1

SO−14 PDIP−14 PDIP−14 TSSOP−14

VD SUFFIX P SUFFIX VP SUFFIX DTB SUFFIX
CASE 751A CASE 646 CASE 646 CASE 948G
14 14 14 14 14

MC33204VDG * MC33204P MC33204VP *

AWLYYWWG AWLYYWWG MC33 MC33
AWLYWW
204 204V
1 1 ALYWG ALYWG
1 G G

1 1

x = 1 or 2
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)
*This marking diagram applies to NCV3320xV
**This marking diagram applies to NCV33202DMR2G

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 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

PACKAGE DIMENSIONS

PDIP−8
P, VP SUFFIX
CASE 626−05
ISSUE N

NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E 2. CONTROLLING DIMENSION: INCHES.
H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
8 5 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
E1 NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
1 4
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
NOTE 8 LEADS UNCONSTRAINED.
c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
b2 B END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 5
INCHES MILLIMETERS
A2 DIM MIN MAX MIN MAX
e/2 A −−−− 0.210 −−− 5.33
A NOTE 3 A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
L b 0.014 0.022 0.35 0.56
b2 0.060 TYP 1.52 TYP
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
SEATING
PLANE D1 0.005 −−−− 0.13 −−−
A1 E 0.300 0.325 7.62 8.26
C M E1 0.240 0.280 6.10 7.11
D1 e 0.100 BSC 2.54 BSC
eB −−−− 0.430 −−− 10.92
e eB L 0.115 0.150 2.92 3.81
8X b END VIEW M −−−− 10 ° −−− 10 °
0.010 M C A M B M NOTE 6
SIDE VIEW

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12
 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

PACKAGE DIMENSIONS

SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS INCHES
G
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 _ B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H M J K 0.40 1.27 0.016 0.050
D
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M Z Y S X S

SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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13
 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

PACKAGE DIMENSIONS

Micro8
DM SUFFIX
CASE 846A−02
ISSUE H
D NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
HE E 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.

MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX
PIN 1 ID
e A −− −− 1.10 −− −− 0.043
b 8 PL A1 0.05 0.08 0.15 0.002 0.003 0.006
b 0.25 0.33 0.40 0.010 0.013 0.016
0.08 (0.003) M T B S A S
c 0.13 0.18 0.23 0.005 0.007 0.009
D 2.90 3.00 3.10 0.114 0.118 0.122
E 2.90 3.00 3.10 0.114 0.118 0.122
e 0.65 BSC 0.026 BSC
SEATING L 0.40 0.55 0.70 0.016 0.021 0.028
−T− PLANE HE 4.75 4.90 5.05 0.187 0.193 0.199
0.038 (0.0015) A

A1 c L

SOLDERING FOOTPRINT*
1.04 0.38
8X 8X
0.041 0.015

3.20 4.24 5.28

0.126 0.167 0.208

0.65
6X
0.0256 SCALE 8:1 ǒinches
mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com
14
 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

PACKAGE DIMENSIONS

PDIP−14
CASE 646−06
ISSUE R

NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
D A 2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
14 8 E AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
H 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
E1 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
1 7 LEADS UNCONSTRAINED.
c
NOTE 8 b2 B 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
NOTE 5 CORNERS).
A2
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
NOTE 3
A −−−− 0.210 −−− 5.33
L A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
b 0.014 0.022 0.35 0.56
SEATING
PLANE b2 0.060 TYP 1.52 TYP
A1 C 0.008 0.014 0.20 0.36
C M D 0.735 0.775 18.67 19.69
D1 D1 0.005 −−−− 0.13 −−−
e eB E 0.300 0.325 7.62 8.26
END VIEW E1 0.240 0.280 6.10 7.11
14X b
e 0.100 BSC 2.54 BSC
NOTE 6
0.010 M C A M B M eB −−−− 0.430 −−− 10.92
SIDE VIEW L 0.115 0.150 2.92 3.81
M −−−− 10 ° −−− 10 °

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15
 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

PACKAGE DIMENSIONS

SOIC−14
CASE 751A−03
ISSUE K

D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
0.25 M B M 13X b DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h
A X 45 _
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
M L 0.40 1.25 0.016 0.049
e A1
SEATING M 0_ 7_ 0_ 7_
C PLANE

SOLDERING FOOTPRINT*
6.50 14X
1.18
1

1.27
PITCH

14X
0.58

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com
16
 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204

PACKAGE DIMENSIONS

TSSOP−14
CASE 948G
ISSUE B
14X K REF NOTES:
1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE
−U− N DAMBAR PROTRUSION. ALLOWABLE
PIN 1 DAMBAR PROTRUSION SHALL BE 0.08
IDENT. F (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
1 7
DETAIL E CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
K

ÉÉÉ
ÇÇÇ
0.15 (0.006) T U S DETERMINED AT DATUM PLANE −W−.
A
−V− K1 MILLIMETERS INCHES

ÇÇÇ
ÉÉÉ
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200

ÇÇÇ
J J1 B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
SECTION N−N F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024

C −W− J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
0.10 (0.004) K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
−T− SEATING D G H DETAIL E M 0_ 8_ 0_ 8_
PLANE

SOLDERING FOOTPRINT
7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

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17
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NCV33202VDR2 NCV33202VDR2G NCV33204DR2 NCV33204DR2G NCV33204DTBR2 NCV33204DTBR2G
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MC33201VDR2 MC33201VDR2G MC33202D MC33202DG MC33202DMR2 MC33202DMR2G MC33202DR2
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MC33202VP MC33202VPG MC33204D MC33204DG MC33204DR2 MC33204DR2G MC33204DTB
MC33204DTBG MC33204DTBR2 MC33204DTBR2G MC33204P MC33204PG MC33204VD MC33204VDG
MC33204VDR2 MC33204VDR2G MC33204VP MC33204VPG NCV33202DMR2G SCY33202DR2G
SCY33201DR2G TCA80122W