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MARKING SCHEME 1.3.2 Computer Architecture

The document discusses the fetch-execute cycle in computer architecture. It describes the stages as fetch, decode, and execute. It also contains questions and answers about computer memory and the fetch-execute cycle. Specifically, it lists the stages of the cycle as: 1) the address is copied to the memory address register from the program counter, 2) the instruction is copied from memory to the memory data register, 3) the instruction is copied to the current instruction register, 4) the instruction is decoded, 5) the program counter is incremented, 6) the address part of the instruction is placed in the memory address register, and 7) the instruction is executed.

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254 views

MARKING SCHEME 1.3.2 Computer Architecture

The document discusses the fetch-execute cycle in computer architecture. It describes the stages as fetch, decode, and execute. It also contains questions and answers about computer memory and the fetch-execute cycle. Specifically, it lists the stages of the cycle as: 1) the address is copied to the memory address register from the program counter, 2) the instruction is copied from memory to the memory data register, 3) the instruction is copied to the current instruction register, 4) the instruction is decoded, 5) the program counter is incremented, 6) the address part of the instruction is placed in the memory address register, and 7) the instruction is executed.

Uploaded by

hassan
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© © All Rights Reserved
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CAMBRIDGE COMPUTER SCIENCE AHMED THAKUR

OL COMPUTER SCIENCE – 2210/01


TOPICAL MARKING SCHEMES

1.3.2 COMPUTER ARCHITECTURE


AND THE FETCH-EXECUTE CYCLE

https://www.facebook.com/groups/OAComputers/
AHMED THAKUR [email protected], 0300-8268885
CAMBRIDGE COMPUTER SCIENCE AHMED THAKUR
Q1 2016-Nov, P13

1 In anyorder:

– Fetch
– Decode
– Execute [3]

Q2 2015-Nov, P13

3 (a) (i)
MAR 1 0 0 0 0 0 0 1

MDR 0 1 0 1 0 0 0 1

[2]
(ii)
MAR 1 0 0 0 1 1 1 0

MDR 0 1 1 1 1 0 0 1

[2]
(iii)
Address Contents
1000 0000 0110 1110
1000 0001 0101 0001
1000 0010 1000 1101
1000 0011 1000 1100

1000 1100
1000 1101
1000 1110 0111 1001
1000 1111
[1]

(b) – CIR (Current Instruction Register)


– PC (Program Counter)
– Acc (Accumulator) [3]

https://www.facebook.com/groups/OAComputers/
AHMED THAKUR [email protected], 0300-8268885
CAMBRIDGE COMPUTER SCIENCE AHMED THAKUR
(c) – Controls operation of memory, processor and input / output
– Instructions are interpreted
– Sends signals to other components telling them “what to do” [3]

Q3 2015-June,P11

(b)
description of stage sequence
number

the instruction is then copied from the memory location contained in the
MAR (memory address register) and is placed in the MDR (memory data 3
register)

the instruction is finally decoded and is then executed 7

the PC (program counter) contains the address of the next instruction to be (1)
fetched

the entire instruction is then copied from the MDR (memory data register)
4
and placed in the CIR (current instruction register)

the address contained in the PC (program counter) is copied to the MAR


2
(memory address register) via the address bus

the address part of the instruction is placed in the MAR (memory address
6
register)

the value in the PC (program counter) is then incremented so that it points


5*
to the next instruction to be fetched

The incrementation of the program counter can appear at any stage after 2. All other
stages must be in the correct given order. [6]

https://www.facebook.com/groups/OAComputers/
AHMED THAKUR [email protected], 0300-8268885

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