REGNO:

St.JOSEPH’S COLLEGE OF ENGINEERING

St.JOSEPH’S INSTITUTE OF TECHNOLOGY

MODEL EXAM- APRIL 2020

Subject: COMPUTER ARCHITECTURE Code: CS8491

Branch: Common to CSE/IT Sem: IV

Duration: 3 hours MAX MARKS: 100

PART- A (10 X 2 = 20 Marks)

1. What are the addressing modes and its various types? (2) CO1 Remember
2. Classify the instructions based on the operations they (2) CO1 Remember
perform and give one example to each category.
3. Convert (1.00101)2 to decimal (2) CO2 Evaluate
4. Subtract (11011)2-(10011)2 using 2‘s complement. (2) CO2 Evaluate
5. Name the control signals required to perform arithmetic (2) CO3 Remember
operations.
6. Convert the following code segment in C to MIPS (2) CO3 Analyze
instructions, assuming all variables are in memory and are
addressable as offsets from $t0:
a=b+c: c=b+f:
7. What are the properties of Multi-Core Systems? (2) CO4 Remember
8. Define GPUs. (2) CO4 Remember
9. What do you mean by static memories? (2) CO5 Remember
10. Define Hit and Miss in cache. (2) CO5 Remember
PART –B ( 5 x 13 = 65 Marks)

11. a (i)Consider the computer with three instruction classes (16 CO Analyze
and CPI measurements as given below and Instruction ) 1
counts for each instruction class for the same program
from two different compilers are given. Assume that the
computer’s clock rate is 4GHZ. Which Code sequence
will execute faster according to execution time?
Code from CPI for this Instruction Class

A B C

CPI 1 2 3

Code from Instruction Count for each Class

Compiler 1 2 1 2
Compiler 2 4 1 1
 (ii) Our favourite program runs in 10 seconds on computer
A, which has a 2 GHz clock. We are trying to help a
computer designer build a computer Which will run this
program in 6 seconds. The designer has determined that a
substantial increase in the clock rate is possible, but this
increase will affect the rest of the CPU design, causing
computer B to require 1.2 times as many clock cycles as
computer A for this program. What clock rate should we
tell the designer to target?

OR

11.b Explain various instruction formats and illustrate the same (16 CO Remember
with an example. ) 1

12. a i) Perform X + Y and Y-X using 2’s complements for (16 CO Evaluate
given two binary numbers X = 0000 1011 1110 1111 and ) 2
Y = 1111 0010 1001 1101. (8)

ii)Express (0.5)10 in single precision and double precision

OR

12.b In a small town, there are three temples in a row and a well (16 CO Evaluate
in front of each temple. A pilgrim came to the town with ) 2
certain number of flowers.
Before entering the first temple, he washed all the flowers
he had with the water of well. To his surprise, flower
doubled. He offered few flowers to the God in the first
temple and moved to the second temple. Here also, before
entering the temple he washed the remaining flowers with
the water of well. And again his flowers doubled. He
offered few flowers to the god in second temple and
moved to the third temple. Here also, his flowers doubled
after washing them with water. He offered few flowers to
the God in third temple.
There were no flowers left when pilgrim came out of third
temple and he offered same number of flowers to the God
in all three temples. What is the minimum number of
flowers the pilgrim had initially (X)? And find the value of
(X/3) using Restoring Division method? How many
flowers did he offer to each God (Y)? And find the value
of (Y/3) using Non-Restoring Division method?

13. a Explain the pipeline hazards in detail (16 CO Remember

OR

13.b A pipelined processor uses the delayed branch (16 CO Analyze &
 technique. You are asked to recommend one of two ) 3 Evaluate
possibilities for the design of the processor. In the
first possibility, the processor has a 4- stage pipeline
and one delay slot, and in the second possibility it has
a 6-stage pipeline with two delay slots. Assume that
20% of the instructions are branch instructions and
that an optimizing compiler succeeds in filling 80%
of the single delay slot. For the second alternative,
the compiler is able to fill the second slot 25% of the
time.

14. a Explain with diagrammatic illustration Flynn’s (16 CO Remember

OR

14. b Explain about the Computer Architecture Of (16 CO Remember

15. a Define Cache Memory? Explain various mapping (16 CO Remember

OR

15.b Assume the miss rate of an instruction cache is 2% and (16 CO Analyze &
the miss rate of the data cache is 4%.If a processor has a ) 5 Evaluate
CPI of 2 without any memory stalls and the miss
penalty is 100 cycles for all misses, determine how
much faster a processor would run with a perfect cache
that never missed. Assume the frequency of all loads
and stores is 36%.

PART –C ( 1 x 15 = 15 Marks)

16.a To achieve the speedup of 31.15 on bigger problem size (15 CO Analyze &
(addition of 40*40matrix and 20 scalar variables) with 50 ) 4 Evaluate
processors, we assumed that the load was perfectly
balanced. That is, each of the 50 processors performs 2%
of the work. In this problem, we have to calculate the
impact on speedup if one processor’s load is higher than
all the rest. Calculate the impact on speedup if the hardest
working processor’s load is 4% and 10%. Also calculate
the utilization of the rest of the processors?

OR

16. b Consider a direct-mapped cache memory organization in (15 CO Analyze &

B) What is the size of the cache memory?

C) How many address lines are needed for addressing

D) What is the size of WORD, BLOCK, and TAG fields?