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Computer Architecture: 1. Draw A Diagram Single Bus Organization of The Data Path Inside A Processor

The document discusses various aspects of computer architecture including: 1. Drawing diagrams of single bus organization and register transfer inside a processor. 2. Explaining how a processor fetches a word from memory by using a memory function complete (MFC) signal to wait for read operations to complete. 3. Defining interrupts and interrupt requests, and how interrupts can be enabled and disabled through program control.

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4K views

Computer Architecture: 1. Draw A Diagram Single Bus Organization of The Data Path Inside A Processor

The document discusses various aspects of computer architecture including: 1. Drawing diagrams of single bus organization and register transfer inside a processor. 2. Explaining how a processor fetches a word from memory by using a memory function complete (MFC) signal to wait for read operations to complete. 3. Defining interrupts and interrupt requests, and how interrupts can be enabled and disabled through program control.

Uploaded by

md sayem
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Computer Architecture

1. Draw a diagram single bus organization of the data path inside a processor.

2. Draw a diagram with register transfer.


3. How to fetch a word from Memory?

To accommodate variability in response time, the processor wait until received a indication that the requested
read operation has been completed – MFC (Memory-Function-Completed) control signal used for this
purpose.
As an example of a read operation, consider the instruction move (R1),R2. The actions needed to execute this
instruction are:
1. MAR← [R1]
2. Start a read operation on the memory bus
3. Wait for the MFC response from the memory
4. Load MDR from the memory bus
5. R2←[MDR]

1. R1out, MARin, Read


2. MDRin E, WMFC
3. MDRout, R2in

Where WMFC is the control signal that causes the processor’s control circuitry to wait for the arrival of the
MFC signal.
4. What is interrupt and interrupt request? Enabling and disabling interrupt.

Interrupt: We already notice that an I/O device requests an interrupt by activating a bus line called
interrupt-request.

interrupt request: Most computer are likely to have several I/O devices that can request an interrupt.
A single interrupt-request line may be used to serve n devices as depicted in the below figure-

Enabling and disabling interrupt:


• The facilities provided in a computer must give the programmer complete control over the events that
take place during program execution.
• The arrival of an interrupt request from an external device causes the processor to suspend the
execution of one program and start the execution of another.
• Because interrupts can arrive any time, they may alter the sequence of events from that visualized by
the programmer.
• Hence, the interruption of program execution must be carefully controlled.
• A fundamental facility found in all computers is ability to enable and disable such interruption as
desired.
• There are many situation in which the processor should ignore interrupt request.
• In another case, it may necessary to guarantee that a particular sequence of instructions is executed to
the end without interruption because interrupt-service routine may change some of the data used by
the instructions in question.
• For these reason, some means for enabling and disabling interrupts must be available to the
programmer.

5. Draw a interrupt hardware implementation arrangement of priority group to serve n devices.


Explain how the devices will be served in the priority group scheme arrangement.
Interrupt Hardware:
• All devices are connected to the line via switches to ground.
• To request an interrupt, a device closes its associated switch. Thus, if all interrupt-request signal INTR 1 to
INTRn are inactive, that is, if all switches are open, the voltage on the interrupt-request line will be equal
to Vdd. This the inactive state of the line.
• When a device requests an interrupt by closing its switch, the voltage on the line drop to 0, causing the
interrupt-request signal, INTR, received by the processor to go to 1.
• Since the closing of one or more switches will cause the line voltage to drop to 0, the value of INTR is
logical OR of the request from individual devices, that is

INTR = INTER1 +…+ INTRn


• It customary to use the complemented form to name the interrupt-request signal on the common
line, because the signal is active when in the low-voltage state.
• In the electronic implementation of the circuit, special gates known as open-controller (for bipolar
circuit) or open-drain (for MOS circuit) are used to drive the line.

6. Figure with I/O devices for an input Devices.

A simple arrangement to connect I/O devices to a computer is to use a single bus arrangement.

The Bus enables all the devices connected to it to exchange information. Typically, it consists of three sets of
lines used to carry address, data, and control signals.
Each I/O device is assigned a unique set of addresses. When the processor places a particular address on the
address lines, the device that recognizes this address responds to the commands issued on the control lines.
The processor requests either a read or a write operation, and the requested data are transferred over the data lines.
When I/O devices and the memory share the same address space, the arrangement is called memory-mapped I/O.
With memory-mapped I/O, any machine instruction can access memory can be used to transfer data to or from an
I/O device. For example, if DATAIN is address of the input buffer associated with the keyboard, the instruction
Most computer systems use memory-mapped I/O. Some processor have special In and Out instructions to perform
I/O transfer.
For Example Processor in Intel family have special I/O instruction and a separate 16- bit address space for I/O
devices.
One advantage of a separate I/O address space is that I/O devices deal with fewer address lines.

7. What is data and control signals?


Data: Data is a collection of facts, such as numbers, words, measurements, observations or just descriptions
of things.
Control Signals:
A pulse or frequency of electricity or light that represents a control command as it travels over a network, a computer ch
annel or wireless. In the data communications world,control signals typically travel the same path as the data either as se
parate packets or contained within the data packets. In the traditional telephone communications world, control signals ar
e sent over a separate network.
8. Figure with single bus structure.

In single bus structure inside the CPU, different components are linked by a single bus. The various
components available inside CPU in this architecture includes Instruction Register (IR), Instruction Decoder
(ID), Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Arithmetic
and Logic Unit (ALU) and General purpose Register. Now, the question is what are CPU registers and what
are the types of registers used in single bus structure Let’s discuss these in details.

9. Execution a complete instruction in three buses.


Step Action:

1. PCout, R=B, MARin, Read, IncPC


2. WMFC
3. MDRout B, R=B, IRin
4. R4outA, R5outB, Select A, Add, R6in, End

10. Draw a basic organization of control unit.

11. What is interrupt nesting? Define interrupt-request line & interrupt service routine.

interrupt nesting: The mechanism by which one interrupt preempts another is called nesting. The handling
of nested interrupts can be unpredict- able. Other issues can arise, such as a variable amount of delay prior to
servicing a low-priority interrupt, or a higher program stack size requirement.

interrupt-request line: Abbreviation of interrupt request line, and pronounced I-R-Q. IRQs


are hardware lines over which devices can send interrupt signals to the microprocessor. When you add a new
device to a PC, you sometimes need to set its IRQ number by setting a DIP switch. This specifies which
interrupt line the device may use. IRQ conflicts used to be a common problem when adding expansion
boards, but the Plug-and-Play specification has removed this headache in most cases.

interrupt service routine: In computer systems programming, an interrupt handler, also known as an
interrupt service routine or isr , is a callback function in microcontroller firmware, an operating system, or a
device driver whose execution is triggered by the reception of an interrupt. when interrupt is generated the
cpu jumps to a special code call isr address.

12. Block diagram of a complete processor.

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