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HDL 2017 PDF

This document contains 8 questions related to hardware description languages. [1] The questions cover topics like VHDL design units, data types, behavioral and structural modeling, [2] Verilog concepts like registers, nets, vectors, tasks and blocking/non-blocking assignments, [3] SystemC topics such as modules, ports, data types and modeling half adders and flip-flops.

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Utkarsh Ugvekar
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
34 views

HDL 2017 PDF

This document contains 8 questions related to hardware description languages. [1] The questions cover topics like VHDL design units, data types, behavioral and structural modeling, [2] Verilog concepts like registers, nets, vectors, tasks and blocking/non-blocking assignments, [3] SystemC topics such as modules, ports, data types and modeling half adders and flip-flops.

Uploaded by

Utkarsh Ugvekar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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B.E. (ETC/ECE) (Semester - VII) (RC) Examination, May/Jun e 2017


HARDWARE DESCRIPTION LANGUAGES (Elective - l)

Duration : 3 Hours Max. Marks : 100

lnstructions: 1) Attempt any 5 questions by taking at least one question


from each Module.
2) Assume suitable data if necessary.
3) Symbols and abbreviations havetheir usual meaning

MODULE - I

1. a) Explain with examples the following design units in VHDL.


i) Library
ii) Architecture
iii) Entity" 6
b) Differentiate between signal and variable in VHDL. Write the code for a
4 x 1 multiplexer using variable data object. 8
c) Given X<="01001"; tndicate the result of the following operations :

i) Y.=x sla 2
ii) Y<=x rol - 3. 2
d) Explain the array data type in VHDL with examples. 4

2. a) Explain the constructs of behavioural modeling in VHDL. Write the code for a
SISO in behavioural modeling. 10

b) Explain the record and physical data types with examples. 6


c) Given the following declarations : 4
Signal a: BIT:='1';
Signal b : BIT_VECTOR(3 downto 0):="1 100";
Signalc : BIT_VECTOR(3 downto 0):="0010";
Signal d : BIT_VECTOR(7 downto 0);
Signal e : Integer range - 128to 127;
i) Perform the following operations and indicate results of x1 , x2, x3 and x4 :

x1 <=a & c'


x2<= a NOR b(3);
x3<=a AND NOT b(0) AND NOT c(1);
x4<=b sla2: p.T.o.
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ii) Justify if the following operations are legal or illegal.


i) a + d(7)
ii) NOT b NOR c
iii) B sra 1

iv) D(6 downto 4)<=b;

MODULE _ II

3. a) Explain the term GENERIC in VHDL. Write the code for a Generic Ripple
Carry Adder. 8
b) Differentiate between simple and guarded block statements. 4
c) Given the declaration : 3
Signal D : std*logic_vector (7 downto 0);
Explain the following attributes :

D'LOW, D'LEFT, D'REVERSE RANGE, D'LENGTH, D'STABLE.


d) Write the code for a JK FF in concurrent style of modeling. 5

4. a) Differentiate between functions and procedures. Write a function in VHDL to


convert a STD_LOGIC_VECTOR to an INTEGER. 10
b) Explain configurations and packages with an example. 6
c) l-ist the various constructs of structural Modeling in VHDL. 4

MODULE _ III

5. a) Explain the following in verilog with examples :

i) Registers
ii) Nets
iii) Vectors.
b) Explain functions in Verilog. Write a function to calculate the factorial of a
number. 6
c) Write the verilog code for a RAM block to store 16 words of one byte each. I
a) A circuit has two 16-bit numbers A and B as input. The output of the circuit is
the Bitwise-OR and Bitwise-XOR of A and B. Write a verilog code to model
this circuit using tasks. T
ililil11tililil||tililil11|il|ilililil|||ilil|il|tilililililil||] ETC/ECE -7 (E- t) (3) (RC)
b) With examples illustrate the use of blocking and non-blocking assignments
in verilog. 6
c) Explain the various operators available in the verilog language. 7

MODULE * IV

7 ^ a) Write a verilog code for the following state machine : I

b) Explain the following semantics of system C :

i) sc_MoDULE
ii) sc_cToR
iii) sc_Brr
iv) SC_Method.
c) Write the system C code for a Half Adder.
8. a) List some commonly used FPGAs of the Xilinx Family. Explain the design
steps using FPGAs. 6
b) Write the System C code for a SR FF using case statements. 7
c) Explain the various data types in the System C language. 7

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