Module 4: Serial Interfaces

Mazen A. R. Saghir

Department of Electrical and Computer Engineering

Full Version

AUB Logo
The AUB logo, as seen on the left, constitutes
the main element of the University’s visual
identity system.

There are two versions of the logo. The full

version of the logo includes the name of the
University spelled out in both English and Arabic
at the bottom. The concise version consists of
the seal, the tree and the acronym only.

The full version of the AUB logo must be used

for official University stationery as well as
Concise Version on both the internal and external websites.
Examples of stationery are included in the
Stationery section of this manual.

The concise version of the logo may appear on

mediums such as brochures, leaflets, banners,
posters, and on merchandise items including
shirts, uniforms, and promotional items. It is
also available for digital use such as digital
presentations.

The logo, either the full or the concise

version, must be used on all official AUB
communications in accordance with some basic
guidelines explained on the following pages.

AUB Logo 2. AUB Logo. 6

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 1 / 60

RS-232C Interface Hardware

+3.3V
0.1F
16 0.1F DB9 female
1
0.1F MAX 2 Vss
TM4C123 3 +5.5V
3232 5
4 6 -5.5V
0.1F 9
0.1F
5 4

PA1/U0Tx RxD 9 8 Sin 8

PA0/U1Rx 3
PB1/U1Tx TxD 10 7 Sout 7
PB0/U1Rx 2
PD7/U2Tx
PD6/U2Rx 6
15
1

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 2 / 60

RS-232C Waveform

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 3 / 60

Universal Asynchronous Receiver Transmitter (UART)

A peripheral controller used to transmit and receive serial data.

Universal: Data format can be configured: 5-8 data bits; even, odd,
or no parity bit; 1 or 2 stop bits.
– Example: 8-N-1 = 8 data bits; No parity; 1 stop bit.

Asynchronous: Data is transmitted/received without reference to

a common clock.
– Communicating devices typically operate at the same baud rate.
– For UARTs, baud rate = bit rate (e.g. 9600 bits/second).

Receiver/Transmitter: A UART is used both to receive and transmit

data, often at the same time (i.e. full duplex communication).

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 4 / 60

8-N-1 Data Frame

One frame

Serial port Start b b b b b b

3.3V
0 2 3 4 5 b6
b 7 Stop
1 0V

Data frame = 1 start bit + 8 data bits (LSB first) + 0 parity bit +
1 stop bit = 10 bits/frame.

At 115200 baud, the effective bit rate = 115200 × 8/10 = 92160 bps.

Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi 12-5

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 5 / 60

Data Integrity

During data transfers some bits might become corrupted due to noise
or interference. Such errors can be easily detected using parity
checks.

When configured to use even parity, a UART transmits an additional

parity bit whose value ensures that the total number of 1’s (data +
parity) is an even number. Odd parity works the same way, but
requires the total number of 1’s to be an odd number.

The receiving UART, which also must be configured to use even

parity, counts the number of received (data + parity) 1’s. If the number
is even it knows there were no transmission errors. Otherwise there is
an error and the data must be re-transmitted.

Parity checks cannot detect multiple bit errors. More complex cyclic
redundancy checks can be used.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 6 / 60

UART Transmitter
UART - Transmitter

Stop 7 6 5 4 3 2 1 0 Start
Shift 1 Data 0 U0Tx
clock
Transmit shift register
16-element
FIFO TXEF Fifo empty flag

TXFF Fifo full flag

Write data UART0_DR_R
Transmit data register
Copyright
c Jonathan Valvano

Bard, Erez, Janapa Reddi, Gerstlauer, Telang, Tiwari, Valvano, Yerraballi 12-10
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 7 / 60
UART Transmitter Operation

Data is written to the UART0 DR R register.

– Data passes through the 16-element FIFO buffer.
– This permits a small amount of data-rate matching between the
processor and the UART.
– TXFE and TXFF flags can be examined by software to determine when
new data can be written into UART0 DR R. This simplifies busy-wait
synchronization.

Shift clock is generated from a 16× clock (Baud16)

– Helps overcome phase differences between transmitter and receiver
clocks.
– When the receiver detects a start bit (idle to low transition), it counts 8
shift clock cycles before sampling the start bit on the data line. It then
counts 16 shift clock cycles to sample each of the remaining frame bits.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 8 / 60

UART Receiver
UART - Receiver

Stop 7 6 5 4 3 2 1 0 Start
Shift 1 Data 0 U0Rx
clock OE BE PE FE Receive shift register
RXFE Fifo empty flag
12-bit, 16-element
FIFO
RXFF Fifo full flag
Read data UART0_DR_R
Receive data register
Copyright
c Jonathan Valvano

Bard, Erez, Janapa Reddi, Gerstlauer, Telang, Tiwari, Valvano, Yerraballi 12-12
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 9 / 60
UART Receiver Operation
Data is read from the UART0 DR R register.
– Although this is the same register used for transmitting data, and has
the same address, the transmitter and receiver use two, separate,
physical registers.
– RXFE and RXFF flags can be examined by software to determine
when new data can be read from UART0 DR R.
– RXFE = 0 when data is available. RXFF = 1 when FIFO is full. This
simplifies busy-wait synchronization.

In addition to data, each FIFO entry includes four control bits:

– BE is set when there is a break error. This occurs when the Tx signal
is held low for more than one frame.
– OE is set when there is an overrrun error. This occurs when the FIFO
is full and a new frame arrives.
– PE is set when there is a parity error.
– FE is set when there is a framing error. This occurs if there is a stop
bit timing error, which occurs when there is a mismatch between
transmitter and receiver baud rates.
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 10 / 60
UART Overrun Error

UART – Overrun Error

Occurs when 17 frames are recieved but none are read.

CDEFGHIJKLMNO
"A"=$41 "B"=$42 "P"=$50 "Q"=$51
s 0 1 2 3 4 5 6 7 s s 0 1 2 3 4 5 6 7 s s 0 1 2 3 4 5 6 7 s s 0 1 2 3 4 5 6 7 s

RXFE=0 RXFF=1 OE=1

Copyright
c Jonathan Valvano

17 frames transmitted and none read

=> overrun error

Bard,
M. Saghir (EECE 425Erez, Janapa
– Spring 2020) Reddi, Gerstlauer, Telang,
Serial Tiwari, Valvano, Yerraballi
Interfaces 12-14 11 / 60
UART0 Registers
TM4C UART0 – Registers
31–12 11 10 9 8 7–0 Name
$4000.C000 OE BE PE FE DATA UART0_DR_R

31–3 3 2 1 0
$4000.C004 OE BE PE FE UART0_RSR_R

31–8 7 6 5 4 3 2–0
$4000.C018 TXFE RXFF TXFF RXFE BUSY UART0_FR_R

31–16 15–0
$4000.C024 DIVINT UART0_IBRD_R

31–6 5–0
$4000.C028 DIVFRAC UART0_FBRD_R

31–8 7 6–5 4 3 2 1 0
$4000.C02C SPS WPEN FEN STP2 EPS PEN BRK UART0_LCRH_R

31–10 9 8 7 6–3 2 1 0
$4000.C030 RXE TXE LBE SIRLP SIREN UARTEN UART0_CTL_R

31–6 5-3 2-0

$4000.C034 RXIFLSEL TXIFLSEL UART0_IFLS_R

31-11 10 9 8 7 6 5 4
$4000.C038 OEIM BEIM PEIM FEIM RTIM TXIM RXIM UART0_IM_R
$4000.C03C OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS UART0_RIS_R
$4000.C040 OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS UART0_MIS_R
$4000.C044 OEIC BEIC PEIC FEIC RTIC TXIC RXIC UART0_IC_R

Copyright
c Jonathan Valvano
Bard,(EECE
M. Saghir Erez,
425Janapa Reddi,
– Spring 2020) Gerstlauer,Serial
Telang, Tiwari, Valvano, Yerraballi
Interfaces 12-13
12 / 60
Setting UART Baud Rate

The UART’s baud rate is set by writing appropriate values in the

UART0 IBRD R and UART0 FBRD R registers.

The registers are used to store the value of a 22-bit clock divider that
consists of a 16-bit integer (in UART0 IBRD R) and a 6-bit fraction
(in UART0 FBRD R).

The divider is used to set the Baud16 rate:

Baud16 = system clock frequency/divider

The baud rate is derived from Baud16:

Baud rate = Baud16/16 = (system clock frequency)/(16 × divider)

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 13 / 60

Setting UART Baud Rate (2)

Example: If the system clock is 8 MHz and we need to set the baud
rate to 19200 bits/sec, the value of the divider must be:
8000000/(16 × 19200) = 26.04167.

So we store 26 (110102 ) in UART0 IBRD R and 3 (0000112 ) in

UART0 FBRD R.

Notice that 3/64 = 0.046875, so that the actual divider value is

26.046875. This corresponds to a 0.02% error compared to the
desired divider value.

The transmitter and receiver baud rates must be with 5% of each

other for the channel to operate properly.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 14 / 60

Initializing the UART

// - - - - - - - - - - - - UART_Init - - - - - - - - - - - -
// Initialize the UART for 115 ,200 baud rate ( assuming 50 MHz UART clo
// 8 bit word length , no parity bits , one stop bit , FIFOs enabled
// Input : none
// Output : none
void UART_Init ( void ){
S Y S C T L _ R C G C U A R T _ R |= 0 x01 ; // activate UART0
S Y S C T L _ R C G C G P I O _ R |= 0 x01 ; // activate port A
while (( SY SC TL _ PR GP IO _ R &0 x01 ) == 0){};
UART0_CTL_R &= ~ U AR T_C TL _U AR T EN ; // disable UART
UART0_IBRD_R = 27; // IBRD = int (50 ,000 ,000 / (16
UART0_FBRD_R = 8; // FBRD = int (0.1267 * 64 + 0.
// 8 bit word length ( no parit
UART0_LCRH_R = ( U A R T _L C R H _ W L EN _ 8 | UART_LCRH_FEN );
UART0_CTL_R |= U AR T_ CT L _U AR TE N ; // enable UART
G P I O _ P O R T A _ A F S E L _ R |= 0 x03 ; // enable alt funct on PA1 -0
G P I O _ P O R T A _ D E N _ R |= 0 x03 ; // enable digital I / O on PA1 -0
// configure PA1 -0 as UART
G P I O _ P O R T A _ P C T L _ R = ( G P I O _ P O R T A _ P C T L _ R &0 xFFFFFF00 )+0 x00000011 ;
G P I O _ P O R T A _ A M S E L _ R &= ~0 x03 ; // disable analog functionalit
}

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 15 / 60

UART Busy-Wait Read and Write

// - - - - - - - - - - - - UART_InChar - - - - - - - - - - - -
// Wait for new serial port input
// Input : none
// Output : ASCII code for key typed
char UART_InChar ( void ){
while (( UART0_FR_R & UART_FR_RXFE ) != 0);
return (( char )( UART0_DR_R &0 xFF ));
}

// - - - - - - - - - - - - UART_OutChar - - - - - - - - - - - -
// Output 8 - bit to serial port
// Input : letter is an 8 - bit ASCII character to be transferred
// Output : none
void UART_OutChar ( char data ){
while (( UART0_FR_R & UART_FR_TXFF ) != 0);
UART0_DR_R = data ;
}

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 16 / 60

UART Interrupts
UARTs on the TM4C can be configured to generate interrupts under
one or more of the following conditions:
– Overrun error: New data is received while receive buffer is full.
– Break error: Rx signal is held low for more than the duration of a
single frame.
– Parity error: Number of 1’s in a frame differs from set parity.
– Framing error: Mismatch between transmitter and receiver baud rates.
– Receive timeout: Internal timer expires before data in a full receive
buffer is read and processed. Timer is automatically reset when data is
read from the receive buffer.
– Transmit: UART is ready to send data.
– Receive: UART has received new data.

If one or more of these conditions occur, only one interrupt is

generated by the UART. Similarly, only one interrupt handler is
executed in response to a UART interrupt. The interrupt handler
checks the UART status register to determine which conditions
caused the interrupt.
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 17 / 60
UART Interrupt Registers

UARTs on the TM4C use a number of registers to configure

interrupts.

UART Interrupt FIFO Level Select (UARTx IFLS R): This register
specifies the FIFO level (1/8 full, 2/8 full, 3/8 full, etc... ) at which
receive and transmit interrupts are triggered. The register uses two,
3-bit fields (RXIFLSEL and TXIFLSEL) to configure the receive and
transmit FIFO levels, respectively.

UART Interrupt Mask (UARTx IM R): Bits 10-4 of this register are
used to arm/disarm the corresponding seven UART interrupt
conditions.

UART Raw Interrupt Status (UARTx RIS R): Provides the current raw
status (i.e. pending or not) of the corresponding interrupt.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 18 / 60

UART Interrupt Registers (2)

UART Masked Interrupt Status (UARTx MIS R): Bits 10-4 of this
register indicate whether a corresponding interrupt has occured or
not.

UART Interrupt Clear (UARTx ICR R): Writing 1’s to bits 10-4 of this
register clears and acknowledges the corresponding interrupts.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 19 / 60

UART Interrupt Initialization
# define NVIC_EN0_IRQ5 0 x00000020 // IRQ5 ( UART0 ) enable
# define U A R T _ L C R H _W L E N _ 8 0 x00000060 // 8 bit word length
# define UART_LCRH_FEN 0 x00000010 // UART Enable FIFOs
# define U A RT _C TL _ UA RT EN 0 x00000001 // UART Enable
# define U A RT _I FL S _R X1 _8 0 x00000000 // RX FIFO >= 1/8 full
# define U A RT _I FL S _T X1 _8 0 x00000000 // TX FIFO <= 1/8 full
# define UART_IM_RTIM 0 x00000040 // Rx Time - Out Int Mask
# define UART_IM_TXIM 0 x00000020 // Tx Int Mask
# define UART_IM_RXIM 0 x00000010 // Rx Int Mask

void UART_Init ( void ){

S Y S C T L _ R C G C U A R T _ R |= 0 x01 ; // activate UART0
S Y S C T L _ R C G C G P I O _ R |= 0 x01 ; // activate port A

RxFifo_Init (); // init empty software FIFOs

TxFifo_Init ();

UART0_CTL_R &= ~ U AR T_C TL _U AR T EN ; // disable UART

// Assuming 80 MHz clock , set baud rate to 115200
UART0_IBRD_R = 43; // int ( 8 0 0 0 0 0 0 0 / ( 1 6 * 1 1 5 2 0 0 ) ) = 43
UART0_FBRD_R = 26; // int ( 0. 4 02 8* 64 + 0. 5) = 26
// 8 bit word length ( no parity bits , one stop bit , FIFOs )
UART0_LCRH_R = ( U A R T _L C R H _ W L EN _ 8 | UART_LCRH_FEN );
...
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 20 / 60
UART Interrupt Initialization (2)

...
// clear TXIFLSEL and RXIFLSEL FIFO level fields
UART0_IFLS_R &= ~0 x3F ;
// configure interrupt for TX FIFO <= 1/8 full
// configure interrupt for RX FIFO >= 1/8 full
UART0_IFLS_R += ( UA RT _ IF LS _T X 1_ 8 | U AR T_ I FL S_ R X1 _8 );
// enable TX and RX FIFO interrupts and RX time - out interrupt
UART0_IM_R |= ( UART_IM_RXIM | UART_IM_TXIM | UART_IM_RTIM );
UART0_CTL_R |= U AR T_ CT L _U AR TE N ; // enable UART

G P I O _ P O R T A _ A F S E L _ R |= 0 x03 ; // enable alt funct on PA1 -0

G P I O _ P O R T A _ D E N _ R |= 0 x03 ; // enable digital I / O on PA1 -0
// configure PA1 -0 as UART
G P I O _ P O R T A _ P C T L _ R = ( G P I O _ P O R T A _ P C T L _ R &0 xFFFFFF00 )+0 x00000011 ;
G P I O _ P O R T A _ A M S E L _ R = 0; // disable PA analog functionality

// Set UART0 priority 2 in NVIC_PRI0_R bits 13 -15

NVIC_PRI1_R = ( NVIC_PRI1_R &0 xFFFF00FF )|0 x00004000 ;
NVIC_EN0_R = NVIC_EN0_IRQ5 ; // enable IRQ5 ( UART0 ) in NVIC
E n a b l e I n t e r r u p t s (); // enable global interrupts in the processor
}

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 21 / 60

UART Character Input/Output Functions

// input ASCII character from UART

// spin if RxFifo is empty
char UART_InChar ( void ){
char letter ;
// RxFifo_Get is the software FIFO read function .
// Read fails when FIFO is empty . Busy - wait until data is read .
while ( RxFifo_Get (& letter ) == FIFOFAIL ){};
return ( letter );
}

// output ASCII character to UART

// spin if TxFifo is full
void UART_OutChar ( char data ){
// TxFifo_Put is the software FIFO write function .
// Write fails when FIFO is full . Busy - wait until data is written .
while ( TxFifo_Put ( data ) == FIFOFAIL ){};
UART0_IM_R &= ~ UART_IM_TXIM ; // disable TX FIFO interrupt
c o p y S o f t w a r e T o H a r d w a r e (); // Critical section
UART0_IM_R |= UART_IM_TXIM ; // enable TX FIFO interrupt
}

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 22 / 60

UART Hardware/Software FIFO Transfer Functions

// copy from hardware RX FIFO to software RX FIFO

// stop when hardware RX FIFO is empty or software RX FIFO is full
void static c o p y H a r d w a r e T o S o f t w a r e ( void ){
char letter ;
while ((( UART0_FR_R & UART_FR_RXFE ) == 0) &&
( RxFifo_Size () < ( FIFOSIZE - 1))){
letter = UART0_DR_R ;
RxFifo_Put ( letter );
}
}

// copy from software TX FIFO to hardware TX FIFO

// stop when software TX FIFO is empty or hardware TX FIFO is full
void static c o p y S o f t w a r e T o H a r d w a r e ( void ){
char letter ;
while ((( UART0_FR_R & UART_FR_TXFF ) == 0) && ( TxFifo_Size () > 0)){
TxFifo_Get (& letter );
UART0_DR_R = letter ;
}
}

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 23 / 60

UART Interrupt Handler Function

void UART0_Handler ( void ){

if ( UART0_RIS_R & UART_RIS _TXRIS ){ // hardware TX FIFO <= 2 items
UART0_ICR_R = UART_ICR_TXIC ; // acknowledge TX FIFO
// copy from software TX FIFO to hardware TX FIFO
c o p y S o f t w a r e T o H a r d w a r e ();
if ( TxFifo_Size () == 0){ // software TX FIFO is empty
UART0_IM_R &= ~ UART_IM_TXIM ; // disable TX FIFO interrupt
}
}
if ( UART0_RIS_R & UART_RIS _RXRIS ){ // hardware RX FIFO >= 2 items
UART0_ICR_R = UART_ICR_RXIC ; // acknowledge RX FIFO
// copy from hardware RX FIFO to software RX FIFO
c o p y H a r d w a r e T o S o f t w a r e ();
}
if ( UART0_RIS_R & UART_RIS _RTRIS ){ // receiver timed out
UART0_ICR_R = UART_ICR_RTIC ; // acknowledge receiver time out
// copy from hardware RX FIFO to software RX FIFO
c o p y H a r d w a r e T o S o f t w a r e ();
}
}

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 24 / 60

Synchronous Serial Interface (SSI)

A low-cost, bi-directional (full duplex), serial interface used to connect

peripheral devices to microcontrollers. SSI is also called serial
peripheral interface (SPI).

Because SSI is a synchronous communication protocol, all data

transfers are synchronized to a system clock.

The clock signal is generated by the master device (sender); a slave

device (receiver) uses the clock to synchronize its acquisition of the
serial bit stream.

Many devices can be connected to the same SSI interface. The

master device selects a slave device by asserting its select input.
Devices not selected will ignore the data transfer.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 25 / 60

SSI signals

SSI uses four signals:

– Master Out Slave In (MOSI)
– Master In Slave Out (MISO)
– Serial Clock (SCLK or SCK). Generated during a data transfer only.
– Chip (or Slave) Select (CS or SS). Must be asserted for data to be
transferred.

SCLK SCLK
SPI MOSI MOSI SPI
Master MISO MISO Slave
SS SS

Copyright
c Wikipedia

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 26 / 60

Connecting a SSI Master to Multiple Slave Devices

SCLK SCLK
MOSI MOSI SPI
SPI MISO MISO Slave
Master SS1 SS
SS2
SS3
SCLK
MOSI SPI
MISO Slave
SS

SCLK
MOSI SPI
MISO Slave
SS

Copyright
c Wikipedia

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 27 / 60

 and slaves contain a serial shift register. The master starts
SSI Data Transfers
ng it to its SPI shift register. As the register transmits th
MOSI Asignal
SSI dataline, theinvolves
transfer slave both
transfers theslave
master and contents
devices of its shift
on the MISO8 signal
exchanging line
bits of data (Figure 7-2).
simultaneously, one bitInatthis way, the co
a time.
sters Two
are shift
exchanged. Both a write and a read operation a
registers are used during the transfer, one on the master
e simultaneously.
side and anotherSPI can
on the therefore
slave be a very
side. Bits shifted out of efficient
the master proto
register are shifted into the slave register, and vice-versa.

Processor Peripheral
MOSI
SPI data SPI data
register register
MISO

transmission
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 28 / 60
SSI Data Transfers (2)

The SSI master initiates all data transfers. SSI slaves respond to data
transfer commands requesting access to their internal registers.

Data Read Command

– SSI master sends a read command and a slave device register
address. Slave device sends the requested data.
– The transaction involves the transfer of three bytes in both directions.
– SSI master ignores the first two bytes it receives, and slave device
ignores the third byte it receives.

Data Write Command

– SSI master sends a write command, a slave device register address,
and the data to be transferred.
– The transaction involves the transfer of three bytes in both directions.
– SSI master ignores the three bytes it receives from the slave device.

Many SSI devices also support burst data transfers where more
than one data byte can be transferred in a single transaction.
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 29 / 60
SSI Clock Polarity and Phase

SSI data transfers can be synchronized to specific clock polarities

(CPOL) and phases (CPHA) that may vary between devices. The SSI
master should be configured to use the appropriate clock polarity and
phase supported by the slave device.

Clock Polarity (CPOL)

– Defines clock activity relative to the idle state.
– When CPOL = 0, idle state = 0 and active state = 1.
– When CPOL = 1, idle state = 1 and active state = 0.

Clock Phase (CPHA)

– Defines the clock edges (i.e. leading or trailing) when data are captured
and produced, respectively. This also depends on clock polarity.
– When CPHA = 0, data is valid on the leading clock edge.
– When CPHA = 1, data is valid on the trailing clock edge.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 30 / 60

SSIPolarity
Timing and Clock Phase
Diagram
The SPI interface defines no protocol for data exchange, limiting overhead and allowing for high
speed data streaming. Clock polarity (CPOL) and clock phase (CPHA) can be specified as ‘0’ or ‘1’ to
form four unique modes to provide flexibility in communication between master and slave as shown in
Figure 2.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 31 / 60

Synchronous Serial 
SSI on the TM4C123
Interface (SSI)
Synchronous Serial 
TM4C
SSI0Tx PA5 Interface (SSI)
PA4
SSI0 SSI0Rx PA3 ST7735
SSI0Fss When software writes to the data register,
SSI0Clk PA2
this 4 to 16-bit register is serially shifted 4 to 16
bit positions by the SSIClk clock
SSI1Tx PD3
SSI1 SSI1Rx PD2
TLV5616
SSI1Fss PD1 SSI0Fss
SSI1Clk LM3S PA3
PD0
TM4C TNF Fifo not full SSI I/O device
master SSI0Clk slave
SSI2Tx PB7 8-element PA2
PB6
Write data
SSI2 SSI2Rx PB5
CC3100 16-bit FIFO PA5 SSI0Tx
SSI2Fss
SSI2Clk PB4 SSI0_DR_R PA4 SSI0Rx
SSI3Tx PD3
PD2 Read data 8-element
SSI3 SSI3Rx PD1 16-bit FIFO Shift
SSI3Fss register
PD0
SSI3Clk RNE Fifo not empty

5
EE 445L – Bard, Valvano
Four SSI modules connected to four GPIO ports. 2
EE 445L – Bard, Valvano
Each SSI module has 8-element Tx and Rx FIFO buffers,
control/status/data registers, and a configurable 4-16-bit shift register.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 32 / 60

 I.6. Legal Stuff
The opinions expressed in these notes do not necessarily reflect the opinions of the University, its
TM4C123
management orI/O Pin
its big time Map
financial donors. Also, there shall be no bologna, Bevis, mustard, chewing the cables,
free lunch, sob stories, running & screaming, whining, hitting, spitting, kicking, biting, or tag backs. Quit it or we’re
telling. (Enjoy the course.)

IO Ain 0 1 2 3 4 5 6 7 8 9 14
PA0 Port U0Rx CAN1Rx
PA1 Port U0Tx CAN1Tx
PA2 Port SSI0Clk
PA3 Port SSI0Fss
PA4 Port SSI0Rx
PA5 Port SSI0Tx
PA6 Port I2C1SCL M1PWM2
PA7 Port I2C1SDA M1PWM3
PB0 USB0ID Port U1Rx T2CCP0
PB1 USB0VBUS Port U1Tx T2CCP1
PB2 Port I2C0SCL T3CCP0
PB3 Port I2C0SDA T3CCP1
PB4 Ain10 Port SSI2Clk M0PWM2 T1CCP0 CAN0Rx
PB5 Ain11 Port SSI2Fss M0PWM3 T1CCP1 CAN0Tx
PB6 Port SSI2Rx M0PWM0 T0CCP0
PB7 Port SSI2Tx M0PWM1 T0CCP1
PC4 C1- Port U4Rx U1Rx M0PWM6 IDX1 WT0CCP0 U1RTS
PC5 C1+ Port U4Tx U1Tx M0PWM7 PhA1 WT0CCP1 U1CTS
PC6 C0+ Port U3Rx PhB1 WT1CCP0 USB0epen
PC7 C0- Port U3Tx WT1CCP1 USB0pflt
PD0 Ain7 Port SSI3Clk SSI1Clk I2C3SCL M0PWM6 M1PWM0 WT2CCP0
PD1 Ain6 Port SSI3Fss SSI1Fss I2C3SDA M0PWM7 M1PWM1 WT2CCP1
PD2 Ain5 Port SSI3Rx SSI1Rx M0Fault0 WT3CCP0 USB0epen
PD3 Ain4 Port SSI3Tx SSI1Tx IDX0 WT3CCP1 USB0pflt
PD4 USB0DM Port U6Rx WT4CCP0
PD5 USB0DP Port U6Tx WT4CCP1
PD6 Port U2Rx M0Fault0 PhA0 WT5CCP0
PD7 Port U2Tx PhB0 WT5CCP1 NMI
PE0 Ain3 Port U7Rx
PE1 Ain2 Port U7Tx
PE2 Ain1 Port
PE3 Ain0 Port
PE4 Ain9 Port U5Rx I2C2SCL M0PWM4 M1PWM2 CAN0Rx
PE5 Ain8 Port U5Tx I2C2SDA M0PWM5 M1PWM3 CAN0Tx
PF0 Port U1RTS SSI1Rx CAN0Rx M1PWM4 PhA0 T0CCP0 NMI C0o
PF1 Port U1CTS SSI1Tx M1PWM5 PhB0 T0CCP1 C1o TRD1
PF2 Port SSI1Clk M0Fault0 M1PWM6 T1CCP0 TRD0
PF3 Port SSI1Fss CAN0Tx M1PWM7 T1CCP1 TRCLK
PF4 Port M1Fault0 IDX0 T2CCP0 USB0epen
Table 2.7. PMCx bits in the GPIO_PORTx_PCTL_R
Copyrightregister
on the TM4C
c Jonathan specify alternate functions. PB1,
Valvano
PB0, PD4 and PD5 are hardwired to the USB device. PA0 and PA1 are hardwired to the serial port. PWM is
not available on LM4F120.
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 33 / 60
TM4C123 SSI Registers

Control 0 Register (SSIx CR0 R)

– Data size select (DSS) configures the size of FIFO buffers elements and
Tiva TM4C123GH6PM Microcontroller ™

the shift register from 4-16 bits.

– Frame format select (FRF). Formats include Freescale SPI Frame
Format (0); TI1: Synchronous
Register SSI Control 0 (SSICR0),Serial Format
offset 0x000(1); and Microwire Frame
Format The(2)SSICR0 register contains bit fields that control various functions within the SSI module.
– SerialFunctionality such as protocol mode, clock rate, and data size are configured in this register.
clock polarity (SPO) and phase (SPH). Configure the SSI clock
polarity
SSI Control (CPOL)
0 (SSICR0)
SSI0 base: 0x4000.8000
and phase (CPHA).
– Serial clock
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
rate ( SCR ). Used with SSIx CPSR R to set the serial Tx and
SSI3 base: 0x4000.B000
OffsetRx
0x000 bit rate.
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SCR SPH SPO FRF DSS

Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces
compatibility with future products, the value of a reserved bit should be34 / 60
 Register 3: SSI Data (SSIDR), offset 0x008
TM4C123 SSI Registers
Register
Important: 2: SSI
This Control
register 1(2)
(SSICR1),
is read-sensitive. Seeoffset 0x004
the register description for details.
The SSICR1 register contains bit fields that control various functions within the SSI module. Master
The
and SSIDR register
slave mode is 16-bits is
functionality wide. When the
controlled SSIDR
by this register is read, the entry in the receive FIFO
register.
Control 1thatRegister is pointed to by(SSIx CR1
the current R) pointer is accessed. When a data value is removed by
FIFO read
SSI Control 1the SSI receive logic from the incoming data frame, it is placed into the entry in the receive FIFO
(SSICR1)
– Synchronous
pointed
SSI0 base: 0x4000.8000 to by serial
the port
current FIFO enable
write (SSE). Enables the SSI module.
pointer.
SSI1 base: 0x4000.9000
– base:
SSI2 Master/slave
When the SSIDR
0x4000.A000 select (MS
register is ). Configures
written to, the entry inthe SSI module
the transmit as
FIFO that is a master
pointed to by the or
write
SSI3 base: 0x4000.B000
pointer is written to. Data values are removed from the transmit FIFO one value at a time by the
slave device. Can only be set while SSI module is disabled.
Offset 0x004
transmit logic. Each data value is loaded into the transmit serial shifter, then serially shifted out onto
Type RW, reset 0x0000.0000
31 the
30 SSInTx
29 pin
28 at the
27programmed
26 25 bit rate.
24 23 22 21 20 19 18 17 16

reserved
When a data size of less than 16 bits is selected, the user must right-justify data written to the
Type RO transmit
RO RO FIFO.ROThe transmit
RO logic ignores
RO RO ROthe unused
RO bits.
RO Received
RO ROdata less
RO than
RO 16 bits
RO is RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
automatically right-justified in the receive buffer.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
reserved EOT reserved MS SSE LBM
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
Type RO RO RO RO RO RO RO RO RO RO RO RW RO RW RW RW
Reset 0 The
0 transmit
0 FIFO
0 and0 the receive
0 0FIFO are
0 not0cleared
0 even0 when 0the SSE 0 bit in0 the SSICR1
0 0
register is cleared, allowing the software to fill the transmit FIFO before enabling the SSI.

SSI Bit/Field
Data (SSIDR) Name Type Reset Description
Data Register
SSI0 base:
31:5
0x4000.8000 (SSIx DR
reserved RO
R) 0x0000.0 Software should not rely on the value of a reserved bit. To provide
SSI1 base: 0x4000.9000
– Holds data read from the Tx FIFO
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
buffer
compatibility withor written
future products, theto the
value Rx FIFO
of a reserved bit should be
preserved across a read-modify-write operation.
buffer.
Offset 0x008
Type RW, reset 0x0000.0000
4 EOT RW 0 End of Transmission
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
This bit is only valid for Master mode devices and operations (MS = 0x0).
reserved

Type RO RO RO RO RO RO RO ROValue RO
Description
RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 The TXRIS interrupt indicates that the transmit FIFO is half full
15 14 13 12 11 10 9 8 or less. 6
7 5 4 3 2 1 0

1DATA The End of Transmit interrupt mode for the TXRIS interrupt is
enabled.
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: In Freescale SPI mode only, a condition can be created where
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces an EOT interrupt is generated for every byte transferred even35 / 60
TM4C123 SSI Registers (3)

Synchronous Serial Interface (SSI)

Status Register
Register 4:(SSIx R)
SR(SSISR),
SSI Status offset 0x00C
– Provides The SSISR register contains
information on bits
thethatstatus
indicate of
the FIFO
the fill
Txstatus
FIFO and the SSI busy
buffer (TFEstatus.
= empty;
= not full), the Rx FIFO buffer (RNE = not empty; RFF = full), and
TNF(SSISR)
SSI Status
SSI0 base: 0x4000.8000
whether
SSI1 base: 0x4000.9000 the SSI module is idle or busy sending/receiving a data frame
SSI2 base: 0x4000.A000

Offset (BSY).
SSI3 base: 0x4000.B000
0x00C
Type RO, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved BSY RFF RNE TNF TFE

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bit/Field Name Type Reset Description

31:5 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

4 BSY RO 0 SSI Busy Bit

Value Description
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 36 / 60
 Synchronous Serial Interface (SSI)
TM4C123 SSI Registers (4)
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
The SSICPSR register specifies the division factor which is used to derive the SSInClk from the
system clock. The clock is further divided by a value from 1 to 256, which is 1 + SCR. SCR is
Clock Prescale Register (SSIx CPSR R)
programmed in the SSICR0 register. The frequency of the SSInClk is defined by:
SSInClk = SysClk / (CPSDVSR * (1 + SCR))
– The CPSDVSR field is used in conjunction with the SCR field of the
The value programmed into this register must be an even number between 2 and 254. The
CR0 R register
SSIx least-significant toprogrammed
bit of the derive the SSI
number clock from
is hard-coded the
to zero. TM4C123
If an odd number is bus
written
clock.to Thethis register,
SSI data readdetermines
clock back from this register
the hasTx the
andleast-significant bit as zero. rate.
Rx transmission
– CPSDVSR is an even number between 2 and 254, while SCR is a number
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
between
SSI1 base: 0x4000.9000 0 and 255.
SSI2 base: 0x4000.A000
– f0x010SSI = fBUS /((CPSDVSR) × (1 + (SCR)))
SSI3 base: 0x4000.B000
Offset
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CPSDVSR

Type RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

M. Saghir (EECE7:0
425 – Spring CPSDVSR
2020) RW 0x00
Serial SSI Clock Prescale Divisor
Interfaces 37 / 60
 Interface (SSI)
SSI Timing on the TM4C123
Synchronous serial timing showing the
data available interval overlaps the data
required interval

T R T R

SSI0Clk
S5max S5min
SSI0Tx must be high or low

S8 S9
SSI0Rx
don’t care
9
Copyright
EE 445L – Bard,
c Valvano
Jonathan Valvano

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 38 / 60

TM4C123 Freescale SPI Interface Modes
SPO=0, SPH=0 SSI0Clk

SSI0Tx n-1 n-2 4 3 2 1 0

SSI0Rx n-1 n-2 4 3 2 1 0

SSI0Fss

SPO=1, SPH=0
SSI0Clk

SSI0Tx n-1 n-2 4 3 2 1 0

SSI0Rx n-1 n-2 4 3 2 1 0

Synchronous
modes of the
SSI0Fss
Freescale SPI
SPO=0, SPH=1 SSI0Clk
interface.
SSI0Tx n-1 n-2 4 3 2 1 0

SSI0Rx n-1 n-2 4 3 2 1 0

SSI0Fss

SPO=1, SPH=1 SSI0Clk

SSI0Tx n-1 n-2 4 3 2 1 0

SSI0Rx n-1 n-2 4 3 2 1 0

SSI0Fss

Copyright
c Jonathan Valvano
EE 445L – Bard, Valvano
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 39 / 60
MAX5353 SSI Interface
Digital to Analog Converter (DAC) that uses SSI to interface with
a microcontroller.
– Uses a 16-bit frame: 3 command bits; 12 data bits; 1 stop bit

C2:C0 D11:D0 S0 Description

x00 Data 0 Load input register; update DAC register
x01 Data 0 Load input register; DAC register unchanged
x10 xxxx x Update DAC register from input register
Logic analyzer 
111 xxxx x Shutdown
Demonstration
011 xxxx x No operation

SSI0Fss/CS

SSI0Clk

Output of
SSI0Tx C2 C1 C0 B11 B10 B1 B0 S0 LM3S
Input of
Max5353 Din C2 C1 C0 B11 B10 B1 B0 S0 Max5353
Copyright
c Jonathan Valvano

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 40 / 60

MAX5353 Initialization and Output Functions

void DAC_Init ( uint16_t data ){

S Y S C T L _ R C G C S S I _ R |= 0 x01 ; // activate SSI0
S Y S C T L _ R C G C G P I O _ R |= 0 x01 ; // activate port A
while (( SY SC TL _ PR GP IO _ R &0 x01 ) == 0){};// ready ?
G P I O _ P O R T A _ A F S E L _ R |= 0 x2C ; // enable alt funct on PA2 ,3 ,5
G P I O _ P O R T A _ D E N _ R |= 0 x2C ; // configure PA2 ,3 ,5 as SSI
G P I O _ P O R T A _ P C T L _ R = ( G P I O _ P O R T A _ P C T L _ R &0 xFF0F00FF )+0 x00202200 ;
G P I O _ P O R T A _ A M S E L _ R = 0; // disable analog functionality on P
SSI0_CR1_R = 0 x00000000 ; // disable SSI , master mode
SSI0_CPSR_R = 0 x02 ; // 8 MHz SSIClk
SSI0_CR0_R &= ~(0 x0000FFF0 ); // SCR = 0 , SPH = 0 , SPO = 0 Freesca
SSI0_CR0_R |= 0 x0F ; // DSS = 16 - bit data
SSI0_DR_R = data ; // load ’ data ’ into transmit FIFO
SSI0_CR1_R |= 0 x00000002 ; // enable SSI
}

// send the 16 - bit code to the SSI

void DAC_Out ( uint16_t code ){
while (( SSI0_SR_R &0 x00000002 )==0){};// wait until room in FIFO
SSI0_DR_R = code ; // data out
}

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 41 / 60

 transmitter (a bus master), a receiver (a bus slave), or both (Figure 8-1). I2C is a
2 than one device may assume the role of bus
multi-master bus, meaning that more
Inter-Integrated Circuit (I C) Bus
master.

VCC VCC

SCL
SDA

Master Slave Master Slave Slave

Figure 8-1. I2C network

ABoth
serial
SDAcommunication bus used
and SCL are bidirectional. toSPI,
Unlike connect different
which has separate ICs
data on
linesthe
for
same PCB. of communication, I2C shares the same signal line for master trans-
each direction
mission
– Uses andtwo
slaveopen-collector
response. Also unlike
wires SPI, I2C clock
(serial does not
SCL;haveserial
several modes
data of to
SDA)
operation. The timing relationship between the clock, SCL, and the data line, SDA,
transfer bidirectional, synchronous data between multiple 2devices.
is simple and straightforward.2 When idle, both SDA and SCL are high. An I C trans-
– Any
action device
begins with on
SDAthe I Clow,
going busfollowed
can serve by SCLas master or slave.
(Figure 8-2). This indicates to
– Transfer speeds vary from 100 Kbps (standard)
all receivers on the bus that a packet transmission is commencing. to While
400 Kbps
SCL is(fast).
low,
SDA– Each device
transitions (highhas a unique
or low) for the 7-bit address
first valid making
data bit. it possible
This is known to connect
as a “START
condition.”
128 devices to the same bus. I2 C also supports a 10-bit extended
addressing scheme.
SDA
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 42 / 60
All transactions begin with a START (S) and are terminated by a STOP (P) (see Figure 5).
Starting
A HIGH to LOWand Stopping
transition Data
on the SDA Transfers
line while Over
SCL is HIGH I2 C Bus
thea START
defines condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.

SDA

SCL
S P

START condition STOP condition

mba608

Fig 5. START and STOP conditions

When the bus is idle, both SCL and SDA lines are high.
START and STOP conditions are always generated by the master. The bus is considered
o be busyA after
master
the initiates a data transfer
START condition. The busbyis creating a START
considered to be freecondition:
again a certain
ime afterSDA is transitioned
the STOP high-to-low
condition. This bus freewhile SCL
situation is remains high.
specified in Section 6.
Oncebusy
The bus stays the data transferSTART
if a repeated is over,
(Sr)the insteadaofSTOP
master creates
is generated a STOP condition:
condition. In
SCLthe
his respect, goes
START high (S)followed by SDA
and repeated START going high.
(Sr) conditions are functionally identical.
For the remainder of this document, therefore, the S symbol is used as a generic term to
epresent both the START and repeated START conditions, unless Sr is particularly
elevant.
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 43 / 60
 communicate on the bus, it can generate a repeated START condition (Sr) and address
another slave without first 2
Data Transfers Over
read/write formatsthe I generating
are then C Bus
possible
a STOP condition. Various combinations of
within such a transfer.

SDA

SCL 1-7 8 9 1-7 8 9 1-7 8 9

S P

START ADDRESS R/W ACK DATA ACK DATA ACK STOP

condition condition
mbc604

Fig 9. A complete data transfer

Once a master creates a START condition, all devices listen for the
next 8 bits: A 7-bit device address MSB
and a directionLSB bit (0 = write; 1 =
read). The slave device responds by sending an acknowledge R/W signal.
Data is transferred in frames of nineslave bits:
address8 bits of data followed by an
mbc608
acknowledge bit from the receiver. If no acknowledge is received the
Fig 10. The first byte after the START procedure
master aborts the data transfer.
UM10204It is possible to transfer multiple data bytes in the same transaction.
All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.

A transaction ends once the

User manual
master creates a STOP condition. 13 of 64
Rev. 6 — 4 April 2014

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 44 / 60

I2C on the TM4C123

There are four I2C modules (I2C0 to I2C3) on the TM4C123. Each is
connected to a different GPIO port to drive the SCL and SDA buses.

Each I2C module can be configured as a master or slave device, but

we will only focus on using the microcontroller as a master device.

Four registers are used to configure an I2C module as a master:

– I2C Master Slave Address Register (I2Cx MSA R)
– I2C Master Control/Status Register (I2Cx MCS R)
– I2C Master Data Register (I2Cx MDR R)
– I2C Master Timer Period Register (I2Cx MTPR R)

Other registers are also available to configure I2C Master interrupts,

but we will not consider these.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 45 / 60

I2C Master Registers
Inter-Integrated Circuit (I2C) Interface

Register 1: I2C Master Slave Address (I2CMSA), offset 0x000

Slave AddressThis registerRegister (I2Cx
consists of eight MSA
bits: seven R) bits (A6-A0), and a Receive/Send bit, which
address
determines if the next operation is a Receive (High), or Transmit (Low).
– Specifies the address of the slave device (SA) and the direction of the
dataSlave
I2C Master transfer (R/S = 1 ⇒ receive; R/S = 0 ⇒ send).
Address (I2CMSA)
I2C 0 base: 0x4002.0000
– The bits of this register are transmitted on the SDA line at the start of a
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
data transfer.
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved SA R/S

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:1 SA R/W 0x00 I2C Slave Address

This field specifies bits A6 through A0 of the slave address.
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 46 / 60
 register is written with the desired address, the R/S bit is cleared, and this register is written with
ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation
I2C Master Registers (2) is completed (or aborted due an error), an interrupt becomes active and the data may be read from
the I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit is normally
set, causing the I2C bus controller to transmit an acknowledge automatically after each byte. This
bit must be cleared when the I2C bus controller requires no further data to be transmitted from the
slave transmitter.

Read-Only Status Register

I2C Master Control/Status (I2CMCS)

I2C 0 base: 0x4002.0000
Control/Status
I2C 1 base: 0x4002.1000 Register (I2Cx MCS R)
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
– Provides status and error information when read:
Offset 0x004
Type RO, reset 0x0000.0020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved CLKTO BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 CLKTO RO 0 Clock Timeout Error

Value Description
0 No clock timeout error.
1 The clock timeout error has occurred.
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 47 / 60
I2C Master Registers (3)

Control/Status Register (I2Cx MCS R) Tiva™ TM4C123GH6PM Microcontroller

– Also configures the I2C master when written.
– The I2C master can be configured to operate in standard or high-speed
Write-Only
modes Control
(HSRegister
); generate acknowledgements for received data
automatically
I2C Master (ACK); generate a STOP condition (STOP); generate a
Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
START
I2C 1 base: or
0x4002.1000
I2C 2 base: 0x4002.2000
repeated START condition (START); and enable transmission
and reception
I2C 3 base: 0x4002.3000
Offset 0x004 of data (RUN).
Type WO, reset 0x0000.0020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved HS ACK STOP START RUN

Type RO RO RO RO RO RO RO RO RO RO RO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

M. Saghir (EECE4425 – Spring 2020)

HS WO 0 Interfaces
Serial High-Speed Enable 48 / 60
 Inter-Integrated Circuit (I2C) Interface

I2C Master Registers (4)

Register 3: I2C Master Data (I2CMDR), offset 0x008
Important: This register is read-sensitive. See the register description for details.

This register contains the data to be transmitted when in the Master Transmit state and the data
received when in the Master Receive state.

Data Register
I2C Master (I2Cx MDR R)
Data (I2CMDR)
I2C 0 base: 0x4002.0000
– Contains the data to be transmitted when in Master Transmit state, and
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
the data received when in Master Receive state.
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved DATA

Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7:0 DATA R/W 0x00 This byte contains the data transferred during a transaction.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 49 / 60

I2C Master Registers (5)
Tiva™ TM4C123GH6PM Microcontroller

Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C

This register is programmed to set the timer period for the SCL clock and assign the SCL clock to
Timer Period Register
either standard (I2Cx
or high-speed mode.MTPR R)

– Sets the timer period for the SCL clock and sets the SCL to either
I2C Master Timer Period (I2CMTPR)
I2C 0 base: 0x4002.0000
standard or high-speed mode.
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
– SCL PERIOD = 20 × (1 + T PR) × BUS CLK PERIOD
I2C 3 base: 0x4002.3000
Offset 0x00C
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved HS TPR

Type RO RO RO RO RO RO RO RO WO R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Bit/Field Name Type Reset Description

31:8 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

7 HS WO 0x0 High-Speed Enable

Value Description
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces
0 The SCL Clock Period set by TPR applies to Standard mode 50 / 60
I2C Master Registers (6) Tiva™ TM4C123GH6PM Microcontroller

Register 9: I2C Master Configuration (I2CMCR), offset 0x020

This register configures the mode (Master or Slave), enables the glitch filter, and sets the interface
for test mode loopback.

Configuration
I2C Master ConfigurationRegister
(I2CMCR) (I2Cx MCR R)
I2C 0 base: 0x4002.0000
–
I2C Configures
1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
the mode ( MFE = 1 ⇒ Master; MFE = 0 ⇒ Slave), enables
I2C 3 base: 0x4002.3000
the glitch filter, and sets the interface for test mode loopback.
Offset 0x020
Type RW, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved

Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved GFE SFE MFE reserved LPBK

Type RO RO RO RO RO RO RO RO RO RW RW RW RO RO RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit/Field Name Type Reset Description

31:7 reserved RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

6 GFE RW 0 I2C Glitch Filter Enable

Value Description
0 I2C glitch filter is disabled.
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces
1 I2C glitch filter is enabled. 51 / 60
 APPLICATIONS 1. Ease of use, no calibration or correction required by the user.
RTD and thermistor replacement 2. Low power consumption.
The ADT7420
Thermocouple Temperature Sensor
cold junction compensation
Medical equipment
3. Excellent long-term stability and reliability.
4. High accuracy for industrial, instrumentation, and medical
Industrial control and test applications.
Food transportation and storage
5. Packaged in a 16-lead, 4 mm × 4 mm LFCSP RoHS-
Environmental monitoring and HVAC
compliant package.
Laser diode temperature control

FUNCTIONAL BLOCK DIAGRAM

VDD 12
CONFIGURATION TEMPERATURE INTERNAL 10 CT
REGISTER VALUE REGISTER OSCILLATOR TCRIT
TLOW TCRIT INTERNAL
REFERENCE
REGISTER REGISTER
9 INT
THYST THIGH TEMPERATURE Σ-Δ
MODULATOR THIGH
REGISTER REGISTER SENSOR
ID STATUS
REGISTER REGISTER
ADT7420 FILTER TLOW
SOFTWARE POINTER LOGIC
RESET REGISTER REGISTER

A0 3 1 SCL
I2C INTERFACE
A1 4 2 SDA

09013-001
11

GND

Figure 1.

Rev. 0 Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
Programmable 13-/16-bit resolution.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved.
Technical Support
Trademarks and registered trademarks are the property of their respective owners. www.analog.com
Can operate in the temperature range: -40C to +150C.
240 msec conversion time.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 52 / 60

 reset is a write-only register. On power-up, the address pointer
TE
The register
ADT7420 is loaded with 0x00 and points to the temperature value
Registers
most significant byte register (Register Address 0x00). Th
can
Table 6. ADT7420 Registers rea
Register Power-On 2-b
Address Description Default loa
0x00 Temperature value most significant byte 0x00 can
0x01 Temperature value least significant byte 0x00 the
0x02 Status 0x00
0x03 Configuration 0x00 Bit
0x04 THIGH setpoint most significant byte 0x20 (64°C) the
0x05 THIGH setpoint least significant byte 0x00 (64°C) dig
0x06 TLOW setpoint most significant byte 0x05 (10°C) and
0x07 TLOW setpoint least significant byte 0x00 (10°C)
0x08 TCRIT setpoint most significant byte 0x49 (147°C)
0x09 TCRIT setpoint least significant byte 0x80 (147°C)
0x0A THYST setpoint 0x05 (5°C)
0x0B ID 0xCB
0x2F Software reset 0xXX

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 53 / 60

read operation is needed for the temperature value register, To read from another register, execute another write to the
THIGH setpoint register, TLOW setpoint register, and the TCRIT address pointer register to set up the relevant register address.
ADT7420 Single Data Read
setpoint register. Reading back the contents of an 8-bit register Thus, block reads are not possible, that is, there is no I2C address
similar to the configuration register is shown in Figure 16. pointer auto-increment except when reading back from a 16-bit
Reading back the contents of the temperature value register register. If the address pointer register has previously been set
is shown in Figure 17. up with the address of the register that is going to receive a read
command, there is no need to repeat a write operation to set up
Reading back from any register first requires a single-byte write the register address again.
operation to the address pointer register to set up the address of
1 9 1 9

SCL

SDA 1 0 0 1 0 A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0

START BY ACK. BY ACK. BY

MASTER ADT7420 ADT7420
FRAME 1 FRAME 2
SERIAL BUS ADDRESS ADDRESS POINTER REGISTER BYTE
BYTE

1 9 1 9

SCL

SDA 1 0 0 1 0 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

REPEAT START ACK. BY NO ACK. BY STOP BY

BY MASTER ADT7420 MASTER MASTER
FRAME 3 FRAME 4

09013-018
SERIAL BUS ADDRESS DATA BYTE FROM CONFIGURATION
BYTE REGISTER

Figure 16. Reading Back Data from the Configuration Register

1 9 1 9
SCL

SDA
1 0 0 1 0 A1 A0 R/W A7 A6 A1 A0

M. Saghir START
(EECE 425 – Spring 2020)
ADT7410 DEVICE ADDRESS Serial
ACK. BY Interfaces
REGISTER ADDRESS[A7:A0] ACK. BY 54 / 60
 SDA 1 0 0 1 0 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

ADT7420 Multiple Data Read

REPEAT START
BY MASTER
FRAME 3
ACK. BY
ADT7420
FRAME 4
NO ACK. BY STOP BY
MASTER MASTER

09013-018
SERIAL BUS ADDRESS DATA BYTE FROM CONFIGURATION
BYTE REGISTER

Figure 16. Reading Back Data from the Configuration Register

1 9 1 9
SCL

SDA
1 0 0 1 0 A1 A0 R/W A7 A6 A1 A0

START ADT7410 DEVICE ADDRESS ACK. BY REGISTER ADDRESS[A7:A0] ACK. BY

ADT7420 ADT7420

SR 1 9 1 9

SCL

SDA R/W D7 D6 D1 D0 D7 D6 D1 D0
1 0 A1 A0

REPEAT ADT7410 DEVICE ADDRESS ACK. BY TEMPERATURE ACK. BY TEMPERATURE NO

START ADT7420 VALUE REGISTER MASTER VALUE REGISTER ACK. BY
MASTER
MSB DATA LSB DATA
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH.
3. THE MASTER GENERATES THE NO ACKNOWLEDGE AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.

09013-023
4. TEMPERATURE VALUE REGISTER MSB DATA AND TEMPERATURE VALIUE REGISTER LSB DATA ARE ALWAYS SEPARATED BY A LOW ACK BIT.
5. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.

Figure 17. Reading Back Data from the Temperature Value Register

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 55 / 60

the ADT7420, depending on which registers are to be written.
data to these registers requires the serial bus address, the data
Writing a single byte of data requires the serial bus address, the
ADT7420 Single Data Write
data register address written to the address pointer register,
register address of the MSB register written to the address
pointer register, followed by the two data bytes written to
followed by the data byte written to the selected data register. the selected data register. This is shown in Figure 15.
This is shown in Figure 14.
If more than the required number of data bytes is written to a
register, the register ignores these extra data bytes. To write to
a different register, a start or repeated start is required.

1 9 1 9
SCL

SDA 1 0 0 1 0 A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0
START BY ACK. BY ACK. BY
MASTER ADT7420 ADT7420
FRAME 1 FRAME 2
SERIAL BUS ADDRESS BYTE ADDRESS POINTER REGISTER BYTE
1 9

SCL (CONTINUED)

SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY STOP BY
ADT7420 MASTER

09013-016
FRAME 3
DATA BYTE

Figure 14. Writing to a Register Followed by a Single Byte of Data

1 9 1 9
SCL

SDA 1 0 0 1 0 A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0
START BY ACK. BY ACK. BY
MASTER ADT7420 ADT7420
M. Saghir (EECE 425 – Spring 2020)
FRAME 1 Serial Interfaces FRAME 2 56 / 60
Example: Interfacing TM4C123 with ADT7420

3.3 V

2.2kΩ 2.2kΩ

SCL

ADT7420 SDA TM4C123

Assume TM4C123 runs on a 50 MHz clock.

We will use the TM4C123’s I2C0 module, which connects to pins 2
and 3 of port B.

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 57 / 60

Example: Interfacing TM4C123 with ADT7420 (2)
# define I2C_MCS_ACK 0 x00000008 // Data Acknowledge Enable
# define I2C_ MCS_DATA CK 0 x00000008 // Acknowledge Data
# define I2C_ MCS_ADRA CK 0 x00000004 // Acknowledge Address
# define I2C_MCS_STOP 0 x00000004 // Generate STOP
# define I2C_MCS_START 0 x00000002 // Generate START
# define I2C_MCS_ERROR 0 x00000002 // Error
# define I2C_MCS_RUN 0 x00000001 // I2C Master Enable
# define I2C_MCS_BUSY 0 x00000001 // I2C Busy
# define I2C_MCR_MFE 0 x00000010 // I2C Master Function Enable

void I2C_Init ( void ){

S Y S C T L _ R C G C I 2 C _ R |= 0 x0001 ; // activate I2C0
S Y S C T L _ R C G C G P I O _ R |= 0 x0002 ; // activate port B
while (( SY SC TL _ PR GP IO _ R &0 x0002 ) == 0){};// ready ?

G P I O _ P O R T B _ A F S E L _ R |= 0 x0C ; // 3) enable alt funct on PB2 ,3

G P I O _ P O R T B _ O D R _ R |= 0 x08 ; // 4) enable open drain on PB3 only
G P I O _ P O R T B _ D E N _ R |= 0 x0C ; // 5) enable digital I / O on PB2 ,3
// 6) configure PB2 ,3 as I2C
G P I O _ P O R T B _ P C T L _ R = ( G P I O _ P O R T B _ P C T L _ R &0 xFFFF00FF )+0 x00003300 ;
G P I O _ P O R T B _ A M S E L _ R &= ~0 x0C ; // 7) disable analog on PB2 ,3
I2C0_MCR_R = I2C_MCR_MFE ; // 9) master function enable
I2C0_MTPR_R = 24; // 8) configure for 100 kbps clock
}
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 58 / 60
Example: Interfacing TM4C123 with ADT7420 (3)
// Send two bytes to slave device
uint32_t I2C_Send2 ( int8_t slave , uint8_t data1 , uint8_t data2 ){
while ( I2C0_MCS_R & I2C_MCS_BUSY ){};// wait for I2C ready
I2C0_MSA_R = ( slave < <1)&0 xFE ; // MSA [7:1] is slave address
I2C0_MSA_R &= ~0 x01 ; // MSA [0] is 0 for send
I2C0_MDR_R = data1 &0 xFF ; // prepare first byte
// generate start / restart and master enable
I2C0_MCS_R = ( I2C_MCS_START | I2C_MCS_RUN );
while ( I2C0_MCS_R & I2C_MCS_BUSY ){};// wait for transmission done
// check error bits
if (( I2C0_MCS_R & ( I2C_MC S_DATACK | I2C_ MCS_ADRA CK |
I2C_MCS_ERROR )) != 0){
I2C0_MCS_R = ( I2C_MCS_STOP ); // stop
// return error bits if nonzero
return ( I2C0_MCS_R &( I2C_MC S_DATACK | I2C_M CS_ADRA CK |
I2C_MCS_ERROR ));
}
I2C0_MDR_R = data2 &0 xFF ; // prepare second byte
// generate stop and master enable
I2C0_MCS_R = ( I2C_MCS_STOP | I2C_MCS_RUN );
while ( I2C0_MCS_R & I2C_MCS_BUSY ){};// wait for transmission done
// return error bits
return ( I2C0_MCS_R &( I2C_MCS _DATACK | I2C_M CS_ADRAC K | I2C_MCS_ERROR ));
}
M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 59 / 60
Example: Interfacing TM4C123 with ADT7420 (4)
// Receive two bytes from slave device
uint16_t I2C_Recv2 ( int8_t slave ){
uint8_t data1 , data2 ;
int retryCounter = 1;
do {
while ( I2C0_MCS_R & I2C_MCS_BUSY ){};// wait for I2C ready
I2C0_MSA_R = ( slave < <1)&0 xFE ; // MSA [7:1] is slave address
I2C0_MSA_R |= 0 x01 ; // MSA [0] is 1 for receive
I2C0_MCS_R = ( I2C_MCS_ACK // positive data ack
| I2C_MCS_START // generate start / restart
| I2C_MCS_RUN ); // master enable
while ( I2C0_MCS_R & I2C_MCS_BUSY ){};// wait for transmission done
data1 = ( I2C0_MDR_R &0 xFF ); // MSB data sent first
I2C0_MCS_R = ( I2C_MCS_STOP // generate stop
| I2C_MCS_RUN ); // master enable
while ( I2C0_MCS_R & I2C_MCS_BUSY ){};// wait for transmission done
data2 = ( I2C0_MDR_R &0 xFF ); // LSB data sent last
retryCounter = retryCounter + 1; // increment retry counter
} // repeat if error
while ((( I2C0_MCS_R &( I2C_M CS_ADRAC K | I2C_MCS_ERROR )) != 0) &&
( retryCounter <= MAXRETRIES ));
return ( data1 < <8)+ data2 ; // usually returns 0 xFFFF on error
}

M. Saghir (EECE 425 – Spring 2020) Serial Interfaces 60 / 60