‰ The advantage of interrupts is that the

INTERRUPTS
microcontroller can serve many
Interrupts vs. devices (not all at the same time)
Polling ¾ Each devices can get the attention of the
(cont’) microcontroller based on the assigned
priority
¾ For the polling method, it is not possible to
assign priority since it checks all devices in
a round-robin fashion
‰ The microcontroller can also ignore
(mask) a device request for service
¾ This is not possible for the polling method

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 4
 ‰ For every interrupt, there must be an
INTERRUPTS
interrupt service routine (ISR), or
Interrupt interrupt handler
Service Routine ¾ When an interrupt is invoked, the micro-
controller runs the interrupt service
routine
¾ For every interrupt, there is a fixed
location in memory that holds the address
of its ISR
¾ The group of memory locations set aside
to hold the addresses of ISRs is called
interrupt vector table

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 5
 ‰ Upon activation of an interrupt, the
INTERRUPTS
microcontroller goes through the
Steps in following steps
Executing an 1. It finishes the instruction it is executing
Interrupt and saves the address of the next
instruction (PC) on the stack
2. It also saves the current status of all the
interrupts internally (i.e: not on the stack)
3. It jumps to a fixed location in memory,
called the interrupt vector table, that
holds the address of the ISR

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 6
 (cont’)
INTERRUPTS 4. The microcontroller gets the address of
the ISR from the interrupt vector table
Steps in and jumps to it
Executing an ƒ It starts to execute the interrupt service
Interrupt subroutine until it reaches the last instruction
(cont’) of the subroutine which is RETI (return from
interrupt)
5. Upon executing the RETI instruction, the
microcontroller returns to the place
where it was interrupted
ƒ First, it gets the program counter (PC)
address from the stack by popping the top
two bytes of the stack into the PC
ƒ Then it starts to execute from that address

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 7
 ‰ Six interrupts are allocated as follows
INTERRUPTS
¾ Reset – power-up reset
Six Interrupts ¾ Two interrupts are set aside for the timers:
in 8051 one for timer 0 and one for timer 1
¾ Two interrupts are set aside for hardware
external interrupts
ƒ P3.2 and P3.3 are for the external hardware
interrupts INT0 (or EX1), and INT1 (or EX2)
¾ Serial communication has a single
interrupt that belongs to both receive and
transfer

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 8
INTERRUPTS Interrupt vector table
Interrupt ROM Location Pin
(hex)
Six Interrupts Reset 0000 9
in 8051 External HW (INT0) 0003 P3.2 (12)
(cont’) Timer 0 (TF0) 000B
External HW (INT1) 0013 P3.3 (13)
Timer 1 (TF1) 001B
Serial COM (RI and TI) 0023

ORG 0 ;wake-up ROM reset location

LJMP MAIN ;by-pass int. vector table
;---- the wake-up program
ORG 30H
MAIN: Only three bytes of ROM space
.... assigned to the reset pin. We put
the LJMP as the first instruction
END and redirect the processor away
from the interrupt vector table.

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 9
 ‰ Upon reset, all interrupts are disabled
INTERRUPTS
(masked), meaning that none will be
Enabling and responded to by the microcontroller if
Disabling an they are activated
Interrupt ‰ The interrupts must be enabled by
software in order for the
microcontroller to respond to them
¾ There is a register called IE (interrupt
enable) that is responsible for enabling
(unmasking) and disabling (masking) the
interrupts

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 10
 IE (Interrupt Enable) Register
INTERRUPTS
D7 D0
EA -- ET2 ES ET1 EX1 ET0 EX0
Enabling and
Disabling an EA (enable all) must be set to 1 in order
Interrupt for rest of the register to take effect

(cont’) EA IE.7 Disables all interrupts

-- IE.6 Not implemented, reserved for future use
ET2 IE.5 Enables or disables timer 2 overflow or capture
interrupt (8952)
ES IE.4 Enables or disables the serial port interrupt
ET1 IE.3 Enables or disables timer 1 overflow interrupt
EX1 IE.2 Enables or disables external interrupt 1
ET0 IE.1 Enables or disables timer 0 overflow interrupt
EX0 IE.0 Enables or disables external interrupt 0

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 11
 ‰ To enable an interrupt, we take the
INTERRUPTS
following steps:
Enabling and 1. Bit D7 of the IE register (EA) must be set
Disabling an to high to allow the rest of register to
Interrupt take effect
(cont’) 2. The value of EA
¾ If EA = 1, interrupts are enabled and will be
responded to if their corresponding bits in IE
are high
¾ If EA = 0, no interrupt will be responded to,
even if the associated bit in the IE register is
high

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 12
 ‰ The timer flag (TF) is raised when the
TIMER timer rolls over
INTERRUPTS ¾ In polling TF, we have to wait until the TF
is raised
ƒ The problem with this method is that the
microcontroller is tied down while waiting for TF
to be raised, and can not do anything else
¾ Using interrupts solves this problem and,
avoids tying down the controller
ƒ If the timer interrupt in the IE register is
enabled, whenever the timer rolls over, TF is
raised, and the microcontroller is interrupted in
whatever it is doing, and jumps to the interrupt
vector table to service the ISR
ƒ In this way, the microcontroller can do other
until it is notified that the timer has rolled over
TF0 Timer 0 Interrupt Vector TF1 Timer 1 Interrupt Vector
1 000BH 1 001BH
Jumps to Jumps to
Department of Computer Science and Information Engineering
HANEL National Cheng Kung University, TAIWAN 14
 ‰ The 8051 has two external hardware
EXTERNAL
HARDWARE
interrupts
INTERRUPTS ¾ Pin 12 (P3.2) and pin 13 (P3.3) of the 8051,
designated as INT0 and INT1, are used as
external hardware interrupts
ƒ The interrupt vector table locations 0003H and
0013H are set aside for INT0 and INT1
¾ There are two activation levels for the
external hardware interrupts
ƒ Level trigged
ƒ Edge trigged

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 20
 EXTERNAL Activation of INT0
HARDWARE Level-triggered
INTERRUPTS INT0
0
IT0
(cont’) (Pin 3.2)
1 IE0
0003

Edge-triggered (TCON.1)

Activation of INT1
Level-triggered
0
INT1 IT1 0013
(Pin 3.3)
1 IE1
Edge-triggered (TCON.3)

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 21
 ‰ In the level-triggered mode, INT0 and
EXTERNAL INT1 pins are normally high
HARDWARE
¾ If a low-level signal is applied to them, it
INTERRUPTS triggers the interrupt
¾ Then the microcontroller stops whatever it
Level-Triggered is doing and jumps to the interrupt vector
Interrupt table to service that interrupt
¾ The low-level signal at the INT pin must
be removed before the execution of the
last instruction of the ISR, RETI; otherwise,
another interrupt will be generated
‰ This is called a level-triggered or level-
activated interrupt and is the default
mode upon reset of the 8051

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 22
 ‰ Pins P3.2 and P3.3 are used for normal
EXTERNAL I/O unless the INT0 and INT1 bits in
HARDWARE the IE register are enabled
INTERRUPTS
¾ After the hardware interrupts in the IE
register are enabled, the controller keeps
Sampling Low sampling the INTn pin for a low-level signal
Level-Triggered once each machine cycle
Interrupt ¾ According to one manufacturer’s data sheet,
ƒ The pin must be held in a low state until the
start of the execution of ISR
ƒ If the INTn pin is brought back to a logic high
before the start of the execution of ISR there
will be no interrupt
ƒ If INTn pin is left at a logic low after the RETI
instruction of the ISR, another interrupt will be
activated after one instruction is executed

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 24
 ¾ To ensure the activation of the hardware
EXTERNAL interrupt at the INTn pin, make sure that
HARDWARE the duration of the low-level signal is
INTERRUPTS around 4 machine cycles, but no more
ƒ This is due to the fact that the level-triggered
Sampling Low interrupt is not latched
Level-Triggered ƒ Thus the pin must be held in a low state until
Interrupt the start of the ISR execution
(cont’)
1 MC
4 machine cycles To INT0 or
1.085us INT1 pins
4 × 1.085us
note: On reset, IT0 (TCON.0) and IT1 (TCON.2) are both
low, making external interrupt level-triggered

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 25
 ‰ To make INT0 and INT1 edge-
EXTERNAL
HARDWARE
triggered interrupts, we must program
INTERRUPTS the bits of the TCON register
¾ The TCON register holds, among other bits,
Edge-Triggered the IT0 and IT1 flag bits that determine
Interrupt level- or edge-triggered mode of the
hardware interrupt
ƒ IT0 and IT1 are bits D0 and D2 of the TCON
register
ƒ They are also referred to as TCON.0 and
TCON.2 since the TCON register is bit-
addressable

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 26
 TCON (Timer/Counter) Register (Bit-addressable)
EXTERNAL
D7 D0
HARDWARE
INTERRUPTS TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TF1 TCON.7 Timer 1 overflow flag. Set by

Edge-Triggered hardware when timer/counter
1 overflows. Cleared by hardware as
Interrupt the processor vectors to the interrupt
(cont’) service routine
TR1 TCON.6 Timer 1 run control bit. Set/cleared by
software to turn timer/counter 1 on/off
TF0 TCON.5 Timer 0 overflow flag. Set by
hardware when timer/counter 0
overflows. Cleared by hardware as the
processor vectors to the interrupt
service routine
TR0 TCON.4 Timer 0 run control bit. Set/cleared by
software to turn timer/counter 0 on/off
Department of Computer Science and Information Engineering
HANEL National Cheng Kung University, TAIWAN 27
 TCON (Timer/Counter) Register (Bit-addressable) (cont’)
EXTERNAL
HARDWARE IE1 TCON.3 External interrupt 1 edge flag. Set by
INTERRUPTS CPU when the external interrupt edge
(H-to-L transition) is detected. Cleared
by CPU when the interrupt is processed
Edge-Triggered
IT1 TCON.2 Interrupt 1 type control bit. Set/cleared
Interrupt by software to specify falling edge/low-
(cont’) level triggered external interrupt
IE0 TCON.1 External interrupt 0 edge flag. Set by
CPU when the external interrupt edge
(H-to-L transition) is detected. Cleared
by CPU when the interrupt is processed
IT0 TCON.0 Interrupt 0 type control bit. Set/cleared
by software to specify falling edge/low-
level triggered external interrupt

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 28
 ‰ In edge-triggered interrupts
EXTERNAL
HARDWARE ¾ The external source must be held high for
INTERRUPTS at least one machine cycle, and then held
low for at least one machine cycle
Sampling Edge- ¾ The falling edge of pins INT0 and INT1
Triggered are latched by the 8051 and are held by
Interrupt the TCON.1 and TCON.3 bits of TCON
register
ƒ Function as interrupt-in-service flags
ƒ It indicates that the interrupt is being serviced
now and on this INTn pin, and no new interrupt
will be responded to until this service is finished
Minimum pulse duration to
detect edge-triggered 1 MC 1 MC
interrupts XTAL=11.0592MHz 1.085us 1.085us

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 30
 ‰ Regarding the IT0 and IT1 bits in the
EXTERNAL TCON register, the following two points
HARDWARE must be emphasized
INTERRUPTS
¾ When the ISRs are finished (that is, upon
execution of RETI), these bits (TCON.1 and
Sampling Edge- TCON.3) are cleared, indicating that the
Triggered interrupt is finished and the 8051 is ready
Interrupt to respond to another interrupt on that pin
(cont’)
¾ During the time that the interrupt service
routine is being executed, the INTn pin is
ignored, no matter how many times it
makes a high-to-low transition
ƒ RETI clears the corresponding bit in TCON
register (TCON.1 or TCON.3)
ƒ There is no need for instruction CLR TCON.1
before RETI in the ISR associated with INT0

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 31
 ‰ TI (transfer interrupt) is raised when
SERIAL
COMMUNI-
the last bit of the framed data, the
CATION stop bit, is transferred, indicating that
INTERRUPT the SBUF register is ready to transfer
the next byte
‰ RI (received interrupt) is raised when
the entire frame of data, including the
stop bit, is received
¾ In other words, when the SBUF register
has a byte, RI is raised to indicate that the
received byte needs to be picked up
before it is lost (overrun) by new incoming
serial data

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 33
 ‰ In the 8051 there is only one interrupt
SERIAL
COMMUNI-
set aside for serial communication
CATION ¾ This interrupt is used to both send and
INTERRUPT receive data
¾ If the interrupt bit in the IE register (IE.4)
RI and TI Flags is enabled, when RI or TI is raised the
and Interrupts 8051 gets interrupted and jumps to
memory location 0023H to execute the ISR
¾ In that ISR we must examine the TI and RI
flags to see which one caused the interrupt
and respond accordingly
TI
0023H
RI
Serial interrupt is invoked by TI or RI flags
Department of Computer Science and Information Engineering
HANEL National Cheng Kung University, TAIWAN 34
 ‰ The serial interrupt is used mainly for
SERIAL
COMMUNI-
receiving data and is never used for
CATION sending data serially
INTERRUPT ¾ This is like getting a telephone call in
which we need a ring to be notified
Use of Serial ¾ If we need to make a phone call there are
COM in 8051 other ways to remind ourselves and there
is no need for ringing
¾ However in receiving the phone call, we
must respond immediately no matter what
we are doing or we will miss the call

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 35
 ‰ The TCON register holds four of the
SERIAL
COMMUNI-
interrupt flags, in the 8051 the SCON
CATION register has the RI and TI flags
INTERRUPT
Interrupt Flag Bits
Interrupt Flag
Interrupt Flag SFR Register Bit
Bits
External 0 IE0 TCON.1
External 1 IE1 TCON.3
Timer 0 TF0 TCON.5
Timer 1 TF1 TCON.7
Serial Port T1 SCON.1
Timer 2 TF2 T2CON.7 (AT89C52)
Timer 2 EXF2 T2CON.6 (AT89C52)

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 42
 ‰ When the 8051 is powered up, the
INTERRUPT
PRIORITY
priorities are assigned according to
the following
¾ In reality, the priority scheme is nothing
but an internal polling sequence in which
the 8051 polls the interrupts in the
sequence listed and responds accordingly
Interrupt Priority Upon Reset

Highest To Lowest Priority

External Interrupt 0 (INT0)
Timer Interrupt 0 (TF0)
External Interrupt 1 (INT1)
Timer Interrupt 1 (TF1)
Serial Communication (RI + TI)

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 43
 ‰ We can alter the sequence of interrupt
INTERRUPT
PRIORITY
priority by assigning a higher priority
(cont’) to any one of the interrupts by
programming a register called IP
(interrupt priority)
¾ To give a higher priority to any of the
interrupts, we make the corresponding bit
in the IP register high
¾ When two or more interrupt bits in the IP
register are set to high
ƒ While these interrupts have a higher priority
than others, they are serviced according to the
sequence of Table 11-13

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 45
 Interrupt Priority Register (Bit-addressable)
INTERRUPT
PRIORITY D7 D0
(cont’) -- -- PT2 PS PT1 PX1 PT0 PX0

-- IP.7 Reserved
-- IP.6 Reserved
PT2 IP.5 Timer 2 interrupt priority bit (8052 only)
PS IP.4 Serial port interrupt priority bit
PT1 IP.3 Timer 1 interrupt priority bit
PX1 IP.2 External interrupt 1 priority bit
PT0 IP.1 Timer 0 interrupt priority bit
PX0 IP.0 External interrupt 0 priority bit

Priority bit=1 assigns high priority

Priority bit=0 assigns low priority

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 46
 ‰ The 8051 compiler have extensive
PROGRAMMING support for the interrupts
IN C
¾ They assign a unique number to each of
the 8051 interrupts
Interrupt Name Numbers
External Interrupt 0 (INT0) 0
Timer Interrupt 0 (TF0) 1
External Interrupt 1 (INT1) 2
Timer Interrupt 1 (TF1) 3
Serial Communication (RI + TI) 4
Timer 2 (8052 only) (TF2) 5

¾ It can assign a register bank to an ISR

ƒ This avoids code overhead due to the pushes
and pops of the R0 – R7 registers

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 51
 Example 11-14
Write a C program that continuously gets a single bit of data from P1.7
PROGRAMMING and sends it to P1.0, while simultaneously creating a square wave of
200 μs period on pin P2.5. Use Timer 0 to create the square wave.
IN C Assume that XTAL = 11.0592 MHz.
(cont’)
Solution:
We will use timer 0 mode 2 (auto-reload). One half of the period is
100 μs. 100/1.085 μs = 92, and TH0 = 256 - 92 = 164 or A4H
#include <reg51.h>
sbit SW =P1^7;
sbit IND =P1^0;
sbit WAVE =P2^5;
void timer0(void) interrupt 1 {
WAVE=~WAVE; //toggle pin
}
void main() {
SW=1; //make switch input
TMOD=0x02;
TH0=0xA4; //TH0=-92
IE=0x82; //enable interrupt for timer 0
while (1) {
IND=SW; //send switch to LED
}
}
Department of Computer Science and Information Engineering
HANEL National Cheng Kung University, TAIWAN 52
 Example 11-16
Write a C program using interrupts to do the following:
PROGRAMMING (a) Receive data serially and send it to P0
(b) Read port P1, transmit data serially, and give a copy to P2
IN C (c) Make timer 0 generate a square wave of 5 kHz frequency on P0.1
(cont’) Assume that XTAL = 11.0592 MHz. Set the baud rate at 4800.
Solution:
#include <reg51.h>
sbit WAVE =P0^1;
void timer0() interrupt 1 {
WAVE=~WAVE; //toggle pin
}
void serial0() interrupt 4 {
if (TI==1) {
TI=0; //clear interrupt
}
else {
P0=SBUF; //put value on pins
RI=0; //clear interrupt
}
}
.....

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 53
 .....
PROGRAMMING
IN C void main() {
(cont’) unsigned char x;
P1=0xFF; //make P1 an input
TMOD=0x22;
TH1=0xF6; //4800 baud rate
SCON=0x50;
TH0=0xA4; //5 kHz has T=200us
IE=0x92; //enable interrupts
TR1=1; //start timer 1
TR0=1; //start timer 0
while (1) {
x=P1; //read value from pins
SBUF=x; //put value in buffer
P2=x; //write value to pins
}
}

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 54
 Example 11-17
PROGRAMMING Write a C program using interrupts to do the following:
IN C (a) Generate a 10 KHz frequency on P2.1 using T0 8-bit auto-reload
(cont’) (b) Use timer 1 as an event counter to count up a 1-Hz pulse and
display it on P0. The pulse is connected to EX1.
Assume that XTAL = 11.0592 MHz. Set the baud rate at 9600.
Solution:
#include <reg51.h>
sbit WAVE =P2^1;
Unsigned char cnt;
void timer0() interrupt 1 {
WAVE=~WAVE; //toggle pin
}
void timer1() interrupt 3 {
cnt++; //increment counter
P0=cnt; //display value on pins
}
.....

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 55
 .....
PROGRAMMING
IN C void main() {
(cont’) cnt=0; //set counter to 0
TMOD=0x42;
TH0=0x-46; //10 KHz
IE=0x86; //enable interrupts
TR0=1; //start timer 0
while (1); //wait until interrupted
}

Department of Computer Science and Information Engineering

HANEL National Cheng Kung University, TAIWAN 56