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Report Title: Traffic Light Controller Using VHDL: Electronic Workshop - 2

1. The document describes a project to design a traffic light controller using VHDL on a Xilinx FPGA. 2. The traffic light controller has two inputs - a clock and a sensor, and three outputs to control the red, yellow, and green lights. 3. The VHDL code implements a state machine with states for red, green, and yellow. It sequences through the states based on the clock and changes the light if the sensor input is low.

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FD Syndrome
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58 views

Report Title: Traffic Light Controller Using VHDL: Electronic Workshop - 2

1. The document describes a project to design a traffic light controller using VHDL on a Xilinx FPGA. 2. The traffic light controller has two inputs - a clock and a sensor, and three outputs to control the red, yellow, and green lights. 3. The VHDL code implements a state machine with states for red, green, and yellow. It sequences through the states based on the clock and changes the light if the sensor input is low.

Uploaded by

FD Syndrome
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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VIVEKANAND EDUCATION SOCIETY'S

INSTITUTE OF TECHNOLOGY

Approved by AICTE & Affiliated to Mumbai University

ELECTRONIC WORKSHOP - 2

REPORT

Report Title: Traffic Light Controller Using


VHDL

PROJECT MEMBERS:

1. Priyal Nile 55
2. Ajay Patkar 59
3. Prasad Pawaskar 61
4. Vishal Thakur 74
Traffic Light Controller

Prasad Pawaskar Ajay Patkar Vishal Thakur

Electronics T.E. Electronics T.E. Electronics T.E.

Vivekanand Institute Of Vivekanand Institute Of Vivekanand Institute Of


technology Mumbai technology Mumbai technology Mumbai

The following are the


specifications needed for the Xilinx
Abstract – As name suggests the project
Simulation:
aims at controlling a traffic signal. The
main purpose is to control the traffic of a
lane and change the signals according to it.
Family : Spartan 3
Index Terms – Introduction, Working
Device : XC3S400
Principle, Circuit Diagram, VHDL Code,
Simulation Results, RTL Schematic , Simulator: ISE simulator(VHDL)
Technology Schematic, Hardware
Implementation, Results, Conclusion.

I. INTRODUCTION

Traffic Light controller project consist


of 2 inputs namely clock and sensor and
3 outputs, the Green , Yellow and Red
light. This project is implemented using
Xilinx Simulator and also Xilinx FPGA
kit.
The working of this is quite simple.

As seen above what we have is only 2


input’s present:

1. Clock

2. Sensor

The working of this system is explained


as below:

1. We give a continuous clock input


to the system.

2. Then after a fixed amount of


Fig a Xilinx Specifications delay the led’s at the output i.e. at
the traffic lamp start glowing once
we sense the traffic by the sensor
input.
II. Circuit Explanation
3. This delay can be adjusted by the
designer by setting the clock
The circuit shown in fig. is explained as
frequency.
follows showing the operation of each
component: 4. Now, the special case in the
system is the Sensor input.

5. Whenever the sensor input is high


the system operates under normal
conditions.

6. But, when the SENSOR pin


input’s a low signal this indicates
that the lane as to be stop
immediately.

7. Thus when Sensor = 0 the Red


LED glows at the traffic lamp

8. This is how the system operates.


III. VHDL CODE green_light=’1’;

yellow_light=’0’;
The code that was written of the above
circuit implementation is as follows: when red=>

red_light=’1’;

library IEEE; green_light=’0’;

use IEEE.STD_LOGIC_1164.ALL; yellow_light=’0’;

use IEEE.STD_LOGIC_ARITH.ALL; if(sensor=’1’) then

use ns<=green;
IEEE.STD_LOGIC_UNSIGNED.ALL; else
entity traffic_light is ns=>red;
port(sensor,clock:in std_logic; end if;
red_light,green_light,yellow_light:out when yellow=>
std_logic);
red_light=’0’;
end traffic_light;
green_light=’0’;
architecture fsm of traffic_light is
yellow_light=’1’;
type t_state is (red,green,yellow);
ns<=red;
signal ps,ns:t_state;
end case;
begin
end process;
process(ps,sensor)
process
begin
begin
case ps is
wait untilclock’event and clock=’1’;
when green=>
ps<=ns;
ns<=yellow;
end process;
red_light=’0’;
end fsm;
IV. RTL Schematic of Given
Design

Fig c. Technology Schematic

VI. Results
The results of the simulation were
seen to be as follows:

Fig b. RTL schematics

V. Technology Schematics
The figure shown below is an
Technology Schematic :
1. The FPGA kit was connected to
the PC via Parallel port slot.
2. Supply was given to the FPGA
kit.
3. The program code was copied
into the Xilinx folder.
4. Then the project was opened in
the Xilinx simulator.
5. Process Synthesize XST was
carried out
6. Then In User Constraints Process
the pin name and numbers of
input and output are defined i.e.
UCF file is created.
7. Then Process Implement Design
was Carried Out.
8. Program file was generated.
9. Then the Process was Run on the
FPGA kit.
10. At last, input conditions are
VII. Hardware Implementation changed and respective output
pins were observed.

The circuit was implemented on a FPGA


kit having several extra peripherals. VIII. Pin Configuration

What we connected is a clock generated


by the FPGA to the input pin assigned
The following were the pins used and the
and a sensor that can be connected to
pin numbers were assigned as follows:
+Vcc or ground.

By changing the conditions of traffic i.e.


the sensor input we observe different
Traffic signal status.
Fig c Table Of Pin configuration
The following were the steps followed
while implementing the code on
hardware:
Pin Name Pin Pin
Number Function
clock 2 Input
sensor 3 Input
green_light 4 Output
yellow_light 5 Output
red_light 7 Output

IX. CONCLUSION

Thus the Above circuit of Traffic Light


Controller was successfully implemented
and simulated too on the Xilinx Software
as well as successfully hardware tested
on Xilinx FPGA kit.

X. REFERENCES
The following were some of the
references used in getting the desired
project successfully implemented

1. FPGA Prototyping by VHDL


Examples: Xilinx Spartan-3
Version By Pong Chu

2. Digital System and Design By


R.P Jai

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