COMPUTER-AIDED DESIGN OF

ALGORITHMIC STATE MACHINE

Safaa Sahib Omran

Foundation of Technical Education, Iraq
[email protected]

Saleem M R Taha
University of Baghdad, Iraq

Ahmed Amer Ibraheem

Engineer

ABSTRACT
The Algorithmic State Machine (ASM) is a method used to solve more complex industrial
problems. The basic advantage of this method is to convert these problems to simpler circuits
which consist only from the basic elements which are AND, OR and NOT gates, which can be
implemented easily by using the Programmable Logic Array (PLA) circuits.
The entry variables (number of inputs and states) for such problems are large, this made the
theoretical (manual) solution is hard to solve. This research constructs a computer package called
(ASM-CAD) to make the entire design using C++ and TC++ programming languages.

Key Words:
Algorithmic State Machine (ASM) method.Programmable Logic Array (PLA) circuit. Quine-McCluskey
is a programmable method.

1. Introduction
An approach to logic design of a digital architecture, also called the data processor.
system is to partition the system into two Such a partition is given in Fig (1) below
entities: a controller and a controlled [1].

Status Information

Commands
Controller Controlled
(ASM) Architecture
(data processor)

External inputs Input data Output data

Fig (1), Partitioning of a digital system.

A well-defined procedure consisting of a There are several significant differences
finite number of steps to the solution of a between the ASM and the well known
problem is called an algorithm. Thus, the flowchart technique used in computer
controller is regarded as a hardware program design. There are several
algorithm and, consequently, it is referred to significant differences, but the main one is
us an Algorithmic State Machine, or, concerned with the representation of time
simply, ASM. relationships. The flowchart usually
Although an algorithmic state machine as a represents a continuous time flow from top
controller facilitates the design of larger to bottom to reflect the sequence of
digital systems incorporating Middle Scale operations performed by the program. The
Integration (MSI) components, an ASM chart, on the other hand, has
algorithmic state machine can also serve as a discontinuities in the time frame and time
stand-alone sequential network module. In moves on in quantum steps as control passes
this case there is no data processor being from one state to the next. Within the
controlled and the network being modeled is portion of the chart devoted to one state
essentially a classical Mealy network or there are no assumed time relationships [4,
Moore network. Hence, the algorithmic state 5].
machine becomes another approach to
clocked synchronous sequential network
modeling [2].
2. Design of ASM-CAD
The ASM or Algorithmic State Machine is
The ASM chart provides a diagrammatical
another name for a sequential network. This
representation of the state-transition
name is often used when the sequential
functions and output functions of a state
network is used to control a digital system
machine. It is used as an aid to the design of
that carries out a step-by-step procedure or
a state machine for the implementation of an
algorithm. It is a special type of flowchart so
algorithm and on completion becomes part
the ASM also called state machine
of the design documentation.
flowchart, the ASM may be used to describe
Because of the many degrees of freedom in
the behavior of a state machine [3].
designing an algorithmic state machines, no
There are two methods for controlling a
single procedure can be considered to be the
digital system, ASM and microcomputer
best available. To provide a framework for
based digital system. There are many
solving this problem, the task can be divided
differences between these two methods,
into a series of steps as follows:
some of them are:
1. Construct an algorithmic state diagram
1. The execution of the circuit by using
or state table for the state machine.
the ASM is more speed than using the
2. Assign proper states with efficient
microcomputer.
codes (using state locus).
2. The hardware cost by using the ASM
3. Construct next state table along with
is less expensive than using the
input information for flip-flops.
microcomputer.
4. Design flip-flops input forming logic.
3. The modification of the hardware by
5. Design output forming logic.
using the ASM is more difficult
6. Draw final circuit diagram using
than using the microcomputer.
Programmable Logic Array (PLA).
For the design of ASM-CAD, the Quine- A- Monitoring the number of picture
McCluskey method is used instead of tubes:
Karnaugh-map since it is easily programmed Two photoelectric barriers (E and H) control
method [6, 7, 8]. the entry of picture tubes to, and their
Using the ASM-CAD package to design the removal from, the buffer store. The light
example down below: barriers’ impulses are transmitted to a
The desired circuit may be considered to counter. If the buffer store is empty at the
operate due to the following design beginning of a shift, the counter can be
specifications. Fig (2) shows the process calibrated by pressing a momentary-contact
schematic. pushbutton.
B- Upper limiting value:
The buffer store is full when it contains
30 picture tubes. Conveyor belt motor
3. Problem definition
Z1 must be stopped immediately.
An assembly line has a picture tube buffer
C- Lower limiting value:
store, which can accommodate up to 30
A lamp must indicate that the buffer
picture tubes.
store contains fewer than 10 picture
tubes.

ON Signal
OFF C Z2

Calibrate D

E
5 4 3 2 1
Z1

H
30

Fig (2), Process schematic of buffer store.

4. Solution procedure H=1 means the tube out from the store.
Firstly, make the following declarations C=1 means the operation is ON.
and assumptions: D=1 means the counter is cleared.
1. Two barriers (E and H) control the G=1 means the store is full.
entry and exit from buffer store F=1 means the store contain fewer than 10
and the counter up and down, tubes then Z2 ON.
respectively. Z3=1 means the counter is incremented.
2. If G=1 (N=30) then the store is full Z4=1 means the counter is decremented.
and Z1 OFF. Secondly, according to the above
3. If F=1 (N<10) then Z2 ON. assumptions, construct the proposed ASM
E=1 means the tube enter the buffer store. control circuit as shown in Fig (3) below.

E Z2
H ASM Control
C to be
D Z1
designed
F
G
Z4

Z3

D Up/Down Counter

Compar Compar F=1 if N<10

ator 2 ator 1
F=0 if N>=10
G=1 if N=30
30 10
G=0 if N<30

Fig (3), Block diagram of buffer store.

Thirdly, construct the ASM-chart as
shown in Fig (4) below.

1 0
C

1
D
0

b Z1

1 0
E

Z3

1 0
G
0
1
c H

Z4
1 0
H

Z4 1 0
F

Z2

Fig (4), ASM-chart for the buffer store.

Fourthly, make the state table from the

ASM-chart as shown in Fig (5)
below.
 Present State Inputs Next Outputs
C D E F G H State Z1 Z2 Z3 Z4
a 0 x x x x x a 0 0 0 0
a 1 0 x x x x a 0 0 0 0
a 1 1 x x x x b 0 0 0 0
b x x 0 0 x 0 b 1 0 0 0
b x x 0 1 x 0 b 1 1 0 0
b x x 0 0 x 1 b 1 0 0 1
b x x 0 1 x 0 b 1 1 0 1
b x x 1 x 1 x c 1 0 1 0
b x x 1 0 0 0 b 1 0 1 0
b x x 1 1 0 0 b 1 1 1 0
b x x 1 0 0 1 b 1 0 1 1
b x x 1 1 0 1 b 1 1 1 1
c x x x x x 0 c 0 0 0 0
c x x x x x 1 b 0 0 0 0

Fig (5), State table for the buffer store.

The procedure of how the package works 5. The package asks the user to assign
is as follows: codes to each state.
1. The user must enter all the data 6. The package computes the state
from the state table that locus and prints it out on the screen.
constructed from the ASM-chart 7. The package print out the assigned
(designed by the user) to the ASM- state table for each state locus.
CAD package. 8. The package repeats steps (5, 6 and
2. The package prints out the original 7) until reaches the number entered
state table as entered on the screen in step (4).
just to make sure from the 9. The package computes the minimum
correctness of the data. state locus and prints it out on the
3. The package computes the number screen.
of the required flip-flop and prints 10. The package asks the user to choose
it out on the screen. one type of a flip-flop.
4. The package asks the user to enter 11. The package computes the next state
the number of assignments. equations for the flip-flop and the
output equations for the circuit.
 The Result lists of the Buffer Store will be OUTPUT EQUATION FOR OUTPUT Z2:
NEXT STATE EQUATION FOR STAGE Z 2 = ( EF + F G ) AB
A: OUTPUT EQUATION FOR OUTPUT Z3:
JA = EG AB and KA = HA Z 3 = E AB
NEXT STATE EQUATION FOR STAGE OUTPUT EQUATION FOR OUTPUT Z4:
B:
Z 4 = ( EH + GH ) AB + HA
JB = CD B and KB = 0
12. Finally, the package draws the PLA
OUTPUT EQUATION FOR OUTPUT
circuit diagram for the circuit which
Z1:
satisfies the above equations as
Z1 = AB shown in Fig (6).

Z1

Z2

Z3

Z4
JA

KA
JB

Logic 0

Clock

Fig (6), PLA circuit diagram for the buffer store.

5. Conclusion References:
As the problems becomes more and more [1] Donald D. Givone, “Digital Principles
complex (large numbers of inputs and and Design”, Tata McGraw-Hill Publishing
outputs), the theoretical solution (the Company Limited, 2003.
manual) becomes unpractical and need a
several hours to make the entire design, so [2] D. Green, “Modern Logic Design”,
this package is very useful and save time Workingham: Addison Wesley, 1986.
and effort (need only a few seconds to make
the entire design), the ASM is a powerful [3] Klingman, Edwin E., “Microprocessor
method on a digital system since it gives a System Design”, Prentice - Hill, Englewood
simple circuit consist of AND, OR and NOT Cliffs, N. J., 1982.
gate only (PLA elements).
A set of test problems have been performed [4] Stephen Brown and Z. Vranesic,
on all parts of the package, comparing “Fundamentals of Digital Logic with VHDL
between the results obtained from the Design”, McGraw-Hill, 2000.
computer and the theoretical (manual)
results lead to identical, valuable and [5] Wiatrowski, Claude A. and Charles H.
reliable results. The program gives error-free House, “Logic Circuits and Microcomputer
results if the user constructs the ASM-chart Systems”, McGraw-Hill Book Co., New
in a proper and correct way. The reason of York, 1980.
why using of Quine-McCluskey method
instead of using Karnaugh-map is that, for [6] David J. Comer, “Digital Logic and State
example consider the studied circuit above Machine Design”, Holt-Saunders
(Buffer Store), there is three states and 6- International Edition, 1984.
inputs this mean needing of 8-variable K-
map (2^8=256 squires). By using Quine- [7] John F. Wakerly, “Digital Design
McCluskey method, this is also need along Principles and Practices”, Prentice-Hall, 3rd
time to solve but it is easily programmed edition, August 2000.
method.
[8] C. R. Clare, “Designing Logic Systems
Using State Machines”, McGraw-Hill Book
Company, 1973.