Saint Louis University

School of Engineering and Architecture

Department of Electrical Engineering

Block Transfer and Search

Gole Cruz, Naomi Aira D

Date Submitted: May 4, 2020

 The Z80 microprocessor has eight very powerful block instructions which allow
operations on blocks of consecutive memory bytes. Four of the instructions are block
transfer instructions which allow the contents of one block of memory bytes to be
transferred to another block of memory; the other four instructions are block search
instructions which allow a block of memory bytes to be searched for one of the bytes
containing a specified value.

BLOCK TRANSFER INSTRUCTIONS

Block data transfer instructions load/store a set of general purpose register

values from/to main memory; the instruction format. These instructions are used for
procedure entry and return (saving and restoring workspace registers), and in writing
memory block copy routines.

The set of registers to be transferred is encoded using a 16-bit value; the

program counter may be included in the list (bit fifteen). The memory block is
determined by the base register Rn, and the bits P and U. The W flag enables base
register write back (auto-indexing). There are also special forms of the instruction for
accessing the user mode registers (when not in user mode) and for restoring the CPSR
when returning from an exception – these options are controlled by the S flag and bit
fifteen.

The instruction syntax is illustrated below:

LDM|STM{<cond>}<add more> Rn{!}, <registers>

LDM{<cond>}<add more> Rn{!}, <registers + pc>^
LDM|STM{<cond>}<add more> Rn{!}, <registers - pc>^

Here is a condition code, is the address mode and is a list of registers. The block
copying address modes are IA, IB, DA and DB – as indicated these
bincrement/decrement the address register after/before each memory access.2 An ! is
used for base register write-back, and the suffix ^ is used to set the S flag.

As an example, if the processor is in supervisor mode with the Z flag set, the instruction

LDMEQDB r0! {r1, r2, pc}^

will perform the following assignments:

r0 ← r0-12; r1 ← mem[r0-12]; r2 ← mem[r0-8]; r15 ← mem[r0-4]; CPSR ← SPSR_svc

All transfers are ordered: registers with lower indices are mapped to lower memory
addresses.

The register list should not be empty i.e. the lowest sixteen bits of the op-code
should not all be clear. This restriction will be enforced by any sensible compiler and/or
assembler, but this does not guarantee that such instructions can never be executed (it
is trivial to write an assembly program that generates and then executes such an
instruction). The ARM6 has an unfortunate load multiple-behaviour when the register list
is empty – a load to the program counter occurs. Rather than specify this at the
programmer’s model level, the hol model of the ARM6 has been modified to give a more
sensible behaviour i.e. no load occurs.

With block stores, if the program counter is in the list then the value stored is
implementation dependent. If the base register is in the list then write-back should not
be specified because the result is unpredictable. The hol programmer’s model
specification has been tailored to conform with ARM6 behaviour for these case.

The hol specification of the block data transfers is shown in Figure 3. The
function LDM STM takes the current programmer’s model state, the processor mode
and the instruction op-code, and it gives the next state. This function is only called when
it is established that op-code n

is a block data transfer instruction that passes the conditional execution test. The state
space constructor ARM takes a triple: the memory mem, the general purpose registers
reg, and the program status registers psr.

Although the definition of LDM STM is not especially large, there are some subtle
aspects to the semantics of block data transfers. Depending on the context, the
processor mode is either mode or mode’ (which might be set to user mode), therefore
one must pay attention as to which mode is being used when accessing registers. The
register bank after incrementing the program counter is denoted by pc reg and after
register write-back this becomes wb reg. If the first register of a block store is the base
register then the value rn is stored (i.e. pc reg is used), otherwise write-back may have
occurred and rn’ is stored (wb reg is used). Write-back occurs only if the base register is
not the program counter.

There are four key sub-functions: DECODE LDM STM, ADDR MODE4, LDM
LIST and STM LIST; these are defined in Appendix B. The function DECODE LDM STM
takes the op-code and splits it into seven fields. For example, the instruction LDMEQDB
r0!, {r1,r2,pc}^ is encoded with the natural number 158367750, and this decodes as
follows:
DECODE_LDM_STM 158367750 = (T,F,T,T,T,0,T)

The function ADDR MODE4 takes the address mode flags (P and U), the base
address rn and the op-code n, and it gives a pair (bl list,rn’). With our example:
ADDR_MODE4 T F rn 158367750 = ([(1,rn - 0xC); (2,rn - 0x8); (15,rn - 0x4)],rn - 0xC)

If write-back is enabled then register Rn takes the value rn’; bl list consists of
pairs of the form (rp,addr) where rp is a register index and addr is the corresponding
memory address. A function REGISTER LIST gives the list of register indices and this is
‘zipped’ with the memory block addresses.

The function LDM LIST folds the list bl list with a memory-read, register-write
operation to give the next state of the register bank. Likewise, the function STM LIST
folds the list with a register-read, memory-write operation to give the state of the main
memory.

Suppose it was necessary to move the contents of a block of ten memory bytes,
starting at the byte labelled SOURCE, to a block starting at a byte labelled DESTIN.
Program 14.1 could be used to perform that function.
Program 14.1 block transfer – the hard way
LD HL,SOURCE set up pointers
LD DE ,DESTIN
LD B,10 and counter
NEXBYT: LD A, (HL) transfer byte
LD (DE),A
INC HL increment pointers
INC DE
 DJNZ NEXBYT and counter
HALT
SOURCE: DEFM 'ABCDEFGHIJ
DESTIN: DEFM '0000000000'

The register pairs HL and DE are set to point to the first byte of the source and
destination blocks of memory bytes, respectively. The register B is to be used as the
counter and is initialised to ten.

In the loop, a byte is transferred from the source block of memory bytes to the
destination block of memory byts via the accumulator. The register pairs HL and DE are
both incremented by one to point to the next bytes in the source and destination blocks
of memory bytes.

When the looping finishes and the HALT instruction is executed, the string of the
first ten letters of the alphabet will have been moved, character by character, to the ten
bytes starting at DESTIN, thereby overwriting the zeros originally contained in those
bytes.

The Z80 microprocessor has an instruction which could replace the instructions
in the loop in Program 14.1. It is the LDIR instruction - LoaD, Increment and Repeat.
Prior to execution of the LDIR instruction, HL must contain the address of the first of the
source block memory bytes, DE must contain the first of the destination block memory
bytes, and BC must contain the number ofn bytes to be transferred. Program 14.2
shows a version of Program 14.1 using the LDIR instruction.

Program 14.2 block transfer the easy way

LD HL,SOURCE set up pointers
LD DE ,DESTIN
LD BC, 1 0 and counter
LDIR transfer block
HALT
SOURCE: DEFM 'ABCDEFGHIJ
DESTIN: DEFM '0000000000'

Program 14.2 is functionally the same as Program 14.1 except that Program 14.2
allows blocks of up to 64K bytes to be transferred, since a register pair is being used as
the counter instead of a single register. For each byte transfer HL and DE are
incremented by one and BC is decremented by one - the transfer continues until BC is
equal to O.
The LDDR - LoaD, Decrement and Repeat instruction is the same as the LDIR
instruction except that, as its mnemonic suggests, HL and DE are decremented instead
of incremented.
 References

Fox, A (n.d.). Verifying the ARM Block Data Transfer Instructions. Retrieved from
https://acjf3.github.io/papers/bdt.pdf
Hutty, R.(1981). Z80 Assembly Language Programming for Students. Retrived from
https://page- one.springer.com/pdf/preview/10.1007/978-1-349-06155-6_14