LABORATORY MANUAL

COURSE CODE:ECE 201

COURSE TITLE
ELECTRONIC DEVICES AND CIRCUITS
EXPERIMENT 1
Experiment :
To implement Full Adder using NAND gates.
Apparatus Required: -
IC 7486, IC 7432, IC 7408, IC 7400, etc.
Learning Objectives:
Students will know how to make Full adder with help of basic NAND gates
Full Adder using basic gates:-

Procedure: -
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to the
truth table.
4. Note down the output readings for half/full adder and half/full subtractor
sum/difference and the carry/borrow bit for different combinations of inputs.
Full Adder Truth Table:

Cautions:

1. Connections must be Tight.

2. Pin Configuration of ICs must be considered carefully before use

3. Continuity of ICS must be tested before use.

 EXPERIMENT 2

Experiment :

To design and realize MOD 10 UP/DOWN Counter

Apparatus Required: -

S.No Equipment required Quantity

1 IC 7476 1

2 POWER SUPPLY ( +15 TO -15V) 1

3 RESISTORS ( 10K, 3.3K, 15.9K) 3
4 BREADBOARD 1
5 741 IC 1
6 CAPACITOR ( 0.01uF) 1
7 CRO 1
8 CONNECTING WIRES

Learning Objectives:

Students will learn the working of Counter

Mod-10 Counter
The modulo-10 counter is a counter that has states from 0 to 9. Thus it is also called a BCD
counter.In this lab, you are required to use your existing mod-16 counter to design a mod-10 counter.
Note
the counter sequence required for modulo-10 counting
0000 – (0)
0001 – (1)
0010 – (2)
.
.
.
1001 – (9)
0000 – (0)
0001 – (1)
.
A MOD 10 counter has 10 possible states. In other words it counts from 0 to 9 and rolls over.
12.1 How many Flip-Flops could do it?
( This could be on single IC, but we wil use JK Flip-Flops.)

The trick is to find a way not to use all of those states. There must be a way to “force” the
counter to stop counting at 9 and roll over to 0.
This is where the asynchronous inputs come into play. The asynchronous inputs can override the
synchronous inputs and force the output either high or low.
When Preset = 1, Q = 1
When Clear = 1, Q = 0

Looking at truth table, the counter should run from

Since the counter has to display 1001, the next number 1010 will be used to reset the counter to
zero. Since the asynchronous inputs are active high, an AND gate will be used. The two flip-flops
where a “1” occurs will be tied to an AND gate, and the output will be tied to the “clear” input.

When the counter goes to 1010, the AND gate will have a 1 on its output and will activate the
“clear “ inputs. This will reset the counter to 0000. The 1010 will never be displayed. In
essence,the counter counted/displayed from 0000 to 1001.
Cautions:
 EXPERIMENT 3

Experiment :

To realize a 7-segment code converter

APPARATUS REQUIRED :

S.No Equipment required Quantity

1 BCD TO SEVENT SEGMENT 1

DECODER DRIVER IC
7446/7447

2 POWER SUPPLY ( +5 TO -5V) 2

3 RESISTORS ( 220 OHM) 7

4 DIGITAL TRAINER KIT 1

Learning Objective:
Design and build gray code to binary converter. And Design and build BCD-to-7 segment converter.

Seven-Segment LEDs
The seven-segment LED display has four individual digits, each with a decimal point. Each of
the seven segments (and the decimal point) in a given digit contains an individual LED. When
a suitable voltage is applied to a given segment LED, current flows through and illuminates
that segment LED. By choosing which segments to illuminate, any of the nine digits can be
shown.
Pin Connections

1. A, B, C, D are the binary inputs.

2. a, b, c, d, e, f, g, h are the driver signals to the display elements.
3. LT is the lamp test control, turns all segment On, active Low
4. BL blanks all segments when activated, active LOW
5. LE is the latch enable control.
Truth table
The funct ion of a BCD to 7-segment decoder is to convert the logic states at the outputs of a
BCD counter such as the 4510 into a form which will drive a 7-segment display. The display
shows the decimal numbers 0-9 and is easily understood.
The individual segments making up a 7-segment display are identified by letters as follows
There are two important types of 7-segment LED display.
In a common cathode display, the cathodes of all the LEDs are joined together and the
individual segments are illuminated by HIGH voltages.

In a common anode display, the anodes of all the LEDs are joined together and the individual
segments are illuminated by connect ing to a LOW voltage.

When the 4511 is set up correctly, the outputs follow this truth table:
Cautions:

1. Connections must be Tight.

2. Pin Configuration of ICs must be considered carefully before use

3. Continuity of ICS must be tested before use.

 EXPERIMENT 4

Experiment :

To realize A/D converters. To realize D/A converters.

Apparatus Required: -

S.No Equipment required Quantity

1 OP-AMP 741 IC 2
2 POWER SUPPLY ( +15 TO -15V) 2
3 BREADBOARD 1
4 RESISTORS( 1K, 2K,4K, 10K) 4
5 CONNECTING WIRES 10
6 SIGNAL GENERATOR 1
7 RESISTORS ( 1K, 2K,4K) 3

Learning Objective:

Students will understand significance and working of A/D and D/A converters

Digital-to-analog converter
A digital-to-analog converter (DAC or D-to-A) is a device for converting a digital (usually
binary) code to an analog signal (current, voltage or electric charge).
A DAC, inputs a binary number and outputs an analog voltage or current signal. In block
diagram form, it looks like this:
This circuit is an operational amplifier circuit with three input voltages.

Each input voltage is either zero volts or five volts and represents a logical 0 or 1.
1. The input resistors are chosen so that they are not all equal.
2. The resistors are related by: Rc = 2Rb = 4Ra.

To understand how this circuit works we will need to obtain a symbolic

expression for the output voltage - one in which we express the output voltage in terms of the
binary number that the input represents. We already have an expression for the output voltage.
Vout = (RfVa /Ra) + (RfVb /Rb) + (RfVc /Rc)
We need to interpret this output voltage expression when the inputs represent a binary number.
Let's examine the expression for the output voltage using the relat ion we required for the
resistors.
Rc = 2Rb = 4Ra
Then, the output voltage expression becomes:
Vout = (RfVa /Ra) + (RfVb /Rb) + (RfVc /Rc)
 Vout = (RfVa /Ra) + (RfVb /2Ra) + (RfVc /4Ra)
Each input voltage is either zero (0) or five (5) volts, represent ing either a zero or a one.
Although we shouldn't mix Boolean algebra variables and ordinary algebraic variables, we are
going to. We're going to say
Va = 5A2
Vb = 5A1
Vc = 5Ao
So
Vout = (Rf/4Ra)(4Va + 2Vb + Vc )
Vout = (5Rf/4Ra)(4A2 + 2A1 + Ao )

A2 A1 A0 Binary 4A2+2A1+Ao
0 0 0 0 0
0 0 1 1 1
0 1 0 2 2
0 1 1 3 3
1 0 0 4 4
1 0 1 5 5
1 1 0 6 6
1 1 1 7 7

In other words, A2 is the 4 bit, A1 is the 2 bit and Ao is the 1

bit. After all this, we reach these conclusions for this circuit.
1. The inputs can be thought of as a binary number, one that can run from zero (0) to
seven (7).
2. The output is a voltage that is proportional to the binary number input.
3. The circuit itself converts a digital representation of a number to an analog version of
the same number. The circuit is a digital-to-analog converter also known as a D/A
converter
 EXPERIMENT 5

Experiment :

Realize JK FF using D FF.

Apparatus Required: -
The basic J-K Flip-flop is shown in Figure 2.

Figure 2 Simple J-K Flip-flop

Learning Objective:
Understanding concept of Desiging of flip Flops
Procedure

Like the R-S flip-flop the outputs follow the inputs when the Clk is logic, but there are
two inputs, traditionally labelled J and K.
If J and K are different then the output Q takes the value of J at the next clock edge.
If J and K are both low then no change occurs. If J and K are both high at the clock edge then
the output will toggle from one state to the other. It can perform the functions of the R-S Flip-
flop and has the advantage that there are no ambiguous states. Due to the extra logic that
ensures only one of the R and S inputs is enabled at any time. This prevents possible
oscillation, which can occur when both inputs of an RS flip-flop are active at the same time.
The truth table of this J-K flip-flop is shown in Table 1.

J K Clk Q Q_bar
0 0 Pos-edge No change
0 1 Pos-edge 0 1
1 0 Pos-edge 1 0
1 1 Pos-edge Toggle

Table 1 Truth table for the simple J-K Flip-flop of Figure 2

One problem with the basic J-K Flip-flop is that spikes can appear on the output and there is
an unstable state when both J & K inputs are logic ‘0’.
This can be eliminated by adding another ‘latch’ circuit of this flip-flop to isolate the outputs Q
and Q_bar
from the inputs J & K as shown in Figure 3.

The inverter connected between the two CLK inputs ensures that the two sections will be
enabled during opposite half-cycles of the clock signal.
 EXPERIMENT 7

Experiment :

To design and implement an emitter follower circuit. To find gain of the transistor in CE, CB and
CC configuration.

7(a)

gain of the transistor in CE configuration.

Apparatus Required: -

S.No. Name Range Qty

1 Transistor BC 107 1
10kohm
2 Resistor 1
1Kohm
Bread
3 1
Board
4 Wires

COMPONENTS REQUIRED:
 S.No. Name Range Qty
1 R.P.S (0-30)V 2

(0–10)mA 1
2 Ammeter
(0–1)A 1

(0–30)V 1
3 Voltmeter
(0–2)V 1

LEARNING OBJECTIVE:

To draw input and output characteristics of All configurations of Transistor

THEORY:
A BJT is a three terminal two – junction semiconductor device in which the
conduction is due to both the charge carrier. Hence it is a bipolar device and it
amplifier the sine waveform as they are transferred from input to output. BJT is
classified into two types – NPN or PNP. A NPN transistor consists of two N types in
between which a layer of P is sandwiched. The transistor consists of three terminal emitter,
collector and base. The emitter layer is the source of the charge carriers and it is heartily
doped with a moderate cross sectional area. The collector collects the charge carries and
hence moderate doping and large cross sectional area. The base region acts a path for the
movement of the charge carriers. In order to reduce the recombination of
holes and electrons the base region is lightly doped and is of hollow cross sectional area.
Normally the transistor operates with
the EB junction forward biased.

In transistor, the current is same in both junctions, which indicates that there is a
transfer of resistance between the two junctions. One to this fact the transistor is known as
transfer resistance of transistor.

PROCEDURE:
INPUT
CHARECTERISTICS:

1. Connect the circuit as per the circuit diagram.

2. Set VCE ,vary VBE in regular interval of steps and note down the
corresponding I B reading. Repeat the above procedure for different values of V CE .

3. Plot the graph: VBE Vs IB for a constant VCE.

OUTPUT
CHARECTERISTICS:

1. Connect the circuit as per the circuit diagram.

2. Set IB, Vary VCE in regular interval of steps and note down the
corresponding I C reading. Repeat the above procedure for different values of I B.
3. Plot the graph: VCE Vs IC for a constant IB.

PIN DIAGRAM:
B

Bottom View BC107 Specification: BC107/50V/0.1A,0.3W,300MHz

E C
 MODEL GRAPH:
INPUT CHARACTERISTICS: OUTPUT CHARACTERISTICS:

µA
m
A

IC
IB
V
C
E
=
0V IB=60 A
V
C
E
=
5V

IB=40 A

IB=20
0
VBE(V)
0
VC
E(
V)
 TABULAR COLUMN:
INPUT CHARACTERISTICS:

Sr no VCE=1 VCE=2
V V
VBE(V) IB(μA) VBE(V) IB(μA)

OUTPUT CHARACTERISTICS:

Sr no IB=20 IB=40 A
A
VCE(V) IC(mA) VCE(V) IC(mA)
1

h- PARAMETER CALCULATION :
%age ERROR :

from data sheet find values of

hie, hre, hfe, hoe and compare these values with practically obtained values to
find %age error

RESULT:
The transistor characteristics of a Common Emitter (CE) configuration were
plotted and uses studied.
CHARACTERISTICS OF CB CONFIGURATION USING BJT

APPARATUS REQUIRED: COMPONENTS REQUIRED:

S.No. Name Range Qty S.No. Name Range Qty
1 R.P.S (0-30)V 2 1 Transistor BC 107 1
10k
(0–10)mA 1 2 Resistor 1
1K
2 Ammeter
Bread
(0–1)A 1 3 1
Board
(0–30)V 1 4 Wires
3 Voltmeter
(0–2)V 1

THEORY:
 In this configuration the base is made common to both the input and out. The
emitter is given the input and the output is taken across the collector. The current gain of this
configuration is less than unity. The voltage gain of CB configuration is high. Due to the
high voltage gain, the power gain is also high. In CB configuration, Base is common to both
input and output. In CB configuration the input characteristics relate I E and VEB for a
constant VCB. Initially let VCB = 0 then the input junction is equivalent to a forward biased
diode and the characteristics resembles that of a diode. Where V CB =
+VI (volts) due to early effect IE increases and so the characteristics shifts to the left.
The output characteristics relate IC and VCB for a constant IE. Initially IC increases and
then it levels for a value IC = IE. When IE is increased IC also increases
proportionality. Though increase in VCB causes an increase in , since is a fraction, it is
negligible and so IC remains a constant for all values of VCB once it levels off.

PIN DIAGRAM:
B

Bottom View BC107 Specification: BC107/50V/0.1A,0.3W,300MHz

E C

CIRCUIT
DIAGRAM:
(0- (0-30)mA
1)mA + - 1K -
10 K + -

+ + +

(0-30)V VE (0-2)V (0-30)V (0-

B 30)V
VE
B (0-2)V (0-30)V (0-
30)V

- -

PROCEDURE:
INPUT CHARACTERISTICS:
It is the curve between emitter current IE and emitter-base voltage VBE at constant
collector-base voltage VCB.
 1. Connect the circuit as per the circuit diagram.
2. Set VCE=5V, vary VBE in steps of 0.1V and note down the corresponding I B.
Repeat the above procedure for 10V, 15V.
3. Plot the graph VBE Vs IB for a constant VCE.
4. Find the h parameters.

OUTPUT CHARACTERISTICS:
It is the curve between collector current IC and collector-base voltage VCB at
constant emitter current IE.
1. Connect the circuit as per the circuit diagram.
2. Set IB=20 A, vary VCE in steps of 1V and note down the corresponding IC.
Repeat the above procedure for 40 A, 80 A, etc.

3. Plot the graph VCE Vs IC for a constant IB.

4. Find the h parameters
TABULAR COLUMN:
INPUT CHARACTERISTICS:

S.No. VCB = V VCB = V VCB = V

VEB IE VEB IE VEB IE
(V) ( A) (V) ( A) (V) ( A)

OUTPUT CHARACTERISTICS:

S.No. IE= mA IE= mA IE= mA

VCB Ic VCB Ic VCB Ic
(V) (mA) (V) (mA) (V) (mA)
INPUT CHARACTERISTICS:

I
C
(mA) VCB1
IE2
VCB2

IE1 VEB1 VEB2 VEB (V)

OUTPUT CHARACTERISTICS:

IC
(mA)

IC2
IC1

VCB1 VC B2 VCB (V)

%age ERROR :

from data sheet find values of

 hic, hrc, hfc, hoc and compare these values with practically obtained values to
find %age error

RESULT:The transistor characteristics of a Common Base (CB) configuration were

plotted and uses studied.

CHARACTERISTICS OF CC CONFIGURATION USING BJT

APPARATUS REQUIRED: COMPONENTS REQUIRED

S.No. Name Range Qty S.No. Name Range Qty

1 R.P.S (0-30)V 2 1 Transistor BC 107 1
(0–30)mA 1 2 Resistor 1k 2
2 Ammeter Bread
(0–250)µA 1 3 1
Board
(0–30)V 4 Wires
3 Voltmeter

THEORY:

A BJT is a three terminal two – junction semiconductor device in which the

conduction is due to both the charge carrier. Hence it is a bipolar device and it
amplifier the sine waveform as they are transferred from input to output.
BJT is classified into two types – NPN or PNP. A NPN
transistor consists of two N types in between which a layer of P is sandwiched. The
transistor consists of three terminal emitter, collector and base. The emitter layer is the
source of the charge carriers and it is heartily doped with a moderate cross sectional area.
The collector collects the charge carries and hence moderate doping and large cross
sectional area. The base region acts a path for the movement of the charge carriers.
In order to reduce the recombination of holes and electrons the
base region is lightly doped and is of hollow cross sectional area.
Normally the transistor operates with the EB junction forward
biased.

In transistor, the current is same in both junctions, which indicates that there is a
transfer of resistance between the two junctions. One to this fact the transistor is known
as transfer resistance of transistor.
PIN DIAGRAM:

Bottom View BC107 Specification: BC107/50V/0.1A,0.3W,300MHz

E C

CIRCUIT DIAGRAM:

PROCEDURE:

INPUT CHARECTERISTICS:

1. Connect the circuit as per the circuit diagram.

2. Set VCE, vary VBE in regular interval of steps and note down the corresponding
IB reading. Repeat the above procedure for different values of V CE.
3. Plot the graph: VBC Vs IB for a constant VCE.
OUTPUT CHARECTERISTICS:
 1. Connect the circuit as per the circuit diagram.
2. Set IB, Vary VCE in regular interval of steps and note down the corresponding I C
reading. Repeat the above procedure for different values of I B.
3. Plot the graph: VCE Vs IC for a constant IB.

MODEL GRAPH:

INPUT CHARACTERISTICS: OUTPUT CHARACTERISTICS:

( A) (mA)
IB Ie

0 VBC(V) 0 VCE(V)

TABULAR COLUMN:

INPUT CHARACTERISTICS:

VCE=1 VCE=2
V V
VBC(V IB(μA) VBC(V IB(μA)
) )

OUTPUT CHARACTERISTICS:

IB=20 IB=40 A
A
VCE(V IE(mA) VCE(V IE(mA)
) )
h- PARAMETER CALCULATION :

%age ERROR :

from data sheet find values of hie, hic , hfc, hoe and compare these values with practically
obtained values to find %age error
RESULT:
The transistor characteristics of a Common Emitter (CC) configuration were
plotted.

(i)hie

(ii)hic

(iii)

hfc

(iv)hoe
 EXPERIMENT 8

Experiment : To find gain of the JFET

APPARATUS REQUIRED:

S.No. Name Range Qty

1 R.P.S (0-30)V 2

2 Ammeter (0–30)mA 1

(0–30)V 1
3 Voltmeter
(0-10)V 1

COMPONENTS REQUIRED:

S.No. Name Range Qty

1 FET BFW10 1

1k 1
2 Resistor
68K 1
Bread
3 1
Board
4 Wires

LEARNING OBJECTIVE:
To draw characteristics of FET and to get the value of gain
THEORY:
FET is a voltage operated device. It has got 3 terminals. They are Source,
Drain & Gate. When the gate is biased negative with respect to the source, the pn
junctions are reverse biased & depletion regions are formed. The channel is more
lightly doped than the p type gate, so the depletion regions penetrate deeply in to the
channel. The result is that the channel is narrowed, its resistance is increased, & I D is
reduced. When the negative bias voltage is further increased, the depletion regions
meet at the center & ID is cutoff completely.
PROCEDURE:
DRAIN CHARACTERISTICS:
1. Connect the circuit as per the circuit diagram.
2. Set the gate voltage VGS = 0V.
3. Vary VDS in steps of 1 V & note down the corresponding I D.
4. Repeat the same procedure for VGS = -1V.
5. Plot the graph VDS Vs ID for constant VGS.
OBSERVATIONS
1. d.c (static) drain resistance, rD = VDS/ID.
2. a.c (dynamic) drain resistance, rd = VDS/ID.
3. Open source impedance, YOS = 1/ rd.
4.
TRANSFER CHARACTERISTICS:
1. Connect the circuit as per the circuit diagram.
2. Set the drain voltage VDS = 5 V.
3. Vary the gate voltage VGS in steps of 1V & note down the corresponding I D.
4. Repeat the same procedure for VDS = 10V.
5. Plot the graph VGS Vs ID for constant VDS.

FET PARAMETER CALCULATION:

Amplification factor μ=rd . gm

CIRCUIT DIAGRAM:
BOTTOM VIEW OF BFW10: SPECIFICATION:Voltage : 30V, IDSS > 8mA.

MODEL GRAPH:
DRAIN CHARACTERISTICS:
 TRANSFER CHARACTERISTICS:

VDS (volts)

ID(mA)

VDS =Cons
VGS (V) VDS =Cons
TABULAR COLUMN: DRAIN CHARACTERISTICS:
VGS = 0V VGS = -
1V
VDS (V) ID(mA) VDS (V) ID(mA)

TRANSFER CHARACTERISTICS:
VDS =5volts VDS = 10volts
VGS (V) ID(mA) VGS (V) ID(mA)

%age ERROR :

from data sheet find values of

gmo and IDSS to get values of Rd gm  IDSS VP using formulas and compare
these values with practically obtained values to find %age error

RESULT:
Thus the Drain & Transfer characteristics of given FET is Plotted.
Rd =
gm =
 =

IDSS =
Pinch off voltage VP =
 EXPERIMENT 9

Experiment :

To perform experiment on clipping , biased clipping and clamping

Apparatus:
1. Function Generator.
2. Oscilloscope.
3. DC Power Supply.
4. Breadboard, Diodes, Capacitors and Resistors
Objective:
To steady the diode applications in a clipping and clamping circuits.
Theory:
This experiment studies the applications of the diode in the clipping & clamping
operations.
1. Clipping Circuits:
the Figure (l) shows a biased clipper, for the diode to turn in the input voltage must be
greater +V, when Vm is greater than +V , the diode acts like a closed switch (ideally)
& the voltage across the output equals +V , this output stays at +V as long as the input
voltage exceeds +V.
when the input voltage is less than +V , the diode opens and the circuit acts as a
voltage divider, as usual , RL should be much greater than R, in this way , most of
input voltage appears across the output.
The output waveforms of Figure (1) summarize the circuit action. The biased clipper
removes all signals above the (+V) level.
2. Clamping Circuits:
A clamper does is adding a DC component to the signal. In Figure (2) the input signal
is a sinewave, the clamper pushes the signal upward, so that the negative peaks fall on
the 0V level. As can see, the shape of the original signal is preserved, all that happen
is a vertical shift of the signal.
We described an output signal for a positive dampen- On the Figure (2) shown
represents a positive clamper ideally here how it is works. On the first negative half
cycle of input voltage, the diode turns on.
At the negative peak, the capacitor must charge to Vp with polarity shown. Slightly
beyond the negative peak, the diode shunts off.
Procedure:
Clipping Circuit:
1. Connect the circuit shown in Figure (3).
2. Ensure that the variable DC is at minimum and the source is at 10VP.P.
3. Observe and Sketch the input and output waveforms.
4. Increase the variable DC voltage to 4V, and notice to what voltage are the
positive
peaks chopped off, sketch the waveforms.
Clamping Circuit:
1. Connect the circuit shown in Figure (4).
2. Ensure the variable DC is at minimum.
3. Set the sine wave generator frequency to 1KHz and its output amplitude to 10VP.P
.
4. Observe and sketch the input waveform with the variable DC at minimum,
Sketch the output waveform.
Discussion:
1. What happened if the DC voltage in the clamping circuit is replaced by an a.c
source?
2. What is the relationship between the clipping level and the DC voltage?
3. If the variable DC source is reversed, how does this affect the clipping?
4. If the input voltage 10VP.P, sketch the output of the circuit shown below.
 EXPERIMENT 10

Experiment :

To perform experiment on voltage regulation

Apparatus Required:

Resistor ( 0 – 1 Kohm) , Zener Diode, Voltmeters, Variable DC Supply

Objectives:
 To recognize zener diodes in various physical forms and to distinguish them from
rectifying diodes.
 To understand the constant-voltage characteristic of a reverse-biased zener diode.
 To understand the use of a zener diode in a simple voltage regulator circuit.

The Zener Diode Reverse Characteristics

• The method obtaining the voltage-current characteristics is the similar to that of

Assignment 1 but notice that the zener diode is reverse biased. Using the power
supply variable control, set VS to the values given in Table
• For each value record Vr, then calculate:
Plot Vd against Id and also plot Vs against Pd
A Simple Zener Diode Voltage Regulator
 The Zener diode has a region in its reverse characteristics of almost constant voltage
regardless of the current through the diode. This can be used to regulate or stabilize a
voltage source against supply or load variations.
 A Zener diode whose breakdown voltage is the desired constant voltage is connected
across the load as shown in Figure

 Construct the circuit of Fig

• Now set the potentiometer temporarily to make IL=0, and then slowly increase VS
until the diode just begins to conduct current, say 1mA. Record VS and IL=0 in the
first row of the table.
• Now set the potentiometer to maximum (clockwise). The extra current drawn by R L
will reduce the diode current to below 1mA.
• Increase VS to 12V; the diode current will increase above 1mA. Then adjust RL until
the diode current just returns to approximately 1mA. Again record VS and IL
  Repeat this for VS=14, 16, 18 and 20V.

Plot IL against VS.

• Every point on your graph represents a condition where the Zener diode has only just
reached its breakdown voltage. Thus, for a given IL, a lower value of VS will take the
diode out of breakdown and, for a given VS, a higher value of IL will do the same.
• Therefore the whole of one side of your graph is an area where the diode is not in
breakdown and thus is not holding VL constant. Mark this area in your graph.
 What sets a limit to the minimum load current and the maximum supply voltage?
 Reduce VS in steps of 1V, each time resetting RL to give Id=150mA approximately
and record IL. Continue until it is no longer possible to set Id to 150mA.
 Plot VS against IL on the same axes used for your previous graph
 Shade on your graph the area that now represents the useable range of VS and IL