994 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO.

2, APRIL 2007

Decentralized Control for Parallel Operation of

Distributed Generation Inverters Using
Resistive Output Impedance
Josep M. Guerrero, Member, IEEE, José Matas, Luis García de Vicuña,
Miguel Castilla, and Jaume Miret, Member, IEEE

Abstract—In this paper, a novel wireless load-sharing controller common electrical distribution bus. In such systems, every unit
for islanding parallel inverters in an ac-distributed system is pro- must be able to operate independently without intercommu-
posed. This paper explores the resistive output impedance of the nication due to the long distance between DG units [2]. In
parallel-connected inverters in an island microgrid. The control
loops are devised and analyzed, taking into account the special order to achieve good power sharing, the controller makes tight
nature of a low-voltage microgrid, in which the line impedance adjustments over the output-voltage frequency and amplitude
is mainly resistive and the distance between the inverters makes of the inverter [3]. This control technique, which is known as
the control intercommunication between them difficult. In con- the droop method, consists in emulating the behavior of large
trast with the conventional droop-control method, the proposed power generators, which drop their frequencies when the power
controller uses resistive output impedance, and as a result, a
different control law is obtained. The controller is implemented by delivered increases.
using a digital signal processor board, which only uses local mea- There are many control schemes for linear load sharing
surements of the unit, thus increasing the modularity, reliability, based on the droop method [4]–[10]. In [8], a controller was
and flexibility of the distributed system. Experimental results are proposed to also share nonlinear loads by adjusting the output-
provided from two 6-kVA inverters connected in parallel, showing voltage bandwidth with the delivered harmonic power. In an-
the features of the proposed wireless control.
other approach [10], every single term of the harmonic current
Index Terms—Distributed generation (DG), droop method, is used to produce a proportional droop in the corresponding
inverters, microgrids. harmonic voltage term. However, the droop method exhibits a
slow dynamic response since it requires low-pass filters with a
I. I NTRODUCTION reduced bandwidth to calculate the average value of the active
and reactive powers [11]. In [12], a wireless controller was
T HE GENERATION of highly reliable good-quality elec-
trical power near the place where it is demanded can imply
a change of paradigm. This concept, which is named distrib-
proposed in order to enhance the dynamic performance of the
paralleled inverters by adding integral–derivative power terms
to the droop-control method.
uted generation (DG), is especially promising when dispersed-
Using the conventional droop method, the output impedance
energy storage systems (fuel cells, compressed-air devices,
and line impedance are considered to be mainly inductive,
or flywheels) and renewable-energy resources (photovoltaic
which is often justified by the large inductor value or by the long
arrays, variable speed wind turbines, or combined cycle plants)
distances between the units. However, this is not always true
are available. These resources can be connected through power
since the output impedance of the inverter depends also on the
conditioning ac units to local electric power networks, which
control strategy [13], [14], and the line impedance is predom-
are also known as microgrids [1]. Hence, inverters or ac–ac
inantly resistive for low-voltage cabling. Another problem of
converters are connected to the local dispersed loads via a
the droop method is that the power sharing is degraded if either
the output impedance or the line impedance is unbalanced. To
Manuscript received September 7, 2005; revised February 24, 2006. Abstract ensure inductive output impedance, fast control loops are added
published on the Internet January 14, 2007. This work was supported by to the droop-control method, thus avoiding the use of an extra
the Spanish Ministry of Science and Technology under Grant DPI 2003-
06508-C02-01. This paper was presented in part at the European Confer-
output inductor.
ence on Power Electronics and Applications (EPE’05), Dresden, Germany, On the other hand, the droop method has been studied
September 11–14, 2005. extensively in parallel dc converters [15]–[21]. In these cases,
J. M. Guerrero is with the Departament d’Enginyeria de Sistemes,
Automàtica i Informàtica Industrial (ESAII), Escola Universitària d’Enginyeria resistive output impedance is enforced easily by subtracting
Tècnica Industrial de Barcelona (EUETIB), Universitat Politècnica de a proportional term of the output current from the voltage
Catalunya (UPC), 08036 Barcelona, Spain (e-mail: josep.m.guerrero@ reference. However, little work has been done in the applica-
upc.edu).
J. Matas, L. García de Vicuña, M. Castilla, and J. Miret are with the Departa- tion of the resistive droop method to parallel inverters [22],
ment d’Enginyeria de Electrònica, Universitat Politècnica de Catalunya, 08036 [23]. The advantages of such an approach are the following.
Barcelona, Spain. 1) The overall system is more damped. 2) It provides automatic
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. harmonic current sharing. 3) Phase errors barely affect active
Digital Object Identifier 10.1109/TIE.2007.892621 power sharing.

0278-0046/$25.00 © 2007 IEEE

GUERRERO et al.: CONTROL FOR PARALLEL OPERATION OF DG INVERTER USING RESISTIVE OUTPUT IMPEDANCE 995

Fig. 1. Distribution scheme of a possible microgrid.

Fig. 2. Equivalent circuit of a DG unit connected to the common ac bus.

In this paper, we propose a novel control scheme that is

Fig. 3. Stable and unstable regions of the power angle.
able to further improve the steady-state and transient response
of parallel-connected inverters without using communication
signals. The controller uses resistive output impedance, which Assuming that the output impedance is resistive (Z = R and
allows good power sharing with low sensitivity to the line- θ = 0◦ ), the active and reactive powers become
impedance unbalances. Finally, the output impedance is de-
signed to share not only active and reactive powers but also the
EV V2
harmonic content of the total loads. P = cos φ − (3)
R R
EV
Q= − sin φ. (4)
II. R ESISTIVE O UTPUT -I MPEDANCE R
P OWER -F LOW A NALYSIS
From (4), the stability bounds of φ can be found. Note that
Fig. 1 shows a general scheme of a microgrid that consists of the range −90◦ < φ < +90◦ causes a negative slope of Q,
a combination of multiple microgenerator DG units, distributed as shown in Fig. 3. Outside of this range, a change of slope
loads, and electric power interfaces that transfer energy to the appears, thus leading to an unstable behavior.
local ac bus. The microgrid can be connected to the utility grid Using polar coordinates, the complex power injected to the
through a single point of common coupling. When the utility ac bus (S = P + jQ) can be written as
grid is not present, the DG units should be able to share the
total power demanded by the local loads, adjusting their output-
V2 EV −jφ
voltage references as a function of the delivered power. S=− + e (5)
Fig. 2 shows the equivalent circuit of a DG unit as an inverter R R
connected to a common ac bus through a decoupling output
which is shown in Fig. 4 as a circumference with a radius of
impedance. The active and reactive powers injected to the bus
EV /R and a center point at −V 2 /R.
by every unit can be expressed as follows [24]:
It is worth pointing out that S (and, thus, both P and Q)

 depends simultaneously on both output-voltage parameters E
EV V2 EV
P = cos φ − cos θ + sin φ sin θ (1) and φ, as shown in Fig. 5. Assuming an initial power SA , the
Z Z Z power moves to SB by increasing E (from EA to EB ), given

 that the circumference diameter becomes higher (φ is constant).
EV V2 EV Note that both P and Q increase when E increases. On the other
Q= cos φ − sin θ − sin φ cos θ (2)
Z Z Z hand, the power moves clockwise from SB to SC , following the
exterior circle by increasing φ from φB to φC (E is constant
where E is the amplitude of the inverter output voltage, V is the now). Note that P decreases and Q increases when φ increases.
common bus voltage, φ is the power angle, and Z and θ are the In practical applications, power angle φ is normally
magnitude and the phase of the output impedance, respectively. small; thus, a P/Q decoupling approximation (cos φ ≈ 1 and
996 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 2, APRIL 2007

Fig. 6. Power stage of the single-phase inverter.

Fig. 4. Polar diagram of the P/Q circumference.

Fig. 7. Inverter equivalent circuit.

its effect appears far above the frequency range of concern [25].
The bilinear differential equations that describe the large-signal
dynamic behavior of this converter are presented as follows:

diL
Fig. 5. P/Q circumferences for E and φ variations. L = Vin u − vo − rL iL (8)
dt
sin φ ≈ φ) can be considered in order to simplify the control dvo
design C = ic = iL − io (9)
dt
V where rL is the ESR of the inductance L and u is the control
P ≈ · (E − V ) (6)
R variable, which can take the values 1, 0, or −1, depending on
EV the state of the pair of switches S1–S2 and S3–S4.
Q≈ − · φ. (7) According to the nonlinear control and feedback lineariza-
R
tion theory, the output voltage of this system is of a second-
Consequently, active power P can be controlled by the inverter order relative degree. Thus, from (8) and (9), the open-loop
output-voltage amplitude E, while reactive power Q can be averaged output-voltage dynamics can be derived, i.e.,
regulated by the power angle φ, which is the opposite strategy
to the conventional droop method. d2 vo  dvo  dio 
LC + rL C + vo  + L + rL io  = Vin u
dt dt dt
(10)
III. C ONTROL D ESIGN
where  means the average value over one switching cycle.
The aim of this section is to propose a controller that
In order to linearize the system in a large-signal sense and
can guarantee proper operation of the inverters without using
achieve good tracking of the output voltage, we propose the
control intercommunications. The proposed controller consists
following controller expression:
of three nested loops, namely; 1) the inner output-voltage
regulation loop; 2) the resistive-output-impedance loop; and d
3) the P/Q-sharing outer loop. Vin u = vref + kp (vref − vo ) + kd (vref − vo ) (11)
dt
where vref is the output-voltage reference. Note that the con-
A. Inner Output-Voltage Regulation Loop
troller does not need any integral term to avoid steady-state
Fig. 6 shows the power stage of a single-phase inverter, which error since it can add lag to the output-voltage tracking. Instead,
includes an insulated-gate bipolar transistor (IGBT) bridge it uses a feedforward term of the filter input voltage Vin · u.
configuration and an L–C filter. The equivalent series resistance Besides, the integral term adds an inductive behavior to the
(ESR) of the filter capacitor is not considered in the model since output impedance [13], which is not desirable for our approach.
GUERRERO et al.: CONTROL FOR PARALLEL OPERATION OF DG INVERTER USING RESISTIVE OUTPUT IMPEDANCE 997

Fig. 8. Root-locus diagrams. (a) kd = 1.3 · 10−4 for 0 ≤ kp ≤ 10 and (b) kp = 4.5 for 10−4 ≤ kd ≤ 10−8 .

By equating (10) and (11), the closed-loop output-voltage TABLE I

POWER STAGE AND CONTROLLER PARAMETERS OF THE INVERTER
dynamic behavior takes the form

kd s + (1 + kp )
vo = vref
LCs2 + (rL C + kd )s + (1 + kp )
Ls + rL
− io (12)
LCs + (rL C + kd )s + (1 + kp )
2

where s is the Laplace operator. From the preceding expres-

sion, the inverter can be modeled by a two-terminal Thevenin
equivalent circuit of the form

vo = G(s) · vref − Zo (s) · io (13)

where G(s) is the voltage gain and Zo (s) is the output im-
resistive and inductive terms; thus, the decoupling between P
pedance, as shown in Fig. 7. On the one hand, the voltage
and Q is not guaranteed.
gain is responsible for good output-voltage tracking. Due to
As shown in Fig. 10, apart from its inductive or resistive
the feedforward term, it is able to perfectly follow the output-
nature, the phase of the output impedance is very sensitive
voltage reference. On the other hand, the output impedance at
to parasitic resistance rL . One problem is that this parameter
low frequency can be easily reduced by increasing kp .
is neither easy to measure nor easy to estimate since it is
The output impedance fixes the dynamics of the output-
determined by the ESR of the filter inductor and other parasitic
voltage inverter. From (12), we can deduce that the system
elements, such as the on resistance of the IGBTs and the
has one fixed zero at rL /L and two complex-conjugated poles,
stiffness of the dc link, among others. Consequently, the power-
which can be adjusted by means of kp and kd . After studying
sharing accuracy can be affected due to the fact that the output
the root locus of the closed-loop output impedance, we can
impedance is not fixed.
consider that the poles are dominant since the zero is far from
them. As a consequence, we can obtain the desired dynamical
response by adjusting these poles. Fig. 8 shows the root locus B. Virtual Resistive-Output-Impedance Loop
for different values of kp and kd . Fig. 8(a) depicts that, by The output impedance of the closed-loop inverter affects
increasing kp , the imaginary part of the poles increases, which the power-sharing accuracy and also determines the droop-
results in a less damped system. From Fig. 8(a), we can observe control strategy [13]. In addition, proper design of the output
that, by decreasing kd , the poles are attracted to the imaginary impedance can reduce the impact of the line-impedance unbal-
axis, making the system become faster but more oscillatory. ance. Hence, to enforce the desired output impedance, we can
Using the parameters listed in Table I, a proper transient drop the output-voltage reference proportionally to the output
response can be obtained, and, as illustrated in Fig. 9, the output current, by using the following instantaneous droop function:
impedance at line frequency (50 Hz) is about −30 dB and 60◦ .
In this situation, the output-impedance value has comparable vref = vo∗ − ZV (s) · io (14)
998 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 2, APRIL 2007

Fig. 9. Bode diagram of the voltage gain and the output impedance of the closed-loop inverter.

Fig. 10. Bode diagram of the output impedance as a function of rL parameter (rL = 0.1, 0.2, and 0.3 Ω).

This fast control loop known as virtual output-impedance

loop can be used to fix the output impedance of the inverter
in terms of magnitude and phase. Resistive output impedance
around the output-voltage frequency can be implemented by
drooping the output-voltage reference proportionally to output
current io . Individual output-impedance values for high-order
current harmonics are obtained by subtracting a voltage, which
Fig. 11. Block diagram of the virtual impedance loop concept. is proportional to the current harmonics, from the output-
voltage reference. Thus, the proposed output-voltage reference
can be expressed as
where ZV (s) is the virtual output impedance and the output-
voltage reference at no load is defined as vo∗ . Fig. 11 shows the
virtual impedance loop in relation to the closed-loop system. 
11
The value of ZV (s) should be larger than Zo (s) and the vref = vo∗ − RD io − (Rh − RD )ioh (15)
maximum line impedance expected. h=3,odd
GUERRERO et al.: CONTROL FOR PARALLEL OPERATION OF DG INVERTER USING RESISTIVE OUTPUT IMPEDANCE 999

where m and md are the proportional and derivative coefficients

of reactive power Q, respectively, and n and nd are those of
active power P , respectively. Note that this special kind of
controller does not use integral terms since, in this case, they
will turn the system unstable. In fact, the frequency and am-
plitude are deviated in order to achieve communication-less
P/Q sharing. These deviations are smaller than those in the
conventional droop method since we can adjust the transient
response through the derivative terms without increasing the
maximum E/ω deviations.
Notice that although (4) shows a relationship between φ and
Q, (17) uses frequency ω instead of φ. This is because the
units does not know the initial phase value of the other units.
However, the initial frequency at no load can be easily fixed as
ω ∗ . Besides, considering the negative sign of (4), the signs of
the Q terms in (17) are deliberately positive in order to achieve
negative feedback.
The proposed control scheme allows us to modify the tran-
sient response by acting on the main control parameters and, at
Fig. 12. Bode diagram of the virtual output impedance. the same time, to keep the static droop/boost characteristics. In
addition, it minimizes the transient circulating current among
the modules and further improves the whole system dynamic
performance. Coefficients m and n fix the steady-state control
objectives, while md and nd are selected to guarantee stability
and good transient response.

IV. D YNAMICS OF THE C LOSED -L OOP S YSTEM

Fig. 13. Static droop/boost characteristics for resistive output impedance. A small-signal analysis is proposed in order to investigate
the stability and transient response of the system. Thus, the
where RD is the virtual output impedance and Rh is the resis- closed-loop system dynamics is derived, taking into account
tive coefficient of every harmonic term ioh . Using this loop, the the well-known stiff load-bus approximation [11], [24]. The
output impedance presented to the fundamental and harmonic small-signal dynamics of the active and reactive powers, i.e., p̂
components can be fixed independently. In this way, the output and q̂, respectively, are obtained by linearizing (3) and (4), and
impedance is fixed RD , but some dips (Rh < RD ) are situated modeling the low-pass filters with a first-order description, i.e.,
ωc V  
in harmonic frequencies in order not to increase the output-
voltage total harmonic distortion excessively. Fig. 12 shows p̂ = cos Φ · ê − E sin Φ · φ̂ (18)
s + ωc R D
the Bode diagram of the virtual impedance loop, i.e., vref /io .
ωc V  
q̂ = − sin Φ · ê + E cos Φ · φ̂ (19)
s + ωc R D
C. Outer P/Q-Sharing Loop
where ∧ denotes perturbed values, capital letters mean equi-
As we stated previously, the conventional droop method has librium point values, RD is the output impedance at the fun-
an inherent tradeoff between P/Q-sharing accuracy and fre- damental frequency, and ωc is the cutoff angular frequency of
quency/amplitude output-voltage regulation. From (6) and (7), the low-pass filters, which is fixed over one decade below the
we can observe that, by increasing the output-voltage ampli- line frequency. For the sake of simplicity, the high-frequency
tude, the delivered real power becomes higher, while increasing impedance values are not considered in this analysis since they
the power angle reduces the reactive power. Consequently, the have little effect over the system dynamics.
power-sharing loop should take into account this behavior. Subsequently, by perturbing (16) and (17), and using (18)
Thus, P −V droop and Q−ω boost functions are needed to and (19), we obtain
ωc V  
obtain proper P/Q sharing, as shown in Fig. 13.
Furthermore, in order to improve the dynamics of the par- ê = −(n+nd s) cos Φ·ê−E sin Φ· φ̂ (20)
alleled system, the following droop/boost control scheme is s+ωc RD
m  ω V  
c
proposed: φ̂ = − +md sin Φ·ê+E cos Φ· φ̂ . (21)
s s+ωc RD
dP
E = E ∗ − nP − nd (16) Finally, substituting (21) into (20), we can find the small-
dt signal dynamics of the closed-loop system
∗ dQ
ω = ω + mQ + md (17)
dt s3 + As2 + Bs + C = 0 (22)
1000 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 2, APRIL 2007

TABLE II mented by using a dual digital signal processor (DSP) board.

PARAMETERS OF THE WIRELESS LOAD-SHARING CONTROL
The output-voltage regulation loop was built by using a fixed-
point DSP together with supervisor algorithms and alarms. In
addition, the power sharing and the virtual impedance loops
were implemented using a fast floating-point DSP because of
the high number of filters and calculations. However, another
implementation would be possible by using a faster fixed-point
DSP and sharing a low-cost microcontroller.

A. Output-Voltage Regulation Controller

The inner voltage regulator controller, which is depicted in
Fig. 15, was implemented by using a TMS320LF2407A TX
Instruments 16-bit fixed-point DSP board running at 40 MHz.
The derivative term was implemented by using a small current
transformer, which senses the capacitor current, in order to
avoid the high-frequency noise, which is usually amplified by
this term. The voltage and current sampling were rated at 10
and 20 kHz, respectively.
where

ωc
A= 2RD + nV cos Φ + nd ωc V cos Φ B. Power-Sharing Controller
Xd

 Fig. 16 depicts the block diagram of the proposed controller.
V
+ md V E cos Φ + nd ωc The average active power P can be obtained by means of mul-
RD

 tiplying the output voltage by the load current and filtering the
ωc V product using a low-pass filter. In a similar manner, the average
B= ωc + nωc V cos Φ + mV E cos Φ + nd ωc
Xd RD reactive power is obtained, but, in this case, the output voltage


V must be delayed by 90◦ . In order to adjust the output-voltage
+ md ωc V E cos Φ + n
RD amplitude and frequency, (16) and (17) are implemented, which

 correspond to a couple of proportional–derivative controllers
ωc V
C= mωc V E cos Φ + n applied over signals Q and P . The power-sharing controller was
Xd RD
implemented by using a TMS320C6711 32-bit floating-point
with Xd = RD + nd ωc V cos Φ. DSP. The filters were performed by using infinite-impulse-
Using (22), the stability of the closed-loop system can be response solutions, and the 90◦ delay was obtained by using
evaluated, and the transient response can be adjusted, following a circular buffer.
a linear third-order dynamics. After studying the eigenvalues
behavior of the system (λ1 , λ2 , and λ3 ) through a series of
C. Virtual Impedance Loop
root-locus diagrams, as in [11] and [12], and using the values
listed in Table II, we can conclude that the output impedance The virtual resistive output-impedance loop was also in-
RD has little effect on the location of the roots in comparison cluded in this DSP. The harmonic components of the output
with the md and nd coefficients. Fig. 14 depicts the root-locus current can be extracted by using a bank of bandpass filters,
diagrams for different values of these coefficients. It can be which was implemented through finite-impulse-response filters
observed that the poles can be adjusted to fix the desired dy- as in [26]. The output current is limited by the virtual output
namics. Fig. 14(a) reveals that, by increasing md , we can obtain impedance loop and can be enhanced by programming higher
near first-order dynamics (dominance of pole λ1 ), while, by impedance when the current is near overload.
decreasing this coefficient, the two complex poles (λ2 and λ3 ) Finally, the two DSPs were interconnected by using the host
become dominant, thus obtaining a second-order behavior. port interface, which is characteristic of the TMS320C67xx
From Fig. 14(b), we can observe that an increase in nd attracts family. The fixed-point DSP controller also includes a phase-
the complex-conjugated poles (λ2 and λ3 ) to the real axis, but locked-loop block in order to synchronize the output voltage
pole λ1 is attracted faster, making the system dynamics more of the inverter in frequency and phase with the common bus.
damped. Consequently, we can guarantee the system stability When the output-voltage synchronization is completed, the
and obtain the desired dynamic response by adjusting these two output static switch is turned on, and the droop/boost control
coefficients properly. is initiated.

V. C ONTROLLER I MPLEMENTATION VI. E XPERIMENTAL R ESULTS

In this section, some practical issues about control imple- Two 6-kVA single-phase inverter units were built and
mentation are described. The overall controller was imple- tested, confirming experimentally the validity of the proposed
GUERRERO et al.: CONTROL FOR PARALLEL OPERATION OF DG INVERTER USING RESISTIVE OUTPUT IMPEDANCE 1001

Fig. 14. Root-locus diagrams: (a) nd = 3 · 10−4 for 0 ≤ md ≤ 10−4 and (b) md = 5 · 10−5 for 0 ≤ nd ≤ 10−3 .

Fig. 15. Block diagram of the output voltage regulation controller.

approach. Each inverter consisted of a single-phase IGBT full- response of the paralleled system. In this case, the output cur-
bridge with a switching frequency of 20 kHz and an L–C rents never exceed the nominal output current of the DG unit.
output filter, using the parameters shown in Tables I and II. The Finally, Fig. 20 illustrates the steady-state output currents
impedance of the lines connected between the inverters and the when the units share nonlinear loads. Two situations are
load was intentionally unbalanced to properly test the control evaluated: In the first one, the load is a typical rectifier load
behavior, as shown in the equivalent circuit of Fig. 17. with high crest factor, while, in the second one, this load is
The outstanding features of the parallel system were exper- in parallel with a resistive load. This shows the very good
imentally evaluated when the two-unit system shares a linear output current equalization of the system when sharing linear
load. Fig. 18 depicts the steady-state and the transient response or nonlinear loads, or even in no-load conditions.
of the output currents and the circulating current (i1 − i2 ) when
a sudden load change occurs from no load to full load. As can
VII. C ONCLUSION
be seen, the circulating current remains very small even for
no-load conditions. These results show an excellent dynamic A power-sharing controller without control wire interconnec-
response of the proposed controller for load-step changes. tions for the parallel operation of DG inverters was proposed.
The dynamic performance of the system was tested by In a clear-cut contrast with the conventional droop method, the
connecting unit 2, while unit 1 was supplying the linear load output impedance of the inverters is enforced to be resistive,
constantly. As shown in Fig. 19, the derivative terms of the giving the following advantages. 1) The system becomes more
proposed P/Q-sharing loop allow us to improve the transient damped. 2) Automatic harmonic sharing is obtained. 3) Phase
1002 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 2, APRIL 2007

Fig. 16. Block diagram of the power-sharing controller.

Fig. 17. Equivalent circuit of two units supplying a common load.

Fig. 18. (a) Steady-state and (b) transient response of (top and bottom) the output currents and (middle) the circulating current (Y -axis: 10 A/div, X-axis:
10 ms/div).

errors barely affect P sharing. Consequently, novel droop- control loop; 2) a resistive virtual output-impedance loop; and
control functions are devised, which are also able to improve 3) an inner output-voltage regulation loop.
the dynamic response of the paralleled system. The controller Experimental results have been presented to validate the
consists of three nested loops, namely: 1) a P/Q-sharing proposed control approach, showing good power sharing when
GUERRERO et al.: CONTROL FOR PARALLEL OPERATION OF DG INVERTER USING RESISTIVE OUTPUT IMPEDANCE 1003

Fig. 19. Transient response of the circulating current (middle) and output currents (top and bottom) when connecting unit 2 while unit 1 supplies the load
constantly (Y -axis: 10 A/div, X-axis: 200 ms/div). (a) md = nd = 0. (b) md = 0.00005 and nd = 0.00003.

Fig. 20. Steady-state output currents when sharing (a) nonlinear load (Y -axis: 2 A/div, X-axis: 5 ms/div) and (b) resistive and nonlinear load (Y -axis: 10 A/div,
X-axis: 5 ms/div).

supplying linear and nonlinear loads, even when the line [7] I.-Y. Chung, S.-W. Park, H.-J. Kim, S.-I. Moon, B.-M. Han, J.-E. Kim,
impedances are unbalanced. The excellent performances of and J.-H. Cho, “Operating strategy and control scheme of premium power
supply interconnected with electric power systems,” IEEE Trans. Power
this wireless controller highlight its applicability to parallel- Del., vol. 20, no. 3, pp. 2281–2288, Jul. 2005.
connected inverters in distributed power systems, such as low- [8] A. Tuladhar, H. Jin, T. Unger, and K. Mauch, “Parallel operation of single
voltage DG systems or microgrids. phase inverter modules with no control interconnections,” in Proc. IEEE
APEC, 1997, pp. 94–100.
[9] ——, “Control of parallel inverters in distributed ac power systems with
consideration of line impedance,” IEEE Trans. Ind. Appl., vol. 36, no. 1,
R EFERENCES pp. 131–138, Jan./Feb. 2000.
[1] R. H. Lasseter et al., “White paper on integration of distributed energy [10] U. Borup, F. Blaabjerg, and P. N. Enjeti, “Sharing of nonlinear load
resources. The CERTS microgrid concept,” in Proc. Consortium Elect. in parallel-connected three-phase converters,” IEEE Trans. Ind. Appl.,
Reliab. Technol. Solutions, 2002, pp. 1–27. vol. 37, no. 6, pp. 1817–1823, Nov./Dec. 2001.
[2] P. L. Villeneuve, “Concerns generated by islanding,” IEEE Power Energy [11] E. A. A. Coelho, P. Cabaleiro, and P. F. Donoso, “Small signal stability
Mag., vol. 2, no. 3, pp. 49–53, May/Jun. 2004. for single phase inverter connected to stiff ac system,” in Proc. IEEE IAS
[3] T. Kawabata and S. Higashino, “Parallel operation of voltage source Annu. Meeting, 1999, pp. 2180–2187.
inverters,” IEEE Trans. Ind. Appl., vol. 24, no. 2, pp. 281–287, [12] J. M. Guerrero, L. García de Vicuña, J. Matas, M. Castilla, and J. Miret, “A
Mar./Apr. 1988. wireless controller to enhance dynamic performance of parallel inverters
[4] M. C. Chandorkar and D. M. Divan, “Control of parallel connected in- in distributed generation systems,” IEEE Trans. Power Electron., vol. 19,
verters in standalone ac supply system,” IEEE Trans. Ind. Appl., vol. 29, no. 5, pp. 1205–1213, Sep. 2004.
no. 1, pp. 136–143, Jan./Feb. 1993. [13] ——, “Output impedance design of parallel-connected UPS inverters with
[5] C.-C. Hua, K.-A. Liao, and J.-R. Lin, “Parallel operation of inverters wireless load-sharing control,” IEEE Trans. Ind. Electron., vol. 52, no. 4,
for distributed photovoltaic power supply system,” in Proc. IEEE PESC, pp. 1126–1135, Aug. 2005.
2002, pp. 1979–1983. [14] J. M. Guerrero, J. Matas, L. García de Vicuña, M. Castilla, and
[6] S. Barsali, M. Ceraolo, P. Pelachi, and D. Poli, “Control techniques of J. Miret, “Wireless-control strategy for parallel operation of distributed
dispersed generators to improve the continuity of electricity supply,” in generation inverters,” IEEE Trans. Ind. Elecron., vol. 53, no. 5, pp. 1461–
Proc. IEEE PES Winter Meeting, 2002, vol. 2, pp. 789–794. 1470, Oct. 2006.
1004 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 2, APRIL 2007

[15] C. Jamerson, T. Long, and C. Mullet, “Seven ways to parallel a magamp,” José Matas received the B.S., M.S., and Ph.D.
in Proc. IEEE APEC, 1993, pp. 469–474. degrees in telecommunications engineering from
[16] B. K. Johnson, R. H. Lasseter, F. L. Alvarado, and R. Adapa, “Expandable the Universitat Politècnica de Catalunya, Barcelona,
multiterminal dc systems based on voltage droop,” IEEE Trans. Power Spain, in 1988, 1996, and 2003, respectively.
Delivery, vol. 8, no. 4, pp. 1926–1932, Oct. 1993. Since 1997, he has been an Associate Profes-
[17] I. Batarseh, K. Siri, and H. Lee, “Investigation of the output droop char- sor in the Departament d’Enginyeria de Electrònica,
acteristics of parallel-connected dc-dc converters,” in Proc. IEEE PESC, Universitat Politècnica de Catalunya. His research
1994, pp. 1342–1351. interests include power-factor-correction circuits,
[18] J. S. Glaser and A. F. Witulski, “Output plane analysis of load-sharing in distributed power systems, and nonlinear control.
multiple converter systems,” IEEE Trans. Power Electron., vol. 9, no. 1,
pp. 43–50, Jan. 1994.
[19] J. Perkinson, “Current sharing of redundant dc–dc converters in high
availability systems—A simple approach,” in Proc. IEEE APEC, 1995,
pp. 952–956.
[20] S. Luo, Z. Ye, R.-L. Lin, and F. C. Lee, “A classification and evaluation
of paralleling methods for power supply modules,” in Proc. IEEE PESC, Luis García de Vicuña received the M.S. and Ph.D.
1999, pp. 901–908. degrees in telecommunications engineering from
[21] J.-W. Kim, H.-S. Choi, and B. H. Cho, “A novel droop method for con- the Universitat Politècnica de Catalunya, Barcelona,
verter parallel operation,” IEEE Trans. Power Electron., vol. 17, no. 1, Spain, in 1980 and 1990, respectively, and the Dr.Sci.
pp. 25–32, Jan. 2002. degree from the Université Paul Sabatier, Toulouse,
[22] K. Wallace and G. Mantov, “Wireless load sharing of single phase France, in 1992.
telecom inverters,” in Proc. IEEE INTELEC, Copenhagen, Denmark, From 1980 to 1982, he was an Engineer with
1999, pp. 1–7. CD-Record. Control Applications. He is currently an Associate
[23] S. J. Chiang, C. Y. Yen, and K. T. Chang, “A multimodule parallelable Professor in the Departament d’Enginyeria de Elec-
series-connected PWM voltage regulator,” IEEE Trans. Ind. Electron., trònica, Universitat Politècnica de Catalunya, where
vol. 48, no. 3, pp. 506–516, Jun. 2001. he teaches power electronics. His research interests
[24] A. R. Bergen, Power Systems Analysis. Englewood Cliffs, NJ: Prentice- include power electronics modeling, simulation and control, active power
Hall, 1986. filtering, and high-power-factor ac–dc conversion.
[25] M. J. Ryan, W. E. Brumsickle, and R. D. Lorenz, “Control topology
options for single-phase UPS inverters,” IEEE Trans. Ind. Appl., vol. 33,
no. 2, pp. 493–501, Mar./Apr. 1997.
[26] P. Mattavelli and F. Marafao, “Repetitive-based control for selective har-
monic compensation in active power filters,” IEEE Trans. Ind. Electron., Miguel Castilla received the M.S. and Ph.D. degrees
vol. 51, no. 5, pp. 1018–1024, Oct. 2004. in telecommunications engineering from the Univer-
sitat Politècnica de Catalunya, Barcelona, Spain, in
1995 and 1998, respectively.
Josep M. Guerrero (S’01–M’03) received the Since 2002, he has been an Associate Professor in
B.S. degree in telecommunications engineering, the the Departament d’Enginyeria de Electrònica, Uni-
M.S. degree in electronics engineering, and the Ph.D. versitat Politècnica de Catalunya, where he teaches
degree in power electronics from the Universitat analog circuits and power electronics. His research
Politècnica de Catalunya, Barcelona, Spain, in 1997, interests include modeling, simulation, and control
2000, and 2003, respectively. of dc-to-dc power converters and high-power-factor
From 1998 to 2004, he was an Assistant Professor rectifiers.
at the Department of Automatic Control Systems
and Computer Engineering, Universitat Politècnica
de Catalunya. In 2004, he became a Senior Lecturer
at the same university, where he teaches digital signal
processing, control theory, and microprocessors. Since 2004, he has been with Jaume Miret (M’98) received the B.S. degree in
the Sustainable Distributed Generation and Renewable Energy Research Group, telecommunications from the Universitat Politècnica
Escola Universitaria d’Enginyeria Técnica Industrial de Barcelona (EUETIB), de Catalunya, Barcelona, Spain, in 1992, the M.S.
Barcelona. His research interests include DSP-/FPGA-based control, unin- degree in electronics engineering from the Univer-
terruptible power systems, inverters for photovoltaic applications, and wind sitat de Barcelona, Barcelona, in 1999, and the
energy conversion in microgrids. Ph.D. degree from the Universitat Politècnica de
Dr. Guerrero is an Associate Editor of the IEEE TRANSACTIONS ON Catalunya, in 2005.
INDUSTRIAL ELECTRONICS. He is a Guest Editor of the Special Issue of From 1993 to 2005, he was an Assistant Profes-
the IEEE TRANSACTIONS ON POWER ELECTRONICS “Power Electronics sor in the Departament d’Enginyeria de Electrònica,
for Wind Energy Conversion” and the Special Section of the IEEE Universitat Politècnica de Catalunya. In 2006, he be-
TRANSACTIONS ON INDUSTRIAL ELECTRONICS “Uniniterruptible Power came a Senior Lecturer at the same university, where
Supply (UPS) Systems.” He is involved on several IEEE IES Committees, and he teaches digital systems and FPGA programming. His research interests
he usually chairs and organizes sessions in IES and PELS conferences. include dc–ac converters, active power filters, and digital control.