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Advanced Digital Electronics Laboratory Exp.6

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42 views2 pages

Advanced Digital Electronics Laboratory Exp.6

Uploaded by

Mohamd barca
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Advanced Digital Electronics Laboratory Exp.

6
Experiment 6
Operators and Attributes: Design Example Parity Generator
Learning Objectives
1. Operators and attributes VHDL will introduced in this experiment, with special emphasis on
those that are synthesizable.
2. Design A VHDL code for a generic parity generator using Xilinx® ISE 9.2i, Simulation results
should be obtained.
3. Develop a User Constraint File “UCF” that maps the input and output signals to Spartan 3E
FPGA. Then test the results.
Equipment and Materials:
1- Full version of Xilinx ISE 9.2i software installed on your laboratory personal computer.
2- Xilinx Spartan-3E Starter Kit, including download cable and power supply cable.
Introduction:
Operators and attributes constitute a relatively long list of general VHDL constructs, which
are often examined only sparsely. We have collected them together in this lab in order to
provide a complete and more consistent view.
A summary of VHDL operators and attributes is presented in tables below.
1- Operators table
Operator type Operators Data types
Assignment <= , := , => Any
Logical NOT, AND, NAND, OR, BIT, BIT_VECTOR, STD_LOGIC,STD_LOGIC_VECTOR,
NOR, XOR, XNOR STD_ULOGIC, STD_ULOGIC_VECTOR
Arithmetic +, -, *, /, ** INTEGER, SIGNED, UNSIGNED
(mod, rem, abs)
Comparison =, /=, <, >, <=, >= All above
Shift sll, srl, sla, sra, rol, ror BIT_VECTOR
Concatenation &, ( , , , ) Same as for logical operators, plus SIGNED and
UNSIGNED
2- Attributes table
Application Attributes Return value
For regular DATA d’LOW Lower array index
d’HIGH Upper array index
d’LEFT Leftmost array index
d’RIGHT Rightmost array index
d’LENGTH Vector size
d’RANGE Vector range
d’REVERSE_RANGE Reverse vector range
For enumerated d’VAL(pos) Value in the position specified
DATA d’POS(value) Position of the value specified
d’LEFTOF(value) Value in the position to the left of the value specified
d’VAL(row, column) Value in the position specified
For a SIGNAL s’EVENT True when an event occurs on s
s’STABLE True if no event has occurred on s
s’ACTIVE True if s is high
1
Advanced Digital Electronics Laboratory Exp.6
Procedures:
1. Write a VHDL code to design a Generic Parity Generator shown in figure below:

2. Implement the designed Generic Parity Generator using Xilinx ISE 9.2i tools for Spartan 3E
FPGA board. Follow the same steps in previous in Experiments to synthesize and obtain a
timing diagram after simulation to verify correct outputs.
3. Develop a User Constraint File “UCF” file.
4. Test it by sliding the programmed switches up and down for ON and OFF.
5. Record your results (VHDL code, RTL, Timing diagram, "UCF" file).
Report :
1- List all operators, attributes and generics employed on your design.
2- Design an arithmetic logic unit shown in figure using operators.

3- Highlights all operators, attributes and generics employed on your design of Q2.

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