2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

Optimization of row decoder for 128x128 6T SRAMs

Vipul Bhatnagar Chandani Artri Sujata Pandey

Amity School of Engineering and Technology Department of Electronics and Department of Electronics and
Amity University Uttar Pradesh, Noida Communication Engineering Communication Engineering
Amity School of Engineering and Technology Amity School of Engineering and Technology
Amity University Uttar Pradesh, Noida Amity University Uttar Pradesh, Noida
Email: [email protected]

Abstract: Most of the power dissipation in SRAMs is due

The address input given at the circuitry, which identifies
to the leakage and it is approximately 40% of total
the cell that is to be accessed, the address bit is split
power dissipation. The leakage power increases as we
into row address bits and colunm address bits. The row
move towards the technology scaling unless effectively
In this paper we report on the optimized design of a 7 to
optimized circuit is introduced to keep the leakage under
128 line row decoder for a 128x 128 6T-SRAM array. The
control. In this paper we report on the optimization of a
row decoder is designed using three pre-decoders and a
row decoder in terms of power and area. The row
second level circuitry. The pre decoders are designed using
decoder is designed using three pre-decoders and a
AND gates and simulated using 180nm CMOS technology
second level circuitry. Comparison of the proposed row
using Cadence Tool. Comparison of the proposed row
decoder is done with the existing architecture using two
decoder is done with the existing architecture using two pre
pre decoders in terms of power consumption. About
decoders in terms of power consumption. About 25%
25% reduction in power dissipation is obtained in the
reduction in power dissipation is obtained in the proposed
proposed architecture.
architecture.

Keywords:6T SRAM, row decoder optimization

Section II discusses about the circuit design, section III
About optimization of row decoder, section IV gives the
I. INTRODUCTION
results and their discussions and section V conclusions.
Fast and low power SRAMs is a critical component of many
VLSI chips [1-3]. SRAM is widely used as on chip cache.
II. CIRCUIT DESIGN
With the use of multi core processors and ever increasing
clock speeds the speed if processor has increased to a
The basic SRAM structure shown in Figure 1 can be
great extent but the memory access time has not reduced
optimized to minimize the delay and power at the cost of
substantially. With technology scaling the circuit designers
some area and the optimization initiates with the schematic
are able to reduce the power supply voltage. Moreover sub
design and layout of the cell.
threshold leakage is becoming dominant with decrease in
both supply voltage and threshold voltage. Also with the
For design and optimization, t he access path of SRAM is
continuous scaling in technology and reduction in size of
split into two parts they are the decoder and the data path.
transistors has increased parasitic capacitance. The main
The decoder encompasses the circuits from the address
interest lie on the development of low power techniques
input to the word line. The data path encompasses the
for SRAM based on chip cache structures used in
circuit from the cell to the input/output ports.
processors [4-5].

In this work, AND gate are considered for the decoder

Some of the low power techniques used in SRAMs like use
design during the designing of decoder we will have t?
of level shifters before flip flops [6] , placing level shifters
take the large inverter for the entire decoder so that It
at various stages along the decoder for ultra low voltage
would drive large capacitance of word line. The delay in
operation [7], Wilson current mirror based design [8] have
the decoder consists of the delay in the gates in the critical
been reported. At architecture ieveI, address
path. The gate delay of the decoder can be minimized
decoder plays an important role since access time and
by the usage of pulsed signal which is used in the
power consumption is determined by its design. B?th
pulsed circuit. The sizing of the gates of decoder will
dynamic and static decoder architectures has been studIed
always allows the tradeoff in between power and delay
in detail [9-10] where hierarchical tree with pre decoding
and binary tree decoder with multiplexers are reported.
If in any access, there is a difference between new address
and previous address, then in that case the word line which
The design of SRAM is generally divided into two parts, the
is old is not taken and the word line with new address is
decoder, and the sense and colmnn circuits. A synchronous
taken. Thus the total delay will be maximum when the old
SRAM architecture is shown in Fig 1. It consist of a row
word line is de-asserted and the delay when to assert the
decoder, a storage array, a colunm decoder, and a sense
new word line, and this delay can be reduced when each
amplifier(SA) and write-control unit. Every memory cell of
gate have equal rise and fall time.
an SRAM contains a pair of inverters that form a bi-stable
element. These inverters are connected to the bit lines
In our work Vcp from control circuitry is passed through
which are through access transistors and they provide the
transmission gates to activate a given word line.
read and write operation. An SRAM contains column and
row Circuitry which are used to access these SRAM cell.
decoder turn on one of the respective word lines which
connect the memory cell of that row to their particular bit
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 2015 International Conference on VLSI Systems, Architecture, Technolo� and Ap);1lications NLSI-SATA b
III. UPTIMIZATION OF ROW DECO ER

Basically decoder is used to access memory in systems.

Whenever there is a need to use some application, input in
binary form is given at the input of the decoder (address).
According to that address a particular cell from the memory
array is accessed. In decoders based on the conventional
gates one of the outputs is asserted based on the input
address. For the next address input the previous output first
OlP has to be disabled and the new one is enabled. This
Data operation reduces the speed because of increased delay.
Control

With each gate having equal delays (rise time and fall time)
can minimize the total delay of the circuit. And this leads to
CQl1lroi the optimization in the circuit. The gate delays in the critical
Ws Control path shown in Figure 3 and delays in the interconnection
. nl�
S bi� dolO bu s between pre-decoder and word line wires form the decoder
delay.

Fig 1: Block diagram of 128xl28 SRAM cell

The generation of a signal is by making together the

outputs of the pre decoder which in turn used to handle the
transmission gates. ADDRESS
INPUT
The row decoder is designed two 2 to 4 and one 3 0

8 decoder at pre-decoder stage as shown in Figure 2. As

now the fan in has increased the speed of the decoder will GLOBAL WORO ORMR
decrease. Hence the decoder design is divided into two
levels.
Figure 3: Critical path of a row decoder

Now we know that the RC delay grows as the square of the

wire length, so the delay due to the word line becomes more
significant in SRAMs. And to improve this, the delay has to
be minimized which can be done by the sizing of the gates
in the decoder. Sizing of gates impacts power also. So there
is a trade-off between the two.

Older designs of decoder used the logic function in a simple

combinational style using static CMOS circuit style. But in
new designs instead of conventional style pulse decoder is
used. In pulsed decoder the output stays active for a
minimum time and then shuts off. In the post-decoder stage
the gate used are conventional but inputs are given in the
form of pulses of short duration and at input of transmission
gate in second level circuitry pulse waveform is given
instead of dc input so that the word line is high only for the
Fig 2: Decoder using two 2 to 4 decoders and one 3 time whenever there is a 0 comes out of the NAND gate for
to 8 decoder the corresponding word line. Only for a particular
combination the output of a word line stays high and rest of
The first level is the pre-decoder stage which is comprised the word lines are deactivated for that time period. The
of two 2 to 4 decoders and one 3 to 8 decoder. Pre­ output of the word line is in high state for its particular
decoding causes common gates to be divided into smaller combination made from the outputs of the pre-decoder
ones saving area and reducing delay. A pre-decoder was stage. With pulsed circuit technique the delay is reduced and
used in the design to reduce the fan in. the speed of the decoder is increased.

The next level is post-decoder where all the outputs from IV: RESULT AND DISCUSSIONS
pre-decoder are combined to form a total of 128 word lines.
The main reason behind the partition of decoder into two 180nm technology has been used to design the decoder
stages is to reduce the logical effort of the complete path designed using AND gates. For schematic entry cadence
as shown in Fig 2. Out of 10 address lines 7 are fed into composer is used, for simulation Cadence Spectre is used.
the pre-decoder. Address lines AO-Al, A2-A3 and A4-A7
forms a total of 7 inputs for the row decoder using two
2 to 4 decoders and one 3 to 8 decoder. Then the 16
outputs of pre- decoder stage are used to drive the word
lines.
 2015 International Conference on VLSI Systems, Architecture Technologv and Applications VLSI-SATA)

Figure 4 shows the pre decoder and post decoder circuitry.

� ""I"
the post decoder which is driven by the outputs of pre­
..."..
decoder stage. Post decoder forms the word lines. Here in
the figure below one AND gate and one NAND gate is used � _I

whose output becomes the input of the inverter and the '"'"
PMOS gate of transmission gate .The output of inverter """f

drives the NMOS of transmission gate. A clock signal is

...".,
given at the input of transmission gate which is passed
�
to the output when the TG is in ON state. Each and every
time one of the output lines of the decoders is high and !>OI+�
---1
two lines are given as the input to the AND whose

i
""'"
output and the third line from the decoder outputs is •
fed into the NAND gate which in turn turns on the TG
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and accordingly the word line is raised high. Likewise -- -=:P-�
every time a combination is made with the outputs of -{
decoders and a word line is raised high in correspondence
to the combination.
Figure 6: Full decoder 7 to 128 word lines

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Figure 4: The pre decoder and post decoder circuitry

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Figure 7: Partial waveforms

.... � � � � :. � � � � � � � � +;t �t� : � � ; � In first architecture to make 7 inputs two 2 to 4 decoder and
one 3 to 8 decoder are used which is called pre-decoder
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stage as discussed in preceding sections.

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The outputs of the pre-decoder stage make a total of 128
combinations. In second architecture one 3 to 8 decoder and
one 4 to 16 decoder is design to form the pre-decoder stage
and further for the outputs are combined to form 128
outputs for next stage i.e. the post- decoder stage. Power
for both is architectures is calculated and compared. Table
1 gives the comparison between the two architectures.

Figure 5: Designed architecture of row decoder for 8 At I V Row Decoder Optimized Row
word lines (one 4 to 16 and Decoder
one 3 to 8 (two 2 to 4 and
Figure 5 shows the schematic of present row decoder decoder) one 3 to 8
in which pre-decoder stage is comprised of two 2 to 4 and decoder)
one 3 to 8 decoder, for 8 word lines. For the comparison Static Power 0.34uW 0.15uW
purpose two different architectures have been designed dissipation
and each design is further divided into levels in order to Dynamic Power 20.16uW 15.75uW
make such a large circuit. Dissipation
Total Power 20.5uW 15.9uW
Fig 6 shows the 7 to 128 row designed decoder Right Dissipation
side shows the zoom of the few word lines and the Table I: Power comparison of both the decoder architectures
waveforms generated are shown in Figure 7 partially.
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

V. CONCLUSION June 2013.

[10]. M. Turi and J. Frias, "High-performance low- power
In this paper the access path of SRAM is split into selective precharge schemes for address decoder,"
two portions: the row decoder and the data path. The IEEE Trans. On Circuits & Systems, vol. 55, no. 9, pp.
Techniques of optimization of the row decoder were 917--621, Sept. 200S.
discussed. The key to high speed in the SRAM data
path is by reducing the swings in the signals and the
swings that are present in the nodes like bit lines and
data lines. By limiting the pulse width of a word line
that is done by controlling pulse width of select lines by
this we can obtain the low voltage swings in the bit
lines. The row decoder designed with 4 to 16 and 3 to S
pre decoders at IV showed total power dissipation is
20.5uW and the optimized design of row decoder with
two 2 to 4 and one 3 to S pre-decoder showed a power
dissipation of 15uW. So, a 25% reduction in power
dissipation is obtained in the optimized design of row
decoder. This work can be extended by implementing it
using NAND, NOR and other gating techniques etc. in
order improve performance

Acknowledgement

The authors would like to thank Mr. Nitin Sehgal from

Silicon Mentor for providing valuable inputs to carry
out this work.

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