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Power Saving Schemes of The ARM CORETX M3

The document discusses the power saving schemes of the ARM Cortex-M3 processor. It describes the fundamental low power modes of run, sleep, and deep sleep. Deeper sleep modes reduce power consumption but increase the time to power back on. The Cortex-M3 architecture enables low power through features like sleep modes, low gate count design, high code density, and a wakeup interrupt controller. The Cortex-M3 has two sleep modes, sleep and deep sleep, entered via WFI/WFE instructions. It also has a sleep-on-exit feature to immediately return to sleep after interrupt handling.

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45 views

Power Saving Schemes of The ARM CORETX M3

The document discusses the power saving schemes of the ARM Cortex-M3 processor. It describes the fundamental low power modes of run, sleep, and deep sleep. Deeper sleep modes reduce power consumption but increase the time to power back on. The Cortex-M3 architecture enables low power through features like sleep modes, low gate count design, high code density, and a wakeup interrupt controller. The Cortex-M3 has two sleep modes, sleep and deep sleep, entered via WFI/WFE instructions. It also has a sleep-on-exit feature to immediately return to sleep after interrupt handling.

Uploaded by

kumarkl
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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18BCB0072 and 18BCB0081

Power Saving Schemes of the ARM CORETX M3

Team: JATIN KUMAR (18BCB0072)


and PRATEEK SINHA (18BCB0081)

The fundamental low energy modes:


Every microcontroller that is based on the Arm Cortex-M processor will have at least three power modes;
Run, Sleep and Deep Sleep. Obviously, the run mode is where the processor is fully powered up and
doing everything that the embedded system was designed to do. Sleep mode will halt the CPU clock but
will leave the system clock, flash and peripheral clocks operational. Deep sleep mode will not just halt the
CPU clock but also turn off the system clock, flash and the PLL.
The microcontroller vendor has the ability to fully customize their low power modules to offer varying
degrees of low power. For example, the NXP Kinetis-L processors don’t just have the standard Cortex-M
low power modes but also modes such as Low-Leakage sleep mode and Very Low Leakage Sleep mode
which draw just micro or nanoamps of current.
It’s important to note that the deeper into sleep the microcontroller goes, the closer it is to being fully
turned off. This is important to realize because as you use deeper and deeper sleep modes, the time
required to power the microcontroller back up and start executing instructions can increase dramatically.
Some processors that offer very deep power modes require the same amount of time as the processor boot
sequence to become operational again. Depending on your application, this could have significant effects
on the real-time performance of the system.
Following are the architectural features which makes Cortex-M3 architecture a low power device:

 It has sleep mode and deep sleep mode supports, which can work with various system-design
methodologies to reduce power consumption during idle period.
 Its low gate count and design techniques reduce circuit activities in the processor to allow
active power to be reduced.
 Since Cortex-M3 has high code density, it has lowered the program size requirement. At the
same time, it allows processing tasks to be completed in a short time, so that the processor can
return to sleep modes as soon as possible to cut down energy use.
 Starting from Cortex-M3 revision 2, a new feature called Wakeup Interrupt Controller (WIC)
is available. This feature allows the whole processor core to be powered down, while processor
states are retained and the processor can be returned to active state almost immediately when an
interrupt takes place.

The following below explains the various modes available in Cortex M3 for power management.
Sleep Modes:
During sleep mode, the system clock can be stopped, but the free-running clock input could still be
running to allow the processor to be woken by an interrupt.
18BCB0072 and 18BCB0081

The two sleep modes are as follows:


a. Sleep: Indicated by the SLEEPING signal from the Cortex-M3 processor
b. Deep sleep: Indicated by the SLEEPDEEP signal from the Cortex-M3 processor
The sleep modes are invoked by Wait-For-Interrupt (WFI) or Wait-For-Event (WFE) instructions.
The events for invoking the sleep modes can be interrupts, a previously triggered interrupt, or an external
event signal pulse via the Receive Event (RXEV) signal.
To decide which sleep mode is to be invoked in case of an event can be set by setting the SLEEPDEEP
bit field of the Nested Vectored Interrupt Controller (NVIC) control register
The sleep mode operation of the processor depends on chip design. In some cases the clock signals can be
stopped to reduce power consumption. The chip can also be designed to shut down part of the chip to
further reduce power, or it is also possible that a design can shut down the chip completely. In a case
where the chip is shut down completely, the only way to wake the system from sleep is via a system reset.

Sleep-On-Exit Feature:
Processor can be programmed to go back to sleep automatically after the interrupt routine exit. In this
way, we can make the core sleep all the time unless an interrupt needs to be servedTo use this feature, we
need to set the SLEEPONEXIT bit in the System Control register.
If the Sleep-On-Exit feature is enabled, the processor can enter sleep at any exception return to thread
level, even if no WFE/WFI instruction is executed.
Wake-up Interrupt Controller:
A new unit called the Wakeup Interrupt Controller (WIC) is available as an optional component. This
controller is coupled to the existing NVIC and is used to generate a wakeup request when an interrupt
arrives.
By using the technology called State Retention Power Gating (SRPG) and WIC together, most portions of
the Cortex-M3 processor can be powered down during deep sleep, leaving a small amount of logic for
state retention.
During this power down state, the WIC remains operational and generates a wakeup request to power up
and restore the system state when an interrupt arrives. Maximum interrupt latency in such case is around
20-30 clock cycles.

Additional low power capabilities:


In addition to being able to enter into a low power mode, there is also another interesting low power mode
feature called Sleep-On-Exit. Sleep-On-Exit allows the processor to immediately go back to sleep once
the interrupt that was executing completes. This allows a developer to save time, and time is energy in
this case, by avoiding unnecessary context switching between the main application and the interrupt. The
processor is allowed to wake-up in the interrupt, do the necessary work and then return to sleep.
18BCB0072 and 18BCB0081

Conclusions:
The low power modes on the Cortex-M processors are one of the major keys to decreasing how much
energy consumption an embedded system uses. As we have seen, developers can use the WFI instruction
to place their system into their low power mode and the system will then wake-up once the previously
configured wake-up event or interrupt has been triggered. Each microcontroller vendor is able to
customize their power modes and we will see microcontrollers with as few as the three default power
modes all the way through parts with a dozen power modes and complex state machines that facilitate
how the processor moves from one mode to the next.

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