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Example Usage: Mov R2, R0 (R2 R0)

This document describes an assignment to implement a 4-stage pipelined processor in Verilog. The processor supports 3 instructions - mov, sll, and j. It has a register file with 8 registers initialized on reset. Students are asked to design the instruction fetch, register file, forwarding, and overall processor modules in Verilog. They also need to test the design using a testbench and verify the register file updating. Questions are included about the processor datapath, control signals, and any problems faced during implementation.

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Divyam Shreevatsal
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34 views

Example Usage: Mov R2, R0 (R2 R0)

This document describes an assignment to implement a 4-stage pipelined processor in Verilog. The processor supports 3 instructions - mov, sll, and j. It has a register file with 8 registers initialized on reset. Students are asked to design the instruction fetch, register file, forwarding, and overall processor modules in Verilog. They also need to test the design using a testbench and verify the register file updating. Questions are included about the processor datapath, control signals, and any problems faced during implementation.

Uploaded by

Divyam Shreevatsal
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Birla Institute of Technology and Science – Pilani, Hyderabad Campus

Second Semester 2019-20


CS F342: Computer Architecture Assignment (20 Marks)
1. (a) Implement 4-stage pipelined processor in Verilog. This processor supports data transfer (mov), shift
left logical (sll) and Unconditional Jump (J) instructions only. The processor should implement
forwarding to resolve data hazards. The processor has Reset, CLK as inputs and no outputs. The processor
has instruction fetch unit, register file (with 8 8-bit registers), Execution and Writeback unit. Read and
write operations on Register file can happen simultaneously and should be independent of CLK. The
processor also contains three pipelined registers IF/ID, ID/EX and EX/WB. When reset is activated the
PC, IF/ID, ID/EX, EX/WB registers are initialized to 0, the instruction memory and registerfile get loaded
by predefined values. When the instruction unit starts fetching the first instruction the pipeline registers
contain unknown values. When the second instruction is being fetched in IF unit, the IF/ID registers will
hold the instruction code for first instruction. When the third instruction is being fetched by IF unit, the
IF/ID register contains the instruction code of second instruction, ID/EX register contains information
related to first instruction and so on. (Assume 8-bit PC. Also Assume Address and Data size as 8-bits)
The instruction and its 8-bit instruction format are shown below:
mov DestinationReg, SourceReg (Moves data in register specified by register number in Rsrc field to a
register specified by register number in RDst field. Opcode for mov is 00)

Example usage: mov R2, R0 (R2R0)

sll DestinationReg, shiftamount (Left shifts data in register specified by register number in RDst field
by shift amount and moves back result to same register. Opcode for sll is 01)

Example usage: sll R0, 4 shifts value in R0 by 4


times and store result back in R0.

j L1 (Jumps to an address generated by appending 2 MSB bits of PC+1 to the data specified in instruction
field (5:0). Opcode for j is 11)
Example usage: j L1 (Jump address is calculated using
Pseudo direct addressing)

Assume the register file contains 8 registers (R0-R7) each register can hold 8-bit data. On reset register
file should get initialized such that R0 = 0, R1 = 1, R2 = 2, R3 = 3 …etc. On reset assume that the
instruction memory gets initialized with four instructions.
mov Rx, Ry
sll Rx, 1
mov Ry, Rx
j L1
sll Ry, 3
L1: mov Rz, Ry
Where x, y, z are related to last 3 digits of your ID No.
If ID number: 20XXXXXXABCH, then x =A mod 8 (A%8),
y= (B+2) mod 8 ((B+2)%8),
z= (C+3) mod 8 ((C+3)%8),
A partial block level representation of 4-stage pipelined processor is shown below. Please note that for
registerfile implementation, both read and write are independent of CLK. Write operation depends
on control signal.

As part of the assignment three files should be submitted in zipped folder.

1. PDF version of this Document with all the Questions below answered with file name as
IDNO_NAME.pdf.

2. Design Verilog Files for all the Sub-modules (instruction fetch, Register file, forwarding unit).

3. Design Verilog file for the main processor.

The name of the zipped folder should be in the format IDNO_NAME.zip

The due date for submission is 25-April-2020, 5:00 PM.

_____________________________________________________________________________________

Name: ID No:

Questions Related to Assignment

1. Draw the complete Datapath and show control signals of the 4-stage pipelined processor. A
sample Datapath for 5-stage pipelined MIPS processor has been discussed in class. A ppt named
Assignmenthelp.ppt contains this 5-stage processor and is uploaded in CMS. You can modify
this according to your specification.
Answer:

2. List the control signals used and also the values of control signals for different instructions.
Answer:

Instructions Control Signals

mov
sll
j

3. Implement the Instruction Fetch block. Copy the image of Verilog code of the Instruction fetch
block here

Answer:
4. Implement the Register File and copy the image of Verilog code of Register file unit here.

Answer:

5. Determine the condition that can be used to detect data hazard?

Answer:

6. Implement the forwarding unit and copy the image of Verilog code of forwarding unit here.

Answer:

7. Implement complete processor in Verilog (using all the Datapath blocks). Copy the image of
Verilog code of the processor here. (Use comments to describe your Verilog implementation)

Answer:

8. Test the processor design by generating the appropriate clock and reset. Copy the image of your
testbench code here.

Answer:

9. Verify if the register file is getting updated according to the set of instructions (mentioned
earlier).

Copy verified Register file waveform here (show only the Registers that get updated, CLK, and RESET):

Unrelated Questions

What were the problems you faced during the implementation of the processor?

Answer:

Did you implement the processor on your own? If you took help from someone whose help did you
take? Which part of the design did you take help for?

Answer:

Honor Code Declaration by student:

 My answers to the above questions are my own work.


 I have not shared the codes/answers written by me with any other students. (I might have helped
clear doubts of other students).
 I have not copied other’s code/answers to improve my results. (I might have got some doubts
cleared from other students).

Name: Date:
ID No.:

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