Dr.

Hanal ABUZANAT
 Addressable memory
 General-purpose registers
 Index and base registers
 Specialized register uses
 Status flags
 Floating-point, MMX, XMM registers

2
General Purpose
Registers

Special Purpose
Registers

Segment
Registers
3
 the general purpose registers:
◦ AX, BX, CX, DX, BP, SI, and DI.
 Although general in nature, each have a
special purpose and name:
 Can carry both Data & Address offsets
 AX – Accumulator
Used also as AX (16 bit), AH (8 bit), and AL (8
bit)
 BX – Base Index often used to address
memory (BX, BH, and BL)
 CX – count, for shifts, rotates, and loops (CX, CH,
and CL)
 DX – data, used with multiply and divide (DX, DH,
and DL)
 BP – base pointer used to address stack data (BP)
 SI – source index (SI) for memory locations, e.g.
with string instructions
 DI – destination index (DI) for memory locations
 SP, IP, and FLAGS
Each has a specific task
◦ SP – Stack pointer: addresses the stack segment used
with functions (procedures) (SP)
◦ IP – Instruction Pointer:
 addresses the next instruction in a program in the code
segment (CS)
◦ FLAGS – indicates latest conditions of the
microprocessor (FLAGS)
 The segment registers are:
◦ CS (code),
◦ DS (data),
◦ ES (extra data. used with string instructions),
◦ SS (stack),
◦ FS, and GS.
 Segment registers define a section of memory
(segment) for a program.
 A segment is either 64K (216) bytes of fixed length (in
the real mode) or up to 4G (232) bytes of variable length
(in the protected mode).
 All code (programs) reside in the code segment.
 Use 8-bit name, 16-bit name, or 32-bit name
 Applies to EAX, EBX, ECX, and EDX

8 8

AH AL 8 bits + 8 bits

AX 16 bits

EAX 32 bits

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 Some registers have only a 16-bit name
for their lower half:

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 Default segment numbers in:
◦ CS for program (code)
◦ SS for stack
◦ DS for data
◦ ES for string destination
 Default offset addresses that go with them:

Segment Offset (16-bit) Purpose

8080, 8086, 80286
IP Program
CS
SP, BP Stack
SS
BX, DI, SI, 8-bit or 16-bit # Data
DS
DI String
ES destination
 flags register is modified automatically by CPU after mathematical
operations:
◦ this allows to determine the type of the result,
◦ and to determine conditions to transfer control to other parts of the program.
 Carry
◦ unsigned arithmetic out of range
 Overflow
◦ signed arithmetic out of range
 Sign
◦ result is negative
 Zero
◦ result is zero
 Parity
◦ sum of 1 bits is an even number

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80386DX
 Protected mode
◦ 4 GB
◦ 32-bit address
 Real mode
◦ 1 MB space
◦ 20-bit address

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 1 MB RAM maximum addressable (220)
 Application programs can access any area
of memory
 Single tasking
 Supported by MS-DOS operating system
 The only mode available on for 8088-8086

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 All real mode 20-bit addresses are a
combination of a segment address (in a segment
register) plus an offset address (in another
register)
 The segment register address (16-bits) is
appended with a 0H or 00002 (or multiplied by
10H) to form a 20-bit start of segment address
 The effective (physical) memory address =
this 20-bit segment address + a 16-bit offset
address in a register
 Segment length is fixed = 216 = 64K bytes
 (11MB)
MB
20-bit (5-hex digits)
Physical Memory address

Effective Address
(physical address)
64 KB +
Segment
16-bit

Appended hexit = 0H
Or multiplied * 16

• 1 hex digit:
•4bit (half byte)
•Nibble
•hexit
 Given a segment address:
◦ multiply it by 16 (add a hexadecimal
zero)
◦ and add it to the offset
 Example: convert 0700:0100 to a
physical address

Adjusted Segment value (x10) : 0 7 0 0 0

Add the offset: 0 1 0 0
Physical address: 0 7 1 0 0

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 Physical Addresses = segment register (SR) x
10H plus offset
(a) SR: 1000H
10000 + 0023 = 10023
(b) SR: AAF0H
AAF00 + 0134 = AB034
(c) SR: 1200H
12000 + FFF0 = 21FF0
What Physical Addresses corresponds to the
segment/offset address 028F:0030?
028F0 + 0030 = 02920

Always use hexadecimal notation for addresses.

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22
 Processor
Control
Control Arithmetic
Arithmetic
Unit
Unit Logic
Logic Unit
Unit (ALU)
(ALU)

Instructions
Data
Information

Input Output
Data Memory Information
Devices Devices

Instructions
Data
Information

Storage
Devices

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Motaz K. Saad, Dept. of CS 24
 PC program
I-1 I-2 I-3 I-4
 Fetch memory fetch

 Decode op1
op2
read

 Fetch operands registers registers

instruction
 Execute I-1 register

 Store output

decode
write

write
flags ALU

execute
(output)

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