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System Verilog Basic Introduction && Assertions: Presenter - Suman Halder

This document provides an introduction to System Verilog and assertions. Some key points covered include: - System Verilog combines features of Verilog and C++ to reduce the gap between design and verification languages. - It supports constrained randomization, object-oriented programming, new data types, assertions, and coverage. - Assertions specify legal and illegal behavior using immediate or concurrent assertions with temporal properties. - Operators like implication, repetition, sequences, and, or are used to define property expressions for assertions. - Built-in functions like $rose, $fell, $stable are used to check signal transitions in assertions.

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Suman Halder
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57 views

System Verilog Basic Introduction && Assertions: Presenter - Suman Halder

This document provides an introduction to System Verilog and assertions. Some key points covered include: - System Verilog combines features of Verilog and C++ to reduce the gap between design and verification languages. - It supports constrained randomization, object-oriented programming, new data types, assertions, and coverage. - Assertions specify legal and illegal behavior using immediate or concurrent assertions with temporal properties. - Operators like implication, repetition, sequences, and, or are used to define property expressions for assertions. - Built-in functions like $rose, $fell, $stable are used to check signal transitions in assertions.

Uploaded by

Suman Halder
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SYSTEM VERILOG BASIC

INTRODUCTION && ASSERTIONS


Presenter – Suman Halder
INTRODUCTION
• System Verilog is a Hardware design and Verification
language having features inherited from Verilog and C++.
System Verilog is a solution to decrease the gap between
design and verification language.

• SystemVerilog is extremely scalable. It can be used by both


HW designers and Verification engineers; SystemVerilog can
be used as part of your Verilog or VHDL Test Bench (TB)
environment, as part of your design or as an external module.
INTRODUCTION
• A designer can enjoy the power of the Random
Generation by simply including some of the
SystemVerilog Random features in the current TB
with no need to change the entire verification
environment.

• In the same way the verification engineer may


include some assertions to verify correctness of a bus
or a protocol as part of the existing full chip
simulation.
Constrained Randomization Easy c model integration

OOP support New data types ie,logic

System Verilog
Assertions Coverage support

Narrow gap b/w design & verification engineer


SVA
• Assertion specifies both legal and illegal behaviour of
a circuit structure (which can be an RTL element, an
interface etc.) inside the design.
SVA
• SystemVerilog provides two types of assertions:
Immediate : Follow simulation event semantics, like code in
always block.
Example:
[LABEL:] assert ( boolean Expression ) [ACTION BLOCK]
ASSERT1 : assert( out1 = r1 + r2) $display(“ASSERTION CHECK
PASSED”) else $WARNING(“OUT1 IS NOT OK FOR r1 %b, r2
%b”,r1,r2);
SVA
• Concurrent Assertion:
Triggers for every given event. (like Posedge of clock).
[Assert_Label:]assert property(Property Expression)
[ACTION BLOCK].
Where property expression can be boolean as well as
temporal( can be Extended for several clock period.)
SVA  concurrent Assertions Failures

• Chk_false_positive : assert property( @(posedge clk) ##3 ack );

• Chk_false_negetive : assert property( @(posedge clk) req ##1 !ack ##1 !ack ##1 !ack );

• Chk_right : assert property( @(posedge clk) !req ##1 req ##1 !ack ##1 !ack ##1 !ack );
SVA – Implication operator & Vacuous
Success
• Chk_right : assert property( @(posedge clk) !req
##1 req |-> ##1 !ack ##1 !ack ##1 !ack );

1) Left side of Implication operator called


antecedent block
2) Right Side is called consequent block
3) If antecedent checking is Successful then only it
Will check the Right Side
4) If antecedent block failed No messege will
generate its called Vacuous success.
Overlapping & Non_overlapping
implication operator
• Chk_right : assert property( @(posedge clk)
!req ##1 req |=> !ack ##1 !ack ##1 !ack );
• 1) By default its Jumps immeadiatly for over
lapping case.
• 2) Non overlapping case its jumps one pulse
later.
In-Built Function --$rose && $fell &&
$stable

• Chk1 : assert property ( @(posedge clk)


$rose(in1) ##1 $fell(in1) |-> ##1 $rose(out1)##1
$fell(out1) );
• $stable  checks whatever value is in previous
posedge is it same or not.
Repetition Operator *

• 1) 1) Chk1 : assert property ( @(posedge clk) $rose(in1) ##1


$fell(in1) |-> ##1 $rose(out1) ##1 $fell(out1) ##1 $rose(out1) ##1
$fell(out1) ##1 $rose(out1) ##1 $fell(out1);

• 2) Chk2 : assert property ( @(posedge clk) $rose(in1) ##1 $fell(in1)


|-> ##1 ( $rose(out1) ##1$fell(out1)[*3] );
Repetition & Range operator

• 1) out1[*2:4] : *2,*3,*4
• 2) out1[*2:$]  from 2 to any Number

• Chk1 : assert property ( @(posedge clk) $rose(in1) ##1 $fell(in1) |-> ##1
$rose(out1) ##1 out1[*2:4] ##1 $fell(out1);
•
sequences
• * we can use sequence block instead of writing the whole
things.
• sequence s1;
$rose(in1)##1$fell(in1)
endsequence
• sequence s2;
$rose(in2)
endsequence
property p1;
@(posedge clk)
s1 | s2
endproperty
Sequence operator  and ,or ,
throughout, within
• 1) and
Property p1
@(posedge clk)
$rose(in1) ##1 $fell(in1) | s1 and s2
2 ) or
Property p1
@(posedge clk)
$rose(in1) ##1 $fell(in1) | s1 or s2
Sequence operator  and ,or ,
throughout, within
2 ) throughout
Property p1
@(posedge clk)
$rose(in1) ##1 $fell(in1) | en throughout s1
Sequence operator  and ,or ,
throughout, within

• property p1;
@( posedge clk)
$rose(in1) ##1 $fell(in1)  ##2 ( ( $rose(out2) ##1 $fell(out2) within
$rose(out1) ##1 out1[*3] ##1 $fell(out1) );
endproperty
In Built function $past

• property p1;
@(posedge clk)
$fell(in1) && $past(in1) && $past($rose(in1),2) |
##1 $rose(out1) ##1 out1 ##1 fell(out1);
endproperty

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