1

Advanced Digital System Design

Part 2

Kuruvilla Varghese
DESE
Indian Institute of Science

Kuruvilla Varghese

Multiplier: Algorithm 2

Multiplicand 1 0 1 1 x
Multiplier 1 1 0 1
------------------
Partial products 1 0 1 1
0 0 0 0
1 0 1 1
1 0 1 1
-----------------------------
1 0 0 0 1 1 1 1
-----------------------------
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 8-bit Multiplier: Issues 3

• Algorithm: Shift and Add

• 8 partial products – 7 Adders ?
– Iterative, use Accumulator, save on Registers for partial products
– Shift Accumulator right, save on muxes at Accumulator to add partial
products
• Resource sharing
– Multiplier & LSB of result (save the Mux otherwise used for selecting
bits)
• Add and Shift in one clock cycle
• If multiplier bit is ‘0’ re-circulate result with shift
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Resources 4

• Multiplicand Register, 8 bit

• Result Register (Multiplier), 16 bit
• 9-bit Adder
• 9-bit, 2 to 1 Multiplexer
• Bit counter (Mod-8 / 3-bit)
• Controller (FSM)

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 mc7:0
clk Multiplier: Data Path
rst MCND REG
load

md7:0 r15:8

ADD

0 r15:8 su8:0

sel 0 1 ml7:0
s0
s8:1
clk
clk L.PROD / MULT rst
prst H. PROD REG REG load
shift shift

r15:8 r7:0

Counter 6

clk
prst count2:0 Decoder max
Counter
shift

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 Controller 7

clk prst
rst load
start Controller
r(0) shift
max sel
done

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Timing Diagram 8

CLK

start

prst

load

sel

shift

max

done

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 Multiplicand Register (MCND) 9

mcndreg: process (clk, rst)

begin
if (rst = '1') then
md md md <= (others => '0');
D Q
mc elsif (clk'event and clk = '1') then
load if (load = '1') then
clk CK md <= mc;
end if;
rst AR
end if;
end process mcndreg;

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H Product Register 10

hprodreg: process (clk, prst)

begin
r15:8 r15:8 if (prst = '1') then
D Q
s8:1 r(15 downto 8) <= (others => '0');
elsif (clk'event and clk = '1') then
shift
if (shift = '1') then
clk CK r(15 downto 8) <= s(8 downto 1);
prst AR end if;
end if;
end process hprodreg;

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 L. PRODUCT / MULT Register 11

mulreg: process (rst, clk)

shift begin
if (rst = '1') then
r7:0 r(7 downto 0) <= (others => '0');
s0 & r7:1 r7:0 elsif (clk'event and clk = '1') then
D Q if (load = '1') then
ml7:0 r(7 downto 0) <= ml;
elsif (shift = '1') then
load
clk
r(7 downto 0) <= s(0) & r(7
CK downto 1);
rst AR end if;
end if;
end process mulreg;
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Counter 12

counter: process (clk, prst)

begin
count if (prst = '1') then
+1
D
count count <= (others => '0');
Q elsif (clk'event and clk = '1') then
if (shift = '1') then
shift count <= count + 1;
clk CK end if;
prst AR end if;
end process;

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 Adder and Mux 13

-- Adder
md7:0 r15:8 su <= ('0' & md) + ('0' & r(15 downto 8));

ADD -- 9 bit 2-to-1 Multiplexer

s(8 downto 0) <= '0' & r(15 downto 8)
0 r15:8 su8:0 when sel = '0' else su(8 downto 0);

0 1
sel

s8:1 s0

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FSM: 3 Blocks view 14

Inputs NS Outputs
Next
D PS Output
State
CK Q Logic
Logic AR

Clock
Reset

NS = f (PS, Inputs)
Moore Outputs = f (PS)
Mealy Outputs = f (PS, Inputs)

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 FSM / Controller: 2 Blocks view 15

Outputs

Inputs
NS D PS
Logic CK Q
AR

Clock
Reset

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Controller 16

clk prst
rst load
start Controller
r(0) shift
max sel
done

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 Timing Diagram 17

CLK

start

prst

load

sel

shift

max

done

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Control Algorithm 18

• Up on reset, come to init state. Wait for start. Initialize

outputs (prst = 1, load = 0, sel = 0, shift = 0, done = 0)
• Up on start, go to next state. Make load = 1
• Transit to next state. Set prst = 0, load = 0, shift = 1, sel =
r(0) (starts the counter, result register is enabled for
loading/shifting) and Wait for max = 1
• Up on max = 1, transit to next state. Set shift = 0, sel = 0
done = 1. Wait until start is low
• Up on start = 1 go to init state.
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 State Diagram 19

power_on
start/
prst = 1, load = 0,
S0 sel = 0, shift = 0,
start
done = 0

start
start/
prst = 0, load = 0, prst = 1, load = 1,
sel = 0, shift = 0, S3 S1 sel = 0, shift = 0,
done = 1 done = 0

max max/
prst = 0, load = 0,
S2 sel = r(0), shift = 1,
done = 0

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State Assignment, Flip-Flops etc 20

• Four states, Binary encoding

• Number of flip-flops: 2
• State Assignment: Sequential
• S0: 00, S1: 01, S2: 10, S3: 11
• Type of Flip-Flops: D Flip flops

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 Next State Table 21

Inputs Present State Next State

start max Q1 Q0 D1 D0
0 X 0 0 0 0
1 X 0 0 0 1
X X 0 1 1 0
X 0 1 0 1 0
X 1 1 0 1 1
0 X 1 1 1 1
1 X 1 1 0 0

D1 = f1 (Q1, Q0, start, max) Equations

D0 = f0 (Q1, Q0, start, max) Minimization
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Output Table 22

Present State Outputs

Q1 Q0 prst load sel shift done
0 0 1 0 0 0 0
0 1 1 1 0 0 0
1 0 0 0 r(0) 1 0
1 1 0 0 0 0 1

Equations
prst = f1 (Q1, Q0) load = f2 (Q1, Q0) sel = f3 (Q1, Q0)
shift = f4 (Q1, Q0) done = f5 (Q1, Q0)
Minimization
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 Methodology 23

1. Specifications
2. Block schematic (Blocks, Signals)
– Data path, Controller(s)
3. System Timing Diagram
4. Data path design (Various Levels)
5. Controller Algorithm
6. State Diagram

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Methodology 24

7. State Diagram Optimization

8. State Assignment
9. Selection of Flip-flops
10. Next State Table, Equations, Minimization
11. Output Table, Equations, Minimization
12. Selection of Device Technology
13. Implementation
14. Test and Debug
15. Documentation

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 Methodology 25

• Steps 1-6: Designer

• Steps 7-11: Tool + Directives
• Steps 12-15: Tools + Designer

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mc7:0
clk Multiplier: Data Path
rst MCND REG
load

md7:0 r15:8

ADD

0 r15:8 su8:0

sel 0 1 ml7:0
s0
s8:1
clk
clk L.PROD / MULT rst
prst H. PROD REG REG load
shift shift

r15:8 r7:0

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13
 VHDL Code 27

• Signals with red dashed line cutting across are ports of the top-level
entity, and others are internal signals. It is easy to code from block
schematic when you use such conventions.

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Multiplier: VHDL Code 28

library ieee; architecture arch_mult8 of mult8 is

use ieee.std_logic_1164.all; type statetype is (s0, s1, s2, s3);
use ieee.std_logic_unsigned.all; signal pr_state, nx_state: statetype;
signal prst, max, load: std_logic;
entity mult8 is port signal sel, shift: std_logic;
(clk, rst, start: in std_logic; signal md: std_logic_vector(7 downto 0);
done: out std_logic; signal su, s: std_logic_vector(8 downto 0);
mc, ml: in std_logic_vector(7 downto 0); signal count: std_logic_vector(2 downto 0);
prod: out std_logic_vector(15 downto 0)); signal r: std_logic_vector(15 downto 0);
end entity; begin

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 Multiplier: VHDL Code 29

-- Multiplier cum Lower Product Register

-- Multiplicand Register mulreg: process (rst, clk)
mcndreg: process (clk, rst) begin
begin if (rst = '1') then
if (rst = '1') then md <= (others => '0'); r(7 downto 0) <= (others => '0');
elsif (clk'event and clk = '1') then elsif (clk'event and clk = '1') then
if (load = '1') then if (load = '1') then
md <= mc; r(7 downto 0) <= ml;
end if; elsif (shift = '1') then
end if; r(7 downto 0) <= s(0) & r(7 downto 1);
end process mcndreg; end if;
end if;
end process mulreg;

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Multiplier: VHDL Code 30

-- 9 bit 2-to-1 Multiplexer -- prod output

s(8 downto 0) <= '0' & r(15 downto 8) prod <= r;
when sel = '0' else su(8 downto 0); -- Counter
counter: process (clk, prst)
-- Higher Product Register begin
hprodreg: process (clk, prst) if (prst = '1') then
begin count <= (others => '0');
if (prst = '1') then elsif (clk'event and clk = '1') then
r(15 downto 8) <= (others => '0'); if (shift = '1') then
elsif (clk'event and clk = '1') then count <= count + 1;
if (shift = '1') then end if;
r(15 downto 8) <= s(8 downto 1); end if;
end if; end process;
end if; -- Max decoder
end process hprodreg; max <= '1' when (count = 7) else '0';
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 Multiplier: VHDL Code 31

-- Adder when s1 =>

su <= ('0' & md) + ('0' & r(15 downto 8)); prst <= '1'; load <= '1'; shift <= '0';
sel <= '0'; done <= '0';
-- FSM, Next state Logic, Output Logic nx_state <= s2;
conlog: process (pr_state, start, r(0), max) when s2 =>
begin prst <= '0'; load <= '0'; shift <= '1';
case pr_state is sel <= r(0); done <= '0';
when s0 => if (max = '1') then nx_state <= s3;
prst <= '1'; load <= '0'; shift <= '0'; else nx_state <= s2;
sel <= '0'; done <= '0'; end if;
if (start = '1') then nx_state <= s1;
else nx_state <= s0;
end if;

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Multiplier: VHDL Code 32

when s3 => -- FSM Flip Flops

prst <= '0'; load <= '0'; shift <= '0'; conff: process (rst, clk)
sel <= '0'; done <= '1'; begin
if (start = '1') then nx_state <= s0; if (rst = '1') then
else nx_state <= s3;
pr_state <= s0;
end if;
elsif (clk'event and clk = '1') then
when others =>
prst <= '0'; load <= '0'; shift <= '0'; pr_state <= nx_state;
sel <= '0'; done <= '0'; end if;
nx_state <= s0; end process;
end case; end arch_mult8;
end process;

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 State Diagram 33

power_on
start/
prst = 1, shift = 0,
S0 load = 0, sel = 0,
start done = 0

start
start/
prst = 0, shift = 0, prst = 1, shift = 0,
load = 0, sel = 0, S3 S1 load = 1, sel = 0,
done = 1 done = 0

max max/
prst = 0, shift = 1,
S2 load = 0, sel = r(0),
done = 0

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Implied Latch in Next State logic 34

conlog: process (pr_state, start, r(0), max) • While coding next state logic, You
begin should specify all transitions explicitly.
case pr_state is • In the above code you should not think
when s0 => the FSM is in state S0, hence the else
prst <= '1'; load <= '0'; shift <= '0'; part need not be specified
sel <= '0'; done <= '0'; • This will create an implied latch, as this
if (start = '1') then nx_state <= s1; is a combinational circuit with pr_state
else nx_state <= s0; as input and nx_state as output.
end if; • S0 in when S0 refers to input (present
state) and S0 in nx_state <= s0 refers to
output (next state).

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 Multiplier: VHDL Code version 2 35

• In the following code, registers with the same control signals

as reset, clock, and various enable signals etc. are combined
into single process.
• Registers with (clk, prst)
– Higher Product Register, Counter
• Registers with (clk, rst)
– Present State (FSM State Register)
– Multiplicand Register
– Multiplier cum Lower Product Register
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Multiplier: VHDL Code version 2 36

-- Components with clk, prst end if;

subreg1: process (clk, prst) end process subreg1;
begin
if (prst = '1') then
-- HPROD Register, Counter clear
r(15 downto 8) <= (others => '0');
count <= (others => '0');
elsif (clk'event and clk = '1') then
-- Higher Product Register, Counter
if (shift = '1') then
r(15 downto 8) <= s(8 downto 1);
count <= count + 1;
end if;
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 Multiplier: VHDL Code version 2 37

-- Components with clk, rst -- Multiplicand Register

subreg2: process (clk, rst) if (load = '1') then
begin md <= mc;
if (rst = '1') then end if;
pr_state <= s0; -- Multiplier cum Lower Product Register
md <= (others => '0'); if (load = '1') then
r(7 downto 0) <= (others => '0’); r(7 downto 0) <= ml;
elsif (clk'event and clk = '1') then elsif (shift = '1') then
pr_state <= s0; r(7 downto 0) <= s(0) & r(7 downto 1);
end if;
end if;
end process subreg2;

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Multiplier: VHDL Code version 3 38

• In the following code, datapath is written as part of the FSM

code.
• Here, control signals going from FSM to various components
(registers, muxes etc.) are not explicitly defined, they become
implicit.
• Hence, to infer the block schematic from such a code will be
bit difficult.
• Another disadvantage of such a code is that resource sharing
among various components would be difficult to code.
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19
 mc7:0 Multiplier
clk
MCND REG
clk count
md7:0 r15:8
Counter =7

ADD

0 su8:0
r15:8
shift
clk sel
rst 0 1 ml7:0
load
start Controller prst s0
s8:1 clk
clk
L.PROD / MULT
r(0) H. PROD REG REG
done

r15:8 r7:0

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Multiplier: VHDL Code version 3 40

library ieee; architecture arch_mult8 of mult8 is

use ieee.std_logic_1164.all; type statetype is (s0, s1, s2, s3);
use ieee.std_logic_unsigned.all; signal state: statetype;
signal md: std_logic_vector(7 downto 0);
entity mult8 is signal su, s: std_logic_vector(8 downto 0);
port signal count: std_logic_vector(3 downto 0);
(clk, rst, start: in std_logic; signal r: std_logic_vector(15 downto 0);
done: out std_logic; begin
mc, ml: in std_logic_vector(7 downto 0); -- prod output
prod: out std_logic_vector(15 downto 0)); prod <= r;
end entity;

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 Multiplier: VHDL Code version 3 41

-- Controller FSM, Datapath case state is

connsl: process (clk) when s0 =>
begin r(15 downto 8) <= (others => '0’);
if (clk'event and clk = '1') then count <= (others => '0');
if (rst = '1') then done <= '0';
state <= s0; if (start = '1') then state <= s1;
r <= (others => '0’); else state <= s0;
count <= (others => '0’); end if;
md <= (others => '0’); when s1 =>
else md <= mc; r(7 downto 0) <= ml;
done <= '0';
state <= s2;

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Multiplier: VHDL Code version 3 42

when s2 => when others =>

r(15 downto 8) <= s(8 downto 1); done <= '0’; state <= s0;
r(7 downto 0) <= s(0) & r(7 downto 1); end case;
count <= count + 1; end if;
done <= '0’; end if;
if (count = 7) then state <= s3; end process;
else state <= s2;
end if; -- 9 bit 2-to-1 Multiplexer
when s3 => s(8 downto 0) <= '0' & r(15 downto 8) when
done <= '1'; r(0) = '0' else su(8 downto 0);
if (start = '1') then state <= s0; -- 8-bit adder
else state <= s3; su <= ('0' & md) + ('0' & r(15 downto 8));
end if; end arch_mult8;
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 Power on Reset 43

Inputs NS Outputs
Next D
Sync Output
State PS
Reset CK Q Logic
Logic AR

Clock
Async Reset

• Use Synchronous Reset,

• Or Asynchronous Reset, former is preferable

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FSM: Clock frequency 44

• Maximum Clock Frequency

– Delays of the blocks
• Max Clock frequency (Min Clock period)
Tclk(min) > Max ((tcq + tNSL + ts)maxpath, (tcq + tOL + … )maxpath)

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 FSM: Minimum Clock frequency 45

CLK

IN1

IN2

IN3

CLK’

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FSM: Minimum Clock frequency 46

• Minimum Clock frequency should be greater than the twice the

Maximum Input rate.
• Sampling the inputs.
• Inputs may not be periodic waveform.
• Pulse width should not be the criteria. How fast to respond to the
event should be the criteria.
• To detect a pulse with certain accuracy, min clock period should be
less than the error.
• Depending on the application you may consider error at the start of
the pulse and end of the pulse.
• Then minimum clock period should less than half the error.
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 Timing Pulse Accuracy 47

Timing Pulse
CLK1

CLK2

• To detect a pulse with certain accuracy, min clock period should be less than
the error

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Pulse detection 48

• Pulse to level converter

• Level to Pulse converter

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 Pulse to toggle 49

I
D Q

CK
P AR

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Level to pulse 50

I
I1 I2 I3
D Q D Q D Q

CK CK CK

clk2

I2

clk2

I3

l2 xor l3

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 Pulse Transfer 51

I
I1 I2 l3
D Q D Q D Q D Q

CK CK CK
CK
P
clk2

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Register to Register Path 52

D Q D Q
Comb
CK CK

CLK

Tclk(min) = [tco+ tcomb + ts ]maxpath + slack

(For each path i)

tco(min)i + tcomb(min)i > th(max)i
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 Naive Question often asked? 53

D Q D Q
Comb
CK CK

CLK

Tclk(min)/2 = [tco + tcomb + ts]maxpath + slack

Tclk(min) = 2 * ([tco + tcomb + ts]maxpath + slack)
Tclk/2 + tco(min) + tcomb(min) > th

If the second register is clocked by CLK/, the frequency of the clock has to be half
that of the previous case. Also, the data still arrives at every clock period of half the
clock frequency
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Moore / Mealy Output 57

Moore Output
rst
start/ Mealy Output
S0 load = 0 rst
start/
start
S0 load = start

S1 load = 1 start

S2 load = 0
S2 load = 0

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 Moore / Mealy Output 58

clk

start
S0 S0 S1 S2
Moore states

load
S0 S0 S2
Mealy states

load

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Mealy Output 59

• Comes earlier to Moore output

• Number of states are less
• Output timing depends on input timing; Glitches
• Hence, ideal when FSM and other blocks are synchronous

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 FSM: Mealy Output 60

Synchr
onous
O1: Mealy Output Sub-
i1 system
FSM
i2

clk O2: Mealy Output

Synchr
onous
Sub-
system

O1 and O2 can be Mealy output as function of states and i1 and/or i2 or any other combination of
synchronous inputs
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Control of Sequential Circuits 61

FSM / Reg /
en (RA_L)
Contr- Counter /
oller Seq Ckt

clk

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 Clock Gating 62

D7:0 D Q D7:0

RA_E

RA_L CLK’
CK
CLK

CLK

RA-L

CLK’

1 2
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Clock Gating 63

• Two active clock edges

• In some cases, where the control signal register a data, edge 1 may not
meet the minimum clock period constraint (i.e. it may not
accommodate [tco + tcomb + ts]maxpath ), edge 2 may be late causing hold
time violation.
• In cases, where a control signal is used to increment some counter,
counter may get incremented twice, instead of once.

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 Re-circulating Buffer 64

0
D Q D7:0
1

RA_L RA_E
CLK CK

CLK

RA-L

Register write on the clock edge

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Re-circulating Buffer 65

• Any number of control signals

• Different data paths
– E.g. Parallel data, shifted data etc.
• Priority of control signals

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 Counter with enable 66

+1 1 count
0
d q
q
en
clk clk
SR

rst

• ‘en’ comes from FSM, en = 1 counter counts otherwise retains the

value.

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VHDL Code 67

process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then q <= (others => '0’);
elsif (en = ‘1’) then q <= q + 1;
end if;
end if;
end process;

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 Counter with enable and load 68

0
+1 count

1
en d q
q

1
din
load
clk
clk SR
rst

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VHDL Code 69

process (clk)
Begin
if (clk'event and clk = '1') then
if (rst = '1') then q <= (others => '0’);
elsif (load = '1') then q <= din;
elsif (en = ‘1’) then q <= q + 1;
end if;
end if;
end process;

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 Re-circulating Buffer 70

0
D Q D7:0
1

RA_L RA_E
CLK CK

CLK

RA-L

Register write on the clock edge

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Re-circulating Buffer – issue / solution 71

• Issue: Power dissipation

• Requirement: Write should be on the clock edge at the
trailing end of the control pulse, then glitch.
• Solution: Move the control pulse to match on period of clock
• How: Resynchronize the control signal with the –ve clock
edge

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 Clock Gating for Low Power 72

D7:0
D Q D7:0
CLK1
RA_L D Q
CK RA_E
CLK2
CK

CLK

CLK

RA-L
CLK1

CLK2

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Clock Gating for Low Power 73

• Here, the requirement is to have a clock pulse with an active clock

edge matching with the trailing edge of the original control signal.
• This can be achieved, if the original control signal is delayed by half a
clock period and this is gated with the original clock. But delaying, by
adding combinational logic delays would not be precise and would not
allow flexibility in changing the clock frequency.
• Hence, the original control signal is resynchronized with negative
(opposite) clock edge and this resynchronized signal is gated with the
clock to generate the control signal.

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