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Real Mode of 80386DX Microprocessor

The document discusses the real and protected modes of the 80386DX microprocessor. It describes the global descriptor table (GDT) and interrupt descriptor table (IDT) mechanisms. It explains the four control registers CR0 through CR3 that define the protected mode configuration. CR0 contains flags like protected mode enable (PE) and paging bits. Paging uses page directories and page tables with page frame addresses. Entries have protection bits like present (P), accessed (A), dirty (D) that define memory access levels from 0 to 3.

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Mohamd barca
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15 views

Real Mode of 80386DX Microprocessor

The document discusses the real and protected modes of the 80386DX microprocessor. It describes the global descriptor table (GDT) and interrupt descriptor table (IDT) mechanisms. It explains the four control registers CR0 through CR3 that define the protected mode configuration. CR0 contains flags like protected mode enable (PE) and paging bits. Paging uses page directories and page tables with page frame addresses. Entries have protection bits like present (P), accessed (A), dirty (D) that define memory access levels from 0 to 3.

Uploaded by

Mohamd barca
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Real Mode of 80386DX microprocessor

Protected Mode of 80386DX microprocessor


Global Descriptor Table Mechanism

Interrupt Descriptor Table Mechanism


Figure (a) Task with Global and local Descriptor Tables
Figure (b) Loading the Local Descriptor Table Register to Define a Local
Descriptor Table
Control Registers/ Intel Corp
 Control Registers

The protected –Mode model includes the four system –control registers, identified
as CR0 through CR3. As shown in the figures above.
The lowers 5-bits of CR0 are system –control flags. These bits make up what is
known as machine status word (MSW). The most significant bit of CR0 and
registers CR2 and CR3 are used by the 80386DX’s paging mechanism. They
contain information about the 80386DX’s protected-mode configuration and status.
The 4-bits labeled PE,MO,EM and R are control bits that define the protected-
mode system configuration. The TS is a status bits. Theses bits can be examined or
modified through software.
 The protected –model enable (PE) bit determines if the 80386DX is in real
or protected mode. If PE is cleared this enables real-mode operation. And if
PE is set this will enable the protected- mode operation. Once the
microprocessor is in protected mode it cannot witch back to real mode under
software control by clearing the PE bit only. The only way to witch back to
real –mode is by initiating a hardware reset.
 The math present (MP) bit is set to one to indicate that a numeric
coprocessor is present in the microcomputer system. If the system to be
configured so that a software emulator is used to perform numeric
Operations, the emulator (EM) bit is set to one. Only one of these two bits
can be set at a time.
 The extension type R-bit is used to indicate whether an 80287 or 80387
numeric coprocessor is in use. Logic one in R indicates an 80387 is installed.
 Task switch (TS) it gets set whenever the 80386Dx switches from one task
to another. It can be cleared under software control.

- Page Directory: This is at the most 4Kbytes in size. Each directory entry
is of 4 bytes, thus a total of 1024 entries are allowed in a directory. The
upper 10 bits of the linear address are used as an index to the
corresponding page directory entry. The page directory entries point to
page tables.
- Page Tables: Each page table is of 4Kbytes in size and many contain a
maximum of 1024 entries. The page table entries contain the starting
address of the page and the statistical information about the page.
 The upper 20 bit page frame address is combined with the lower 12 bit of the
linear address. The address bits A12- A21 are used to select the 1024 page
table entries. The page table can be shared between the tasks.
 The P bit of the above entries indicate, if the entry can be used in address
translation. If P=1, the entry can be used in address translation, otherwise it
cannot be used. The P bit of the currently executed page is always high.
 The accessed bit A is set by 80386 before any access to the page. If A=1, the
page is accessed, else unaccessed.
 The D bit ( Dirty bit) is set before a write operation to the page is carried
out. The D-bit is undefined for page director entries.
 The OS reserved bits are defined by the operating system software.
 The User / Supervisor (U/S) bit and read/write bit are used to provide
protection. These bits are decoded to provide protection under the 4 level
protection model.
 The level 0 is supposed to have the highest privilege, while the level 3 is
supposed to have the least privilege.
 This protection provide by the paging unit is transparent to the segmentation
unit.

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