Computer Engineering Department: Second Class Ass. Lecturer Suhad Haddad
Computer Engineering Department: Second Class Ass. Lecturer Suhad Haddad
Second Class
The Oscillator
feedback circuit that produces phase shift and provides attenuation, as shown in
Figure 2.
1- Feedback Oscillators
Positive Feedback
Positive Feedback is characterized by the condition wherein a portion of the output
voltage of an amplifier is fed back to the input with no net phase shift, resulting in
a reinforcement of the output signal. This basic idea is illustrated in Figure 3(a). As
you can see, the in phase feedback voltage Vf , is amplified to produce the output
voltage, which in turn produces the feedback voltage.
That is, a loop is created in which the signal sustains itself and a continuous
sinusoidal output is produced. This phenomenon is called oscillation. In some
types of amplifiers, the feedback circuit shifts the phase 1800 and an inverting
amplifier is required to provide another 1800 phase shift so that there is no net
phase shift. This is illustrated in Figure 3(b).
The voltage gain around the closed feedback loop Acl, is the product of the
amplifier gain Av, and the attenuation, B, of the feedback circuit.
Acl = Av B
If a sinusoidal wave is the desired output, a loop gain greater than 1 will rapidly
cause the output to saturate at both peaks of the waveform, producing unacceptable
distortion. To avoid this, some form of gain control must be used to keep the loop
gain at exactly 1 once oscillations have started. For example, if the attenuation of
the feedback circuit is 0.01, the amplifier must have a gain of exactly 100 to
overcome this attenuation and not create unacceptable distortion (0.01 * 100 = 1).
An amplifier gain of greater than 100 will cause the oscillator to limit both peaks
of the waveform.
Start-Up Conditions
So far, you have seen what it takes for an oscillator to produce a continuous
sinusoidal output. Now let’s examine the requirements for the oscillation to start
when the dc supply voltage is first turned on. As you know, the unity-gain
condition must be met for oscillation to be sustained. For oscillation to begin, the
voltage gain around the positive feedback loop must be greater than 1 so that the
amplitude of the output can build up to a desired level. The gain must then
decrease to 1 so that the output stays at the desired level and oscillation is
sustained. The voltage gain conditions for both starting and sustaining oscillation
are illustrated in Figure 5.
A question that normally arises is this: If the oscillator is initially off and there is
no output voltage, how does a feedback signal originate to start the positive
feedback buildup process? Initially, a small positive feedback voltage develops
from thermally produced broad-band noise in the resistors or other components or
from power supply turn-on transients. The feedback circuit permits only a voltage
with a frequency equal to the selected oscillation frequency to appear in phase on
the amplifier’s input. This initial feedback voltage is amplified and continually
reinforced, resulting in a buildup of the output voltage as previously discussed.
Figure 5: When oscillation starts at t0, the condition Acl > 1 causes the sinusoidal output voltage amplitude to
build up to a desired level. Then Acl decreases to 1 and maintains the desired amplitude.
R2
R1
The response curve for the lead-lag circuit shown in Figure 6(b) indicates that the
output voltage peaks at a frequency called the resonant frequency fr , At this point,
the attenuation (Vout /Vin) of the circuit is 1/ 3 if R1 = R2 and XC1 = XC2 as
stated by the following equation
The Basic Circuit The lead-lag circuit is used in the positive feedback loop of an
op-amp, as shown in Figure 7(a). A voltage divider is used in the negative
feedback loop.
The circuit is redrawn in Figure 7(b) to show that the op-amp is connected across
the bridge circuit. One leg of the bridge is the lead-lag circuit, and the other is the
voltage divider.
Positive Feedback Conditions for Oscillation As you know, for the circuit to
produce a sustained sinusoidal output (oscillate), the phase shift around the
positive feedback loop must be 0° and the gain around the loop must equal unity
(1). The 0° phase-shift condition is met when the frequency is fr because the
phase shift through the lead-lag circuit is 0° and there is no inversion from the
noninverting (+) input of the op-amp to the output. This is shown in Figure 8(a).
Acl = 3
This offsets the 1/3 attenuation of the lead-lag circuit, thus making the total gain
around the positive feedback loop equal to 1, as depicted in Figure 8(b). To
achieve a closed-loop gain of 3,
R1 = 2R2
Then
Start-Up Conditions Initially, the closed-loop gain of the amplifier itself must be
more than 3 (Acl > 3) until the output signal builds up to a desired level. Ideally,
the gain of the amplifier must then decrease to 3 so that the total gain around the
loop is 1 and the output signal stays at the desired level, thus sustaining oscillation.
This is illustrated in Figure 9.
The circuit in Figure 10 illustrates a method for achieving sustained oscillations.
Notice that the voltage-divider circuit has been modified to include an additional
resistor R3 in parallel with a back-to-back zener diode arrangement. When dc
power is first applied,
Both zener diodes appear as opens. These places R3 in series with R1 thus
increasing the closed-loop gain of the amplifier as follows (R1 = 2R2):
A JFET operating with a small or zero VDS is operating in the ohmic region. As
the gate voltage increases, the drain-source resistance increases. If the JFET is
placed in the negative feedback path, automatic gain control can be achieved
because of this voltage-controlled resistance.
A JFET stabilized Wien Bridge is shown in Figure 11. The gain of the op-amp is
controlled by the components shown in the green box, which include the JFET.
The JFET’s drain-source resistance depends on the gate voltage. With no output
signal, the gate is at zero volts, causing the drain-source resistance to be at the
minimum. With this condition, the loop gain is greater than 1. Oscillations begin
and rapidly build to a large output signal. Negative excursions of the output signal
forward-bias D1, causing capacitor C3 to charge to a negative voltage. This
voltage increases the drain-source resistance of the JFET and reduces the gain (and
hence the output). This is classic negative feedback at work. With the proper
selection of components, the gain can be stabilized at the required level.
Figure 11 : Self-starting Wien-bridge oscillator using a JFET in the negative feedback loop.
© Ass.Lecturer // Suhad Haddad Page 15
Digital Electronics/Second Class Third Subject
Solution:
For the lead-lag circuit, R1 = R2 = R = 10 kΩ and C1 = C2 = C = 0.01 µF. The
frequency is
© Ass.Lecturer // Suhad Haddad Page 16
Digital Electronics/Second Class Third Subject
The closed-loop gain must be 3.0 for oscillations to be sustained. For an inverting
amplifier, the gain expression is the same as for a noninverting amplifier.
amp itself provides the additional 180° to meet the requirement for oscillation of a
360° (or 0°) phase shift around the feedback loop.
B =1/29
Where B = R3/Rf .To meet the greater-than-unity loop gain requirement, the
closed-loop voltage gain of the op-amp must be greater than 29 (set by Rf and
R3). The frequency of oscillation fr is also derived on the companion website and
is stated in the following equation, where R1 = R2 = R3 = R and C1 = C2 = C3 =
C.
1-Monostable Operation
The 555 timer can also be used as a one-shot or monostable multivibrator
circuit, as shown in Fig. 14. When the trigger input signal goes negative, it triggers
the one shot, with output at pin 3 then going high for a time period
Thigh = 1.1RaC
The negative edge of the trigger input causes comparator 2 to trigger the flip-flop,
with the output at pin 3 going high. Capacitor C charges toward VCC through
resistor Ra . During the charge interval, the output remains high. When the voltage
across the capacitor reaches the threshold level of 2/3VCC, comparator 1 triggers
the flip-flop, with output going low. The discharge transistor also goes low,
causing the capacitor to remain at near 0 V until triggered again. Figure 16-b
shows the input trigger signal and the resulting output waveform for the 555 timer
operated as a one-shot. Time periods for this circuit can range from
microseconds to many seconds, making this IC useful for a range of
applications.
Figure 14: Operation of 555 timers as one-shot: (a) circuit; (b) waveforms.
2-Astable Operation:
A 555 timer connected to operate in the astable mode as a free-running
relaxation oscillator ( astable multivibrator ) is shown in Figure 15. Notice that the
threshold input (Thresh) is now connected to the trigger input (Trig). The external
components R1, R2 and Cext form the timing circuit that sets the frequency of
oscillation. The 0,001µF capacitor connected to the control (Cont) input is strictly
for decoupling and has no effect on the operation.
Initially, when the power is turned on, the capacitor Cext is uncharged and thus
the trigger voltage (pin 2) is at 0 V. This causes the output of the lower comparator
to be high and the output of the upper comparator to be low, forcing the output of
the flip-flop, and thus the base of Qd, low and keeping the transistor off. Now,
Cext begins charging through and as indicated in Figure 16. When the capacitor
voltage reaches 1⁄3VCC, the lower comparator switches to its low output state, and
when the capacitor voltage reaches 2⁄3VCC, the upper comparator switches to its
high output state. This resets the flip-flop, causes the base of Qd to go high, and
turns on the transistor. This sequence creates a discharge path for the capacitor
through R2 and the transistor, as indicated. The capacitor now begins to
discharge, causing the upper comparator to go low. At the point where the
capacitor discharges down to 1⁄3VCC, the lower comparator switches high, setting
the flip-flop, which makes the base of Qd low and turns off the transistor. Another
charging cycle begins, and the entire process repeats. The result is a rectangular
wave output whose duty cycle depends on the values of R1 and R2 or RA and RB
Figure 18: The VCO output frequency varies inversely with VCONT because the charging
and discharging time of Cext is directly dependent on the control voltage.