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LMR36006
SNVSB48C – APRIL 2018 – REVISED OCTOBER 2019

LMR36006 4.2-V to 60-V, 0.6-A Ultra-Small Synchronous Step-Down Converter

1 Features 2 Applications
1• Designed for reliable and rugged applications • Field transmitters and sensors, PLC modules
– Input transient protection up to 66 V • Thermostats, video surveillance, HVAC systems
– Junction temperature range –40°C to +150°C • AC and servo drives, rotary encoders
– Protection features: thermal shutdown, input • Industrial transport, asset tracking
undervoltage lockout, cycle-by-cycle current
limit, hiccup short-circuit protection 3 Description
– 0.2-V dropout with 0.6-A load (typical) The LMR36006 regulator is an easy-to-use,
synchronous, step-down DC/DC converter. With
• Suited for scalable industrial power supplies
integrated high-side and low-side power MOSFETs,
– Pin compatible with: up to 0.6 A of output current is delivered over a wide
– LMR36015 (60 V, 1.5 A) input voltage range of 4.2 V to 60 V. Tolerance goes
– LMR33620/LMR33630 (36 V, 2 A or 3 A) up to 66 V. The transient tolerance reduces the
necessary design effort to protect against
– 1-MHz, 2.1-MHz frequency options overvoltages and meets the surge immunity
• Low power dissipation across load spectrum requirements of IEC 61000-4-5.
– 87% efficiency at 1 MHz (24VIN, 5VOUT, 0.6A) The LMR36006 uses peak-current-mode control to
– 92% efficiency at 1 MHz (12VIN, 5VOUT, 0.6A) provide optimal efficiency and output voltage
– Increased light load efficiency in PFM accuracy. Precision enable gives flexibility by
enabling a direct connection to the wide input voltage
– Low operating quiescent current of 26 µA or precise control over device start-up and shutdown.
• Small 2-mm × 3-mm HotRod™ package The power-good flag, with built-in filtering and delay,
• Solution with few external components offers a true indication of system status eliminating
the requirement for an external supervisor.
• LMR36006-Q1 and LMR36015-Q1 available in
400 kHz and 2.1 MHz, adjustable output, and The LMR36006 is in a HotRod™ package which
fixed 3.3 VOUT enables low noise, higher efficiency, and the smallest
package to die ratio. The device requires few external
• Optimized for ultra low EMI requirements
components and has a pinout designed for simple
– Meets CISPR25 class 5 standard PCB layout. The small solution size and feature set of
– Hotrod™ package minimizes switch node the LMR36006 are designed to simplify
ringing implementation for a wide range of end equipment,
including space critical applications of ultra-small field
– Parallel input path minimizes parasitic
transmitters and vision sensors.
inductance
– Spread spectrum reduces peak emissions Device Information(1)
• Create a custom design using the LMR36006 with PART NUMBER PACKAGE BODY SIZE (NOM)
the WEBENCH® Power Designer LMR36006 VQFN-HR (12) 2.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

100%
Simplified Schematic
90%
BOOT
80% VIN VIN
CBOOT

CIN EN SW VOUT
Efficiency

70% L1
COUT
PGND
60%
LMR36006

50% VCC PG

RFBT
CVCC
40% VIN = 12V FB
VIN = 24V RFBB
30% AGND
0 0.06 0.12 0.18 0.24 0.3 0.36 0.42 0.48 0.54 0.6
Output Current (A) typi

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes........................................ 16
2 Applications ........................................................... 1 9 Application and Implementation ........................ 19
3 Description ............................................................. 1 9.1 Application Information............................................ 19
4 Revision History..................................................... 2 9.2 Typical Application .................................................. 20
9.3 What to Do and What Not to Do ............................. 34
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 4 10 Power Supply Recommendations ..................... 35
7 Specifications......................................................... 5 11 Layout................................................................... 36
11.1 Layout Guidelines ................................................. 36
7.1 Absolute Maximum Ratings ...................................... 5
11.2 Layout Example .................................................... 38
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions ...................... 5 12 Device and Documentation Support ................. 39
7.4 Thermal Information .................................................. 6 12.1 Device Support .................................................... 39
7.5 Electrical Characteristics........................................... 6 12.2 Documentation Support ........................................ 39
7.6 Timing Requirements ................................................ 7 12.3 Receiving Notification of Documentation Updates 39
7.7 System Characteristics ............................................. 8 12.4 Support Resources ............................................... 40
7.8 Typical Characteristics .............................................. 9 12.5 Trademarks ........................................................... 40
12.6 Electrostatic Discharge Caution ............................ 40
8 Detailed Description ............................................ 10
12.7 Glossary ................................................................ 40
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 11 13 Mechanical, Packaging, and Orderable
8.3 Feature Description................................................. 11
Information ........................................................... 40

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (February 2019) to Revision C Page

• Added EMI description to the Features .................................................................................................................................. 1

• Added Figure 33 through Figure 42 ..................................................................................................................................... 28

Changes from Revision A (November 2018) to Revision B Page

• Updated package quantities in Device Comparison Table. ................................................................................................... 3

Changes from Original (April 2018) to Revision A Page

• First release of production-data data sheet ........................................................................................................................... 1

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5 Device Comparison Table

ORDERABLE PART OUTPUT VOLTAGE FPWM fSW PACKAGE QUANTITY

NUMBER
LMR36006BRNXT Adjustable No 1 MHz 250
LMR36006BRNXR Adjustable No 1 MHz 3000
LMR36006CRNXT Adjustable No 2.1 MHz 250
LMR36006CRNXR Adjustable No 2.1 MHz 3000

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6 Pin Configuration and Functions

RNX Package
12-Pin VQFN-HR
Top View
SW
12
5
PGND 1 11 PGND

VIN 2 10 VIN

NC 3 9 EN

BOOT 4 8 PG

5 6 7
VCC AGND FB

Pin Functions
NO. NAME TYPE DESCRIPTION
1, 11 PGND G Power ground terminal. Connect to system ground and AGND. Connect to CIN with short wide traces.
2, 10 VIN P Input supply to regulator. Connect to CIN with short wide traces.
Connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT capacitor to the
3 NC —
SW pin. This pin has no internal connection to the regulator.
Boot-strap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from this
4 BOOT P pin to the SW pin. Connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT
capacitor to the SW pin.
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads.
5 VCC P Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to
GND.
Analog ground for regulator and system. Ground reference for internal references and logic. All electrical
6 AGND G
parameters are measured with respect to this pin. Connect to system ground on PCB.
Feedback input to regulator. Connect to tap point of feedback voltage divider. DO NOT FLOAT. DO
7 FB A
NOT GROUND.
Open drain power-good flag output. Connect to suitable voltage supply through a current limiting
8 PG A resistor. High = power OK, low = power bad. Goes low when EN = Low. Can be open or grounded when
not used.
9 EN A Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; DO NOT FLOAT.
Regulator switch node. Connect to power inductor. Connect the SW pin to NC on the PCB. This
12 SW P
simplifies the connection from the CBOOT capacitor to the SW pin.
A = Analog, P = Power, G = Ground

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7 Specifications
7.1 Absolute Maximum Ratings
Over operating junction temperature range of -40°C to 150°C (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage VIN to PGND –0.3 66 V
Input voltage EN to AGND –0.3 66.3 V
Input voltage FB to AGND –0.3 5.5 V
Input voltage PG to AGND –0.3 22 V
Input voltage AGND to PGND –0.3 0.3 V
Output voltage SW to PGND –0.3 66.3 V
Output voltage SW to PGND less than 10-ns transients –3.5 66.3 V
Output voltage CBOOT to SW –0.3 5.5 V
Output voltage VCC to AGND –0.3 5.5 V
Junction Temperature TJ -40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
Electrostatic
V(ESD) Human-body model (HBM) (1) ±2500 V
discharge
Electrostatic
V(ESD) Charged-device model (CDM) (2) ±750 V
discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40 ℃ to 150 ℃ (unless otherwise noted) (1)
MIN MAX UNIT
VIN to PGND 4.2 60 V
Input voltage EN to PGND (2) 0 60 V
PG to PGND (2) 0 18 V
Output current IOUT 0 0.6 A

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.

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7.4 Thermal Information

LMR36006
THERMAL METRIC (1) RNX (VQFN-HR) UNIT
12 PINS
RθJA Junction-to-ambient thermal resistance 72.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 35.9 °C/W
RθJB Junction-to-board thermal resistance 23.3 °C/W
ψJT Junction-to-top characterization parameter 0.8 °C/W
ψJB Junction-to-board characterization parameter 23.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 Electrical Characteristics

Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits (1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating quiescent current (non-
IQ-nonSW VEN = 3.3 V (PFM variant only) 18 26 36 µA
switching) (2)
Shutdown quiescent current;
ISD VEN = 0 V 5 µA
measured at VIN pin
ENABLE (EN PIN)
VEN-VCC-H Enable input high level for VCC output VENABLE rising 1.14 V
VEN-VCC-L Enable input low level for VCC output VENABLE falling 0.3 V
VEN-VOUT-H Enable input high level for VOUT VENABLE rising 1.157 1.231 1.3 V
VEN-VOUT-HYS Enable input hysteresis for VOUT Hysteresis below VENABLE-H; falling 110 mV
ILKG-EN Enable input leakage current VEN = 3.3V 0.2 nA
INTERNAL LDO (VCC PIN)
VCC Internal VCC voltage 6 V ≤ VIN ≤ 60 V 4.75 5 5.25 V
VCC-UVLO-
Internal VCC undervoltage lockout VCC rising 3.6 3.8 4.0 V
Rising
VCC-UVLO-
Internal VCC undervoltage lockout VCC falling 3.1 3.3 3.5 V
Falling
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage 0.985 1 1.015 V
ILKG-FB Feedback leakage current FB = 1 V 0.2 nA
CURRENT LIMITS AND HICCUP
ISC High-side current limit (3) 0.8 1 1.2 A
(3)
ILS-LIMIT Low-side current limit 0.6 0.8 0.95 A
IL-ZC Zero cross detector threshold PFM variants only 0.02 A
IPEAK-MIN Minimum inductor peak current (3) 0.18 A

(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.

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Electrical Characteristics (continued)

Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER GOOD (PGOOD PIN)
VPG-HIGH-UP Power-Good upper threshold - rising % of FB voltage 105% 107% 110%
VPG-LOW-DN Power-Good lower threshold - falling % of FB voltage 90% 93% 95%
Power-Good hysteresis (rising &
VPG-HYS % of FB voltage 2%
falling)
Power-Good rising/falling edge
TPG 80 140 200 µs
deglitch delay
Minimum input voltage for proper
VPG-VALID 2 V
Power-Good function
RPG Power-Good on-resistance VEN = 2.5 V 80 165 Ω
RPG Power-Good on-resistance VEN = 0 V 35 90 Ω
OSCILLATOR
FOSC Internal oscillator frequency 2.1-MHz variant 1.95 2.1 2.35 MHz
FOSC Internal oscillator frequency 1-MHz variant 0.85 1 1.15 MHz
MOSFETS
RDS-ON-HS High-side MOSFET ON-resistance IOUT = 0.5 A 225 435 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance IOUT = 0.5 A 150 280 mΩ

7.6 Timing Requirements

Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits (1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
MIN NOM MAX UNIT
tON-MIN Minimum switch on-time 55 83 ns
tOFF-MIN Minimum switch off-time 53 73 ns
tON-MAX Maximum switch on-time 7 12 µs
tSS Internal soft-start time 3 4.5 6 ms

(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

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7.7 System Characteristics

The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25℃ only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = –40℃ to 150℃. These specifications are not ensured by production
testing.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Operating input voltage range 4.2 60 V
Adjustable output voltage
VOUT PFM operation –1.5% 2.5%
regulation (1)
Input supply current when in VIN = 24 V, VOUT = 3.3 V, IOUT = 0 A,
ISUPPLY 26 µA
regulation RFBT = 1 MΩ, PFM variant
DMAX Maximum switch duty cycle (2) 98%
FB pin voltage required to trip short-
VHC 0.4 V
circuit hiccup mode
Time between current-limit hiccup
tHC 94 ms
burst
tD Switch voltage dead time 2 ns
TSD Thermal shutdown temperature Shutdown temperature 170 °C
TSD Thermal shutdown temperature Recovery temperature 158 °C

(1) Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to 0.6A
(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN =
1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).

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7.8 Typical Characteristics

Unless otherwise specified the following conditions apply: TA = 25°C. VIN = 24 V.

32
10
31
30 9

Shutdown Current (µA)

29
Quiescent Current (µA)

8
28
27 7
26 6
25
5
24
23 4
22 25C
3 150C
21 -40C
20 2
5 10 15 20 25 30 35 40 45 50 55 60 5 10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V) Input Voltage (V) Shut
LMR3
VFB = 1 V EN = 0 V

Figure 1. Non-Switching Input Supply Current Figure 2. Shutdown Supply Current

1.5 1

1.3 0.8
Current (A)

0.6
Current (A)

1.1

0.9 0.4

0.7 0.2

0.5 0
-40 0 40 80 120 150 -40 0 40 80 120 150
Temperatuer (°C) Temperature (°C) ls-c
hs-c
VIN = 24 V VIN = 24 V

Figure 3. High Side Current Limit Figure 4. Low Side Current Limit

1.02 400
1.016
350
Peak Inductor Currente (mA)

1.012
1.008
300
Voltage (V)

1.004
1 250
0.996
200
0.992
0.988 25C
150
0.984 150C
-40C
0.98 100
-40 0 40 80 120 150 5 10 15 20 25 30 35 40 45 50 55 60
Temperature (°C) vref
Input Voltage (V) LMR3
IOUT = 0 A VOUT = 3.3 V
ƒSW = 1000 kHz

Figure 5. Reference Voltage Drift Figure 6. IPEAK-MIN

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8 Detailed Description

8.1 Overview
The LMR36006 is a synchronous peak-current-mode buck regulator designed for a wide variety of industrial
applications. The regulator automatically switches modes between PFM and PWM depending on load. At heavy
loads, the device operates in PWM at a constant switching frequency. At light loads the mode changes to PFM,
with diode emulation allowing DCM. This reduces the input supply current and keeps efficiency high. The device
features internal loop compensation which reduces design time and requires fewer external components than
externally compensated regulators.
The LMR36006 is designed with a flip-chip or HotRod™ technology, greatly reducing the parasitic inductance of
pins. In addition, the layout of the device allows for reduction in the radiated noise generated by the switching
action through partial cancellation of the current generated magnetic field. As a result the switch-node waveform
exhibits less overshoot and ringing.

2V/div
50ns/div
BW:500MHz

Figure 7. Switch Node Waveform

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8.2 Functional Block Diagram

VCC VIN

INT. REG.
OSCILLATOR
BIAS BOOT
ENABLE
EN LOGIC
HS CURRENT
SENSE

1.0V
Reference

ERROR PWM
AMPLIFIER COMP.
+ CONTROL
- LOGIC DRIVER SW
+
FB -

LS CURRENT
PG PFM MODE
CONTROL
SENSE

POWER GOOD
CONTROL

AGND PGND
8.3 Feature Description
8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR36006 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. Output voltage excursions
lasting less than tPG do not trip the power-good flag. Power-good operation can best be understood by reference
to Figure 8 and Figure 9. Note that during initial power-up a delay of about 4 ms (typical) is inserted from the time
that EN is asserted to the time that the power-good flag goes high. This delay only occurs during start-up and is
not encountered during normal operation of the power-good function.
The power-good output consists of an open drain NMOS; requiring an external pullup resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT, through an appropriate resistor, as desired. If this function
is not needed, the PG pin must be grounded. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into this pin to ≤ 4
mA.

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Feature Description (continued)

VOUT

VPG-HIGH_UP (107%)
VPG-HIGH-DN (105%)

VPG-LOW-UP (95%)

VPG-LOW-DN (93%)

PG

High = Power Good

Low = Fault

Figure 8. Static Power-Good Operation

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Feature Description (continued)

Glitches do not cause false operation nor reset timer

VOUT

VPG-LOW-UP (95%)
VPG-LOW-DN (93%)

<tPG

PG

tPG tPG tPG

Figure 9. Power-Good-Timing Behavior

8.3.2 Enable and Start-up

Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO (see the section). Applying a voltage of ≥ VEN-
VCC-H causes the device to enter standby mode, powering the internal VCC, but not producing an output voltage.
Increasing the EN voltage to VEN-OUT-H (VEN-H in Figure 10) fully enables the device, allowing it to enter start-up
mode and beginning the soft-start period. When the EN input is brought below VEN-OUT-H (VEN-H in Figure 10) by
VEN-OUT-HYS (VEN-HYS in Figure 10), the regulator stops running and enters standby mode. Further decrease in the
EN voltage to below VEN-VCC-L completely shuts down the device. This behavior is shown in Figure 10. The EN
input may be connected directly to VIN if this feature is not needed. This input must not be allowed to float. The
values for the various EN thresholds can be found in the Electrical CharacteristicsElectrical Characteristics table.
The LMR36006 utilizes a reference-based soft start that prevents output voltage overshoots and large inrush
currents as the regulator is starting up. A typical start-up waveform is shown in Figure 11 along with typical
timings. The rise time of the output voltage is about 4 ms.

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Feature Description (continued)

EN

VEN-H
VEN-H ± VEN-HYS

VEN-VCC-H
VEN-VCC-L

VCC

5V

VOUT

VOUT

Figure 10. Precision Enable Behavior

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Feature Description (continued)

Figure 11. Typical Start-up Behavior

VIN = 24 V, VOUT = 3.3 V, IOUT = 0.6 A

8.3.3 Current Limit and Short Circuit

The LMR36006 incorporates valley current limit for normal overloads and for short-circuit protection. In addition
the high-side power MOSFET is protected from excessive current by a peak current limit circuit. Cycle-by-cycle
current limit is used for overloads, while hiccup mode is used for short circuits. Finally, a zero current detector is
used on the low-side power MOSFET to implement diode emulation mode (DEM) at light loads (see Glossary).
During overloads the low-side current limit, ILIMIT, determines the maximum load current that the LMR36006 can
supply. When the low-side switch turns on, the inductor current begins to ramp down. If the current does not fall
below ILIMIT before the next turnon cycle, then that cycle is skipped, and the low-side MOSFET is left on until the
current falls below ILIMIT. This is somewhat different than the more typical peak current limit and results in
Equation 1 for the maximum load current.
VIN VOUT VOUT
IOUT max
ILIMIT ˜
2 ˜ fSW ˜ L VIN
where
• fSW = switching frequency
• L = inductor value (1)
If, during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters
into hiccup mode. In this mode the device stops switching for tHC or about 94 ms, and then goes through a
normal re-start with soft start. If the short-circuit condition remains, the device runs in current limit for about 20
ms (typical) and then shuts down again. This cycle repeats, as shown in Figure 12 as long as the short-circuit
condition persists. This mode of operation helps to reduce the temperature rise of the device during a hard short
on the output. Of course the output current is greatly reduced during hiccup mode. Once the output short is
removed and the hiccup delay is passed, the output voltage recovers normally as shown in Figure 12.
The high-side-current limit trips when the peak inductor current reaches ISC. This is a cycle-by-cycle current limit
and does not produce any frequency or load current fold back. It is meant to protect the high-side MOSFET from
excessive current. Under some conditions, such as high input voltages, this current limit may trip before the low-
side protection. Under this condition, ISC determines the maximum output current. Note that ISC varies with duty
cycle.

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Feature Description (continued)

Figure 12. Short-Circuit Transient and Recovery

8.3.4 Undervoltage Lockout and Thermal Shutdown

The LMR36006 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC pin).
When VCC reaches 3.8 V (typ.), the device receives the EN signal and starts switching. When VCC falls below
3.3 V (typ.), the device shuts down, regardless of EN status. Because the LDO is in dropout during these
transitions, the previously mentioned values roughly represent the input voltage levels during the transitions.
Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction
temperature reaches about 170°C, the device shuts down; re-start occurs when the temperature falls to about
158°C .

8.4 Device Functional Modes

8.4.1 Auto Mode
In auto mode the device moves between PWM and PFM as the load changes. At light loads the regulator
operates in PFM. At higher loads the mode changes to PWM.
In PWM the regulator operates as a constant frequency, current mode, full synchronous converter using PWM to
regulate the output voltage. While operating in this mode the output voltage is regulated by switching at a
constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line
and load regulation and low output voltage ripple.
In PFM the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The
duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The frequency of these
bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency (see
Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current required
to regulate the output voltage at small loads. This trades off very good light-load efficiency for larger output
voltage ripple and variable switching frequency. Also, a small increase in output voltage occurs at light loads. The
actual switching frequency and output voltage ripple depends on the input voltage, output voltage, and load.
Typical switching waveforms in PFM and PWM are shown in Figure 13 and Figure 14. See the Application
Curves for output voltage variation with load in auto mode.

Figure 13. Typical PFM Switching Waveforms Figure 14. Typical PWM Switching Waveforms
VIN = 24 V, VOUT = 5 V, IOUT = 30 mA VIN = 24 V, VOUT = 5 V, IOUT = 600 mA, ƒS = 1000 kHz

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Device Functional Modes (continued)

8.4.2 Dropout
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage is
reduced to near the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value.
Beyond this point the switching may become erratic and/or the output voltage falls out of regulation. To avoid this
problem the LMR36006 automatically reduces the switching frequency to increase the effective duty cycle and
maintain regulation. In this data sheet the dropout voltage is defined as the difference between the input and
output voltage when the output has dropped by 1% of its nominal value. Under this condition the switching
frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4 V short circuit detection
threshold is not activated when in dropout mode. Typical dropout characteristics can be found in Figure 15 and
Figure 16.

6 1.2E+6
IOUT = 1.5 mA 1.1E+6
IOUT = 300 mA
5.5 IOUT = 600 mA 1E+6
9E+5
Output Voltage (V)

5 8E+5

Frequency (Hz)
7E+5
4.5 6E+5
5E+5
4 4E+5
3E+5
3.5 2E+5
IOUT = 300 mA
1E+5 IOUT = 600 mA
3 0
4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6 6.1
Input Voltage (V) D003
Input Voltage (V) LMR3
Figure 15. Overall Dropout Characteristic Figure 16. Typical ƒSW vs Output Current
VOUT = 5 V ƒSW = 1000 kHz

8.4.3 Minimum Switch On-Time

Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking times
associated with the control circuits. This imposes a minimum switch duty cycle and therefore a minimum
conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend
the minimum controllable duty cycle, the LMR36006 automatically reduces the switching frequency when the
minimum on-time limit is reached. In this way the converter can regulate the lowest programmable output voltage
at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage, before
frequency foldback occurs is found in Equation 2. As the input voltage is increased, the switch on-time (duty
cycle) reduces to regulate the output voltage. When the on-time reaches the limit, the switching frequency drops,
while the on-time remains fixed.
VOUT
VIN d
t ON ˜ fSW (2)

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Device Functional Modes (continued)

2.4E+6
2.2E+6
2E+6

Switching Frequency (Hz)

1.8E+6
1.6E+6
1.4E+6
1.2E+6
1E+6
8E+5
6E+5
4E+5
IOUT = 300 mA
2E+5 IOUT = 600 mA
0
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V) LMR3

Figure 17. Switching Frequency vs Input Voltage

VOUT = 3.3 V

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMR36006 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum output current of 0.6 A. The following design procedure can be used to select
components for the LMR36006. Alternately, the WEBENCH® Design Tool may be used to generate a complete
design. This tool utilizes an iterative design procedure and has access to a comprehensive database of
components. This allows the tool to create an optimized design and allows the user to experiment with various
options.

NOTE
All of the capacitance values given in the following application information refer to effective
values; unless otherwise stated. The effective value is defined as the actual capacitance
under DC bias and temperature; not the rated or nameplate values. Use high-quality, low-
ESR, ceramic capacitors with an X7R or better dielectric throughout. All high value
ceramic capacitors have a large voltage coefficient in addition to normal tolerances and
temperature effects. Under DC bias the capacitance drops considerably. Large case sizes
and/or higher voltage ratings are better in this regard. To help mitigate these effects,
multiple capacitors can be used in parallel to bring the minimum effective capacitance up
to the required value. This can also ease the RMS current requirements on a single
capacitor. A careful study of bias and temperature variation of any capacitor bank should
be made in order to ensure that the minimum value of effective capacitance is provided.

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9.2 Typical Application

Figure 18 shows a typical application circuit for the LMR36006. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick start guide, Table 1 provides typical
component values for a range of the most common output voltages.
L
VOUT
VIN VIN SW

CIN CHF1 CHF2 VIN

CBOOT
4.7 µF 220 nF 220 nF BOOT COUT
EN
VPU 0.1 µF
LMR36006
100 NŸ
CFF RFBT

PG 100 NŸ

VCC FB

CVCC PGND PGND AGND RFBB

1 µF

Figure 18. Example Applications Circuit

Table 1. Typical External Component Values

Nominal COUT Minimum COUT
ƒSW
VOUT (V) L (µH) (rated (rated RFBT (Ω) RFBB (Ω) CIN CFF
(kHz)
capacitance) (1) capacitance) (2)
1000 3.3 10 2 × 15 µF 1 × 15 µF 100 k 43.2 k 4.7 µF + 2 × 220 nF 20 pF
2100 3.3 6.8 2 × 15 µF 1 × 15 µF 100 k 43.2 k 4.7 µF + 2 × 220 nF 20 pF
1000 5 15 2 × 15 µF 1 × 15 µF 100 k 24.9 k 4.7 µF + 2 × 220 nF 20 pF
2100 5 10 2 × 15 µF 1 × 15 µF 100 k 24.9 k 4.7 µF + 2 × 220 nF 20 pF
1000 12 33 2 × 15 µF 1 × 15µF 100 k 9.09 k 4.7 µF + 2 × 220 nF 20 pF
2100 12 22 2 × 15 µF 1 × 15 µF 100 k 9.09 k 4.7 µF + 2 × 220 nF 20 pF

(1) Optimized for superior load transient performance from 0 to 100% rated load.
(2) Optimized for size constrained end applications.

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9.2.1 Design 1: Low Power 24-V, 600-mA PFM Converter

9.2.1.1 Design Requirements

Example requirements for a typical 5-V or 3.3-V application. The input voltages are here for illustration purposes
only. See Specifications for the operating input voltage range.

Table 2. Detailed Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage 12 V to 24 V steady state, 4.2 V to 60-V transients
Output voltage 5 V/3.3 V
Maximum output current 0 A to 0.6 A
Switching frequency 1000 kHz
Current consumption at 0-A load Critical: Need to ensure low current consumption to reduce battery drain
Switching frequency at 0-A load Not critical: Need fixed frequency operation at high load only

Table 3. List of Components for Design 1

VOUT FREQUENCY RFBB COUT L U1
5V 1000 kHz 24.9 kΩ 1 × 15 µF 10 µH, 45 mΩ LMR36006BRNX
3.3 V 1000 KHz 43.3 kΩ 1 × 15 µF 10 µH, 45 mΩ LMR36006BRNX

9.2.1.2 Detailed Design Procedure

The following design procedure applies to Figure 18 and Table 2.

9.2.1.2.1 Custom Design With WEBENCH Tools

Click here to create a custom design using the LMR36006 device and the WEBENCH Power Designer.
1. Start by entering the input voltage, output voltage, and output current requirements
2. Optimize the design for key performance such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases the following features are available with this tool:
• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to help understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print full design reports in PDF.
Get more information at ti.com

9.2.1.2.2 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence a
more compact design. For this example 1 MHz is used.

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9.2.1.2.3 Setting the Output Voltage

The output voltage of LMR36006 is externally adjustable using a resistor divider network. The range of
recommended output voltage is found in the table. The divider network is comprised of RFBT and RFBB, and
closes the loop between the output voltage and the converter. The converter regulates the output voltage by
holding the voltage on the FB pin equal to the internal reference voltage, VREF. The resistance of the divider is a
compromise between excessive noise pick-up and excessive loading of the output. Smaller values of resistance
reduce noise sensitivity but also reduce the light-load efficiency. The recommended value for RFBT is 100 kΩ;
with a maximum value of 1 MΩ. If a 1 MΩ is selected for RFBT, then a feed-forward capacitor must be used
across this resistor to provide adequate loop phase margin (see CFF Selection). Once RFBT is selected, is used to
select RFBB. VREF is nominally 1 V.
RFBT
RFBB
ª VOUT º
« 1»
¬ VREF ¼ (3)
For this 5-V example values are: RFBT = 100 kΩ and RFBB = 24.9 kΩ.

9.2.1.2.4 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the maximum
output current. Experience shows that the best value for inductor ripple current is 30% of the maximum load
current. Note that when selecting the ripple current for applications with much smaller maximum load than the
maximum available from the device, use the the maximum device current. Equation 4 can be used to determine
the value of inductance. The constant K is the percentage of inductor current ripple. For this example we choose
K = 0.4 and find an inductance L = 16.4 µH; we select the standard value of 10 µH.
VIN VOUT V
L ˜ OUT
fSW ˜ K ˜ IOUT max VIN (4)
Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, ISC.
This ensures that the inductor does not saturate even during a short circuit on the output. When the inductor core
material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly.
Although the valley current limit, ILIMIT, is designed to reduce the risk of current runaway, a saturated inductor can
cause the current to rise to high values very rapidly. This may lead to component damage; do not allow the
inductor to saturate! Inductors with a ferrite core material have very hard saturation characteristics, but usually
have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some
relaxation in the current rating of the inductor. However, they have more core losses at frequencies above about
1 MHz. In any case, the inductor saturation current must not be less than the device low-side current limit, ILIMIT.
In order to avoid sub-harmonic oscillation, the inductance value must not be less than that given in Equation 5:
VOUT
LMIN t 0.28 ˜
fSW (5)

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9.2.1.2.5 Output Capacitor Selection

The value of the output capacitor, and its ESR, determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements, rather than the
output voltage ripple. Equation 6 can be used to estimate a lower bound on the total output capacitance, and an
upper bound on the ESR, required to meet a specified load transient.
'IOUT ª K2 º
COUT t ˜«1 D ˜ 1 K ˜ 2 D»
fSW ˜ 'VOUT ˜ K ¬« 12 ¼»

2 K ˜ 'VOUT
ESR d
ª K2 § 1 ·º
2 ˜ 'IOUT «1 K ˜ ¨¨1 ¸¸»
¬« 12 © (1 D) ¹¼»

VOUT
D
VIN
where
• ΔVOUT = output voltage transient
• ΔIOUT = output current transient
• K = Ripple factor from Inductor Selection (6)
Once the output capacitor and ESR have been calculated, Equation 7 can be used to check the output voltage
ripple.
1
Vr # 'IL ˜ ESR 2 2
8 ˜ fSW ˜ COUT
where
• Vr = peak-to-peak output voltage ripple (7)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
In practice the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help to reduce high frequency noise. Small case size ceramic capacitors in the range of
1 nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.
Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever
is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well
as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load
and loop stability must be performed.

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9.2.1.2.6 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum ceramic capacitance of 4.7-µF is required on
the input of the LMR36006. This must be rated for at least the maximum input voltage that the application
requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input
voltage ripple and/or maintain the input voltage during load transients. In addition a small case size 220-nF
ceramic capacitor must be used at the input, as close a possible to the regulator. This provides a high frequency
bypass for the control circuits internal to the device. For this example a 4.7-µF, 100-V, X7R (or better) ceramic
capacitor is chosen. The 220 nF must also be rated at 100-V with an X7R dielectric. The VQFN package
provides two input voltage pins and two power ground pins on opposite sides of the package. This allows the
input capacitors to be split, and placed optimally with respect to the internal power MOSFETs, thus improving the
effectiveness of the input bypassing. In this example, place two 220-nF ceramic capacitors at each VIN-PGND
location.
It is often desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially
true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR of this
capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.
Most of the input switching current passes through the ceramic input capacitor(s). The approximate RMS value of
this current can be calculated from Equation 8 and should be checked against the manufacturers' maximum
ratings.
I
IRMS # OUT
2 (8)

9.2.1.2.7 CBOOT
The LMR36006 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This capacitor
stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of
100 nF and at least 16 V is required.

9.2.1.2.8 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general this output
must not be loaded with any external circuitry. However, this output can be used to supply the pullup for the
power-good function (see Power-Good Flag Output). A value in the range of 10 kΩ to 100 kΩ is a good choice in
this case. The nominal output voltage on VCC is 5 V.

9.2.1.2.9 CFF Selection

In some cases a feed-forward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help to mitigate this effect. Equation 9 can be used to estimate the value of CFF.
The value found with Equation 9 is a starting point; use lower values to determine if any advantage is gained by
the use of a CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters
with Feed-forward Capacitor Application Report is helpful when experimenting with a feed-forward capacitor.
VOUT ˜ COUT
CFF
VREF
120 ˜ RFBT ˜
VOUT (9)

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9.2.1.2.9.1 External UVLO

In some cases an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in Figure 19 can be used. The input voltage at which the device turns
on is designated VON; while the turnoff voltage is VOFF. First a value for RENB is chosen in the range of 10 kΩ to
100 kΩ and then Equation 10 is used to calculate RENT and VOFF.
VIN

RENT

EN

RENB

Figure 19. Set-up for External UVLO Application

§ VON ·
RENT ¨¨ 1¸¸ ˜ RENB
© VEN H ¹

§ VEN HYS ·
VOFF VON ˜ ¨¨1 ¸¸
© VEN ¹
where
• VON = VIN turnon voltage
• VOFF = VIN turnoff voltage (10)

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9.2.1.2.10 Maximum Ambient Temperature

As with any power conversion device, the LMR36006 dissipates internal power while operating. The effect of this
power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss and the effective thermal resistance,
RθJA of the device and PCB combination. The maximum internal die temperature for the LMR36006 must be
limited to 150°C. This establishes a limit on the maximum device power dissipation and therefore the load
current. Equation 11 shows the relationships between the important parameters. It is easy to see that larger
ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The converter
efficiency can be estimated by using the curves provided in this data sheet. If the desired operating conditions
cannot be found in one of the curves, then interpolation can be used to estimate the efficiency. Alternatively, the
EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly.
The correct value of RθJA is more difficult to estimate. As stated in Semiconductor and IC Package Thermal
Metrics, the values given in Thermal Information are not valid for design purposes and must not be used to
estimate the thermal performance of the application. The values reported in that table were measured under a
specific set of conditions that are rarely obtained in an actual application.
TJ TA K 1
IOUT MAX
˜ ˜
R TJA 1 K VOUT
where
• η = Efficiency (11)
The effective RθJA is a critical parameter and depends on many factors such as power dissipation, air
temperature/flow, PCB area, copper heat-sink area, number of thermal vias under the package, and adjacent
component placement; to mention just a few. Due to the ultra-miniature size of the VQFN (RNX) package, a DAP
is not available. This means that this package exhibits a somewhat greater RθJA. A typical example of RθJA vs
copper board area can be found in Figure 20. Note that the data given in this graph is for illustration purposes
only, and the actual performance in any given application depends on all of the factors mentioned above.
70

65

60
JA (ƒC/w)

55
R

50

45

RNX, 4L
40
0 10 20 30 40 50 60 70
Copper Area (cm2) C005

Figure 20. RθJA versus Copper Board Area for the VQFN (RNX) Package

Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given application
environment:
• Thermal Design by Insight not Hindsight Application Report
• Semiconductor and IC Package Thermal Metrics Application Report
• Thermal Design Made Simple with LM43603 and LM43602 Application Report
• Using New Thermal Metrics Application Report

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9.2.2 Application Curves

Unless otherwise specified the following conditions apply: VIN = 24 V, TA = 25°C. The circuit is shown in
Figure 18, with the appropriate BOM from Table 3.

100% 100%
90% 90%
80% 80%
70% 70%
60% 60%

Efficiency
Efficiency

50% 50%
40% 40%
30% 30%
8 VIN 6 VIN
20% 12 VIN 20% 12 VIN
10% 24 VIN 10% 24 VIN
48 VIN 48 VIN
0 0
0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 1 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 1
Output Current (A) LMR3
Output Current (A) LMR3
VOUT = 5 V 1000 kHz VOUT = 3.3 V 1000 kHz

Figure 21. Efficiency Figure 22. Efficiency

5.07 3.34
8 VIN 6 VIN
5.06 12 VIN 3.33 12 VIN
24 VIN 24 VIN
5.05 48 VIN 48 VIN
3.32
Output Voltage (V)

Output Voltage (V)

5.04
3.31
5.03
3.3
5.02
3.29
5.01

5 3.28

4.99 3.27
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
Output Current (A) LMR3
Ouput Current (A) LMR3
VOUT = 5 V 1000 kHz VOUT = 3.3 V 1000 kHz

Figure 23. Load Regulation Figure 24. Load Regulation

6 1.2E+6
IOUT = 1.5 mA 1.1E+6
IOUT = 300 mA
5.5 IOUT = 600 mA 1E+6
9E+5
Output Voltage (V)

5 8E+5
Frequency (Hz)

7E+5
4.5 6E+5
5E+5
4 4E+5
3E+5
3.5 2E+5
IOUT = 300 mA
1E+5 IOUT = 600 mA
3 0
4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6 6.1
Input Voltage (V) D003
Input Voltage (V) LMR3
VOUT = 5 V 1000 kHz VOUT = 5 V 1000 kHz

Figure 25. Overall Dropout Characteristic Figure 26. Frequency Dropout Characteristic

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45 400

350
40
Input Supply Current (µA)

300

Output Current (mA)

35
250

200
30

150
25
100

20 50
5 10 15 20 25 30 35 40 45 50 55 60 5 10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V) LMR3
Input Voltage (V) LMR3
VOUT = 3.3 V IOUT= 0 A RFBT= 100 kΩ VOUT = 3.3 V 1000 kHz

Figure 27. Input Supply Current Figure 28. Mode Change Thresholds

VOUT = 5 V 1000 kHz VOUT = 3.3 V 1000 kHz

Figure 29. Start-Up Waveform Figure 30. Start-Up Waveform

VOUT = 5 V 1000 kHz ILOAD= 10 mA - 0.6 A VOUT = 3.3 V 1000 kHz ILOAD= 10 mA - 0.6 A
Slew Rate = 1 µs/A Slew Rate = 1 µs/A

Figure 31. Load Transient Figure 32. Load Transient

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VIN = 13.5 V VOUT = 5 V IOUT = 1.5 A VIN = 13.5 V VOUT = 5 V IOUT = 1.5 A
Frequency Tested: 150kHz to 30 MHz Frequency Tested: 30 MHz to 108 MHz

Figure 33. Conducted EMI vs. CISPR25 Limits (Yellow: Figure 34. Conducted EMI vs. CISPR25 Limits (Yellow:
Peak Signal, Blue: Average Signal) Peak Signal, Blue: Average Signal)

VIN = 13.5 V VOUT = 5 V IOUT = 1.5 A VIN = 13.5 V VOUT = 5 V IOUT = 1.5 A
Frequency Tested: 150 kHz to 30 MHz Frequency Tested: 30 MHz to 200 MHz

Figure 35. Radiated EMI Rod vs. CISPR25 Limits Figure 36. Radiated EMI Bicon Vertical vs. CISPR25 Limits

VIN = 13.5 V VOUT = 5 V IOUT = 1.5 A VIN = 13.5 V VOUT = 5 V IOUT = 1.5 A
Frequency Tested: 30 MHz to 200 MHz Frequency Tested: 200 MHz to 1 GHz

Figure 37. Radiated EMI Bicon Horizontal vs. CISPR25 Figure 38. Radiated EMI Log Vertical vs. CISPR25 Limits
Limits

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VIN = 13.5 V VOUT = 5 V IOUT = 1.5 A VIN = 13.5 V VOUT = 5 V IOUT = 1.5 A
Frequency Tested: 200 MHz to 1 GHz Frequency Tested: 1.83 GHz to 2.5 GHz

Figure 39. Radiated EMI Log Horizontal vs. CISPR25 Limits Figure 40. Radiated EMI Horn Vertical vs. CISPR25 Limits

83H9652
IN+ VIN
FB1
+
CD = 100 uF

IN± GND
CF1 = 4.7 uF CF2 = 0.1 uF
CF3 = 4.7 uF

VIN = 13.5 V VOUT = 5 V IOUT = 1.5 A

Frequency Tested: 1.8 GHz to 2.5 GHz
Figure 42. Recommended Input EMI Filter
Figure 41. Radiated EMI Horn Horizontal vs. CISPR25
Limits

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9.2.3 Design 2: High Density 24-V, 600-mA PFM Converter

9.2.3.1 Design Requirements

Example requirements for a typical 5-V or 3.3-V application. The input voltages are here for illustration purposes
only. See Specifications for minimum operating input voltage.

Table 4. Detailed Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage 18-V to 24-V steady state, 4.2-V to 60-V transients
Output voltage 3.3 V/5 V
Maximum output current 0 A to 600 mA
Switching frequency 2100 kHz
Current consumption at 0-A load Critical: Need to ensure low current consumption to reduce battery drain
Switching frequency at 0-A load Not critical: Need fixed frequency operation at high load only

Table 5. List of Components for Design 2

VOUT FREQUENCY RFBB COUT L U1
5V 2100 KHz 24.9 kΩ 1 × 15 µF 10 µH, 21 mΩ LMR36006CRNXR
3.3 V 2100 kHz 43.2 kΩ 1 × 15 µF 7.8 µH, 13.6 mΩ LMR36006CRNXR

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9.2.3.2 Application Curves

Unless otherwise specified the following conditions apply: VIN = 24 V, TA = 25°C. The circuit is shown in
Figure 18, with the appropriate BOM from Table 5.

100% 100%
90% 90%
80% 80%
70% 70%
60% 60%

Efficiency
Efficiency

50% 50%
40% 40%
30% 30%
8 VIN 6 VIN
20% 12 VIN 20% 12 VIN
10% 24 VIN 10% 24 VIN
48 VIN 48 VIN
0 0
0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 1 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 1
Output Current (A) LMR3
Output Current (A) LMR3
VOUT = 5 V 2100 kHz VOUT = 3.3 V 2100 kHz

Figure 43. Efficiency Figure 44. Efficiency

5.04 3.34
8 VIN 6 VIN
5.035 12 VIN 12 VIN
3.33
24 VIN 24 VIN
5.03 48 VIN 48 VIN
3.32
Output Voltage (V)

Output Voltage (V)

5.025
3.31
5.02
3.3
5.015
3.29
5.01

5.005 3.28

5 3.27
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
Output Current (A) LMR3
Output Current (A) LMR3
VOUT = 5 V 2100 kHz VOUT = 3.3 V 2100 kHz

Figure 45. Load Regulation Figure 46. Load Regulation

6 2.4E+6
2.2E+6
5 2E+6
Switching Frequency (Hz)

1.8E+6
Output Voltage (V)

4 1.6E+6
1.4E+6
3 1.2E+6
1E+6
2 8E+5
6E+5
1 IOUT = 1.5 mA 4E+5
IOUT = 300 mA IOUT = 300 mA
IOUT = 600 mA 2E+5 IOUT = 600 mA
0 0
0 5 10 15 20 25 30 35 40 45 50 55 60 10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V) LMR3
Input Voltage (V) LMR3
VOUT = 5 V 2100 kHz VOUT = 5 V 2100 kHz

Figure 47. Line Regulation Figure 48. Switching Frequency vs Input Voltage

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5.6

5.4

5.2
Output Voltage (V)

4.8

4.6

4.4
IOUT = 1.5 mA
4.2 IOUT = 300 mA
IOUT = 600 mA
4 VOUT = 5 V 2100 kHz
4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6
Input Voltage (V) LMR3
VOUT = 5 V 2100 kHz

Figure 49. Overall Dropout Characteristic Figure 50. Start-Up Waveform

VOUT = 3.3 V 2100 kHz VOUT = 5 V 2100 kHz ILOAD= 10 mA - 0.3 A

Slew Rate = 1
Figure 51. Start-Up Waveform µs/A

Figure 52. Load Transient

VOUT = 3.3 V 2100 kHz ILOAD= 10 mA - 0.3 A VOUT = 5 V 2100 ILOAD= 10 mA - 0.6 A
Slew Rate = kHz
1 µs/A Slew Rate = 1
µs/A
Figure 53. Load Transient
Figure 54. Load Transient

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VOUT = 3.3 V 2100 kHz ILOAD= 10 mA - 0.6 A

Slew Rate = 1 µs/A

Figure 55. Load Transient

9.3 What to Do and What Not to Do

• Don't: Exceed the Absolute Maximum Ratings.
• Don't: Exceed the ESD Ratings.
• Don't: Allow the EN input to float.
• Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
• Don't: Use the thermal data given in the Thermal Information table to design your application.
• Do: Follow all the guidelines and/or suggestions found in this data sheet before committing the design to
production. TI application engineers are ready to help critique your design and PCB layout to help make your
project a success (see Community Resources).

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10 Power Supply Recommendations

The characteristics of the input supply must be compatible with the Specifications found in this data sheet. In
addition, the input supply must be capable of delivering the required input current to the loaded regulator. The
average input current can be estimated with Equation 12.
VOUT ˜ IOUT
IIN
VIN ˜ K
where
• η is the efficiency (12)
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip may cause the
regulator to momentarily shutdown and/or reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator and/or use an aluminum or tantalum input capacitor in parallel with
the ceramics. The moderate ESR of these types of capacitors help to damp the input resonant circuit and reduce
any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help to
hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success With Conducted EMI From DCDC Converters User's Guide provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow may damage the device.

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11 Layout

11.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout
can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad
PCB layout can mean the difference between a robust design and one that cannot be mass produced.
Furthermore, to a great extent the EMI performance of the regulator is dependent on the PCB layout. In a buck
converter the most critical PCB feature is the loop formed by the input capacitor(s) and power ground, as shown
in Figure 56. This loop carries large transient currents that can cause large transient voltages when reacting with
the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because
of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the
parasitic inductance. Figure 57 shows a recommended layout for the critical components of the LMR36006.
1. Place the input capacitor(s) as close as possible to the VIN and GND terminals. VIN and GND pins are
adjacent, simplifying the input capacitor placement.
2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and
routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the BOOT
and SW pins. Route the SW pin to the N/C pin and used to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act as
a heat dissipation path.
6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
7. Provide enough PCB area for proper heat-sinking. As stated in the Maximum Ambient Temperature section,
enough copper area must be used to ensure a low RθJA, commensurate with the maximum load current and
ambient temperature. The top and bottom PCB layers must be made with two ounce copper; and no less
than one ounce. If the PCB design uses multiple copper layers (recommended), these thermal vias can also
be connected to the inner layer heat-spreading ground planes.
8. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time the total area of this node must be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies Application Report
• Simple Switcher PCB Layout Guidelines Application Report
• Construction Your Power Supply- Layout Considerations Seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report

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Layout Guidelines (continued)

VIN

CIN SW

GND

Figure 56. Current Loops with Fast Edges

11.1.1 Ground and Thermal Considerations

As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control circuitry.
Connect the AGND and PGND pins to the ground planes using vias next to the bypass capacitors. PGND pins
are connected directly to the source of the low side MOSFET switch and also connected directly to the grounds
of the input and output capacitors. The PGND net contains noise at the switching frequency and may bounce
due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one side of
the ground planes. The other side of the ground plane contains much less noise; use for sensitive routes.
Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat
dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1
oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current
conduction impedance, proper shielding and lower thermal resistance.

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11.2 Layout Example

VOUT VOUT
INDUCTOR

COUT COUT COUT COUT

GND GND

CIN CIN
CHF CHF
1 12 11
2 10

VIN 3 9 EN VIN
CBOO
T

4 8 PGOOD

5 6 7

CVCC RFBB RFBT

GND
GND
HEATSINK
HEATSINK

INNER GND PLANE

Top Trace/Plane

Inner GND Plane

VIN Strap on Inner Layer

Top
VIA to Signal Layer Inner GND Plane
VIN Strap and
VIA to GND Planes GND Plane
Signal
traces and
VIA to VIN Strap
GND Plane
Trace on Signal Layer
Figure 57. Example Layout

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support
• Two-Stage Power Supply Reference Design for Field Transmitters
• Wide Vin Power Supply Reference Design for Space-Constrained Industrial Sensors
• Automotive ADAS camera power supply reference design optimized for solution size and low noise
• How a DC/DC converter package and pinout design can enhance automotive EMI performance
• Introduction to Buck Converters Features: UVLO, Enable, Soft Start, Power Good
• Introduction to Buck Converters: Understanding Mode Transitions
• Introduction to Buck Converters: Minimum On-time and Minimum Off-time Operation
• Introduction to Buck Converters: Understanding Quiescent Current Specifications
• Trade-offs between thermal performance and small solution size with DC/DC converters
• Reduce EMI and shrink solution size with Hot Rod packaging

12.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR36006 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Designing High-Performance, Low-EMI Automotive Power Supplies Application Report
• Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report
• Texas Instruments, Construction Your Power Supply- Layout Considerations Application Report
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
• Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

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12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks
HotRod, Hotrod, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

40 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

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 PACKAGE OPTION ADDENDUM

www.ti.com 3-Oct-2019

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

LMR36006BRNXR ACTIVE VQFN-HR RNX 12 3000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 150 NH06B
& no Sb/Br)
LMR36006BRNXT ACTIVE VQFN-HR RNX 12 250 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 150 NH06B
& no Sb/Br)
LMR36006CRNXR ACTIVE VQFN-HR RNX 12 3000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 150 NH06C
& no Sb/Br)
LMR36006CRNXT ACTIVE VQFN-HR RNX 12 250 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 150 NH06C
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 3-Oct-2019

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LMR36006 :

• Automotive: LMR36006-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Oct-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMR36006BRNXR VQFN- RNX 12 3000 180.0 8.4 2.3 3.2 1.0 4.0 8.0 Q1
HR
LMR36006BRNXT VQFN- RNX 12 250 180.0 8.4 2.3 3.2 1.0 4.0 8.0 Q1
HR
LMR36006CRNXR VQFN- RNX 12 3000 180.0 8.4 2.3 3.2 1.0 4.0 8.0 Q1
HR
LMR36006CRNXT VQFN- RNX 12 250 180.0 8.4 2.3 3.2 1.0 4.0 8.0 Q1
HR

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Oct-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMR36006BRNXR VQFN-HR RNX 12 3000 195.0 200.0 45.0
LMR36006BRNXT VQFN-HR RNX 12 250 195.0 200.0 45.0
LMR36006CRNXR VQFN-HR RNX 12 3000 195.0 200.0 45.0
LMR36006CRNXT VQFN-HR RNX 12 250 195.0 200.0 45.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RNX 12 VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
2 x 3 mm, 0.5 mm pitch

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224286/A
 PACKAGE OUTLINE
RNX0012B SCALE 4.500
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2.1
B A
1.9

PIN 1 INDEX AREA

3.1
2.9 0.1 MIN

(0.05)

SECTION A-A
A-A 40.000

TYPICAL

0.9
C
0.8

SEATING PLANE
0.05
0.00 0.08 C
1

SYMM
(0.2) TYP
5 7

4X 0.5
4 8

2X
0.675
PKG

2X
2X 1.725
1.125 1.525
0.65
A 11
A
1

12
PIN 1 ID 0.3
0.3 11X
0.2
0.2
0.1 C B A
0.5
11X 0.05 C
0.3

4223969/C 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RNX0012B VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(0.25)
12

11X (0.6)
1 2X (0.65)
11

11X
(0.25) (1.825)
2X
(1.125)
(0.788)

PKG

2X
(0.675) 4X (0.5)

8 (1.4)
4

(R0.05) TYP

5 7
SYMM

(1.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:25X

0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
SOLDER MASK
METAL EDGE OPENING

EXPOSED EXPOSED
METAL SOLDER MASK METAL METAL
OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) PADS 1, 2, 10-12

SOLDER MASK DETAILS

4223969/C 10/2018
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
RNX0012B VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2X (0.25)
2X (0.812) 12
11X (0.6)
11X (0.25)
1
11

2X
EXPOSED METAL (0.65) (1.294)
2X
(1.125)

PKG

(0.282)
2X (0.675)
4X (0.5)

8 (1.4)
4

(R0.05) TYP

5 7
SYMM

(1.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

FOR PAD 12
87.7% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4223969/C 10/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
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