An over view of 8085:

Sub Topics:
1) Block diagram of 8085 microprocessor
2) 8085 system bus
3) 8085 registers
4) Timing and Control unit
5) Interrupt control unit
6) 8085 PIN DIAGRAM

1) Block diagram of 8085 microprocessor:

Fig1.1: Block Diagram of 8085 microprocessor

2) 8085 system bus:
Address Bus:
 The address bus is a group of 16 lines generally identified as A0 to A15.
 The address bus is unidirectional: bits flow in one direction-from the MPU to
peripheral devices.
 The MPU uses the address bus to perform the first function: identifying a peripheral
or a memory location.

Fig1.2: 8085 bus structure

Data Bus:
 The data bus is a group of eight lines used for data flow. These lines are bi-
directional data flow in both directions between the MPU and memory and
peripheral devices.
 The MPU uses the data bus to perform the second function: transferring binary
information.
 The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF
(28 = 256 numbers).
 The largest number that can appear on the data bus is 11111111.
Control Bus:
 The control bus carries synchronization signals and providing timing signals.
 The MPU generates specific control signals for every operation it performs. These
signals are used to identify a device type with which the MPU wants to
communicate.
3) 8085 Registers:
 The 8085 have six general-purpose registers to store 8-bit data during program
execution.
  These registers are identified as B, C, D, E, H, and L.
 They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit
operations.

Fig 1.3: 8085 Registers

Accumulator (A):
 The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
 This register is used to store 8-bit data and to perform arithmetic and logical
operations.
 The result of an operation is stored in the accumulator.
Flags:
 The ALU includes five flip-flops that are set or reset according to the result of an
operation.
 The microprocessor uses the flags for testing the data conditions. They are Zero (Z),
Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.
 The most commonly used flags are Sign, Zero, and Carry.
 The bit position for the flags in flag register is,

A) Sign Flag (S):

 After execution of any arithmetic and logical operation, if D7 of the result is 1, the
sign flag is set.
 Otherwise it is reset. D7 is reserved for indicating the sign.
 The remaining is the magnitude of number. If D7 is 1, the number will be viewed as
negative number. If D7 is 0, the number will be viewed as positive number.
B) Zero Flag (z):
  If the result of arithmetic and logical operation is zero, then zero flag is set
otherwise it is reset.
C) Auxiliary Carry Flag (AC):
 If D3 generates any carry when doing any arithmetic and logical operation, this
flag is set. Otherwise it is reset.
D) Parity Flag (P):
 If the result of arithmetic and logical operation contains even number of 1's then
this flag will be set and if it is odd number of 1's it will be reset.
E) Carry Flag (CY):
 If any arithmetic and logical operation result any carry then carry flag is set
otherwise it is reset.

iii) Arithmetic and Logic Unit (ALU):

 It is used to perform the arithmetic operations like addition, subtraction,
multiplication, division, increment and decrement and logical operations like
AND, OR and EX-OR.
 It receives the data from accumulator and registers. According to the result it set
or reset the flags.
iv) Program Counter (PC):
 This 16-bit register is used to sequencing the execution of instructions.
 It is a memory pointer. Memory locations have 16-bit addresses, and that is why
this is a 16-bit register.
 The function of the program counter is to point to the memory address of the next
instruction to be executed.
 When an opcode is being fetched, the program counter is incremented by one to
point to the next memory location.
v) Stack Pointer (Sp)
 The stack pointer is also a 16-bit register used as a memory pointer.
 It points to a memory location in R/W memory, called the stack.
 The beginning of the stack is defined by loading a 16-bit address in the stack
pointer (register).
vi) Temporary Register:
 It is used to hold the data during the arithmetic and logical operations.
vii) Instruction Register:
 When an instruction is fetched from the memory, it is loaded in the instruction
Register.
viii) Instruction Decoder:
 It gets the instruction from the instruction register and decodes the instruction.
  It identifies the instruction to be performed.
ix) Serial I/O Control:
 It has two control signals named SID and SOD for serial data transmission.

4) Timing and Control unit:

 It has three control signals ALE, RD (Active low) and WR (Active low) and three
status signals IO/M (Active low), S0 and S1.
 ALE is used for provide control signal to synchronize the components of
miroprocessor and timing for instruction to perform the operation.
 RD (Active low) and WR (Active low) are used to indicate whether the operation
is reading the data from memory or writing the data into memory respectively.
 IO/M (Active low) is used to indicate whether the operation is belongs to the
memory or peripherals.

5) Interrupt Control Unit:

 It receives hardware interrupt signals and sends an acknowledgement for receiving
the interrupt signal.
 Interrupt is nothing but signals send by an external device to the processor, to request
the processor to perform a particular task or work.
 Mainly in the microprocessor based system the interrupts are used for data transfer
between the peripheral and the microprocessor.
 The processor will check the interrupts always at the 2nd T-state of last machine
cycle.
 If there is any interrupt it accept the interrupt and send the INTA (active low) signal
to the peripheral.
 The vectored address of particular interrupt is stored in program counter.
 The processor executes an interrupt service routine (ISR) addressed in program
counter. It returned to main program by RET instruction.

Types of Interrupts:
It supports two types of interrupts.
i) Software
ii) Hardware

i) Software interrupts:
 The software interrupts are program instructions.
 These instructions are inserted at desired locations in a program.
 The 8085 has eight software interrupts from RST 0 to RST 7.
 The vector address for these interrupts can be calculated as follows.
Interrupt number * 8 = vector address
EX: - For RST 5, 5 * 8 = 40 = 28H
Vector address for interrupt RST 5 is 0028H
The Table shows the vector addresses of all interrupts.

ii) Hardware Interrupts:

 An external device initiates the hardware interrupts and placing an appropriate signal
at the interrupt pin of the processor.
 If the interrupt is accepted then the processor executes an interrupt service routine.
 The 8085 has five hardware interrupts
(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR
(1) TRAP:
 This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt
enable.
 TRAP is the highest priority and vectored interrupt.
 TRAP interrupt is edge and level triggered.
 This means hat the TRAP must go high and remain high until it is acknowledged. In
sudden power failure, it executes a ISR and send the data from main memory to
backup memory.
 The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor
receives HOLD and TRAP at the same time then HOLD is recognized first and then
TRAP is recognized).
 There are two ways to clear TRAP interrupt.
 By resetting microprocessor (External signal)
 By giving a high TRAP ACKNOWLEDGE (Internal signal)

(2) RST 7.5:

 The RST 7.5 interrupt is a maskable interrupt.
 It has the second highest priority.
 It is edge sensitive (i.e) Input goes to high and no need to maintain high state until it
is recognized.
 It is disabled by, 1.DI instruction 2.System or processor reset. 3.After reorganization
of interrupt.
 It is enabled by EI instruction.
(3) RST 6.5 and 5.5:
The RST 6.5 and RST 5.5 both are level triggered. (i.e) Input goes to high and stay high
until it recognized.
Maskable interrupt. It is disabled by, 1.DI, SIM instruction 2.System or processor
reset. 3. after reorganization of interrupt.
Enabled by EI instruction.
 The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
(4) INTR:
INTR is a maskable interrupt. It is disabled by, 1.DI, SIM instruction 2.System or
processor reset. 3. after reorganization of interrupt.
a) It is enabled by EI instruction.
b) It is non-vectored interrupt. After receiving INTA (active low) signal, it has to
supply the address of ISR.
c) It has lowest priority.
d) It is a level sensitive interrupts. ie. Input goes to high and it is necessary to
maintain high state until it recognized.

HARDWARE INTERRUPTS TABLE:

INTERRUP MASKBLE/N PR EDGE/LEV VECTORED/N
T TYPE ON IO EL ON
TRAP MASKABLE
NON MASKABLE 1RI SENSITIVE
EDGE&LEVE VECTORED
RST 7.5 MASKABLE 2 L
EDGE VECTORED
RST 6.5 MASKABLE 3 LEVEL VECTORED
RST 5.5 MASKABLE 4 LEVEL VECTORED
INTR MASKABLE 5 LEVEL NON
VECTORED
8085 PIN DIAGRAM:

 The microprocessor is a clock-driven semiconductor device consisting of electronic

logic circuits manufactured by using either a large-scale integration (LSI) or very-large-
scale integration (VLSI) technique.
 The microprocessor is capable of performing various computing functions and
making decisions to change the sequence of program execution.
 In large computers, a CPU implemented on one or more circuit boards performs these
computing functions.
 The microprocessor is in many ways similar to the CPU, but includes the logic
circuitry, including the control unit, on one chip.
 The microprocessor can be divided into three segments for the sake clarity,
arithmetic/logic unit (ALU), register array, and control unit.
8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows
i) Power supply and clock signals
ii) Address bus
iii) Multiplexed Address / Data Bus
iv) Control and status signals
v) Interrupts and externally initiated signals
vi) Direct memory access
vii) Serial I/O ports
i) Power supply and Clock frequency signals:
 Vcc + 5 volt power supply
  Vss Ground
 X1, X2: Crystal or R/C network or LC network connections to set the frequency
of internal clock generator.
 The frequency is internally divided by two. Since the basic operating timing
frequency is 3 MHz, a 6 MHz crystal is connected externally.
 CLK (output)-Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.
ii) Address Bus:
 A8 - A15 lines.
 It carries the most significant 8 bits of the memory address or the 8 bits of the I/O
address.
iii) Multiplexed Address / Data Bus:
 AD0 - AD7 (input/output; 3-state)
 These multiplexed set of lines used to carry the lower order 8 bit address as well
as data bus.
 During the opcode fetch operation, in the first clock cycle, the lines deliver the
lower order address A0 - A7.
 In the subsequent IO / memory, read / write clock cycle the lines are used as data
bus.The CPU may read or write out data through these lines.

Fig (a) - Pin Diagram of 8085 & Fig (b) - logical schematic of Pin diagram.
iv) Control and Status signals:
 ALE (output) - Address Latch Enable.
 This signal helps to capture the lower order address presented on the multiplexed
address / data bus.
 RD (output 3-state, active low) - Read memory or IO device.
 This indicates that the selected memory location or I/O device is to be read and
that the data bus is ready for accepting data from the memory or I/O device.
 WR (output 3-state, active low) - Write memory or IO device.
 This indicates that the data on the data bus is to be written into the selected
memory location or I/O device.
 IO/M (output) - Select memory or an IO device.
 This status signal indicates that the read / write operation relates to whether the
memory or I/O device. It goes high to indicate an I/O operation. It goes low for memory
operations.
 Status Signals:
 It is used to know the type of current operation of the microprocessor.

v) Interrupts and externally initiated operations:

 They are the signals initiated by an external device to request the microprocessor
to do a particular task or work.
  On receipt of an interrupt, the microprocessor acknowledges the interrupt by the
active low INTA (Interrupt Acknowledge) signal.
 Reset In (input, active low): This signal is used to reset the microprocessor. The
program counter inside the microprocessor is set to zero.
 Reset Out (Output): It indicates CPU is being reset. Used to reset all the
connected devices when the microprocessor is reset.

vi) Direct Memory Access (DMA):

Tri state devices:

 3 output states are high & low states and additionally a high impedance state.
 When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is
0, Q is 1, otherwise Q is 0).
 However, when E is low the gate is disabled and the output Q enters into a high
impedance state.
  When E is low, Q enters a high impedance state; high impedance means it is
electrically isolated from the OR gate's input, though it is physically connected.
Therefore, it does not draw any current from the OR gate's input.
 When 2 or more devices are connected to a common bus, to prevent the devices
from interfering with each other, the tristate gates are used to disconnect all
devices except the one that is communicating at a given instant.
 The CPU controls the data transfer operation between memory and I/O device.
Direct Memory Access operation is used for large volume data transfer between
memory and an I/O device directly.
 The CPU is disabled by tri-stating its buses and the transfer is effected directly by
external control circuits.
 HOLD signal is generated by the DMA controller circuit. On receipt of this
signal, the microprocessor acknowledges the request by sending out HLDA signal
and leaves out the control of the buses. After the HLDA signal the DMA controller
starts the direct transfer of data.
 READY (input)
 Memory and I/O devices will have slower response compared to microprocessors.
 Before completing the present job such a slow peripheral may not be able to
handle further data or control signal from CPU.
 The processor sets the READY signal after completing the present job to access
the data.
 The microprocessor enters into WAIT state while the READY pin is disabled.
Single Bit Serial I/O port:
 SID (input) - Serial input data line
 SOD (output) - Serial output data line
These signals are used for serial communication.