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Ec0033-Asic Design-Model Qp-Vii Sem-Set1

This document contains exam questions for an ASIC Design course. It has two parts: Part A contains 10 short answer questions worth 2 marks each for a total of 20 marks. Part B contains 5 long answer questions worth 16 marks each for a total of 80 marks. The questions cover topics like ASIC design approaches, implementing logic with transmission gates, FPGA architectures from Xilinx and Altera, writing synthesizable VHDL models, and using algorithms like D-algorithm to determine test vectors for stuck-at faults. Students are required to answer all questions in the allotted 3 hours and score a maximum of 100 marks.

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101 views

Ec0033-Asic Design-Model Qp-Vii Sem-Set1

This document contains exam questions for an ASIC Design course. It has two parts: Part A contains 10 short answer questions worth 2 marks each for a total of 20 marks. Part B contains 5 long answer questions worth 16 marks each for a total of 80 marks. The questions cover topics like ASIC design approaches, implementing logic with transmission gates, FPGA architectures from Xilinx and Altera, writing synthesizable VHDL models, and using algorithms like D-algorithm to determine test vectors for stuck-at faults. Students are required to answer all questions in the allotted 3 hours and score a maximum of 100 marks.

Uploaded by

skarthikpriya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Reg. No.

(OR)
SRM INSTITUTE OF SCIENCE AND TECHNOLOGY b. What is BIST? Explain the various components associated with it.
Model Exam – Oct - 2019
Seventh Semester – Department of Electronics and Communication 15 a. Apply KL algorithm for figure2 and find the minimum cut cost
Engineering (OR)
b. With an example explain left edge channel routing algorithm and Lee
PEC0033 – ASIC Design maze routing
Duration: 3 Hrs Max. Marks: 100
PART – A (10 X 2 = 20 Marks)
Answer ALL Questions X

1. Size a 3 input NOR gate to achieve equal rise time and fall time
2. Design a XOR gate using Transmission gates B
3. Draw ACT1 logic module Y
4. What is shanon’s expansion theorem?
5. List different types of FSM Synthesis
C Z
6. What is logic mapping?
7. Draw a boundary scan cell Figure1
8. Find the test vector for SA1 at the output of 2 input NAND gate
9. What are the objectives of placement?
10. What is the goal of detail routing

PART – B (5 X 16= 80 Marks)


Answer ALL questions

11. a. Explain the various ASIC design approaches


(OR)
b. Implement D latch, DFF using Transmission gates. Figure2

12. a. Draw and explain the features of XILINX XC3000 architecture


(OR)
b. Draw and explain the features of Altera Flex architecture

13 a. Write a Synthesizable memory model in VHDL


(OR)
b. Write short notes on various types of simulation

14 a. Determine the Test vector for SA1 fault shown below in figure1 using
D algorithm

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