Subject Code: ECL 48 IA marks: 25

Hours per week: 03 Exam Hours:03

Total Hrs: 42 Exam Marks:50
Note:
1. Programming can be done using any VHDL compiler. Download the programs on a
FPGA/CPLD board and test performance using 16/32 channel pattern generator and logic
analyzer apart from verification by simulation.
2. Use the pattern generator to generate input signal and truth tables.
PROGRAMMING:
1. Write VHDL code to realize all the logic gates
2. Write a VHDL program for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer
d. 4 bit binary to gray converter
e. Multiplexer, demultiplexer, comparator
3. Write a VHDL code to describe the functions of a Full Adder Using three modeling styles.
4. Write a model for 32 bit ALU using the schematic diagram shown below.(example only)
 ALU should use combinational logic to calculate an output based on the four bit op-code input
 ALU should pass the result to the out bus when enable line in high, and tri-state the out bus
when the enable line is low.
 ALU should decode the 4 bit op-code according to the given in example below
OPCODE ALU OPERATION
a) A + B
b)A - B
c) A Complement
d) A * B
e) A AND B
f) A OR B
g) A NAND B
h) A XOR B
5. Develop the VHDL codes for the following flip-flops, SR, D, JK, T.
6. Design 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset) and “any
sequence”counters.

INTERFACING
1.Write VHDL code to display messages on the given seven segment display and LCD and
accepting Hex key pad input data.
2 .Write a VHDL code to accept 8 channel Analog signal, Temperature sensors and display the
data on LCD panel or Seven segment display.
3. Write VHDL code to simulate elevator operations.
4. Write VHDL code to control external lights using relays.
5. Write VHDL codes to control speed, direction of DC and Stepper motor.
6. Write VHDL Code to generate different waveforms (Sine square Triangle, Ramp etc) using DAC
change the frequency and amplitude.
 ABSTRACT

The semiconductor industry has been experiencing an unprecedented growth fuelled by

the developments in the VLSI industry. The VLSI industry has already crossed the quarter-
micron threshold and devices with 0.18 micron feature-size are already in market. Thus, it
becomes extremely difficult to design complex circuits with the help of conventional designing
methods. The computer aided design tools introduced serve the purpose.

INTRODUCTION

There are now two industry standard hardware description languages, VHDL and
Verilog. The complexity of ASIC and FPGA designs has meant an increase in the number of
specialist design consultants with specific tools and with their own libraries of macro and mega
cells written in either VHDL or Verilog. As a result, it is important that designers know both
VHDL and Verilog and that EDA tools vendors provide tools that provide an environment
allowing both languages to be used in unison. For example, a designer might have a model of a
PCI bus interface written in VHDL, but wants to use it in a design with macros written in
Verilog.
VHDL is a hardware description language that offers a broad set of constructs for
describing even the most complicated logic in a compact fashion. The VHDL language is
designed to fill a number of requirements throughout the design process:
 Allows the description of the structure of a system — how it is decomposed into
subsystems, and how those subsystems are interconnected.
 Allows the specification of the function of a system using familiar programming
language forms.

BACKGROUND

VHDL (Very high speed integrated circuit Hardware Description Language) became
IEEE standard 1076 in 1987. It was updated in 1993 and is known today as "IEEE standard 1076
1993". The Verilog hardware description language has been used far longer than VHDL and has
been used extensively since it was launched by Gateway in 1983. Cadence bought Gateway in
1989 and opened Verilog to the public domain in 1990. It became IEEE standard 1364 in
December 1995.

There are two aspects to modeling hardware that any hardware description language
facilitates; true abstract behavior and hardware structure. This means modeled hardware behavior
is not prejudiced by structural or design aspects of hardware intent and that hardware structure is
capable of being modeled irrespective of the design's behavior.
PROCEDURE:

Software part:
1. Click on the Project navigator icon on the desktop of your PC. Go to Create New
Project, give project Name.
2. Set Spartan 2, xc2s100, tq144. -5 and ISE Simulator / Modelsim for FPGA Family.
3. Go to Create new source in process View, Select VHDL MODULE and give name(it
should be other than the project name). i.e. Entity name and give the inputs, outputs
and select the architecture name. Then click on next icon & Finish Icon.
4. Then Write the VHDL code and save the file.
5. Then click on Check syntax in Synthesis-XST in Process view, and if there is any
error in the code debug it.
6. To see output in Test Bench Waveform(ISE Simulator / Modelsim):
Go to Create new source, select TEST BENCH WAVEFORM and give a
different file name and select COMBINATIONAL for combination circuits and
SINGLE CLOCK for Sequential Circuits. Then set the corresponding inputs &
outputs, then save and then click on simulate Behavioral model/ Modelsim simulator
i.e. depending upon the module.
7. To see output in VHDL kit:
Go to Create new source, select IMPLENTATION CONSTRAINTS FILE
and Open a new UCF(User Constraint File) file and assign the pins of the design with
FPGA/CPLD I/O pins(for Clock input always P18) and save the file.
8. Implement the design in process view by double clicking on the Implement Design
and View Pad Report to verify the pin numbers.
9. Click on Generate Programming File in Process View and then click on Configure
Device.
10. Now check the cable connections and select mode as SLAVE SERIAL MODE and
then verify the output at LEDS.
11. To see output in Pattern Generator / Logic Analyser:
Repeat steps from 1 to 10 except step 6, then choose appropriate Baud Rate,and then
click on save and see the output.

Hardware part:
1. Connect the FPGA kit to the parallel port of the PC through the cable provided along
with the Kit. Connect the FRC cable provided with the kit to the Bit Pattern generator
and logic analyzer.
2. For all the combinational experiments Use FRC1&FRC2 for sending bit patterns to
FPGA (pattern generator) and use FRC3 &FRC4 for receiving the logic from FPGA
(logic Analysis).
3. For all sequential circuits Use FRC 1 for sending bit patterns to FPGA (pattern
generator) and use last input pin as the clock for the design and connect it to the FPGA
clock pin through the jumper provided on the Kit. Use FRC2 for receiving the logic
from FPGA (logic Analysis).
4. For interfacing the cards connect the required part of the interfacing card to the FRC
connector Provided on the FPGA kit.
PART-A
 1. Write VHDL code to realize all the logic gates.

Block Diagram:

Op_not
A Op_or
Op_and
Op_nor

LOGIC GATES Op_nand

B Op_xor
Op_xnor

Truth Table:

INPUT OUTPUTS
S
A B Op_not Op_or Op_and Op_nor Op_nand Op_xor Op_xnor
(Considering
input A)
0 0 1 0 0 1 1 0 1
0 1 1 1 0 0 1 1 0
1 0 0 1 0 0 1 1 0
1 1 0 1 1 0 0 0 1
Program:

1) Using VHDL

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity gate is
Port ( A : in std_logic; -- First Input
B : in std_logic; -- Second Input
Op_not : out std_logic;
Op_or : out std_logic;
Op_and : out std_logic;
Op_nor : out std_logic;
Op_nand : out std_logic;
Op_xor : out std_logic;
Op_xnor : out std_logic);
End gate;

Architecture Behavioral of gate is

Begin
Op_not <= not A;
Op_or <= A or B;
Op_and <= A and B;
Op_nor <= A nor B;
Op_nand <= A nand B;
Op_xor <= A xor B;
Op_xnor <= A xnor B;
End Behavioral;
2) Using Verilog

module gates(a,b,op_not,op_or,op_nor,op_xor,op_xnor,op_and,op_nand);
input a,b;
output op_not,op_or,op_nor,op_xor,op_xnor,op_and,op_nand;
assign op_not=~a;
assign op_or= a| b;
assign op_nor= ~(a|b);
assign op_xor= a^ b;
assign op_xnor= ~(a^ b);
assign op_and= a &b;
assign op_nand= ~(a&b);
endmodule
2. Write a VHDL program for 2 to 4 Decoder

Block Diagram:

Enable
D_OUT (3:0)
DECODRE 2_4
D_IN (1:0)

Truth Table:

INPUTS OUTPUTS
E D_IN(0) D_IN(1) D_OUT(3) D_OUT(2) D_OUT(1) D_OUT(0)
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0

a) Using Data Flow Model:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity Decoder2_4 is
port (Enable: in STD_LOGIC;
D_IN: in STD_LOGIC_VECTOR (1 downto 0); -- Two Bit Input for the
Decoder
D_OUT: out STD_LOGIC_VECTOR (3 downto 0)); -- Four Bit Output for
 the Decoder
End Decoder2_4;

Architecture Data_flow of Decoder2_4 is

Signal s1, s2: std_logic;
Begin
s1<= not D_IN (0);
s2<=not D_IN (1);
D_OUT(0)<=s1 and s2 and Enable;
D_OUT(1)<=s1 and D_IN(1) and Enable;
D_OUT(2)<= D_IN(0) and s2 and Enable;
D_OUT(3)<= D_IN(0) and D_IN(1) and Enable;
End Data_flow;

b) Using Behavioral Method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity Decoder2_4 is
port ( Enable: in STD_LOGIC);
D_IN: in STD_LOGIC_VECTOR (1 downto 0); -- Two Bit Input for the
Decoder
D_OUT: out STD_LOGIC_VECTOR (3 downto 0)); -- Four Bit Output
for the Decoder
End Decoder2_4;

Architecture Behavioral of Decoder2_4 is

Begin
Process (Enable, D_IN)
Begin
if (Enable = '1') then
D_OUT <= "0000";
Else
case D_IN is
when "00" => D_OUT <= "0001";
when "01" => D_OUT <= "0010";
when "10" => D_OUT <= "0100";
when "11" => D_OUT <= "1000";
when others => NULL;
End case;
 End if;
End process;
End Behavioral;

Using Verilog:

module decoder(data, code);

output[3:0]data;
input[1:0]code;
reg [3:0]data;
always @(code)
case (code)
0:data=4'b 0001;
1:data=4'b 0010;
2:data=4'b 0100;
3:data=4'b 1000;
default: data=4'bx;
endcase
endmodule
 3. Write a VHDL program for 8 to 3 Encoder without
Priority.

Block Diagram:

Enable
D_OUT (2:0)
ENCODER 8_4

D_IN (7:0)

a) Using Behavioral Method:

b)
TRUTH TABLE

INPUTS OUTPUTS
D_IN(7
D_IN(6) D_IN(5) D_IN(4) D_IN(3) D_IN(2) D_IN(1) D_IN(0) D_OUT(2) D_OUT(1) D_OUT(0)
)
1 0 0 0 0 0 0 0 1 1 1
0 1 0 0 0 0 0 0 1 1 0
0 0 1 0 0 0 0 0 1 0 1
0 0 0 1 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 0 1 0 0 0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity Encoder8_3 is
Port ( ENABLE: in STD_LOGIC; --Enable Pin to Enable the Encoder
D_IN: in STD_LOGIC_VECTOR(7 downto 0); --Eight Input Lines of the
Encoder
D_OUT: out STD_LOGIC_VECTOR(2 downto 0) ); --Three Output Lines
of Encoder
End Encoder8_3;

Architecture Behavioral of encoder8_3 is

Begin
Process(ENABLE,D_IN)
Begin
if ( ENABLE = '1') then
D_OUT <= "000";
Else
case D_IN is
when "00000001" => D_OUT <= "000";
when "00000010" => D_OUT <= "001";
when "00000100" => D_OUT <= "010";
when "00001000" => D_OUT <= "011";
when "00010000" => D_OUT <= "100";
when "00100000" => D_OUT <= "101";
when "01000000" => D_OUT <= "110";
when "10000000" => D_OUT <= "111";
when others => NULL;
end case;
end if;
end process;
End Behavioral;
Using verilog

module encoder(code, data);

output [2:0] code;
input [7:0]data;
reg [2:0]code;
always @ (data)
case(data)
8'b 00000001: code=0;
8'b 00000010: code=1;
8'b 00000100: code=2;
8'b 00001000: code=3;
8'b 00010000: code=4;
8'b 00100000: code=5;
8'b 01000000: code=6;
8'b 10000000: code=7;
Default : code=3'bx;
endcase

endmodule
 4. Write a VHDL program for 8 to 3 Encoder with
Priority.

a) Using Behavioral Method:

Entity pri_Encoder is
Port ( ENABLE: in STD_LOGIC; --Enable Pin to Enable the Encoder
D_IN: in STD_LOGIC_VECTOR(7 downto 0); --Eight Input Lines of the Encoder
D_OUT: out STD_LOGIC_VECTOR(2 downto 0) ); --Three Output Lines of Encoder
End pri_Encoder;

Architecture Behavioral of pri_Encoder is

Begin
D_OUT<="111" when D_IN(7)='1' else
"110" when D_IN(6)='1' else
"101" when D_IN(5)='1' else
"100" when D_IN(4)='1' else
"011" when D_IN(3)='1' else
"010" when D_IN(2)='1' else
"001" when D_IN(1)='1' else
"000” when D_IN (0) = '1' else
"ZZZ";
End Behavioral;

TRUTH TABLE

INPUTS OUTPUTS
D_IN(7
D_IN(6) D_IN(5) D_IN(4) D_IN(3) D_IN(2) D_IN(1) D_IN(0) D_OUT(2) D_OUT(1) D_OUT(0)
)
1 x x x x x x x 1 1 1
x 1 x x x x x x 1 1 0
x x 1 x x x x x 1 0 1
x x x 1 x x x x 1 0 0
x x x x 1 x x x 0 1 1
x x x x x 1 x x 0 1 0
x x x x x x 1 x 0 0 1
x x x x x x x 1 0 0 0
Using veilog
module priority (code, valid_data, data);
output[2:0] code;
output valid_data;
input[7:0]data;
reg[2:0]code;
assign valid_data= |data; // “reduction or” operator
always @ (data)
casex(data)

8'b 1xxxxxxx: code=7;

8'b 01xxxxxx: code=6;
8'b 001xxxxx: code=5;
8'b 0001xxxx: code=4;
8'b 00001xxx: code=3;
8'b 000001xx: code=2;
8'b 0000001x: code=1;
8'b 00000001: code=0;
default: code=3'bx;
endcase
endmodule
5. Write a VHDL program for 8:1 MUX

BLOCK DIAGRAM

D MUX_OUT

F 8:1 MUX
G

SEL

Select Lines INPUT’S OUTPUT

S0 S1 S2 A B C D E F G H Mux OUT
0 0 0 0 x x x x x x x 0
0 0 0 1 x x x x x x x 1
0 0 1 x 0 x x x x x x 0
0 0 1 x 1 x x x x x x 1
0 1 0 x x 0 x x x x x 0
0 1 0 x x 1 x x x x x 1
0 1 1 x x x 0 x x x x 0
0 1 1 x x x 1 x x x x 1
1 0 0 x x x x 0 x x x 0
1 0 0 x x x x 1 x x x 1
1 0 1 x x x x x 0 x x 0
1 0 1 x x x x x 1 x x 1
1 1 0 x x x x x x 0 x 0
1 1 0 x x x x x x 1 x 1
1 1 1 x x x x x x x 0 0
1 1 1 x x x x x x x 1 1
a) Using Behavioral Method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity Mux8_1 is
Port ( SEL: in STD_LOGIC_VECTOR(2 downto 0); -- Select Lines
A,B,C,D,E,F,G,H :in STD_LOGIC; -- Inputs of the Mux.
MUX_OUT: out STD_LOGIC ); -- OutPut of the Mux.
End Mux8_1;

Architecture Behavioral of Mux8_1 is

Begin
Process (SEL,A,B,C,D,E,F,G,H)
Begin
case SEL is
when "000" => MUX_OUT <= A;
when "001" => MUX_OUT <= B;
when "010" => MUX_OUT <= C;
when "011" => MUX_OUT <= D;
when "100" => MUX_OUT <= E;
when "101" => MUX_OUT <= F;
when "110" => MUX_OUT <= G;
when "111" => MUX_OUT <= H;
when others => null;
end case;
end process;
end Behavioral;

Using Verilog
Module mux8x1(I0,I1,I2, I3,I4,I5,I6,I7,y,sel);
input I0,I1,I2, I3,I4,I5,I6,I7;
input [2:0]sel;
output y;
reg y;
always @ (I0,I1,I2, I3,I4,I5,I6,I7,sel)
begin
case (sel)
3'b000 : y=I0;
3'b001 : y=I1;
3'b010 : y=I2;
3'b011 : y=I3;
3'b100 : y=I4;
3'b101 : y=I5;
3'b110 : y=I6;
3'b111 : y=I7;
endcase
end
endmodule

6. Write a VHDL program for 4 bit binary to gray

 converter.

Boolean Equation:
G3=B3;
G 2= B 3 xor B 2;
G1= B2 xor B 1;
G0= B1 xor B0;

BLOCK DIAGRAM

Truth Table:
 Binary Input Gray output
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
0 1 0 0 0 1 1 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

a) Using Data Flow Method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity Binary_Gray is
port( B_IN: in std_logic_vector(3 downto 0); --Binary Input
G_OUT: out std_logic_vector(3 downto 0)); --Gray Output
End binary_gray;

Architecture behavioral of Binary_gray is

Begin
G_OUT(3)<= B_IN(3);
G_OUT(2)<= B_IN(3) xor B_IN(2);
G_OUT(1)<= B_IN(2) xor B_IN(1);
G_OUT(0)<= B_IN(1) xor B_IN(0);
 End behavioral;

Using Verilog

7. Write a VHDL program for 1:4 DEMUX.

BLOCK DIAGRAM

4
Y
D_in
1:4
DEMUX

2
S

Select lines INPUT OUTPUTS

Sel(1) Sel(0) D_in Y(3) Y(2) Y(1) Y(0)
0 0 1 x x x 1
0 1 0 x x 0 x
1 0 1 x 1 x x
1 1 0 0 x x x

a) Using Behavioral Method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Demux1_4 is
port ( d_in: in STD_LOGIC; --Input For Demultiplexer
sel: in STD_LOGIC_VECTOR (1 downto 0); --Select Line
of Demux
d_out: out STD_LOGIC_VECTOR (3 downto 0)); --Output
Lines of Demux
end Demux1_4;

architecture demux1_4_arch of Demux1_4 is

begin
 process(d_in, sel)
begin
d_out<="0000";
case sel is
when "00" => d_out(0)<=d_in;
when "01" => d_out(1)<=d_in;
when "10" => d_out(2)<=d_in;
when others => d_out(3)<=d_in;
end case;
end process;
end demux1_4_arch;

Using Verilog
8.Write a VHDL program for N Bit Comparator.
BLOCK DIAGRAM

A A =B

A <B
N Bit
B Comparator
A >B

TRUTH TABLE

INPUTS OUTPUTS
A B A=B A<B A>B
0 0 1 0 0
0 1 0 1 0
1 0 0 0 1
1 1 1 0 0

PROGRAM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comparator is
Generic (N: integer := N); --- Generalizing the Inputs
Port( A,B: in STD_LOGIC_VECTOR(N downto 0); -- Inputs for
Comparison
ALB,AGB,AEB: out STD_LOGIC); -- Output Signals to show
Less than,Greater than and Equal.
end comparator;

architecture behavioral of comparator is

begin
process(A,B)
begin
if ( A < B ) then ALB <= '1';
else ALB <= '0'; end if;
if ( A > B ) then AGB <= '1';
 else AGB <= '0'; end if;
if ( A = B ) then AEB <= '1';
else AEB <= '0'; end if;
end process;
end behavioral;

Using Verilog
9. Write a VHDL program for the implementation of Half
Adder.
BLOCK DIAGRAM

A SUM

Half
Adder CARRY
B

TRUTH TABLE

Input Output
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

a) Using Data Flow Method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Halfadder is
Port ( A, B : in std_logic; --2Bit Input
Sum, Carry : out std_logic); --sum& carry
end Halfadder;

architecture dataflow of Halfadder is

begin
Sum <= A xor B;
Carry<= A and B;
end dataflow;

Using Verilog

10 Write a VHDL program for the implementation

 of Full Adder.

BLOCK DIAGRAM

A
SUM
B

FULL ADDER Cout

Cin

Truth Table:-

Ci C ou
A B S
n t

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

a) Using Data Flow Method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FullAdder is
Port ( Ain : in std_logic; --Input One
Bin : in std_logic; --Input Two
Cin : in std_logic; --Carry Input
 Cout : out std_logic; --Carry Output
Sum : out std_logic); --Sum Output
end FullAdder;

architecture dataflow of FullAdder is

begin
Sum<= Ain xor Bin xor Cin;
Cout<= (Ain and Bin) or (Bin and Cin) or (Ain and cin);
end dataflow;

b) Using Behavioral Method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FullAdder is
Port ( Ain : in std_logic; --Input One
Bin : in std_logic; --Input Two
Cin : in std_logic; --Carry Input
Carry : out std_logic; --Carry Output
Sum : out std_logic); --Sum Output
end FullAdder;

architecture behavioral of FullAdder is

begin
process(Ain,Bin,Cin)
begin
if(Ain='0'and Bin='0'and Cin='0')then
sum<='0';carry<='0';
elsif((Ain='0'and Bin='0'and Cin='1')or(Ain='0'and Bin='1'and
Cin='0')or
(Ain='1' and Bin='0' and Cin='0')) then
sum<='1';carry<='0';
elsif((Ain='0'and Bin='1'and Cin='1')or(Ain='1'and Bin='0'and
Cin='1')or
(Ain='1' and Bin='1' and Cin='0')) then
sum<='0';carry<='1';
elsif(Ain='1'and Bin='1'and Cin='1') then
sum<='1';carry<='1';
end if;
 end process;
end behavioral;

c)Using Component Instantiation Method(or)

strcuctural method

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FullAdder is
Port ( Ain : in std_logic; --Input One
Bin : in std_logic; --Input Two
Cin : in std_logic; --Carry Input
Cout : out std_logic; --Carry Output
Sum : out std_logic); --Sum Output
end FullAdder;

architecture structural of FullAdder is

Component Halfadder
Port ( Ain : in std_logic;
Bin : in std_logic;
Sum : out std_logic;
Carry : out std_logic);
end Component;
 component or1 is
port(p,q:in std_logic;
r: out std_logic);
end component;

Signal temp1,temp2, temp3: std_logic; -- Signal Declaration

begin
U1: Halfadder port map( Ain, Bin,temp1,temp2);
U2: Halfadder port map( temp1,Cin,Sum,temp3);
U3: or1 port map (temp2,temp3,Cout);
end structural;

entity halfadder is
Port ( Ain,Bin : in STD_LOGIC;
sum, carry : out STD_LOGIC);
end halfadder;

architecture Behavioral of halfadder is

begin
Sum <= Ain xor Bin;
Carry<= Ain and Bin;

end Behavioral;

entity or1 is
Port ( p,q : in STD_LOGIC;
r : out STD_LOGIC);
end or1;

architecture Behavioral of or1 is

begin
r<= p or q;
end Behavioral;
12. ALU

Block Diagram
A [3:0]
B [3:0]
Y [7:0]
Enable ALU
opcode [2:0]

Truth Table

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0);
e: in std_logic;
opc : in STD_LOGIC_VECTOR (2 downto 0));
end ALU;

architecture Behavioral of ALU is

begin
process(opc,e)
begin
if (e ='0')then
y <="00000000";
\elsif (e = '1')then
case opc is
when "000" => y<= “0000” & (a + b);
when "001" => y<= “0000” & (a – b);
 when "010" => y<= “0000” & (not a) ;
when "011" => y<= a * b;
when "100" => y<= “0000” & (a and b);
when "101" => y<= “0000” & (a or b);
when "110" => y<= “0000” & (a nand b);
when "111" => y<= “0000” & (a xor b);
when others => null;
end case;
end if;
end process;
end Behavioral;

Sequential circuits:
11. Write a VHDL program for SR F/F

Block diagram
S

CLK Q
SR
R FLIP-FLOP

RESET

a) Using Behavioral Method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rsff is
Port ( r,s,reset,clk : in std_logic;
q,qb : out std_logic);
end rsff;

architecture Behavioral of rsff is

 signal p:std_logic:='0';
begin
process(clk,reset,s,r)
begin
if(reset='1')then p<='0';
elsif(rising_edge(clk))then
if(s='0' and r='0')then p<=p;
elsif(s='0' and r='1')then p<='0';
elsif(s='1' and r='0')then p<='1';
else p<='X';
end if;
end if;
end process;
q<=p;
qb<=not p;
end Behavioral;

Clock Reset S R Q Qb
1 1 x x 0 1
1 0 0 0 No change No change
1 0 0 1 Reset Set
1 0 1 0 Set Reset
1 0 1 1 Illegal Illegal

Using verilog

11. Write a VHDL program for D F/F

Block Diagram

D Q
FLIP-FLOP
CLK

RESET

Truth Table
INPUT OUTPUT
CLK RESET D Q
1 0 1 0
1 1 0 0
1 1 1 1

a) Using Behavioral Method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff is
Port ( d,rst,clk : in STD_LOGIC;
q : out STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
process(rst,clk)
begin
if rst = '0' then
q <= '0';
elsif (clk'event and clk = '1') then
 q <= d;
end if;
end process;
end Behavioral;

Using Verilog

Write a VHDL program for JK F/F

Block Diagram

CLK Q
JK
K FLIP-FLOP

Reset
Truth Table

INPUTS OUTPUTS
CLK J K Q
1 0 0 No change
1 0 1 Reset
1 1 0 set
1 1 1 Toggle

a) Using Behavioral Method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jk is
Port ( s,r, j,k,clk : in STD_LOGIC;
q : inout STD_LOGIC;
qn : out STD_LOGIC := '1');
end jk;

architecture Behavioral of jk is
begin
process(s,r,clk)
begin
if r = '0' then q<= '0';
elsif s = '0' then q <= '1';
elsif clk = '0' and clk'event then
q <= ((j and (not q)) or ((not k) and q));
end if;
end process;
end Behavioral;

11. Write a VHDL program for T F/F

Block Diagram

T Q

T
FLIP-FLOP
CLK Qb

RESET

Truth Table
INPUTS OUTPUT
CLK Reset T Q
 1 0 0 0
1 1 0 0
1 1 1 Toggle

a) Using Behavioral Method:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tff is
Port ( rst,clk,t : in STD_LOGIC;
q : inout STD_LOGIC);
end tff;

architecture Behavioral of tff is

begin
process(clk,rst)
begin
if (rst = '0') then
q<='0';
elsif(clk'event and clk = '1')then
q<= q xor t;
end if;
end process;

end Behavioral;
Using Verilog

VHDL code for 4-bit BINARY COUNTER with Asynchronous Reset

entity asbin_counter is
Port ( sclk,reset: in std_logic;
q : out std_logic_vector(3 downto 0));
end asbin_counter;

architecture Behavioral of asbin_counter is

signal count:std_logic_vector(3 downto 0):="0000";
begin
process(clk,reset)
begin
if(reset='1')then count<="0000";
elsif(rising_edge(clk)) then
count<=count+1;
end if;
end process;
q<=count;
end Behavioral;

VHDL code for 4-bit BINARY COUNTER with synchronous Reset

entity sbin_counter is
Port ( clk,reset: in std_logic;
q : out std_logic_vector(3 downto 0));
end sbin_counter;

architecture Behavioral of sbin_counter is

signal count:std_logic_vector(3 downto 0):="0000";
begin
process(clk,reset)
begin
if(rising_edge(clk)) then
if(reset='1')then count<="0000";
else
count<=count+1;
end if;
end if;
end process;
q<=count;
end Behavioral;

VHDL code for 4-bit BCD COUNTER with synchronous Reset.

entity sbcdcounter is
Port ( clk,reset: in std_logic;
q : out std_logic_vector(3 downto 0));
end sbcdcounter;

architecture Behavioral of sbcdcounter is

signal count:std_logic_vector(3 downto 0):="0000";
begin
process(clk,reset)
begin
if(rising_edge(clk)) then
if(reset='1')then count<="0000";
else
count<=count+1;
end if;
if(count="1001") then count<="0000";
end if;
end if;
end process;
q<=count;
end Behavioral;

VHDL code for 4-bit BCD COUNTER with Asynchronous Reset.

entity asbcdcounter is
Port ( sclk,reset: in std_logic;
q : out std_logic_vector(3 downto 0));
end asbcdcounter;

architecture Behavioral of asbcdcounter is

signal count:std_logic_vector(3 downto 0):="0000";
begin
process(clk,reset)
begin
if(reset='1')then count<="0000";
elsif(rising_edge(clk)) then
if(count="1001") then count<="0000";
else
count<=count+1;
end if;
end if;
end process;
q<=count;
end Behavioral;