UNIT2,3

• Arithmetic instructions
• instructions to increment and decrement the contents of registers and RAM
• Perform signed and unsigned addition and subtraction
• Perform unsigned multiplication and division
• Perform BCD addition
• There are 24 arithmetic opcodes in this group
• INC destination ; Increment destination by 1
• DEC destination ; Decrement destination by 1
• ADD/ADDC destination, source ;ADD source to destination without/with Carry flag
• SUBB destination, source ;Subtract,with borrow source from destination
• MUL AB ;Multiply the contents of registers A and B
• DIV AB ;Divide the contents of registers A by the contents of register B
• DA A ;Decimal Adjust the A register.

Unsigned addition:

• The numbers that are 8 bit positive binary numbers ranging from 00h to FFh.
• Carry flag is used to detect when the result of an ADD operation is a number larger that FFh.
The OV flag is not used for unsigned addition and subtraction
Signed Addition:
• Signed numbers use bit 7(MSB) of the number as a sign bit , Bits 0 to 6 is the magnitude of the
number.
• Signed numbers use a 1 in bit position D7 of the MSB as a negative sign and a 0 as a positive
sign.
• The negative numbers are in two’s complement form.
• In signed form,a single byte number may range in size from 10000000b(=-128d) to
01111111b(=+127d).
• Addition of Unlike Signed numbers:
The result cannot be greater than -128d or +128d and the sign of the result will always be correct.
-001d = 11111111b =FFh
+027d = 00011011b =1Bh
______ __________ ____
+026d 1)00011010b 1)1Ah
There is a carry from bit 7,hence carry flag is 1. There is also a carry from bit 6,and OV flag is 0. For this
condition, no action need be taken by the program to correct the sum.
The programming actions needed for the C and OV flags are:
Flags Action
C OV
0 0 None
0 1 Complement the sign
 1 0 None
1 1 Complement the sign
The OV flag also indicates that the sum exceeds the largest positive or negative numbers range.
Decimal Arithmetic

• 8051 works on hexadecimal numbers.

• We work with decimal system. so programmer can provide decimal results when required using
DA A .
• DA A= Decimal adjust sum of two BCD numbers in accumulator after addition.
• C flag is set to one if adjusted number exceeds 99BCD.
• DA A uses AC flag during nibble sum to adjust to decimal form.
• DA A works only with ADD ADDC instructions.
• NO adjust for SUBB, MUL and DIV
•
8051 -subtraction of two signed or unsigned numbers.
Register A is the destination address for subtraction.
Carry flag is treated as a borrow and always the carry flag is subtracted as a part of the operation.
C flag is set if a borrow is needed into bit 7 and reset otherwise.
AC flag is set if there is a borrow is needed into bit 3 and reset otherwise.
OV flag is set if there is a borrow into bit 7 and not bit 6 or if there is a borrow into bit 6 and not bit
7. The OV flag is the XOR of the borrows into bit positions 7 and 6.
nitially C flag should be cleared.
The result will be in true form, with no borrow if the source number is smaller than A, or in two’s
complement form with a borrow if the source is larger than A.
Unsigned Subtraction:
subtraction of a larger number from a smaller number
C flag:set to 1;OV flag set to 0;Two’s complement of result
C flag:set to 0;OV flag set to 0;Magnitude of the result is in true form.
Signed subtraction:Subtraction of like Signed numbers:
Result does not exceed the positive or negative magnitude limits of +127d or -128d.
If there is a borrow into bit position 7 and 6.
Carry flag is set to 1 OV flag is cleared.
Subtraction of unlike Signed numbers:
overflow may be possible. –sum >-128, or borrow into bit position 6 only ,0r D7 only , Both OV and
Carry flag may are set , answer must be adjusted.
Complement sign bit
Multiplication:
The unsigned number in Reg. A is mutiplied by the unsigned number in Reg.B
MUL AB ;Multiply A by B;put the low order byte of the
product in A and high order product in B
OV flag will be set if A×B>FFh.It does not imply that the result is wrong. It signals that the result is
larger than 8 bits and the higher byte of the result is available in B register.
Carry flag is always cleared to 0.
Multiplication:
The unsigned number in Reg. A is mutiplied by the unsigned number in Reg.B
MUL AB ;Multiply A by B;put the low order byte of the
product in A and high order product in B
OV flag will be set if A×B>FFh.It does not imply that the result is wrong. It signals that the result is
larger than 8 bits and the higher byte of the result is available in B register.
Carry flag is always cleared to 0.
The logical operations can be at two data levels: byte or bit

Byte Level Logical Operations:

• The entire byte is affected with the operation
• The A register or a direct address in internal RAM is the destination of the logical operation
result.No flags are affected by the byte level logical operations unless the direct address is the
PSW.
• ANL A,#n ;AND each bit of A with the same bit of immediate

• number n;put the result in A

• ANL A,addr ;AND each bit of A with the same bit of direct RAM
address;put the result in A
• ANL A,Rr ;AND each bit of A with the same bit of Rr;put the result
in A
• ANL A,@Rp ;
• ANL addr,A ;
• ANL addr,#n ;
• Eg:
• MOV A,#0FFh
• MOV R0,#77h
• ANL A,R0
XRL A,#n ;XOR each bit of A with the same bit of n
;put the result in A
XRL A,addr ;
XRL A,Rr
XRL A,@Rp
XRL addr,A
XRL addr,#n

Rotate and Swap Operations

• The A register can be rotated one bit position to the left or right with or without including the C
flag in the rotation.
RL A Rotate the A register one bit position to the left.
RLC A Rotate the A register along with Carry one bit position
 to the left
RR A Rotate the A register one bit position to the right.
RRC A Rotate the A register along with Carry one bit position to the
right
SWAP A Interchange the nibbles of register A; put the high nibble in the low nibble position and
the low nibble in the high nibble position

• No other flags, other than the Carry flag in RRC and RLC are affected.

Bit Level Boolean Operations

• Bit level Boolean logical opcodes operate on any addressable RAM or SFR bit.
• The Carry flag in the PSW special function register is the destination for most of the opcodes. C
flag either sets or resets depending on the operation.
• ANL C,bAND C and the addressed bit; put the result in C
• ANL C,/b AND C and the complement of the addressed bit; put the
result in C; the addressed bit is not altered.
• ORL C,b OR C and the addressed bit; put the result in C
• ORL C,/b OR C and the complement of the addressed bit; put
• the result in C; the addressed bit is not altered.
• CPL C Complement the C flag
• CPL b Complement the addressed bit
• CLR C Clear the C flag to 0

CLR b Clear the addressed bit to 0.

MOV C,b Copy the addressed bit to the C flag.
MOV b,C Copy the C flag to the addressed bit.
SETB C Set the C flag to 1
SETB b Set the addressed bit to 1
The bit instructions that can use a SFR latch bit are: CLR, CPL, MOV and SETB.
Eg: SETB 00h Bit 0 of bit addressable RAM byte 20h=1
MOV C,00h C=1
MOV 7Fh,C Bit 7 of RAM byte 2Fh=1

Jump and Call Instructions

• The jumps and call codes are decision codes that alter the flow of the program by examining the
results of the action codes and changing the contents of the program counter.
• A jump permanently changes the contents of the program counter if certain program conditions
exist.
• A call temporarily changes the program counter to allow another part of the program to run.
• Jumps and Calls may also be generally referred to as “branches”, which emphasizes that two
divergent paths are made possible by this type of instruction.
The Jump and Call program Range
The difference, in bytes, of the new address from the address in the program where the jump or call is
located is called the range of the jump or call.
Absolute addressing has the advantage of allowing jumps or calls over longer programming distances
than does relative addressing.
Long Absolute Range:Addresses that can access the entire program space from 0000h to FFFFh use long-
range addressing. It is more likely to be used in large programs.
Jumps:The 8051 has a rich set of jumps that can operate at the bit and byte levels.
Jumps operate by testing for conditions that are specified in the jump mnemonic.
If Condition is true: the PC is altered to the address that is part of the jump instruction.
If Condition is false: instruction immediately following the jump instruction is executed.

Bit Jumps: operate according to the status of the Carry flag in the PSW or the status of any bit-
addressable location.All bit jumps are relative to the program counter.
JC radd Jump relative if the Carry flag is set to 1
JNC radd
JB b, radd Jump relative if addressable bit is set to 1
JNB b, radd
JBC b, radd Jump relative if addressable bit is set, and clear the
addressable bit to 0.
Byte Jumps: jump instructions that tests bytes of data.
If the condition that is tested is true, the jump is taken.
If the condition is false, the instruction after jump is executed.
All byte jumps are relative to the program counter.
CJNE A,add,radd Compare the contents of the A register with the contents of the direct address;if
they are not equal,then jump to the relative address;set the carry flag to 1 if A<contents of direct
address.
CJNE A,#n,radd Similar to the above instruction
CJNE Rr,#n,radd
CJNE @Rp,#n,radd
DJNZ Rr,radd ;no flags are affectd
DJNZ add,radd ;Decrement the direct address by 1 and jump to the relative address if the
result is not zero;no flags are affected unless the direct address is the PSW.
JZ radd ;Jump to the relative address if register content is zero
JNZ radd
Unconditional Jumps:
• They do not test any bit or byte to determine whether the jump should be taken.
• All jump ranges are found in this group of jumps as the jump can be to any location in memory.
JMP @A+DPTR ;Jump to the address formed by adding A to the DPTR;the address can be anywhere in
the program memory;A,DPTR and the flags are unchanged.
AJMP sadd ;Jump to absolute short range address sadd;no flags are affected
LJMP ladd ;Jump to absolute long range address ladd;no flags are affected.
SJMP radd ;Jump to relative address radd; no flags affected.
NOP(no operation) ;Do nothing and go to the next instruction; used in a software timing loop;no
flags affect
CALL Instruction- Subroutine call
Subroutines are subtasks often called by main program .
Writing subroutines makes main program more structured.
Instructions under this –
ACALL address -2K range
LCALL address -64k range.
When subroutines are called
1.Address of next instruction below the CALL (PC address) is saved on to the stack.
2. PC is now loaded with address specified in front of CALL instruction.(where subroutine is written)
3.After execution of subroutine RET instruction shifts back to main program, wherein the PC address on
stack is POPed back.
Programmer must therefore ensure RET instruction at end of subroutine.
How to generate time delays
ORG 0
BACK: MOV A,#55H ;load A with 55H
MOV P1,A ;send 55H to port 1
LCALL DELAY ;time delay
MOV A,#0AAH ;load A with AA (in hex)
MOV P1,A ;send AAH to port 1
LCALL DELAY
SJMP BACK ;keep doing this indefinitely ...
END ;end of asm program
As machine cycles of each instruction is known , given clock frequency we can use machine cycles to
generate delays.
Data serialisation
Write an ALP to send 55h in A register serially to port p2.2
MOV A, #55h
MOV R0, #08h
BACK:RRC A
MOV P2.2,C
DJNZ R0, BACK
END

UNIT 3 : EMBEDDED ‘C’ PROGRAMMING and Timers ,counters

• Code for the 8051 is written for direct use on the processor, without need for separate
operating system.
• To support this, the Keil compiler has added several extensions to the C language to support use
of onchip resources directly.
• Reg51.h is the Header file has all SFR address declared.
 • Variable Types
• The Keil C compiler supports most C variable types and adds several types related to different
microcontrollers .
• C data types for 8051:
• Data Type Size in Bits Data Range/Usage
unsigned char 8-bit 0 to 256
signed char 8-bit -128 to +127
unsigned int 16-bit 0 to 65535
Signed int 16-bit -32768 to +32767
sbit 1-bit SFR bit-addressable only
bit 1-bit RAM bit-addressable only
sfr 8-bit RAM addresses 80 –FH

• As RAM space constitute register banks , stack and general purpose area,
• In 8051 compiler first allocates 8bytes of RAM for registers(bank0) rest of allocation is then for
variables and stack declared.
• So compiler allocates
• Bank 0 addresses 0-7
• Individual variables addressess 08 onwards
• Array addresses right after above declared
variables
• Stack after array
Write an 8051 C program to
a) toggle bits of P1 ports continuously with a 100ms using delay routine and assume DS8051 is
employed with 1mesc =1275count value.
b) Toggle P2.0 continouly 100msec
#include <reg51.h>
void Delay1(unsigned int);
void main(void)
{
while (1) //repeat forever
{ P1=0x55; Delay1(100);
P1=0xAA; Delay1(100);
} }
void Delay1(unsigned int TIME)
{
unsigned int i,j;
for (i=0;i<TIME;i++)
for (j=0;j<1275;j++);
}
LOGICAL OPERATORS
• The most important feature of the C language is its ability to perform bit manipulation.
• The bitwise operators used in C are
• AND (&),
• OR ( | ),
• EX-OR ( ^ ),
• inverter (~),
• Shift right (>>)
• Shift left (<<).
• Packed BCD to ASCII conversion
Example : Write an 8051 C program to convert packed BCD number 0x45 to ASCII and
display on P1 and P2.

#include <reg51.h>
void main(void)
{
unsigned char x,y,z;
unsigned char data=0x45;
x=data&0x0F; // 05
P1=x|0x30; // 35
y=data&0xF0; //40
y=y>>4; //04
P2=y|0x30; //34
}
Example : Write a C program to send out the value 55H serially one bit at a time via P1.0. The
LSB should go out first.
#include <reg51.h>
sbit P1out=P1^0;
sbit AD0=ACC^0;
void main(void)
{
unsigned char databyte=0x55;
unsigned char x;
for (x=0;x<8;x++)
{
ACC = databyte;
P1out = AD0;
ACC = ACC>>1;
databyte = ACC;
} }
 Packed BCD to ASCII conversion
Example : Write an 8051 C program to convert
packed BCD number 0x45 to ASCII and display on
P1 and P2.

#include <reg51.h>
void main(void)
{
unsigned char x,y,z;
unsigned char data=0x45;
x=data&0x0F; // 05
P1=x|0x30; // 35
• Programming 8051 Timers:
y=data&0xF0; //40
• The 8051 has two timers/counters
• They can be used eithery=y>>4; //04or as event counters to count
as Timers to generate a time delay
events happening outside the microcontroller.
P2=y|0x30; //34
}

•
•
•

•
• Timers start and stop by either by software or hardware control.
• The start and stop of the timer are controlled by program(software )by the TR (timer run) bits
TR0 or TR1. The SETB instruction starts it and it is stopped by the CLR instruction.
• These instructions start and stop the timers as long as GATE=0 in the TMOD register.
• The hardware control of start and stop of the timer can be done external source used to make
GATE=1 in the TMOD register.
•
• Timer 0 and Timer 1 are 16 bits wide. Since 8051 has an 8-bit architecture, each 16-bits timer
is accessed as two separate registers of low byte and high byte.
• The low byte register is called TL0/TL1 and the high byte register is called TH0/TH1.
• These registers can be accessed like any other register.
MOV TL0,#4FH
MOV R5,TH0
• TIMER
• In the "timer" function mode, it is incremented in every machine cycle.
• We can count machine cycles. So rate is 1/12th of Osc frequency
• COUNTER
• In the "counter" function mode, the register is incremented in response to a 1 to 0 transition
at its corresponding external input pin (T0 or T1).
• It requires 2 machine cycles to detect a high to low transition. Hence maximum count rate is
1/24 th of oscillator frequency.
Delay=[max value of count-initial value]*clk period in decimal

• Timer Mode-0
f/12

The lower 5 bits of TLX and 8 bits of THX are used for the 13
bit count . Upper 3 bits of TLX are ignored. When the maximum
value of IFFFh is reached -rolls over to 0000h, TFX flag is set

If TR1/0 bit is 1 and Gate bit is 0, the timer uses reference crystal
frequency 11.0598Mhz. This mode is useful to measure the
width of a given pulse fed to input.
Input pulse frequency to TLX is f/12
TLX divides this by 5
THX divides by 8 therefore f/12*32*256
Generates timing =0.00088secs
 • Timer Mode-1

Input pulse frequency to TLX is f/12

TLX divides this by 8 therefore
THX divides by 8
Therefore f/12*256*256
Generates timing =0.071secs

• Steps to program in mode 1

• To generate a time delay, using timer in mode 1, following are the steps:
• 1. Load the TMOD value register indicating which timer (timer 0 or timer 1) is to be used and
which timer mode
(0 or 1) is selected.
• 2. Load registers TL and TH with initial count value.
• 3. Start the timer.
• 4. Keep monitoring the timer flag (TF) with the JNB TFx, target instruction to see if it is raised.
Get out of the loop when TF becomes high.
• 5. Stop the timer.
• 6. Clear the TF flag for the next round.
• 7. Go back to Step 2 to load TH and TL again.

ALP:
MOV TMOD ,#10h
BACK:MOV TH1 #0FFh
MOV TL1,#OE9H
SETB TR1
HLD: JNB TF1 HLD
CLR TR1
CLR TF1
SJMP BACK
C program
#include <reg 51.h>
 Void main()
{
TMOD=0x10;
While(1)
{
TL1=0xEA;
TH1=0xFF;
TR1=1;
While(TF1==0);
TR1=0;
TF1=0;
}}

Timer Mode 2
1. This is a 8 bit counter/timer operation.
2. THX is loaded with 8bit count value , which is automatically reloaded to TLX register which
increments every machine cycle.
3. when the timer overflows i.e. TLX reaches FFH, it is fed with the count value stored in THX.
4. This mode is useful in applications like fixed time sampling, baud rate generation

• Steps to program in mode 2:

• To generate a time delay
• 1. Load the TMOD value register indicating which timer (timer 0 or timer 1) is to be used, and
the timer mode (mode 2) is selected.
• 2. Load the TH registers with the initial count value.
• 3. Start timer.
• 4. Keep monitoring the timer flag (TF) with the JNB TFx, target instruction to check if it is
raised. Get out of the loop when TF goes high.
• 5. Clear the TF flag and
• 6. Go back to Step 4, since mode 2 is auto reload.
 • Find the frequency of the square wave generated on pin P1.0
in the following program . Assume 50% duty cycle.

MOV TMOD, #20H ; T1/8-bit/auto reload

MOV TH1, #5 ; TH1 = 5
BACK: SETB TR1 ; start the timer 1
JNB TF1, BACK ; till timer rolls over
CPL P1.0 ; P1.0 to high, low
CLR TF1 ; clear Timer 1 flag
SJMP BACK ; mode 2 is auto-reload

Delay
• TH can have 8 bit value of maximum FF(256).
• (256 - 05) î 1.085 us = 251 î 1.085 us = 272.33 us is the high
portion of the pulse. Since it is a 50% duty cycle square wave,
the period T is twice that; as a result T = 2 î 272.33 us =
544.67 us and the frequency = 1.83597 kHz
•

• COUNTER
• Timers can also be used as counters, counting events happening real world. When it is used as
a counter, it is an external pulse that increments the TH, TL register.
• TMOD and TH, TL registers are used as in timer programming except for the source of the
frequency.
• C/T bit in TMOD register
• The C/T bit in the TMOD registers decides the source of the clock for the timer. When C/T = 1,
the timer is used as a counter and gets its pulses from outside. The counter counts up as
pulses are fed from pins 14 and 15, these pins are called T0 (timer 0 input) and T1 (timer 1
input).
• Example : Assuming that clock pulses are fed into pin T1, write a program for counter 1 in
mode 2 to count the pulses
• MOV TM0D,#60h ;counter 1, mode 2,C/T=1
• MOV TH1,#0 ;clear TH1
• SETB P3.5 ;make T1 input
• L1: SETB TR1 ;start the counter
• BK:JNB TF1,BK ;in loop do nothing, if TF = 0
• CLR TR1 ;stop the counter 1
• CLR TF1 ;make TF=0
• SJMP L1 ;Repeat
NOTE: THIS IS ONLY REFERENCE MATERIAL FOR SUPPORT AND
NOT COMPLETE NOTES. STUDENT HAS TO REFER TO
PRESCRIBED TEXT/REFERENCEs and LAB excercises FOR
PROGRAMS