Chapter 1

Introduction

1.1 Brief Introduction:

FPGAs (Field Programmable Gate Arrays) are chips created originally in 1985 to perform
only digital functions but today they have already both analogue and mixed signal
blocks. Customers like to use FPGA because they are easy to use and cost effective
reprogrammable devices.  FPGA are known for their flexibility and their ability to be
reprogrammed in the field. There is no need to have a full blown design flow and
tooling, therefore the NRE investment is very low and as consequence time to market is
fast. FPGAs usually cost more upfront than a microprocessor or ASIC. Microprocessors
have a lower unit cost and higher volume of production. On the other hand, an FPGA can
be reprogrammed over and over for different tasks, making them very cost efficient by
avoiding recurring expenses. Where performance is king, FPGAs set themselves apart in
highly parallelized tasks. While modern microprocessors can execute on many cores
with out-of-order instructions, not all functions are well-suited to this approach, like
massive image or digital signal processing applications. As a bonus, FPGAs may have
many hard or soft microprocessors operating inside of one package. In view of the
complexity of FPGAs, software is used to design the function of an FPGA. The FPGA
design process is started by the user providing a Hardware Description Language (HDL)
definition or a schematic design. Common HDLs are VHDL (where VHDL stands
for VHSIC Hardware Description Language) and VERILOG. Once this has been completed
the next task in the FPGA design process is to produce a netlist which is generated for
the particular FPGA family being used. This describes the connectivity required within
the FPGA and it is generated using an electronic design automation tool(Xilinx
VIVADO).The netlist can then be fitted to the actual FPGA architecture using a process
called place-and-route, usually performed by the FPGA company's proprietary place-

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and-route software(Xilinx VIVADO).Finally the design is committed to the FPGA and it
can be used in the electronic circuit board(BASYS3) for which it is intended. Now,
according to Moore’s law the number of transistors on a chip doubles every year. But it
is equally important to be able to use the increased amount of transistors. Thus the
“design productivity gap” increases as the number of transistors on chip increases. The
FPGA technology will help narrow this gap because the gate level design of the
functionalities utilizing the RTL design allows the designer to use the increased number
of transistors optimally. Also the RTL design tools and pre defined test benches along
with the ready to implement test benches allow the design and testing period to be
minimal. The FPGA design platforms have modular intellectual properties(IPs) which are
pre-programmed and tested modules. These can be directly be used in the design by
applying required configuration. Thus all this sum up to considerably decrease time to
market and obtain unmatched performance through the FPGA technology. FPGA is the
future for embedded systems currently in use thus to implement a simple embedded
system on FPGA was our goal. The stepper motor controller is thus implemented on the
XiliinxARTIX7 based BASYS3 board. The controller can control the direction of rotation as
well. The application of this is thus shown by controlling the tap changer assembly of a
tap changing transformer.

1.2 Purpose of Project:

The stepper motor controllers today are based on microcontrollers. The stepper motor
controller consists of a pulse generator and a motor driver. The microcontroller
generates the pulses and sends it to the driver, which make these pulses powerful
enough to drive the motor. The controller can be open loop or closed loop according to
application. The motive of developing this system on a FPGA board is to Ancash the
extensive advantages of FPGA which are discussed before. The FPGA board is powerful
enough to accommodate more such controllers on single chip. One section of the chip
can function as a stepper motor controller and other slices can be employed for various
other applications. As stated before the FPGA board can be coupled with an AI algorithm

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to develop a “smart control system”. The FSM uses two signals “EN” and “DR” as enable
and direction signal to control the stepper motor these signals are simulated through
the switches on the board. But these signals can be signals form sensors as feedback
signals in a closed loop control system. Thus the algorithm can be directly used as a
stepper motor controller in the field just by appropriately selecting sensors in the closed
loop system.

1.3 Components required:

Following are the components used in the project:BASYS3 FPGA board- It is a software
development kit with a very rich peripheral interface at its heart is the Xilinx
Artix7.PMOD STEPPER MOTOR DRIVER- the PMOD STEP provides a four channel drive
for a stepper motor via the ST L293DD.NEMA17 STEPPER MOTOR- It is a stepper motor
with a 1.7X1.7 inch face plate. It can be either used in 4 wire or 6 wire mode.
Transformer with taps at 10,15,20, 24 volts in the secondary winding. Tap changing
assembly model: tap changer assembly made for demonstration purpose on a plywood
base.

1.4 Contents of other chapters:

This project report is subdivided in five chapters. The first chapter gives a brief outlook
of project to the reader. Along with that, it also highlights the significance of the FPGA in
control applications. The second chapter enables us to get a detailed insight of the
hardware used to accomplish the project which includes the working principle, block
diagrams as well as certain important ICs and the devices employed. It also justifies the
need of the particular set of devices used. The third chapter emphasizes on the software
employed in the project. It also gives a comparison of the VERILOG and VHDL languages.
It also encompasses the working of the finite state machine diagram (FSMD) which is

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used to generate the square wave of required duty cycle to drive the stepper motor. It
also introduces the reader to the VIVADO design suite and how RTL design takes place in
it. The fourth chapter elaborates the details and results of the simulation in the VIVADO
design suite, it also makes the reader realise the problems faced while testing the
running of the FSMD generated output and the methodologies employed to trouble
shoot these problems. It also throws light on how the required delay is generated using
the clock division code. A brief description of how to identify the terminals of the
stepper motor is also given. The fifth chapter shows how the FSMD successfully
generated the square waves and how the hardware drives the stepper motor using this
generated square waves. It also highlights the future scope of improvement in the
design and working of the project.

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 Chapter 2

Hardware elucidation

2.1 Components Employed:

The project is accomplished by interconnection of BASYS3 FPGA board with PMOD STEP
through the interfaced ports of the BASYS3.The PMOD is basically a stepper motor driver
employing ST L2993DD motor driver IC. It gives either 4 terminal or 6 terminal output.
The PMOD is required because the FPGA Board does not have the current capacity to
drive the stepper motor. We have employed the Bipolar stepper motor(NEMA17) in 4
wire configuration. So the output of the PMOD is taken from the 4 terminal output pins
of the PMOD. The motor is connected to the PMOD through female-female wire
connectors. We have used a NEMA17 stepper motor which is completely in accordance
to the ratings of the PMOD. The motor shaft rotates a metal beam which supports the
conductor for harnessing different voltages from different tap terminals. The
transformer has a primary supply of 230 volts 50 hertz and four output taps in the
secondary. This transformer is a model of a tertiary winding of a transformer and thus
the tap changing is offload tap changing. If we wish to use this assembly for on-load tap
changing application we would require a ‘make before break’ arrangement and the
assembly needs to be oil immersed.

2.1.1 Appropriateness for this Project:

The PMOD ports are arranged in a 2x6 right-angle, and are 100-mil female connectors
that mate with standard 2x6 pin headers. Each 12-pin PMOD port provides two 3.3V VCC
signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as
shown in Fig. 20. The VCC and Ground pins can deliver up to 1A of current. PMOD data

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signals are not matched pairs, and they are routed using best-available tracks without
impedance control or delay matching. The pins of the PMOD ports of the BASYS3 board
provide only 1A of driving current. The rating of the stepper motor is 2A (APPROX.). Also
the input impedance of the motor is high. So the output of the PMOD pins of BASYS3 are
insufficient to drive the stepper motor. Thus the PMOD step is connected to the output
port of the BASYS3. PMOD step is basically a stepper motor driver. The PMOD step
utilises ST L2993DDs four channel driver to drive stepper motor at high currents then a
system board can typically provide from their logic outputs. ST L2993DD is a push pull
four channel driver with diodes. For more information on PMOD step, refer appendix.

2.1 .2 Working Principle:

The project is all about controlling a stepper motor through FPGA board. The
programming of the FSMD is done in VERILOG HDL language on VIVADO. The
implemented design is then converted into a bit stream and downloaded on the device
through a USB cable. The FSMD controls the stepper motor with two exciting signals
namely ‘EN’ and ‘DR’ which are simulated through the switches available on the BASYS3.
When the user toggles ‘EN’ switch, the motor starts rotating in 1.8 o steps in a direction
which depends on the position of ‘DR’ switch. The output of the FSMD only depends on
the state which is currently activated. With EN high the FSMD changes state according to
the clock frequency derived from ‘clock divider’ program. The stepper motor rotates and
thus the beam rotates. The beam while rotating changes the tap of the transformer. The
transformers tap changer mechanism works on off-load tap changing mechanism.

2.1.3 General Description and Block diagram:

The BASYS 3 is an entry-level FPGA development board designed exclusively for VIVADO

Design Suite, featuring Xilinx Artix-7 FPGA architecture. BASYS 3 is the newest addition
to the popular BASYS line of FPGA development boards, and is perfectly suited for

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students or beginners just getting started with FPGA technology. The BASYS 3 includes
the standard features found on all BASYS boards: complete ready-to-use hardware, a
large collection of on-board I/O devices, all required FPGA support circuits, a free version
of development tools, and at a student-level price point. Due to the migration from the
Spartan-3E family to the Artix-7 class of device, the BASYS 3 offers a substantial increase
in hardware capabilities. With the new Artix FPGA comes 15X the logic cells (from 2,160
to 33,280) and the upgrade from multipliers to true DSP slices. It also adds over 26X the
amount of RAM. The BASYS3 board contains a 32 mega bit non volatile serial flash device
which is attached to the artix7 FPGA using a dedicated quad mode spi bus. FPGA
configuration files can be written on quad SPI files and mode settings are available to
cause the FPGA to automatically read a configuration from this device at power on. An
artix7 configuration file requires just over 2 megabyte of memory living approximately
48% of flash device.

Figure 1 BLOCK DIAGRAM

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From the above project block diagram, we can see how the control signal flows from the
FPGA board to the stepper motor through the PMOD step. The output of the PMOD step
is connected to the stepper motor through four female-female connectors. The output is
in the form of 1000,0100,0010,0001 according to the state of the FSMD implemented in
the BASYS3. Here, we can see that the output of the tap changing transformer is not
connected to any load though the voltages of the taps can be checked through a digital
multimeter. The output can be loaded with any impedance through a DRB or Inductance
or Capacitance box to simulate load if required.

2.2 PMOD step:

The PMOD STEP provides a four channel drive for a stepper motor via the ST L293DD.
Users may wire two pairs of channels in series to drive up to 600 mA of current per
channel and can view the current status of a GPIO signal through a set of user LEDs.
Features:
 Stepper motor driver for 4 and 6-pin motors
 Can drive both motors simultaneously
 Multiple LEDs to indicate signal propagation
 Jumper for optional external power
 Small PCB size for flexible designs 2.8“ × 1.3” (7.1 cm × 3.3 cm)
 2×6-pin PMOD connector with GPIO interface
 Follows Digilent PMOD Interface Specification Type 1

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 Figure 2 PMOD STEP

The PMODSTEP utilizes ST's four channel driver, a L293DD, to drive stepper motors at
higher currents than a system board can typically provide from their logic outputs.
External test point headers and LEDs are provided for easy testing and observation of
the propagation of signals.

2.2.1 INTERFACING WITH PMOD:

The PMODSTEP communicates with the host board via the GPIO protocol. This PMOD
offers headers for both 4-pin and 6-pin stepper motors. Stepper motors work by
alternately energizing the coils to different polarities inducing the stepper motor to
rotate. 4-pin stepper motors only work in the bipolar configuration, requiring that the
two inputs on each electromagnetic coil are brought to the correct logic level voltages to
induce current flow in the correct direction. The 6-pin stepper motor header on this
PMOD can be oriented for either bipolar or unipolar configuration. The two extra pins on
this header provide two positive power pins as a source of current for when an input on
one end of a coil is driven to a logic low voltage level. Any external power applied to the
PMODSTEP must be within 4.5V and 36V; it is recommended that PMOD is operated at
5V.

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 Pin Signa Description
l
1 Sig1 Signal 1
2 Sig2 Signal 2
3 Sig3 Signal 3
4 Sig4 Signal 4
5 Gnd Power Supply Ground
6 Vcc Positive Power Supply
7 Sig5 Signal 5/Output 1 for the Stepper Motor
8 Sig6 Signal 6/Output 1 for the Stepper Motor
9 Sig7 Signal 7/Output 1 for the Stepper Motor
10 Sig8 Signal 8/Output 1 for the Stepper Motor
11 Gnd Power Supply Ground
12 Vcc Positive Power Supply

Table 1. Pin description table

For schematic diagram of PMOD STEP, Refer appendix.

2.2.2 INSIDE OF A PMOD STEP:

This is the block diagram of ST 293DD motor driver IC that runs PMOD STEP. Each of
these triangles is called buffer and they act as switches. When a high voltage (logic high)
is applied to IN pin of one of these buffers, it toggles the OUT pin of the respective buffer
from low to high voltage as well.

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 Figure 3: block diagram of ST L293DD

In a PMOD STEP, the enable pins are hardwired to high voltage so all these buffers are
enabled all the time. The PMOD STEP thus are very simple to use rather than the H
bridges. They make the design hassle free and compatible with BASYS3.

2.3 NEMA17 stepper motor:

Here, we have used NEMA17 stepper motor whose specifications are below:

 Two phase bi-polar hybrid stepper motor

 Model Step Angle-1.8 degree
 Rated Voltage-3.4 volts
 Rated Current-1.7 A
 Phase Resistance- 2 Ohms
 Phase Inductance- 3 mH
 Type- 42BYGHW609

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 Figure 4: NEMA17 stepper motor

NEMA stands for national electrical manufacturing association. It defines the standards
used in North America for various grades of electrical enclosure typically used in
industrial applications. The motor has dimensions of enclosure as 1.7X1.7 inches which
has a code ‘17’ according to NEMA standards. The motor selected here has a rated
voltage of 3.4V and the output of the PMOD STEP is also 3.3-3.4V. Also the rated current
of the motor is 1.7A DC. The output of PMOD also has a current rating of about 2A. The
motor has a holding torque of 3.5 milli Newton metre. The stepper motor has to drive
the beam which might be weighing 500 grams. So the torque of the motor is appropriate
to drive such a load. It can even drive heavier beams for larger tap changer assembly.
The ratings of the motor are in complete harmony with the ratings of the motor driver.
Further, it can even drive heavier loads then load used here. Thus, this motor was
selected for this application.

2.3.1 UNIPOLAR versus BIPOLAR stepper motor:

Both unipolar and bipolar stepper motors are widely used. However, they have their
own advantages and disadvantages from application point of view. The advantage of
unipolar stepper motor is that we do not have to use a complex H bridge circuit to
control the stepper motor. Only a simple driver like ULN2003A will do the task
satisfactorily. But there is a disadvantage of unipolar stepper motors, the torque
generated is quite less. This is because the current is only flowing through the half
winding. Hence they are used in low torque applications. On the other hand, the bipolar

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stepper motor are little complex to wire because we use a current reversing H bridge
driver IC like L293DD. But the advantage is that the current will flow through the full coil.
The resulting torque generated by the motor is larger as compared to a unipolar motor.

2.4. TAP CHANGING TRANSFORMER:

Regulating the voltage of a transformer is a requirement that often arises in a power

application or power system. Below is the figure of the tap changing transformer:

Figure 5: tap changing transformer

In an application it may be needed

 To supply a desired voltage to the load.

 To counter the voltage drops due to loads.

 To counter the input supply voltage changes on load.

On a power system the transformers are additionally required to perform the task of
regulation of active and reactive power flows. The tap-changing transformer is designed

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in such a way that it has 4 taps are at 100% , 83.33% , 62.5% , 41.66% of the winding.
The tap changing assembly is used to obtain a variable voltage of the winding for
compensating various purposes which is listed above. The stepper motor thus actuates
this tap changing assembly.

2.5 BASYS3:

The BASYS 3 board is a complete, ready-to-use digital circuit development platform

based on the latest Artix7 Field Programmable Gate Array (FPGA) from Xilinx.

Figure 6: BASYS3 board

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With its high-capacity FPGA (Xilinx part number XC7A35T1CPG236C), low overall cost,
and collection of USB, VGA, and other ports, the BASYS 3 can host designs ranging from
introductory combinational circuits to complex sequential circuits like embedded
processors and controllers. It includes enough switches, LEDs, and other I/O devices to
allow a large number of designs to be completed without the need for any additional
hardware, and enough uncommitted FPGA I/O pins to allow designs to be expanded
using Digilent PMODs or other custom boards and circuits. The Artix-7 FPGA is optimized
for high performance logic, and offers more capacity, higher performance, and more
resources than earlier designs. Artix-7 35T features include:

 33,280 logic cells in 5200 slices (each slice contains four 6-input LUTs and 8 flip-
flops).
 1,800 Kbits of fast block RAM.
 Five clock management tiles, each with a phase-locked Loop (PLL) 90 DSP slices.
 Internal clock speeds exceeding 450MHz
 On-chip analog-to-digital converter (XADC)

2.5.1 OSCILATORS/CLOCKS:

The BASYS 3 board includes a single 100 MHz oscillator connected to pin W5 (W5 is a
MRCC input on bank 34). The input clock can drive MMCMs or PLLs to generate clocks of
various frequencies and with known phase relationships that may be needed throughout
a design. Some rules restrict which MMCMs and PLLs may be driven by the 100 MHz
input clock. For schematic diagram, refer appendix.

2.6 ARTIX7:

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2.6.1 Defining the Parts of an FPGA

Every FPGA chip is made up of a finite number of predefined resources with

programmable interconnects to implement a reconfigurable digital circuit and I/O blocks
to allow the circuit to access the outside world.

Figure 7: The Different Parts of an FPGA

FPGA resource specifications often include the number of configurable logic blocks,
number of fixed function logic blocks such as multipliers, and size of memory resources
like embedded block RAM. Of the many FPGA chip parts, these are typically the most
important when selecting and comparing FPGAs for a particular application.

The configurable logic blocks (CLBs) are the basic logic unit of an FPGA. Sometimes
referred to as slices or logic cells, CLBs are made up of two basic components: flip-flops
and lookup tables (LUTs). Various FPGA families differ in the way flip-flops and LUTs are
packaged together, so it is important to understand flip-flops and LUTs.

2.6.2 Lookup Tables (LUTs)

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Much of the logic in a CLB is implemented using very small amounts of RAM in the form
of LUTs. It is easy to assume that the number of system gates in an FPGA refers to the
number of NAND gates and NOR gates in a particular chip.

Figure 8: Four-Input LUT

But, in reality, all combinatorial logic (ANDs, ORs, NANDs, XORs, and so on) is
implemented as truth tables within LUT memory. A truth table is a predefined list of
outputs for every combination of inputs.

2.6.3 ARTIX7 AS PROGRAMMABLE LOGIC CONTROL:

Artix-7 devices deliver the industry’s most optimized transceivers, highest performance,
and lowest power. This family is the perfect fit for cost-sensitive applications that need
high-end features. The Artix-7 family is the industry’s cost-optimized performance leader
in nearly every category of performance, including logic fabric, signal processing,
embedded memory, LVDS I/O, memory interfaces, and in particular, transceivers.

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 Figure 9 Artix7 as a PLC

Employing the Artix-7 FPGA and Xilinx IP solutions enables a smaller form factor
programmable logic controller (PLC) with greater flexibility, lower BOM cost, and lower
power consumption compared to traditional architectures. Serving as a companion
device to the main processor, the FPGA replaces communication expansion modules.

 Micro Blaze 32-bit processor for real-time control off loads Industrial Ethernet
tasks from main CPU.
 High-performance, high-precision motor control drive functions.
 Isolation Design Flow to separate safe and non-safe hardware functions in a
single device.
 Small footprint (15x15mm) and single-chip solution for small form factor
modules.
 High-density I/O support for maximum connectivity.
 Reprogrammable fabric for upgradeability and future-proof design.

Chapter 3

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 Software Description

This chapter includes firstly how to activate peripherals of BASYS3. Then it gives brief
comparison between VERILOG and VHDL as RTL- design tools. Then it explains why we
prefer VERILOG for this application. Then there is detailed explanation of the FSMD
which is the core of the program which generates the square wave for driving the
stepper motor. Section 3.4 describes the flow chart of the design procedure of digital
design. It also includes the advantages of the RTL design over other abstraction levels.
The last section deals with the VIVADO design suite the platform on which the code is
synthesized, implemented, and tested through the simulation.

3.1BASYS3 Peripherals:
To use the peripherals and IOs of the BASYS3 FPGA board, we have to use an XDC file.
We have to uncomment the respective declaration in the XDC file to activate an IO or
Peripheral. The excitation signal/variable which will trigger IO or peripheral must have a
same declaration name as in the code. The signals generated by the implemented design
thus trigger the respective activated peripherals. In our case, two switches are used as
inputs to FSMD. An internal clock is generated which controls the timing of the FSMD
and the output of the FSMD triggers the PMOD ports of the board. If the variable names
the declaration and the square brackets of the XDC code are different then there occurs
an error and the bit stream is not downloaded on the device.

3.2 VERILOG v/s VHDL

VERILOG and VHDL are Hardware Description languages that are used to write programs
for electronic chips. These languages are used in electronic devices that do not share a
computer’s basic architecture. VHDL is the older of the two, and is based on ADA and
Pascal, thus inheriting characteristics from both languages. VERILOG is relatively recent,
and follows the coding methods of the C programming language. VHDL is a strongly

19
typed language, and scripts that are not strongly typed, are unable to compile. A
strongly typed language like VHDL does not allow the intermixing, or operation of
variables, with different classes. VERILOG uses weak typing, which is the opposite of a
strongly typed language. Another difference is the case sensitivity. VERILOG is case
sensitive, and would not recognize a variable if the case used is not consistent with what
it was previously. On the other hand, VHDL is not case sensitive, and users can freely
change the case, as long as the characters in the name, and the order, stay the same. In
general, VERILOG is easier to learn than VHDL. This is due, in part, to the popularity of
the C programming language, making most programmers familiar with the conventions
that are used in VERILOG. VHDL is a little bit more difficult to learn and program. Both
have advantages and disadvantages. VHDL is more academic, verbose and complex. You
have to write more code, but the rigor means it's more likely to work. VERILOG is
simpler for typical digital design, but makes it easier to create tricky bugs. VHDL is more
common at universities. VERILOG is more common in big semiconductor companies.
Usually the choice of one or the other is driven by the tools you are using. Some of the
popular FPGA tools do better with VHDL. Some popular ASIC tools do better with
VERILOG.

3.2.1 Need of VERILOG

VERILOG HDL has evolved as a standard hardware description language. VERILOG HDL
offers many useful features. VERILOG HDL is a general-purpose hardware description
language that is easy to learn and easy to use. It is similar in syntax to the C
programming language. Designers with C programming experience will find it easy to
learn VERILOG HDL. VERILOG HDL allows different levels of abstraction to bemixed in the
same model. Thus, a designer can define a hardware model in terms of switches, gates,
RTL, or behavioral code. Also, a designer needs to learn only one language for stimulus
and hierarchical design. Most popular logic synthesis tools support VERILOG HDL. This
makes it the language of choice for designers. All fabrication vendors provide VERILOG
HDL libraries for post logic synthesis simulation. Thus, designing a chip in VERILOG HDL
allows the widest choice of vendors. The Programming Language Interface (PLI) is a

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powerful feature that allows the user to write custom C code to interact with the
internal data structures of VERILOG. Designers can customize a VERILOG HDL simulator
to their needs with the PLI.The FSMD is implemented in VERILOG language using IF-ELSE
cases. The structures and syntax of the VERILOG are very similar to the C language. Also
the programming is not done at gate level so the digital structure of the implementation
is not required. The VHDL is excellent for description of the logic gate level
programming. It is very straight forward to define data of required data type and
number of bits (if binary). So it is very handy to program the clock-divider code in
VERILOG than in VHDL.VHDL also has IF-ELSE but to perform certain arithmetic
operation on data requires libraries and may be error prone. The C language type
structure of the VERILOGis very efficient for arithmetic operations. Thus it was much
easier for us to write the clock-divider program in VERILOG than VHDL.

3.3 FSM Diagram:

The below is the finite state machine diagram which is implemented in VERILOG code.
The FSMD is a Moore state machine i.e. its output only depends on the current state of
the machine.

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 Figure 10: FSMD

The Moore machine a synchronous machine which gets a clock from the clock divider
code. The frequency of change of state when ‘EN’ is high thus corresponds to the clock
frequency. The state machine comprises of 5 states out of which one is an idle state and
has an output ‘0000’ i.e. no output. The other four states are the states for which one of
the bit, out of the four bits output is high. These four output bits are fed to the stepper
motor. The state machine works on two input signals ‘EN’ and ‘DR’ Enable and direction
respectively. The enable signal is the signal which keeps the four states switching on
each clock pulse. The machine keeps on changing the states on each clock pulse. The
fifth state is an idle state. The machine jumps to this state from the current state in the
Next clock pulse if the ‘EN’ signal is low i.e. a negative edge is sensed. The machine
remains in this state till ‘EN’ is low and positive edge is sensed. The outputs of the four
states are in a sequence 1000,0010,0100,0001 which allows a stepper motor to rotate in

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the selected direction in ‘full step’ mode. The other input control signal is the ‘DR’ i.e.
direction signal governs the sequence in which the states are switched on each clock
pulse. The sequence of the changing state and thus the output of the machine reverses
when ‘DR’ is toggled. So the motor starts rotating in the reverse. The whole state
machine is implemented using IF ELSE structure in VERILOG language. Refer appendix for
the code.

3.4 RTL-FPGA design:

The design flow shown in Figure 10 is typically used by designers who use HDLs. In any
design, specifications are written first. Specifications describe abstractly the
functionality, interface, and overall architecture of the digital circuit to be designed. At
this point, the architects do not need to think about how they will implement this circuit.
A behavioral description is then created to analyze the design in terms of functionality,
performance, and compliance to standards, and other high-level issues. Behavioral
descriptions are often written with HDLs.

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 Figure 11: Typical design flow

Register Transfer Level (RTL) is an abstraction for defining the digital portions of a
design. It is the principle abstraction used for defining electronic systems today and
often serves as the golden model in the design and verification flow. The RTL design is
usually captured using a hardware description language (HDL) such as VERILOG or VHDL.
While these languages are capable of defining systems at other levels of abstraction, it is
generally the RTL semantics of these languages, and indeed a subset of these languages
defined as the synthesizable subset. This means the language constructs that can be
reliably fed into a logic synthesis tool which in turn creates the gate-level abstraction of
the design that is used for all downstream implementation operations.RTL is based on
synchronous logic and contains three primary pieces namely, registers which hold state

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information, combinatorial logic which defines the nest state inputs and clocks that
control when the state changes.

3.4.1 Need of RTL-FPGA design:

VERILOG supports designing at many different levels of abstraction. Three of them are
very important:

Behavioral level -This level describes a system by concurrent algorithms (Behavioral).

Each algorithm itself is sequential, that means it consists of a set of instructions that are
executed one after the other. Functions, Tasks and Always blocks are the main elements.
There is no regard to the structural realization of the design.

Register-Transfer Level -Designs using the Register-Transfer Level specify the

characteristics of a circuit by operations and the transfer of data between the registers.
An explicit clock is used. RTL design contains exact timing bounds: operations are
scheduled to occur at certain times. Modern RTL code definition is "Any code that is
synthesizable is called RTL code".

Gate level-Within the logic level the characteristics of a system are described by logical
links and their timing properties. All signals are discrete signals. They can only have
definite logical values (`0', `1', `X', `Z`). The usable operations are predefined logic
primitives (AND, OR, NOT etc gates). Using gate level modelling might not be a good idea
for any level of logic design. Gate level code is generated by tools like synthesis tools and
this netlist is used for gate level simulation and for backend.

Today's designers are mainly working on register-transfer-level when designing the

functions, architectures, and communication of complex digital systems and synthesizing
their designs into gate-level implementations. However, many of them still need to
spend a significant amount of time in gate-level implementations because some design
issues can only be discovered and resolved at the gate-level. These issues include
debugging, verification, timing optimization, and design changes without re-synthesis.

25
Invariably, gate-level implementations are too complex for designers to fully understand
and they are often left to cling precariously to a manually annotated golden RTL
reference models while attempting to navigate the gate-level implementations. When a
modification is needed, sometime the designers will have to manually change the gate-
level implementations, or both, resulting in the destruction of the guaranteed
correspondence. There obviously exists a knowledge gap between the two different
levels of abstraction. Correlating design objects between these two abstraction levels
becomes critical in the design flow. As technology advances at a rapid rate and designs
are getting more complex every day, the need for an effective and efficient correlation
toolset increases greatly.

3.5 VIVADO Suite:

VIVADO Design Suite is a software suite produced by Xilinx for synthesis and analysis of
HDL designs, superseding Xilinx ISE with additional features for system on a chip
development and high-level synthesis.

What is the VIVADO Design Suite?

The VIVADO Design Suite is designed to improve productivity. This tool suite is
architected to increase the overall productivity for designing, integrating, and
implementing systems. Xilinx devices are now much larger and come with a variety of
new technology, including stacked silicon interconnect (SSI) technology, up to 28
gigabyte (GB) high speed I/O interfaces, hardened microprocessors and peripherals,
analog mixed signal, and more. These larger and more complex devices create
multidimensional design challenges, when handled incorrectly, that can prevent the
achievement of faster time-to-market and increased productivity. With the VIVADO
Design Suite, you can accelerate design implementation with place and route tools that
analytically optimize for multiple and concurrent design metrics, such as timing,
congestion, total wire length, utilization and power. The VIVADO Design Suite provides
you with design analysis capabilities at each design stage. This allows for design and tool
setting modifications earlier in the design processes where they have less overall

26
schedule impact, thus reducing design iterations and accelerating productivity. The
VIVADO Design Suite replaces the existing Xilinx ISE® Design Suite of tools. It replaces all
of the ISE Design Suite point tools, such as Project Navigator, Xilinx Synthesis Technology
(XST), implementation, CORE Generator™ tool, Timing Constraints Editor, ISE Simulator
(ISim), ChipScope Analyzer, Xilinx Power Analyzer, FPGA Editor, PlanAhead design tool,
and SmartXplorer. All of these capabilities are now built directly into the VIVADO Design
Suite and leverage a shared scalable data model. Built on the shared scalable data model
of the VIVADO Design Suite, the entire design process can be executed in memory
without having to write or translate any intermediate file formats, which accelerates run
times, debug, and implementation while reducing memory requirements. All of the
VIVADO Design Suite tools are written with a native tool command language (Tcl)
interface. All of the commands and options available in the VIVADO Integrated Design

Environment (IDE), which is the graphical user interface (GUI) for the VIVADO Design
Suite, is accessible through Tcl. The VIVADO Design Suite also provides powerful access
to the Design data for reporting and configuration as well as the tool commands and
options. You can interact with the VIVADO Design Suite using:

• GUI-based commands in the VIVADO IDE

• Tcl commands entered in the Tcl Console in the VIVADO IDE, in the VIVADO Design
Suite Tcl shell outside the VIVADO IDE, or saved to a Tcl script file that is run either in the
VIVADO IDE or in the VIVADO Design Suite Tcl shell.

• A mix of GUI-based and Tcl commands.

27
 Chapter 4

Simulation and Testing

4.1 VIVADO simulation results:

After running the code in the VIVADO and following all the steps which include running
synthesis, running simulation and running implementation gives the implemented
design. We can stimulate a forced clock and also simulate both the control signal ‘EN’
and ‘DR’ in the software before generating the bit stream and downloading in the
hardware. The waveforms generated after running the code in the hardware must be
similar to the waveforms obtained here.

The figure (15) shows the simulation results of the state machine program. The four
output signals are clearly seen to follow a sequence that will allow the motor to run in
clockwise direction.

figure 15 Clockwise direction

28
The four output signals are square wave with each signal time shifted so that at a given
instant only one out of the four outputs is high. The 'EN' and 'DR' are forced at constant
values to give these simulation results.

The simulation result shown in figure (16) is obtained by toggling the direction signal to a
value which is the compliment of the previous value (simulated by changing of the
switch on the hardware).

figure 16 Anticlockwise direction

The graph clearly depicts the reverse order of occurrence of square waves on the
respective output nets.

The figure (17) shows the interconnection of modules namely clock_division and
PMOD_step_interface modules with all the control signals.

29
 figure 17 block diagram design

The four output signals are shown as buffer outputs.

4.1.1UTILISATION OF THE ARTIX7 FPGA:

From the simulation results obtained in the VIVADO it is observed that only 1% of the
total available LUTs are utilized in the running of this project. Also only 1% of the total
filp-flops available in the ARTIX7 FPGA are utilized. Further it is observed that only 8% of
i/o s are utilized. Thus, we conclude that many more such stepper motor controlling
modules can be synthesized on the board. After implementing the design still there are
enough slices available for multiple applications which the user desires.

30
Figure: 12 Hardware utilisation of FPGA

31
 Figure 13 Hardware appearance

Figure 14 slice arrangement in FPGA

32
4.2 PROBLEMS FACED:

After solving all the syntax errors in the code the bit stream was finally generated and
downloaded on the hardware. The PMOD was then connected to the second PMOD port
of the board as configured by the XDC file. The stepper motor is then connected to the
PMOD step. Now when the enable ‘EN’ switch was toggled to logic 1 the motor should
have rotated. But instead of rotating the motor shaft started oscillating. The motor shaft
did not rotate even when the direction switch ‘DR’ toggled, it still oscillated. The code
was checked multiple times for any logical or syntax error. The wire’s connectivity were
also checked but the problem still persisted.

4.3 TROUBLESHOOTING:

The motor shaft’s oscillations created a suspicion that PMOD output signals were unable
to drive the stepper motor. But on double checking the ratings of both the motor and
PMOD step it was clear that the ratings were in complete correspondence. So the input
resistance on the terminals of motor was checked. The input resistance was found to be
the same as the rated value. The inductance of the windings was checked through the
motor terminals, they were also found to be nearly 3 mH, which is the rated inductance.
So it is inferred that there was nothing wrong with the windings of the motor. Now while
the system was connected and running the waveforms were checked on a digital signal
oscillator. It was found that this square wave was perfectly of 3.3 volts at the output of
the PMOD step when it is unconnected to the motor. As soon as the motor was
connected to PMOD step the square wave got distorted and its value reduces to
somewhere around 2 volts. Now we observed the wiring found that a wire’s exterior
shield was cracked, so the wires were changed with new once. But still the motor was
oscillated. When the signal was checked again on the digital signal oscillator it was found

33
that the duty cycle of signal was low and it might be insufficient to generate the large
starting torque required by the stepper motor. So the delay generated by the clock
divider was increased to get approximately 40% duty cycle. Now it was observed that
due to the increased duty cycle and frequency the motor rotated. But the motor rotated
with a lower speed, so the frequency was adjusted through the clock divider code to get
a satisfying rotating speed.

4.4 IDENTIFYING THE STEPPER MOTOR TERMINALS:

The NEMA 17 stepper motor has six terminals but we need only four terminals to drive
the stepper motor in the full step mode. The other two terminals would be required
when the motor is required to be run in half step mode. The full step angle of the motor
is 1.8 degrees. So it is important to identify the terminal to which the four wires to the
from the PMOD step are to be connected. The identification of the terminals was done
using a digital multimeter. The multimeter was set in the continuity checking mode and
we found that the terminals 1 and 4, 3 and 6 are shorted. Thus the four wires were to be
connected in the sequence 1, 3, 4 and 6. The numbering are given from left to right.

4.5 CLOCK DIVISION:

The clock division code has a basic function to divide the clock of 100 MHz on which the
board works to a frequency which can be used for driving the FSMD. The code works by
defining a constant ‘define speed’. The constant is a 26 bit number which is incremented
by 1 on every clock pulse of the board. The clock division code is required because the
100 MHz frequency is too high for the implementation in the FSMD. The clock division is
achieved using a counter with a 26 bit initial value incremented by 1 every clock pulse.
When the value reaches the highest value represented by the 26 bit number, the
derived clock value ‘new_clock’ is toggled every time the counter has completed
counting. Thus reduced clock frequency is obtained. The counter variable ‘define_speed’

34
can be varied to change the rate of state changing in the FSMD and thus the rate of
rotation of the stepper motor.

The formula for deciding the value of the ‘define_speed’ variable for obtaining the
desired working speed of the FSMD is

100 × 106
Define_speed = Hz
2×(desired ¿ )

Now, the working clock frequency chose for working of code is 10Hz. replacing the value
of 10Hz in desired_clock_frequency. We get the value ’50000000’ as define_speed. This
value gives a speed a speed of 3 rpm for the motor.

The motor speed has 3 modes. The first mode is a high speed mode in which the motor
rotates at 3 rpm. In second mode the motor rotates at 2 rpm. In the third mode, the
motor rotates at very slow speed. The third mode is very important for the adjustment
purposes. Suppose the motor misses a particular terminal then this mode can be used to
precisely position the motor at a point.

In an automatic system, if a sensor failure occurs and the motor need to be positioned
manually then, this mode is employed. Two push buttons are used as the inputs to use
this these two specific modes.

35
 Chapter 5

Result and Summary

5.1 Results:

After troubleshooting the problem faced initially the motor was smoothly rotating in
both directions. The software was successfully implemented on the hardware. The finite
state machine diagram which controls the transition of output of the PMOD step to
drive the stepper motor is thus implemented on the hardware successfully.
This stepper motor rotates and thus the taps change. But when the beam connected to
the motor shaft reaches a tap we have to toggle the enable switch ‘EN’ manually to stop
the motor at the tap because we have simulated the enable signal is coming from the
field. This is a drawback. Thus we have successfully implemented this stepper motor
controller on the FPGA board.

Figure 18 The square wave driving the stepper motor

36
Figure 16 shows the square wave which drives the stepper motor. The rated voltage
required to drive the stepper motor is 3.3v. The square wave is thus able to drive the
motor. As seen from the figure 16 the frequency of the wave is 10Hz which is in
accordance to the delay calculation from the clock divider code.

5.2 Conclusion:

From this project, we learned that a common embedded system like the stepper motor
controller can be implemented efficiently on a FPGA chip with just one percent of the
LUTs and one percent of flip flops utilised from the total of 33,200 logic slices. Thus,
leaving a very large room for implementing other embedded systems on the same chip.
We have also generated an alternate algorithm to control a stepper motor using digital
design of a Moore state machine. We also learned how to derive usable clock frequency
from the chip working frequency which is very high. The derived frequency from very
high working frequency of ARTIX7 thus can be used to control the speed of revolution of
the stepper motor because the speed of revolution of the stepper motor depends on the
rate at which the state machine changes its state when the enable signal is high.

5.3 Scope of Improvement

The direction and enable signals were simulated through the switches present on the
FPGA board but we can make a fully automatic tap changing assembly using a sensor
which senses the position of the beam and when it approaches the tap the feedback
signal will automatically toggle the enable signal from high to low and thus stop the
motor precisely at tap position. When the tap needs to be changed, the enable signal
will automatically be triggered from low to high by the system.In high voltage
applications, the changing of taps with stepper motor can cause sparks when the taps
are changed but this can be avoided using a ‘make before break’ mechanism but this will

37
make design complex. The design used here is a very simple rotating beam supporting
the conductor for the tap changing.

38
 APPENDIX A

BASYS3 DATASHEET

Overview

The BASYS 3 board is a complete, ready-to-use digital circuit development platform

based on the latest Artix®-7 Field Programmable Gate Array (FPGA) from Xilinx®. With its
high-capacity FPGA (Xilinx part number XC7A35T- 1CPG236C), low overall cost, and
collection of USB, VGA, and other ports, the BASYS 3 can host designs ranging from
introductory combinational circuits to complex sequential circuits like embedded
processors and controllers. It includes enough switches, LEDs, and other I/O devices to
allow a large number of designs to be completed without the need for any additional
hardware, and enough uncommitted FPGA I/O pins to allow designs to be expanded
using Digilent PMODs or other custom boards and circuits.
The Artix-7 FPGA is optimized for high performance logic, and offers more capacity,
higher performance, and more resources than earlier designs. Artix-7 35T features
include:

 33,280 logic cells in 5200 slices (each slice contains four 6-input LUTs and 8 flip-
flops)
 1,800 Kbits of fast block RAM
 Five clock management tiles, each with a phase-locked loop (PLL) 90 DSP slices
 Internal clock speeds exceeding 450MHz
 On-chip analog-to-digital converter (XADC)

The BASYS 3 works with Xilinx's new high-performance Vivado™ Design Suite. Vivado
includes many new tools and design flows that facilitate and enhance the latest design
methods. It runs faster, allows better use of FPGA resources, and allows designers to

39
focus their time evaluating design alternatives. The System Edition includes an on-chip
logic analyzer, high-level synthesis tool, other cutting-edge tools, and the free
WebPACK™ version allows BASYS 3 designs to be created at no additional cost.

Power Supplies

The BASYS 3 board can receive power from the Digilent USB-JTAG port (J4) or from a
5V external power supply. Jumper JP3 (near the power switch) determines which
source is used. All BASYS 3 power supplies can be turned on and off by a single logic-
level power switch (SW16). A power-good LED (LD20), driven by the "power good"
output of the LTC3633 supply, indicates that the supplies are turned on and operating
normally.
The USB port can deliver enough power for the vast majority of designs. A few
demanding applications, including any that drive multiple peripheral boards, might
require more power than the USB port can provide. Also, some applications may need
to run without being connected to a PC's USB port. In these instances an external
power supply or battery pack can be used. An external power supply can be used by
plugging into the external power header (J6) and setting jumper JP2 to "EXT". The
supply must deliver 4.5VDC to 5.5VDC and at least 1A of current (i.e., at least 5W of
power). Many suitable supplies can be purchased through Digi-Key or other catalog
vendors. An external battery pack can be used by connecting the battery's positive
terminal to the "EXT" pin of J6 and the negative terminal to the "GND" pin of J6. The
power provided to USB devices that are connected to Host connector J2 is not
regulated. Therefore, it is necessary to limit the maximum voltage of an external
battery pack to 5.5V DC. The minimum voltage of the battery pack depends on the
application; if the USB Host function (J2) is used, at least 4.6V needs to be provided. In
other cases, the minimum voltage is 3.6V. Voltage regulator circuits from Linear
Technology create the required 3.3V, 1.8V, and 1.0V supplies from the main power
input.

FPGA Configuration

40
After power-on, the Artix-7 FPGA must be configured (or programmed) before it can
perform any functions. You can configure the FPGA in one of three ways: 1. A PC can
use the Digilent USB-JTAG circuitry (portJ4, labelled "PROG") to program the FPGA any
time the power is on. 2. A file stored in the non-volatile serial (SPI) flash device can be
transferred to the FPGA using the SPI port. 3. A programming file can be transferred
from a USB memory stick attached to the USB HID port.
The FPGA configuration data is stored in files called bitstreams that have the .bit file
extension. The Vivado software from Xilinx can create bitstreams from VHDL,
VERILOG®, or schematic-based source files. Bitstreams are stored in SRAM-based
memory cells within the FPGA. This data defines the FPGA's logic functions and circuit
connections, and it remains valid until it is erased by removing board power, by
pressing the reset button attached to the PROG input, or by writing a new
configuration file using the JTAG port. An Artix-7 35T bitstream is typically 17,536,096
bits and can take a long time to transfer. The time it takes to program the BASYS 3 can
be decreased by compressing the bitstream before programming, and then allowing
the FPGA to decompress the bitsream itself during configuration. Depending on design
complexity, compression ratios of 10x can be achieved. Bitstream compression can be
enabled within the Xilinx Tools (Vivado) to occur during generation. For instructions
on how to do this, consult the Xilinx documentation for the toolset being used. After
being successfully programmed, the FPGA will cause the "DONE" LED to illuminate.
Pressing the "PROG" button at any time will reset the configuration memory in the
FPGA. After being reset, the FPGA will immediately attempt to reprogram itself from
whatever method has been selected by the programming mode jumper. The following
sections provide greater detail about programming the BASYS 3 using the different
methods available.

JTAG Programming

The Xilinx Tools typically communicate with FPGAs using the Test Access Port and
Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG

41
programming, a .bit file is transferred from the PC to the FPGA using the onboard
Digilent USB-JTAG circuitry (port J4) or an external JTAG programmer, such as the
Digilent JTAG-HS2 attached to port J5 (located below port JA). You can perform JTAG
programming any time after the BASYS 3 has been powered on regardless of what the
mode jumper (JP1) is set to. If the FPGA is already configured, then the existing
configuration is overwritten with the bitstream being transmitted over JTAG. Setting
the mode jumper to the JTAG setting (seen in Fig. 3) is useful to prevent the FPGA
from being configured from any other bitstream source until a JTAG programming
occurs. Programming the BASYS 3 with an uncompressed bitstream using the on-
board USB_JTAG circuitry usually takes around five seconds. JTAG programming can
be done using the hardware server in Vivado. The demonstration project available at
digilentinc.com provides an in-depth tutorial on how to program your board.

JTAG Programming

When programming a nonvolatile flash device, a bitstream file is transferred to the

flash in a two-step process. First, the FPGA is programmed with a circuit that can
program flash devices, and then data is transferred to the flash device via the FPGA
circuit (this complexity is hidden from the user by the Xilinx Tools). After the flash
device has been programmed, it can automatically configure the FPGA at a
subsequent power-on or reset event as determined by the mode jumper setting .
Programming files stored in the flash device will remain until they are overwritten,
regardless of power-cycle events. Programming the flash can take as long as one or
two minutes, which is mostly due to the lengthy erase process inherent to the
memory technology. Once written, however, FPGA configuration can be very fast –
less than a second. Bitstream compression, SPI bus width, and configuration rate are
factors controlled by the Xilinx Tools that can affect configuration speed. Quad-SPI
programming can be performed using Vivado.

USB Host Programming

42
You can program the FPGA from a pen drive attached to the USB-HID port (J2) by
doing the following:
1. Format the storage device (Pen drive) with a FAT32 file system.
2. Place a single .bit configuration file in the root directory of the storage device.
3. Attach the storage device to the BASYS 3.
4. Set the JP1 Programming Mode jumper on the BASYS 3 to "USB".
5. Push the PROG button or power-cycle the BASYS 3.
The FPGA will automatically be configured with the .bit file on the selected storage
device. Any .bit files that are not built for the proper Artix-7 device will be rejected by
the FPGA. The Auxiliary Function Status, or "BUSY" LED (LD16), gives visual feedback
on the state of the configuration process when the FPGA is not yet programmed:
1.When steadily lit, the auxiliary microcontroller is either booting up or currently
reading the configuration medium (pen drive) and downloading a bit stream to the
FPGA.
2. A slow pulse means the microcontroller is waiting for a configuration medium to be
plugged in
3. In case of an error during configuration, the LED will blink rapidly.

When the FPGA has been successfully configured, the behavior of the LED is
application-specific. For example, if a USB keyboard is plugged in, a rapid blink will
signal the receipt of an HID input report from the keyboard.

Memory

The BASYS 3 board contains a 32Mbit non-volatile serial Flash device, which is
attached to the Artix-7 FPGA using a dedicated quad-mode (x4) SPI bus. FPGA
configuration files can be written to the Quad SPI Flash (Spansion part number
S25FL032), and mode settings are available to cause the FPGA to automatically read a
configuration from this device at power on. An Artix-7 35T configuration file requires
just over two Mbytes of memory, leaving approximately 48% of the flash device
available for user data.

43
Oscillators/Clocks

The BASYS 3 board includes a single 100 MHz oscillator connected to pin W5 (W5 is a
MRCC input on bank 34). The input clock can drive MMCMs or PLLs to generate clocks
of various frequencies and with known phase relationships that may be needed
throughout a design. Some rules restrict which MMCMs and PLLs may be driven by
the 100 MHz input clock. For a full description of these rules and of the capabilities of
the Artix-7 clocking resources, refer to the "7 Series FPGAs Clocking Resources User
Guide" available from Xilinx. Xilinx offers the LogiCORE™ Clocking Wizard IP to help
users generate the different clocks required for a specific design. This wizard properly
instantiates the needed MMCMs and PLLs based on the desired frequencies and
phase relationships specified by the user. The wizard will then output an easy to use
wrapper component around these clocking resources that can be inserted into the
user's design. The Clocking Wizard can be accessed from within IP Catalog, which can
be found under the Project Manager section of the Flow Navigator in Vivado.

USB-UART Bridge (Serial Port)

The BASYS 3 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J4)
that allows you to use PC applications to communicate with the board using standard
Windows COM port commands. Free USB-COM port drivers, available from
www.ftdichip.com under the "Virtual Com Port" or VCP heading, convert USB packets
to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire
serial port (TXD/RXD). After the drivers are installed, I/O commands can be used from
the PC directed to the COM port to produce serial data traffic on the B18 and A18
FPGA pins. Two on-board status LEDs provide visual feedback on traffic flowing
through the port: the transmit LED (LD18) and the receive LED (LD17). Signal names
that imply direction are from the point-of-view of the DTE (Data Terminal Equipment),
in this case the PC. The FT2232HQ is also used as the controller for the Digilent USB-
JTAG circuitry, but the USB-UART and USB-JTAG functions behave entirely

44
independent of one another. Programmers interested in using the UART functionality
of the FT2232 within their design do not need to worry about the JTAG circuitry
interfering with the UART data transfers, and vice-versa. The combination of these
two features into a single device allows the BASYS 3 to be programmed,
communicated with via UART, and powered from a computer attached with a single
Micro USB cable.

USB HID Host

The Auxiliary Function microcontroller (Microchip PIC24FJ128) provides the BASYS 3

with USB HID host capability. After power-up, the microcontroller is in configuration
mode, either downloading a bit stream to the FPGA or waiting for it to be
programmed from other sources. Once the FPGA is programmed, the microcontroller
switches to application mode, which in this case is USB HID Host mode. Firmware in
the microcontroller can drive a mouse or a keyboard attached to the type A USB
connector at J2 labelled "USB." Hub support is not currently available, so only a single
mouse or a single keyboard can be used. The PIC24 drives several signals into the
FPGA – two are used to implement a standard PS/2 interface for communication with
a mouse or keyboard, and the others are connected to the FPGA's two-wire serial
programming port, so the FPGA can be programmed from a file stored on a USB pen
drive.

HID Controller

The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and
emulates an old-style PS/2 bus. The microcontroller behaves just like a PS/2 keyboard
or mouse would. This means new designs can re-use existing PS/2 IP cores. Mice and
keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to
communicate with a host. On the BASYS 3, the microcontroller emulates a PS/2 device
while the FPGA plays the role of the host. Both the mouse and the keyboard use 11-bit
words that include a start bit, data byte (LSB first), odd parity, and stop bit, but the

45
data packets are organized differently, and the keyboard interface allows bidirectional
data transfers (so the host device can illuminate state LEDs on the keyboard).

The clock and data signals are only driven when data transfers occur; otherwise they are held
in the idle state at logic '1.' This requires that when the PS/2 signals are used in a design,
internal pull-ups must be enabled in the FPGA on the data and clock pins. The clock signal is
normally driven by the device, but may be held low by the host in special cases. The timings
define signal requirements for mouse-to-host communications and bi-directional keyboard
communications. A PS/2 interface circuit can be implemented in the FPGA to create a
keyboard or mouse interface. When a keyboard or mouse is connected to the BASYS 3, a "self-
test passed" command (0xAA) is sent to the host. After this, commands may be issued to the
device. Since both the keyboard and the mouse use the same PS/2 port, one can tell the type
of device connected using the device ID. This ID can be read by issuing a Read ID command
(0xF2). Also, a mouse sends its ID (0x00) right after the "self-test passed" command, which
distinguishes it from a keyboard.

Keyboard

The keyboard uses open-collector drivers so the keyboard, or an attached host device,
can drive the two-wire bus (if the host device will not send data to the keyboard, then
the host can use input-only ports). PS/2-style keyboards use scan codes to
communicate key press data. Each key is assigned a code that is sent whenever the
key is pressed. If the key is held down, the scan code will be sent repeatedly about
once every 100ms. When a key is released, an F0 key-up code is sent, followed by the
scan code of the released key. If a key can be shifted to produce a new character (like
a capital letter), then a shift character is sent in addition to the scan code and the host
must determine which ASCII character to use. Some keys, called extended keys, send
an E0 ahead of the scan code (and they may send more than one scan code). When an
extended key is released, an E0 F0 key-up code is sent, followed by the scan code.

A host device can also send data to the keyboard. The keyboard can send data to the
host only when both the data and clock lines are high (or idle). Because the host is the
bus master, the keyboard must check to see whether the host is sending data before

46
driving the bus. To facilitate this, the clock line is used as a "clear to send" signal. If the
host drives the clock line low, the keyboard must not send any data until the clock is
released. The keyboard sends data to the host in 11-bit words that contain a '0' start
bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit, and
terminated with a '1' stop bit. The keyboard generates 11 clock transitions (at 20 to 30
KHz) when the data is sent, and data is valid on the falling edge of the clock.

Mouse

Once entered in stream mode and data reporting has been enabled, the mouse
outputs a clock and data signal when it is moved. Otherwise, these signals remain at
logic '1.' Each time the mouse is moved, three 11-bit words are sent from the mouse
to the host device, as shown in Fig. 10. Each of the 11-bit words contains a '0' start bit,
followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated
with a '1' stop bit. Thus, each data transmission contains 33 bits, where bits 0, 11, and
22 are '0' start bits, and bits 11, 21, and 33 are '1' stop bits. The three 8-bit data fields
contain movement data as shown in the Fig. 10. Data is valid at the falling edge of the
clock, and the clock period is 20 to 30 KHz.

The mouse assumes a relative coordinate system wherein moving the mouse to the
right generates a positive number in the X field, and moving to the left generates a
negative number. Likewise, moving the mouse up generates a positive number in the
Y field, and moving down represents a negative number (the XS and YS bits in the
status byte are the sign bits – a '1' indicates a negative number). The magnitude of the
X and Y numbers represent the rate of mouse movement; the larger the number, the
faster the mouse is moving (the XV and YV bits in the status byte are movement
overflow indicators – a '1' means overflow has occurred). If the mouse moves
continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R
fields in the status byte indicate Left and Right button presses (a '1' indicates that the
button is being pressed).

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VGA Port

The BASYS3 board uses 14 FPGA signals to create a VGA port with 4-bits per colour
and the two standard sync signals (HS – Horizontal Sync, and VS – Vertical Sync). The
colour signals use resistor-divider circuits that work in conjunction with the 75 ohm
termination resistance of the VGA display to create 16 signal levels each on the red,
green, and blue VGA signals. produces video colour signals that proceed in equal
increments between 0V (fully off) and 0.7V (fully on). Using this circuit, 4096 different
colours can be displayed, one for each unique 12-bit pattern. A video controller circuit
must be created in the FPGA to drive the sync and colour signals with the correct
timing in order to produce a working display system.

VGA System Timing

VGA signal timings are specified, published, copyrighted, and sold by the VESA®
organization. The following VGA system timing information is provided as an example
of how a VGA monitor might be driven in 640 by 480 mode. NOTE: For more precise
information, or for information on other VGA frequencies, refer to documentation
available at the VESA website. CRT-based VGA displays use amplitude-modulated
moving electron beams (or cathode rays) to display information on a phosphor-coated
screen. LCD displays use an array of switches that can impose a voltage across a small
amount of liquid crystal, thereby changing light permittivity through the crystal on a
pixel-by-pixel basis. Although the following description is limited to CRT displays, LCD
displays have evolved to use the same signal timings as CRT displays (so the "signals"
discussion below pertains to both CRTs and LCDs). Color CRT displays use three
electron beams (one for red, one for blue, and one for green) to energize the
phosphor that coats the inner side of the display end of a cathode ray tube.

Electron beams emanate from "electron guns" which are finely-pointed heated
cathodes placed in close proximity to a positively charged annular plate called a "grid."
The electrostatic force imposed by the grid pulls rays of energized electrons from the

48
cathodes, and those rays are fed by the current that flows into the cathodes. These
particle rays are initially accelerated towards the grid, but they soon fall under the
influence of the much larger electrostatic force that results from the entire phosphor-
coated display surface of the CRT being charged to 20kV (or more). The rays are
focused to a fine beam as they pass through the center of the grids, and then they
accelerate to impact on the phosphor-coated display surface. The phosphor surface
glows brightly at the impact point, and it continues to glow for several hundred
microseconds after the beam is removed. The larger the current fed into the cathode,
the brighter the phosphor will glow. Between the grid and the display surface, the
beam passes through the neck of the CRT where two coils of wire produce orthogonal
electromagnetic fields. Because cathode rays are composed of charged particles
(electrons), they can be deflected by these magnetic fields. Current waveforms are
passed through the coils to produce magnetic fields that interact with the cathode
rays and cause them to transverse the display surface in a "raster" pattern,
horizontally from left to right and vertically from top to bottom, As the cathode ray
moves over the surface of the display, the current sent to the electron guns can be
increased or decreased to change the brightness of the display at the cathode ray
impact point. Information is only displayed when the beam is moving in the "forward"
direction (left to right and top to bottom), and not during the time the beam is reset
back to the left or top edge of the display. Much of the potential display time is
therefore lost in "blanking" periods when the beam is reset and stabilized to begin a
new horizontal or vertical display pass. The size of the beams, the frequency at which
the beam can be traced across the display, and the frequency at which the electron
beam can be modulated determine the display resolution. Modern VGA displays can
accommodate different resolutions, and a VGA controller circuit dictates the
resolution by producing timing signals to control the raster patterns. The controller
must produce synchronizing pulses at 3.3V (or 5V) to set the frequency at which
current flows through the deflection coils, and it must ensure that video data is
applied to the electron guns at the correct time. Raster video displays define a number
of "rows" that corresponds to the number of horizontal passes the cathode makes
over the display area, and a number of "columns" that corresponds to an area on each
row that is assigned to one "picture element" or pixel. Typical displays use from 240 to

49
1200 rows and from 320 to 1600 columns. The overall size of a display and the
number of rows and columns determines the size of each pixel.

A VGA controller circuit must generate the HS and VS timings signals and coordinate
the delivery of video data based on the pixel clock. The pixel clock defines the time
available to display one pixel of information. The VS signal defines the "refresh"
frequency of the display, or the frequency at which all information on the display is
redrawn. The minimum refresh frequency is a function of the display's phosphor and
electron beam intensity, with practical refresh frequencies falling in the 50Hz to 120Hz
range. The number of lines to be displayed at a given refresh frequency defines the
horizontal "retrace" frequency. For a 640-pixel by 480-row display using a 25 MHz
pixel clock and 60 +/-1Hz refresh, the signal timings can be derived. Timings for sync
pulse width and front and back porch intervals (porch intervals are the pre- and post-
sync pulse times during which information cannot be displayed) are based on
observations taken from actual VGA displays.

A VGA controller circuit, such as the one diagrammed, decodes the output of a
horizontal-sync counter driven by the pixel clock to generate HS signal timings. You
can use this counter to locate any pixel location on a given row. Likewise, the output
of a vertical-sync counter that increments with each HS pulse can be used to generate
VS signal timings, and you can use this counter to locate any given row. These two
continually running counters can be used to form an address into video RAM. No time
relationship between the onset of the HS pulse and the onset of the VS pulse is
specified, so you can arrange the counters to easily form video RAM addresses, or to
minimize decoding logic for sync pulse generation.

Basic I/O

The BASYS3 board includes sixteen slide switches, five push buttons, sixteen individual
LEDs, and a four-digit seven segment display. The pushbuttons and slide switches are
connected to the FPGA via series resistors to prevent damage from inadvertent short

50
circuits (a short circuit could occur if an FPGA pin assigned to a pushbutton or slide
switch was inadvertently defined as an output). The five pushbuttons, arranged in a
plus-sign configuration, are "momentary" switches that normally generate a low
output when they are at rest, and a high output only when they are pressed. Slide
switches generate constant high or low inputs depending on their position. The
sixteen individual high-efficiency LEDs are anode-connected to the FPGA via 330 ohm
resistors, so they will turn on when a logic high voltage is applied to their respective
I/O pin. Additional LEDs, which are not user accessible, indicate power-on, FPGA
programming status, and USB port status.

Seven-Segment Display

The BASYS 3 board contains one four-digit common anode seven-segment LED display.
Each of the four digits is composed of seven segments arranged in a "figure 8" pattern,
with an LED embedded in each segment. Segment LEDs can be individually
illuminated, so any one of 128 patterns can be displayed on a digit by illuminating
certain LED segments and leaving the others dark. Of these 128 possible patterns, the
ten corresponding to the decimal digits are the most useful.
The anodes of the seven LEDs forming each digit are tied together into one "common
anode" circuit node, but the LED cathodes remain separate, as shown in Fig. 18. The
common anode signals are available as four "digit enable" input signals to the 4-digit
display. The cathodes of similar segments on all four displays are connected into seven
circuit nodes labelled CA through CG (for example, the four "D" cathodes from the
four digits are grouped together into a single circuit node called "CD"). These seven
cathode signals are available as inputs to the 4-digit display. This signal connection
scheme creates a multiplexed display, where the cathode signals are common to all
digits but they can only illuminate the segments of the digit whose corresponding
anode signal is asserted. To illuminate a segment, the anode should be driven high
while the cathode is driven low. However, since the BASYS3 uses transistors to drive
enough current into the common anode point, the anode enables are inverted.
Therefore, both the AN0..3 and the CA..G/DP signals are driven low when active.
A scanning display controller circuit can be used to show a four-digit number on this

51
display. This circuit drives the anode signals and corresponding cathode patterns of
each digit in a repeating, continuous succession at an update rate that is faster than
the human eye can detect. Each digit is illuminated just one-fourth of the time, but
because the eye cannot perceive the darkening of a digit before it is illuminated again,
the digit appears continuously illuminated. If the update, or "refresh", rate is slowed
to around 45Hz, a flicker can be noticed in the display. For each of the four digits to
appear bright and continuously illuminated, all four digits should be driven once every
1 to 16ms, for a refresh frequency of about 1 KHz to 60Hz. For example, in a 62.5Hz
refresh scheme, the entire display would be refreshed once every 16ms, and each
digit would be illuminated for 1/4 of the refresh cycle, or 4ms. The controller must
drive the cathodes low with the correct pattern when the corresponding anode signal
is driven high. To illustrate the process, if AN0 is asserted while CB and CC are
asserted, then a "1" will be displayed in digit position 1. Then, if AN1 is asserted while
CA, CB, and CC are asserted, a "7" will be displayed in digit position 2. If AN0, CB, and
CC are driven for 4ms, and then AN1, CA, CB, and CC are driven for 4ms in an endless
succession, the display will show "71" in the first two digits.

PMOD Ports

The PMOD ports are arranged in a 2x6 right-angle, and are 100-mil female connectors
that mate with standard 2x6 pin headers. Each 12-pin PMOD port provides two 3.3V
VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals,
as shown in Fig. 20. The VCC and Ground pins can deliver up to 1A of current. PMOD
data signals are not matched pairs, and they are routed using best-available tracks
without impedance control or delay matching. Pin assignments for the PMOD I/O
connected to the FPGA

Dual Analog/Digital PMOD

The on-board PMOD expansion port, labelled "JXADC", is wired to the auxiliary analog
input pins of the FPGA. Depending on the configuration, this connector can be used to

52
input differential analog signals to the analog-todigital converter inside the Artix-7
(XADC). Any or all pairs in the connector can be configured either as analog input or
digital input-output. The Dual Analog/Digital PMOD on the BASYS 3 differs from the
rest in the routing of its traces. The eight data signals are grouped into four pairs, with
the pairs routed closely coupled for better analog noise immunity. Furthermore, each
pair has a partially loaded anti-alias filter laid out on the PCB. The filter does not have
capacitors C33-C36. In designs where such filters are desired, the capacitors can be
manually loaded by the user. NOTE: The coupled routing and the anti-alias filters
might limit the data speeds when used for digital signals. The XADC core within the
Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1
MSPS. Either channel can be driven by any of the auxiliary analog input pairs
connected to the JXADC header. The XADC core is controlled and accessed from a user
design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to
voltage monitors that are present on each of the FPGA's power rails, and a
temperature sensor that is internal to the FPGA. For more information on using the
XADC core, refer to the Xilinx document titled "7 Series FPGAs and Zynq-7000 All
Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter.".

Built-In Self-Test

A demonstration configuration is loaded into the SPI Flash device on the BASYS 3
board during manufacturing. The source code and prebuilt bitstream for this design
are available for download from the Digilent website. If the demo configuration is
present in the SPI Flash device and the BASYS 3 board is powered on in SPI mode, the
demo project will allow basic hardware verification. Here is an overview of how this
demo drives the different onboard components:
1.The user LEDs are illuminated when the corresponding user switch is placed in the
on position.
2.The VGA port displays feedback from a USB Mouse.
3.Connecting a mouse to the USB-HID Mouse port will allow the pointer on the VGA
display to be controlled.

53
4.On power-up, each digit of the seven-segment display will display a counter output
from 0-9 that increments once a second.
5.Pressing BTNU, BTNL, BTNR, or BTND will cause a digit of the seven-segment display
to go blank.
6.Pressing BTNC will reset the design.
7.On power-up, a welcome message is sent over the UART. Also, every time a button
is pressed a message is sent. The UART can be connected to using a terminal program
with 9600 Baud, 8 data bits, 1 stop bit, and no parity.
All BASYS3 boards are 100% tested during the manufacturing process. If any device on
the BASYS3 board fails test or is not responding properly, it is likely that damage
occurred during transport or during use. Typical damage includes stressed solder
joints and contaminants in switches and buttons resulting in intermittent failures.
Stressed solder joints can be repaired by reheating and reflowing solder and
contaminants can be cleaned with off-the-shelf electronics cleaning products. If a
board fails test within the warranty period, it will be replaced at no cost.

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 APPENDIX B
BASYS3 SCHEMATIC

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56
57
58
 APPENDIX C
PMOD STEP DATASHEET

Overview

The PMODSTEP provides a four channel drive for a stepper motor via the ST L293DD.
Users may wire two pairs of channels in series to drive up to 600 mA of current per
channel and can view the current status of a GPIO signal through a set of user LEDs.

Functional Description

The PMODSTEP utilizes ST's four channel driver, a L293DD, to drive stepper motor at
higher currents than a system board can typically provide from their logic outputs.
External test point headers and LEDs are provided for easy testing and observation of
the propagation of signals.

Interfacing with the PMOD

The PMODSTEP communicates with the host board via the GPIO protocol.
This PMOD offers headers for both 4-pin and 6-pin stepper motors. Stepper motors
work by alternately energizing the coils to different polarities inducing the stepper
motor to rotate.
4-pin stepper motors only work in the bipolar configuration, requiring that the two
inputs on each electromagnetic coil are brought to the correct logic level voltages to
induce current flow in the correct direction. The 6-pin stepper motor header on this
PMOD can be oriented for either bipolar or unipolar configuration. The two extra pins
on this header provide two positive power pins as a source of current for when an input
on one end of a coil is driven to a logic low voltage level.

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Any external power applied to the PMODSTEP must be within 4.5V and 36V; it is
recommended that PMOD is operated at 5V.

Physical Dimensions

The pins on the pin header are spaced 100 mil apart. The PCB is 2.8 inches long on the
sides parallel to the pins on the pin header and 1.38 inches long on the sides
perpendicular to the pin header.

PMOD schematic

The schematic of PMOD is as below:

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Bibliography

[1] Arvind Kumar and Mrs. Valarmathi, “High Precision Stepper Motor

Controller Implementation on FPGA with GUI on LabVIEW,” in International

Journal of Advanced Research in Electrical, Electronics and Instrumentation
Engineering, Vol.2, Issue 4, April 2013.

[2] “Stepper Motors: Principles, Construction and Drives,” Version 2 EE IIT,

Kharagpur.

[3] “VERILOG HDL: A Guide to Digital Design and Synthesis, Second Edition

by Samir Palnitkar, “Feb. 21, 2003. [Online]. Available:

http://d1.amobbs.com/files_33.

[4] "Electrical and Electronic Measurements and Instrumentation by A.K.

Sawhney"

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