Proceedings of The 29th Annual Conference of the IEEE Industrial Electronics Society Paper # 000291 1

Simple Methods for Detecting Zero Crossing

R.W. Wall, Senior Member, IEEE

crossing nor does it compensate for diode forward voltage

Abstract— Affects of noise, harmonics, and multi-frequency drop.
signal make frequency and period measurements difficult for
synchronizing control events. Various methods are presented to II. ZERO CROSSING MEASUREMENT TECHNIQUES
minimize errors in period and phase measurements. Both
frequency and amplitude domain approaches are analyzed. Post Whether measuring period, frequency, or phase, the sources
detection processing allows greater accuracy. Static and dynamic of errors are the same. When measuring a signal for the
hysteresis as well as interpolation methods of zero-crossing purposes of synchronization, fast and accurate frequency
detection are investigated. measurements are required.[5][6] This requirement also
translates into low phase distortion that can be introduced by
Index Terms— filtering, frequency, hysteresis, interpolation,
period measurement, phase measurement, voltage comparator,
frequency filtering and by measurement delays. The purpose
phase locked loops, zero crossing detection. of the instrumentation circuits and techniques discussed below
are to reduce frequency errors due to multiple zero crossings
I. INTRODUCTION (more than two per period) and reduce phase errors by
advanced or delayed zero crossing.
Z ero crossing detection is the most common method for
measuring the frequency or the period of a periodic
signal. When measuring the frequency of a signal, usually the
Methods that require extensive processing have significant
time delays from when changes of input frequency occur to
when the change is reflected on the output. For this reason,
number of cycles of a reference signal is measured over one or
methods described in this paper exclude highly computational
more time periods of the signal being measured. Measuring
methods including DFT and Wavelet type algorithms. The
multiple periods helps to reduce errors caused by phase noise
discussion methods is limited here to hardware and combined
by making the perturbations in zero crossings small relative to
hardware and software techniques with low process delay.
the total period of the measurement. The net result is an
Although these methods can be applied to any frequency, the
accurate measurement at the expense of slow measurement
discussion here focuses on electric power system applications.
rates.
Zero crossing is the point of choice for measuring phase A. Pre-Detection Low Pass filtering
and frequency. The reference is usually easy to establish and Low pass filtering or band pass filtering helps to restrict the
the signal’s amplitude rate of change is maximum at signal bandwidth to the frequencies close to the frequency of the
zero. Phase synchronized triggering requires placing signal being measured. This technique is well suited for
additional constraints on zero crossing detection. signals that are expected to have small deviations about a
Weidenburg et. al. reviewed several method for synchronizing nominal fixed frequency. It is also well suited for signals
for firing thyristor based power converters and proposed corrupted by harmonics or other periodic signals that are
adaptive online waveform reconstruction.[1] Vainio et. al. sufficiently distinguishable from the signal of interest.
describes a predictive digital filter for noise reduction.[2][3][4] A simple first order filter that can be constructed with a
Depending upon the frequency for a particular application and resistor and capacitor is effective in reducing noise as shown
the degree of signal processing, these methods can require in Fig. 1. The magnitude and phase response for a first- order
high-speed processing components that are too expensive for low pass filter is shown in Fig. 2. The cutoff frequency for
low cost applications. this filter is set for 600 Hz. Although the filter has little effect
Fairchild Semiconductor has developed special purpose on the amplitude, there is significant phase shift at 60 Hz as
integrated circuits for silicon controlled rectifier (SCR) and shown in Fig. 1 which is predictable from the phase at 60 Hz
triac control for low power applications. Such optical-isolated on the filter’s Bode plot shown in Fig. 2.
devices offer an additional advantage of electrical isolation Higher order filters can appear to have zero phase shift but
between instrumentation and gate firing circuits.[4] However, in reality, such filters merely have phase shifts of integer
the design has no provision for mitigating multiple zero multiples of 360 degrees. This is true for both analog and
digital filters. For digital filters, the phase delay is
compounded by process delays.
Richard W. Wall is an Associate Professor in the Department of Electrical
and Computer Engineering at the University of Idaho, Moscow, ID 83844-
1023. (e-mail: [email protected]).
Proceedings of The 29th Annual Conference of the IEEE Industrial Electronics Society Paper # 000291 2

probability that the next zero crossing will be close to the next
half period. The inhibit period must be constrained to allow
natural variations in the input signal.
Digital filtering has the ability to discriminate events based
upon frequency of occurrence just as passive filtering but
overcomes their disadvantages by having high accuracy and
predictability. Such a method is the software implementation
of a phase locked loop (PLL) with feed-forward control
described by Wall and Hess.[5] The phase locked loop does
compensate for advanced or delayed zero crossing detection
due to noise and even, to a degree, that which is caused by
harmonic or alien signal corruption. There is a compromise
between the degree of rejection and the speed of adapting to
new steady state conditions. There is no phase error because
of the nature of the phased locked loop. Capture and lock
dynamics can be dynamically changed if the PLL is
Fig. 1. Filtering signal to eliminate noise
implemented in software. Implementing a feed-forward
algorithm increases the filter’s response to changes in input
frequency.
Low Pass Analog Butterworth Filter
10
The software implementation of the PLL is a second order
digital filter and requires minimal processor capability. The
Microchip PIC16C73B, a microcontroller with 4K word
Phase Shift - degrees

5 program memory and 192 byte RAM, is sufficient to execute

Magnitude - db

the PLL algorithm. Thus it remains a low cost

implementation.
0 A significant improvement in performance can be realized
by using both post processing techniques that allows event
discrimination based on time and frequency. The time
5 discrimination reduces the probability of erroneous zero
crossing detection and the phased locked loop attempts to
average the effect over a long period of time.
10 3
1 10 100 1 .10
Frequency - Hz C. Simple Optical Isolated Semiconductor Devices.
One of the more simple approaches is to use an optical
Fig. 2. Frequency and phase response of a 1st order Butterworth filter with isolator with a Schmitt triggered logical output such as the
cutoff at 600 Hz. TLP2200 in a circuit represented by top half of Fig. 3.[7] The
Filter phase delay can be compensated for mathematically if data sheet for the TLP2200 specify that the LED forward
the filters characteristics are predictable. Unfortunately, filters voltage drop is 1.55 to 1.7vdc with a negative 0.2 mv/ºC
constructed from physical resistors and capacitors have low temperature coefficient. This voltage drop constitutes a phase
accuracy, repeatability, and temperature stability. For the filter shift that is device dependent, input signal level, and
design used in this example, the phase shift is highly temperature dependent. Let the input signal be characterized
dependent on the frequency. This dependency further by (1). The approximate slope of the input signal at the zero
complicates phase compensation techniques. As the cutoff crossing is described by (2). Equation (3) provides the
frequency is increased, the phase shift from filtering is less expression that represents the first order approximation of the
dependent on a specific frequency but the filters effectiveness phase shift as a function of volts around the zero crossing.
for noise reduction is likewise reduced. Thus, for a 12 vac input signal, α equals 3.38 degrees/volt.

B. Post Processing Signal Conditioning x(t ) = Am ⋅ sin (ω t )

( 1)
Multiple outputs for a single zero crossing must be
expected in designs requiring accuracy and precision. Digital s = d (x (t ) ) = ω Am ⋅ cos(ω t ) t = 0 volts / s ( 2)
processing of the output signal does present significant dt
advantages. There are two approaches: rule based and digital
filtering. Rule based design eliminates events that don’t meet
expected timing requirements. This approach inhibits zero
crossing detection for a specified period after an earlier
detection event. This approach relies on the statistical
Proceedings of The 29th Annual Conference of the IEEE Industrial Electronics Society Paper # 000291 3

ω rad / sec 1
α= = rad / volt or 6
ω ⋅ Am volts / sec Am
( 3) 4
180 Out +
α = °angular per volt Out -
π Am 2 Est. Zero

Volts 0
For the TLP2200 optical isolator, this expected zero
crossing detection is 5.233 to 5.739 degrees leading or lagging -2
the actual zero crossing with a 0.6752 angular degree per ºC
-4 Input Sine Signal
temperature coefficient. As (3) reveals, α is inversely
proportional to signal amplitude. Hence for a 120 vac input -6
-0.5 0 0.5
signal, the phases computed above will be only one tenth as Time - ms
great.
D. Zero-Crossing Detection by Interpolation Fig. 4. Oscilloscope capture of the sine wave signal,
optoisolator outputs and computed zero crossing.
The implementation used in this design identifies two
points on the sine wave: the first just before the positive going The voltage drop of the external diodes D1 and D2
zero crossing and the second just after the same zero crossing. combined with the optoisolators internal LEDs cause the
This implementation uses two optoisolators as shown in Fig. 3 optoisolator outputs to switch state before and after that actual
to compensate for variations in level sensitivity and switching zero crossing. Processor algorithms inhibit recognizing more
time delays. Optoisolators with Schmitt triggered outputs are than one Out- or Out+ outputs in succession. This is discussed
used to provide additional hysteresis. in further detail in Section F. As Fig. 4 demonstrates, this
Input signals with constant frequency render delays due to method is not immune from phase error due to unequal turn
optoisolator output switching indistinguishable from delays on and turn off voltage levels.
due to threshold levels. The interpolation method requires
E. Comparator Circuits with Fixed Hysteresis
additional processor resources to accurately determine when
two events occur. This usually requires that the processor have It is common to use a circuit similar to that shown in Fig. 5
interrupt capability and capture and compare resources. The to translate voltage levels and provide noise immunity using
processor is programmed to capture the time of the times fixed hysteresis. Note that this circuit used a single voltage
when Out- optoisolator output goes high and the Out+ supply. Manufacturers of electronic comparator integrated
optoisolator output goes low. The true zero crossing is circuits specify that the maximum negative voltage on either
computed by linear interpolation between these two times. positive or negative input is 0.3 volts.[8] Schotky diodes, D1,
Fig. 4 shows that this method results in an improved degree of and D2, clip the input voltage to limit the comparator input
accuracy. The Est. Zero shown in Fig. 4 is computed from below recommended positive and negative levels.
the phase-locked loop algorithm that estimates the next zero This method works well provided that the signal being
crossing time.[5] measured is free of distortion from harmonics that can
+5V
potentially generate multiple zero-crossings per fundamental
R1
` cycle. The Schotky diodes do not provide any appreciable
D1
noise rejection nor do they prevent multiple zero crossings per
Out+
period due to distortion. Signal distortion from harmonic or
U1 other periodic signals can be reduced using classical
+5V frequency filtering techniques as described above. Signals can
R2 `
be filtered before passing through the zero crossing detector
D2
provided that they meet the constraints previously described.
Out-
Noise, on the other hand, is generally broad band and
U2
frequency filtering alone is insufficient to reduce detecting
multiple zero crossings per half period. Although the resistive
Fig. 3. Circuit for dual point interpolation method for feedback hysteresis circuit shown in Fig. 5 provides a degree
detecting a zero crossing of immunity to noise, the circuit cannot prevent an advanced
or delayed zero crossing. Hysteresis is used to prevent noise
from generating multiple zero crossings during the time that
the measured signal is very close to zero. The comparator’s
hysteresis voltage appears at its positive input and is labeled
Vc in Fig. 5. Since the hysteresis snap action occurs when V1
is nearly zero, the amount of hysteresis is computed by (5). If
R0 + R1 is much greater than R2, then V2 nearly equally 5
volts when Vc is positive.
Proceedings of The 29th Annual Conference of the IEEE Industrial Electronics Society Paper # 000291 4

+5V +5V

R0
+5V R2 +5V R2
C
R0

+5V +5V
D1 D1
R1 R1
V1 + V1 +
Vc V2 Vc V2
D2 D2
- Comparator -
Comparator

Fig. 5. Resistive feedback hysteresis circuit Fig. 6. Dynamic hysteresis comparator circuit

V 2 = 0 for Vc < 0
R0  ( 4)
Vc = V 2 ⋅  5 ⋅ ( R 0 + R1)
R 0 + R1 V 2 = for Vc> 0 R0 ⋅ R1 ⋅ C ⋅ s + R1 ( 5)
 R 0 + R1 + R 2 Vc( s ) = V 2( s ) ⋅
Inherently, the signal to noise ratio is the lowest at a zero R0 ⋅ R1 ⋅ C ⋅ s + R0 + R1
crossing thus requiring large hysteresis voltages when high The bias at steady state can be effectively removed by
noise levels are expected. The resistive hysteresis circuit also removing resistor R0 in Fig. 6. At DC, the gain of the transfer
creates a time delay in the comparator transition from positive function is zero and unity at frequencies much greater than α.
five volts to zero when the input sine passes through zero with This allows the high frequencies from the V2 step function to
a negative slope. Although a greater hysteresis voltage is pass to the comparator positive input at Vc. This results in a
desirable for better noise immunity, the period distortion is step increase of Vc when the comparator first goes positive
also greater. This has no adverse affects if period is being providing a large hysteresis and then decays to zero over time.
measured only when the input has a positive slope zero R1 ⋅ C ⋅ s s
crossing. However, faster response measurements are Vc( s ) = V 2( s ) ⋅ = ( 6)
possible if periods are measured twice each cycle. This is R1 ⋅ C ⋅ s + R1 s + α
usually not done with fixed hysteresis since the two half It is therefore desirable to have no voltage offset
periods are not symmetrical. immediately before the input signals zero crossing and very
high hysteresis immediately after the first zero crossing. The
F. Comparator Output Frequency Filtering
capacitive feedback comparator circuit shown in Fig. 6 has
The comparator output is frequently connected to some these characteristics. As before, it is reasonable to assume
other electronic device that is capable of recording high- that R1 is much greater than R2, V2(s) switched between zero
frequency binary outputs at V2 shown in Fig. 3 and 4. and five volts.
Regardless of the input frequency filtering and the amount of
voltage hysteresis, the probability of multiple comparator III. RESULTS OF DYNAMIC COMPARATOR HYSTERESIS
outputs for a single zero crossing remains. One is tempted to
eliminate these high frequency events by using a simple Fig. 6 and 7 demonstrate the simulated response for input
passive or even active low pass filter between the sine wave, V1, with a 34 db signal to noise ratio. These plots
comparator’s output and the input to the next measuring readily show that the difference voltage between Vc and the
circuit. This is not recommended because of the additional input sine wave, V1 goes to zero well before the next zero
unpredictable delay from the temperature dependent low crossing but provides a large hysteresis until the wave form
accuracy passive components. Phase locked loops are the has reached almost half of its peak value. For this simulation,
exception to this caution as the principle is to maintain the R2 is 47K ohms, C is 10 nF, and R2 is 4.7K ohms. Diodes,
phase relationship. Phase locked loops are discussed further in D1 and D2 were omitted because, as observed previously,
the next section. they cannot prevent erroneous zero crossings. The input
signal level for this simulation is 5 volts peak.
G. Comparator Circuits with Dynamic Hysteresis
The circuit shown in Fig. 6 is suggested to ensure fast
transitions and prevent multiple output pulses and the input
signal passes through the reference signal on the comparator’s
negative input terminal.[9] The transfer function defined by
Vc(s)/V2(s) from (5) is a high pass filter with a DC gain of
R1/R0+R1 and unity high frequency gain. Hence, at steady
state, the circuit functions identical to that of Fig. 5.
Proceedings of The 29th Annual Conference of the IEEE Industrial Electronics Society Paper # 000291 5

V. REFERENCES

[1]
Richard Weidenburg, F.P Dawson, and R Bonert, “New Synchronization
Method for Thyristor Power Converters to Weak AC-Systems” , IEEE
Transactions on Industrial Electronics, VOL 40, NO 5. October, 1993, pp.
505-511.

[2]
Olli Vainio and S.J.Ovaska, “Noise Reduction in Zero Crossing Dection by
Predictive Digital Filtering”, IEEE Transactions on Industrial Electronics,
VOL 42, NO 1. February, 1995, pp.58-62.

[3]
Olli Vainio and S.J. Ovaska, “Digital Filtering for Robust Zero Crossing
Dectors”, IEEE Transactions on Instrumentation and Measurements, April,
1996, pp 426-430.

[4] ]
Olli Vainio and S.J.Ovaska, Adaptive Lowpass Filters for Zero-Crossing
Fig. 7. The response of the dynamic zero crossing detector Detectors”, Proceedings of the 28th Annual International Conference of IEEE,
Sevilla, Spain, November 5-8, 2002.

[4]
Fairchild Semiconductor Application Note AN-3004, “Applications of
Zero Voltage Crossing Optically Isolated Triac Drivers, www.fairchild.com

[5]
Wall, R.W., and H.L. Hess. “Design of Microcontroller Implementation of
a Three Phase SCR Power Journal of Circuits, Systems, and Computers, Vol.
6, No. 6, March 1997, pp. 619-633.

[6]
Hess, H.L., R.W. Wall, et al. “A Microcontroller-Based Pulsed Width
Modulated Voltage Source Inverter,” North American Power Symposium,
Bozeman, Montana, October 2, 1995

[7]
TLP2200 GaAlAs IRED & PHOTO isolated bus driver data sheet,
TOSHIBA SEMICONDUCTOR

[8]
LM193, LM293, LM393 Dual Differential Comparator data sheet, Texas
Instruments
Fig. 8. Expanded plot of the dynamic zero crossing detector for positive
output step [9] The Art of Electronics 2nd Ed, Paul Horowitz and Winfield Hill,
Cambridge University Press, 1989, ISBN 0 521 37095 7, pp.579.
It is apparent that, although this approach results in reduced
multiple zero crossing, it cannot eliminate advanced or
delayed zero crossing detection. The dynamic hysteresis does
eliminate distortion of period measurements made on two
successive half periods.

IV. CONCLUSION
The accuracy of measuring zero crossing for synchronizing
power system control and instrumentation requires a diverse
approach to minimize phase detection errors from signals
corrupted with noise and extraneous signals. Using optical
isolated gates to detect a zero crossing can result in phase
distortion due to the diode’s non-zero forward voltage. This
phase shift can be reduced using the interpolation method.
The dynamic hysteresis circuit provides high signal to noise
ratio without period distortion due to DC level shifts on the
measured AC signal. Although proper signal conditioning can
improve the reliability of period measurements, phase errors
cannot be totally eliminated. Using pre-filtering and post
processing can improve zero crossing detection when
combined with dynamic hysteresis or the interpolation
method.