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Pipeline : Processor and Memory/cache Communication

Pipelining improves processor performance by allowing simultaneous execution of instructions by decomposing instructions into stages that can overlap, analogous to an assembly line. It completes one instruction per clock cycle at first but can be expanded to multiple stages to process more than one instruction per cycle. Pipeline hazards like structural, data, and control hazards can occur and require solutions like stalling or interlock logic.

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Millen Marbun
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67 views3 pages

Pipeline : Processor and Memory/cache Communication

Pipelining improves processor performance by allowing simultaneous execution of instructions by decomposing instructions into stages that can overlap, analogous to an assembly line. It completes one instruction per clock cycle at first but can be expanded to multiple stages to process more than one instruction per cycle. Pipeline hazards like structural, data, and control hazards can occur and require solutions like stalling or interlock logic.

Uploaded by

Millen Marbun
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Pipeline

 Pipelining is one way of improving the overall processing performance of a processor.


 This approach allows the simultaneous execution of several instructions.
 It is transparent to the programmer; it exploits parallelism (pseudo) at the instruction level by
overlapping the execution process of instructions.
 It is analogous to an assembly line where workers perform a specific task and pass the partially
completed product to the next worker.
 It decomposes an instruction into several segments or stages.
 Refer to discussion on processor and memory/cache communication , then initially an
instruction can be decomposed into two stages: fetch (F) and execution (E).
 Pipelining can be constructed by overlapping fetch stage of one instruction with execution stage
of the previous one.

Cloc 1 2 3 4 5
k
F1 E1
F2 E2
F3 E3
F4 E4
F5

 The overall, the above scheme completes the processing of one instruction in each clock cycle.
 It means that the rate of instruction processing is twice of sequential operation.
 The rate can be improved four time of the sequential operation by further decomposing the E
stage into other stages like follow

F E

(E)xecute (W)rite
(D)ecode

So the instruction stages becomes

F D E W

 One better approach is to decompose the instruction into five stages so that the rate becomes
five times of the sequential operation.
F D OF E W

Where OF is Operand Fetch

 Further decomposing the instruction into more stages will produce a scheme called
superpipelined architecture; this, however, still completes processing of one instruction in one
clock cycle.

1 2 3 4 5 6
F1 D1 E1 W1
F2 D2 E2 W2
F3 D3 E3 W3
F4 D4 E4
F5 D5
F6

 Another approach is completing processing of more than one instruction in one clock cycle.. This
is called superscalar.

1 2 3 4 5 6 7 8
F1 D1 E1 W1
F2 D2 E2 W2
F3 D3 E3 W3
F4 D4 E4 W4
F5 D5 E5 W5
F6 D6 E6 W6
F7 D7 E7 W7
F8 D8 E8 W8
F9 D9 E9 W9
F10 D10 E10 W10

Pipeline Hazard
 Condition that leads to unexpected/incorrect behavior
 Three types of hazard
o Structural
Two instructions or more require the use of a given H/W resource at the same time.
o Data
Condition in which operands (input or output) of an instruction are not available at the time
expected.
o Control/Instruction
Condition in which an instruction is not available (miss operation) or an instruction affects
which next instruction is (branch instruction)
.
 Solution?
o Stall
o Pipeline Interlock Logic that detects hazard
o Partial Stall

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