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Operating Systems: Memory Management

The document discusses several topics related to memory management in operating systems, including: 1) Effective memory access time calculations based on hit ratios in caches and translation lookaside buffers. 2) Memory protection using protection bits associated with each memory frame. 3) Common memory management techniques like multi-level paging, hashed page tables, and inverted page tables. 4) Challenges of implementing shared memory pages with inverted page tables.

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31 views

Operating Systems: Memory Management

The document discusses several topics related to memory management in operating systems, including: 1) Effective memory access time calculations based on hit ratios in caches and translation lookaside buffers. 2) Memory protection using protection bits associated with each memory frame. 3) Common memory management techniques like multi-level paging, hashed page tables, and inverted page tables. 4) Challenges of implementing shared memory pages with inverted page tables.

Uploaded by

Owner JustACode
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Operating Systems

CS F372

Memory Management

Biju K Raveendran
Effective Access Time
• Example
– Hit ratio 80%
– 20 nsec to search in TLB
– 100 nsec to access Memory
– Effective Memory Access Time [Assume no Cache]
– (E M A T) = (0.80 X 120) + (0.20 X 220) = 140 nsec
– (0.8 X 120 + 0.2 X 120) / 0.8 = 150nSec
If hit ratio is 98% then
EAT = (0.98 X 120) + (0.02 X 120) / 0.98= 122.45 nsec
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Memory Protection
• Memory protection implemented by associating
protection bit with each frame
• One bit to specify the page is read write or read only
• Valid-invalid bit attached to each entry in the page
table:
– “valid” indicates that the associated page is in the
process’ logical address space, and is thus a legal
page
– “invalid” indicates that the page is not in the process’
logical address space
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Valid (v) or Invalid (i) bit in a page table

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Structure of the page table
• Hierarchical Paging

• Hashed Page Tables

• Inverted Page Tables

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Two level Page Table Scheme

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Two level Paging Example
• A logical address (on 32-bit machine with 4K page size) is
divided into:
– a page number consisting of 20 bits
– a page offset consisting of 12 bits
– Need 1MB address space for one process’s page table
• Since the page table is paged, the page number is further
divided into:
– a 10-bit page number
– a 10-bit page offset

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Two level Paging Example
• Thus, a logical address is as follows:
where pi is an index into the outer page table,
and p2 is the displacement within the page of
the outer page table.
• This address translation scheme is called
forward mapped page table
page number page offset

32 10 10 12
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Address Translation Scheme

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Three level Paging Scheme

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Multi-level paging and Performance
• Since each level is stored as a separate table in memory,
covering a logical address to a physical one may take
four memory accesses.
• Even though time needed for one memory access is
quintupled, caching permits performance to remain
reasonable.
• Cache hit rate of 98 percent yields:
Effective access time = (0.98 x 120 + 0.02 x 420)/0.98
= 128.57 nanoseconds.
which is only a 28.57% slowdown in memory access time.

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Hashed Page Tables
• Common in address spaces > 32 bits
• The virtual page number is hashed into a page
table
– This page table contains a chain of elements
hashing to the same location
• Virtual page numbers are compared in this
chain searching for a match
– If a match is found, the corresponding
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physical frame is extracted
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Hashed Page Table

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Inverted Page Table
• One entry for each real page of memory
• Entry consists of the virtual address of the page stored in that real
memory location, with information about the process that owns
that page
• Decreases memory needed to store each page table, but increases
time needed to search the table when a page reference occurs
• Use hash table to limit the search to one — or at most a few —
page-table entries
– TLB can accelerate access
• But how to implement shared memory?
– One mapping of a virtual address to the shared physical
address
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Inverted Page Table Architecture

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Shared Pages
• Shared code
– Shared code must appear in same location in the logical
address space of all processes
– Very difficult to implement for the systems that uses inverted
page tables.
• Private code and data
– Each process keeps a separate copy of the code and data
– The pages for the private code and data can appear anywhere
in the logical address space

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Shared Pages Example

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