An Introduction to Integrated

Circuits and CMOS Technology

Hooman Nabovati
Department of Electrical Engineering
Sadjad Institute for Higher Education
Mashhad, Iran
 Brief History

 19th Century - Solid-State Rectifiers

 1907 - Application of Crystal Detector in Radio
 1947 - BJT Constructed by Bardeen and Brattain and
schockly
 1959 – Integrated Circuit Constructed by Kilby

2
 Transistor History
 Invention: 1947,at Bell Laboratories.

 John Bardeen, Walter Brattain, and

William Schockly developed the first
model of transistor (a Three Points
transistor, made with Germanium)
 They received Nobel Prize in Physics.

3 12/21/2009
 Integrated circuits: Example-Pentium
Example Pentium 4TM
 Device characteristics
 # of transistors 42 000 000
 Line width: 0.18 µm=>( 0.13 µm)
 P4 die size: 224 mm2

4
5 12/21/2009
Evolution in Complexity

6
 Semicond ctor Technology
Semiconductor Technolog Roadmap
MPU Gate Length (nm)
35

30

25

20

15

10

0
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024

7
 T h l
Technology R
Roadmap
d (Fl
(Flash
hMMemories)
i )
bits/cm2
1 00E+12
1.00E+12

1 00E+11
1.00E+11

1.00E+10
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024

8 12/21/2009
 S i
Semiconductor
d t M Manufacturing
f t i Market
M k t

System IC
Design Fabrication Packaging Test
specification $200 billion

Tools: design
simulation Equipment Material Equipment Equipment
emulation

$3.4 billion $16.8 billion $2.0 billion $5.2 billion

11
IC Technology
 A CMOS Inverter

13
 Inverter Cross-section
Cross section
 Typically use p-type substrate for nMOS transistors
 Requires n-well for body of pMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+
p p+
p
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

14
 Well and Substrate Taps
 Substrate must be tied to GND and n-well to VDD
 Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
 Use heavily doped well and substrate contacts / taps

A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

15 21/‫دﺳﺎﻣﺒﺮ‬/09
 Inverter Mask Set
 Transistors and wires are defined by masks
 Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

16
 Detailed Mask Views
 Six masks
n wellll

 n-well
 Polysilicon
 n+ diffusion Polysilicon

 p+ diffusion
n+ Diffusion

 Contact
 Metal
p+ Diffusion

Contact

Metal

17 21/‫دﺳﺎﻣﺒﺮ‬/09
 Fabrication Steps
 Start with blank wafer
 Build inverter from the bottom up
 First step will be to form the n-well
 Cover wafer with protective layer of SiO2 (oxide)
 Remove layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer
 Strip off SiO2

p substrate

18
 Oxidation
 Grow SiO2 on top of Si wafer
 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

19 21/‫دﺳﺎﻣﺒﺮ‬/09
 Photoresist
 Spin on photoresist
 Photoresist is a light-sensitive organic polymer
 Softens where exposed to light

Photoresist
SiO2

p substrate

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 Lithography
 Expose photoresist through n-well mask
 Strip off exposed photoresist

Photoresist
SiO2

p substrate

21 21/‫دﺳﺎﻣﺒﺮ‬/09
 Etch
 Etch oxide with hydrofluoric acid (HF)
 Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

22
 Strip Photoresist
 Strip off remaining photoresist
 Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in next step

SiO2

p substrate

23
 n well
n-well
 n-well is formed with diffusion or ion mplantation
 Diffusion
 Place wafer in furnace with arsenic gas
 Heat until As atoms diffuse into exposed Si
 Ion Implanatation
 Blast wafer with beam of As ions
 Ions blocked by SiO2, only enter exposed Si

SiO2

n well

24 21/‫دﺳﺎﻣﺒﺮ‬/09
 Strip Oxide
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
 Subsequent steps involve similar series of steps

n well
p substrate

25
 Polysilicon
 Deposit very thin layer of gate oxide
 < 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon layer
 Place wafer in furnace with Silane gas (SiH4)
 Forms many small crystals called polysilicon
 Heavily doped to be good conductor

Polysilicon
Thi gate
Thin t oxide
id

n well
p substrate

26
 Polysilicon Patterning
 Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
P l ili
Thin gate oxide

n well
p substrate

27
 Self Aligned Process
Self-Aligned
 Use oxide and masking to expose where n+ dopants
should
h ld beb diffused
diff d or iimplanted
l t d
 N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate

28
 N diffusion
N-diffusion
 Pattern oxide and form n+ regions
 S lf li d process where
Self-aligned h gate
t bl
blocks
k diff
diffusion
i
 Polysilicon is better than metal for self-aligned gates because it
doesn’t melt during later processing

n+ Diffusion

n well
p substrate

29
 N diffusion cont
N-diffusion cont.
 Historically dopants were diffused
 Usually ion implantation today
 But regions are still called diffusion

n+ n+ n+
n well
p substrate

30
 N diffusion
N-diffusion
 Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

31 21/‫دﺳﺎﻣﺒﺮ‬/09
 P Diffusion
P-Diffusion
 Similar set of steps form p+ diffusion regions for
pMOS
MOS source and d drain
d i and d substrate
b t t contact
t t

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

32
 Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+
n well
p substrate

33 21/‫دﺳﺎﻣﺒﺮ‬/09
 Metallization
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires

M e ta l

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

34