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Full Subtractor Dataflow

This document describes a full subtractor module in Verilog. It defines the module with inputs A, B, C and outputs Diff and Borrow. It assigns Diff to be the XOR of A, B, and C and assigns Borrow to be the OR of AND expressions involving A, B, and C. It also includes a testbench module that initializes and tests the full subtractor module with different input combinations over time.

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rajeevrvs083
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323 views

Full Subtractor Dataflow

This document describes a full subtractor module in Verilog. It defines the module with inputs A, B, C and outputs Diff and Borrow. It assigns Diff to be the XOR of A, B, and C and assigns Borrow to be the OR of AND expressions involving A, B, and C. It also includes a testbench module that initializes and tests the full subtractor module with different input combinations over time.

Uploaded by

rajeevrvs083
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Full Subtractor

Data flow modeling:


module full_subtractor_dataflow(A,B,CDiff,Borrow);
input A,B,C;
output Diff,Borrow;
assign Diff=A^B^C;
assign Borrow=(~A)&(B^C)|B&C;
endmodule

Test code:
module test3_v;

reg A,B,C;
wire Diff,Borrow;

half_subtractor_dataflow uut(
.A(A)
.B(B)
.C(C)
.Diff(Diff)
.Borrow(Borrow)
);

initial begin
A=0;
B=0;
C=0;
#100;

A=0;
B=0;
C=1;
#100;

A=0;
B=1;
C=0;
#100;

A=0;
B=1;
C=1;
#100;

A=1;
B=0;
C=0;
#100;

A=1;
B=0;
C=1;
#100;

A=1;
B=1;
C=0;
#100;

A=1;
B=1;
C=1;
#100;

end
endmodule

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