Home Work Assignment on Input/Output Organization and Pipeline

Q1. Assume that three I/O devices are connected to a 32-bit, MIPS CPU. The first
device is a hard drive with a maximum transfer rate of 1MB/sec. It has a 32-bit bus.
The second device is a flash drive with a transfer rate of 25KB/sec over a 16-bit
bus, and the third device is a keyboard that must be polled thirty times per
second.Assuming that the polling operation requires 20 instructions for each I/O
device, determine the percentage of CPU time required to poll each device.
Solution: The hard drive can transfer 1MB/sec or 250 K 32-bit words every second. Thus, this hard
drive should be polled using at least this rate. Using 1K=210, the number of CPU instructions required
would be 250 x 210 x 20 = 5120000 instructions per second.
Percentage of CPU time required for polling is(5.12 x 106 )/ (10 x106 ) = 51.2%
The floppy disk can transfer 25K/2= 12.5 x 210 half-words per second.
It should be polled with at least this rate.
The number of CPU instructions required will be 12.5 x 210 x 20 = 256,000 instructions per second.
Therefore, the percentage of CPU time required for polling is (0.256 x 106 )/ (10 x 106 ) = 2.56%.
For the keyboard, the number of instructions required for polling is 30 x 20 = 600 instructions per
second. Therefore, the percentage of CPU time spent in polling is 600 / (10 x 106 ) = 0.006%
It is clear from this example that while it is acceptable to use polling for a keyboard or a floppy drive,
it is very risky to use polling for the hard drive. In general, for devices with a high data rate, the use of
polling is not adequate.

Q2. a. What should be the polling frequency for an I/O device if the average delay
between the time when the device wants to make a request and the time when it
is polled, is to be at most 10 ms?

b. If it takes 10,000 cycles to poll the I/O device, and the processor operates at
100MHz, what % of the CPU time is spent polling?
Solution:
a. Assuming that the I/O requests are distributed evenly in time, the average time that a device will
have to wait for the processor to poll is half the time between polling attempts. Therefore, to provide
an average delay of 10 ms, the processor will have to poll every 20 ms, or 50 times per second.

b. If each polling attempt takes 10,000 cycles, then the processor will spend 500,000 cycles polling
each second. The % of CPU time spent in polling is then (0.5x106 )/(100x106 )=0.5%
Q3. A processor with a 500 MHz clock requires 1000 clock cycles to perform a
context switch and start an ISR. Assume each interrupt takes 10,000 cycles to
execute the ISR and the device makes 200 interrupt requests per second. Also,
assume that the processor polls every 0.5msec during the time when there are no
interrupts. Further assume that polling an I/O device requires 500 cycles. Compute
the following:

a. How many cycles per second does the processor spend handling I/O from the
device if only interrupts are used?

b. What fraction of the CPU time is used in interrupt handling for part (a)?

c. How many cycles per second are spent on I/O if polling is also used with
interrupts?

d. How often should the processor poll so that polling incurs the same overhead as
interrupts?
Solution:
a. The device makes 200 interrupt requests per second, each of which takes 10,000 + 2x1000 (context
switching to the ISR and back from it) = 12,000 cycles. Thus, a total of 200x12,000=2,400,000 cycles
per second are spent handling I/O using interrupts.

b. The percentage of the processor time used in interrupt handling is 2,400,000/(500x106) or 0.48%.

c. There are 200 interrupt requests per second, or one interrupt request every 5 ms. Every interrupt
consumes a total of 12,000 cycles, as calculated in part (a). For a 500 MHz CPU, this is 12000/(500 x
106 ) = 24 microseconds. For 200 interrupts per second, this is 4.8 msec. This leaves 1000 - 4.8 = 995.2
msec for polling. Since the processor polls once every 0.5 msec during the time when there is no
interrupt, this corresponds to 995/0.5 = 1990 times per second. The total number of cycles required
for polling is 1990 x 500 = 995,000 cycles per second. Thus, the total time spent on I/O when using
polling with interrupts is2,400,000 + 995,000 = 3,395,000 cycles per second.

d. The interrupt overhead is 1000 cycles per second for a context switch to the ISR and 1000 cycles
per second back from it. This is a total of 2 x 1000 cycles per second. With 200 interrupts per second,
this is 200 x 2000 = 400,000 cycles per second. The polling overhead is 500 cycles per second. Thus,
for the same overhead as interrupts, the polling operation should be performed 400,000 / 500 = 800
times per second, or 1/800 = every 1.25 msec
Q4. Consider the pipelined execution of the following sequence of instructions:

Add $t1, $t3, $t2

Or $t7, $t6, $t5

Subtract $t8, $t7, $t4

Draw a diagram to show the pipelined execution of these instructions

Q5. The 5 stages of the processor have the following latencies:

Fetch Decode Execute Memory Write back

a. 300ps 400ps 350ps 550ps 100ps

b. 200ps 150ps 100ps 190ps 140ps

Assume that when pipelining, each pipeline stage costs 20ps extra for the registers
between pipeline stages.

a. Non-pipelined processor: what is the cycle time? What is the latency of an

b. Pipelined processor: What is the cycle time? What is the latency of an

c. If you could split one of the pipeline stages into 2 equal halves, which one would
you choose? What is the new cycle time? What is the new latency? What is the
new throughput?
Solution
As there is no pipelining, Cycle time must allow the instruction to go through all stage in one cycle.
The latency is same as the cycle time since it take the instruction one cycle to go from the beginning
of fetch the end of the writeback. The throughput is defined as 1/CT inst/s.

CT = 300ps+400ps+350ps+550ps+100ps= 1700ps
Latency =1700ps
Throughput= 1/CT =1/1700 inst/s.

CT = 200ps+ 150ps+100ps+190ps+140ps = 780ps

B. Pipelining reduce the cycle time to the length of the longest stage plus the register delay. Latency
become CT*N where N is the number of stage as one instruction will need to go through each of the
stage and each stage take one cycle.throughput formula remain same.

CT= 550+20=570ps
Latency =5*570=2850ps
Throughput = 1/CT =1/570 inst/s.

CT =200+20 =220
Latency = 5*220 =1100 ps
Throughput =1/CT =1/220 inst/s
c) We would want to choose a longest stage to split in half. The new cycle time become the
Origianally 2nd longest stage. Calculate Latency and Throughput correspondingly. But remember that
there is now 6 stage instead of 5
CT =400+20 =420ps
Latency =6*420 =2520ps
Throughput -1/CT =1/420 inst/s

CT = 190 +20 =210ps

Q6. Hazards occur in pipeline due to various reasons. Either due to unavailability of
correct data ( Data Hazard ) or execution of instructions in the wrong part of a
branch that get executed and their results are saved in memory ( Control Hazard ).
Two code snippets have been provided which when executed on a pipelined
processor would result in pipeline hazard. Mention the hazards that would occur in
each case with justification for your choice.

a. Code 1 :

add $t1, $t2, $t3

sub $t3, $t1, $t4

b. Code 2 :

beq .foo

mov $t1, 4

add $t2, $t4, $t3

.......

........

.foo : add $t4, $t1, $t2