"TEXAS

INSTRUMENTS

High.Performance
FIFO Memories
Standard and Specialty Memories
From 1·8it to 36·8it Widths

1996 Advanced System Logic Products

--========
General Information
~~~~~~~~~~1fI
III
Telecom Single-Bit FIFOs .

Reduced-Width FIFOs
~~~~~~~~~~.
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..
9-Bit Clocked/Strobed FIFOs •

8- and 9-Bit Asynchronous FIFOs

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18-Bit Clocked FIFOs

~~~~~~~~~====
18-Bit Strobed FIFOs
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..
..
~~~~~~~~~====~
MUlti-QTM 18-Bit FIFO ...

3.3-V Low-Powered 18-Bit FIFOs

DSP 32- and 36-Bit Clocked FIFOs

Internetworking 36-Bit Clocked FIFOs

High-Bandwidth Computing 36-Bit Clocked FIFOs

Military FIFOs

Application Reports

Mechanical Data
 High-Performance
FIFO Memories Data Book

Standard and Specialty Memories

From 1-Bit to 36-Bit Widths

• TEXAS
INSTRUMENTS
 IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Copyright © 1996, Texas Instruments Incorporated

Printed in U.S.A. by
Custom Printing Company
Owensville, Missouri
 INTRODUCTION

First-in, first-out (FIFO) memories from Texas Instruments (TI) are valuable data-path
elements for eliminating bottlenecks and regulating flow. Data transfers in and out of a FIFO
memory are independent of one another and allow the device to be the communication
medium between two asynchronous systems. Empty and full status flags that prevent
underflow and overflow conditions are standard with all devices, and many have
programmable almost-full and almost-empty flags to optimize the control of a particular
system.
Each advanced FIFO is constructed with a dual-port SRAM, read and write address-
incrementing logic, and flag circuitry. Rising-edge-triggered clocks are featured on all TI
FIFOs, with self-timed reads and writes on memory that allow a large variance of usable
pulse widths. TI's strobed style FIFO writes data to memory on each low-to-high transition
of the load-clock (LOCK) input and reads data on each rising edge of the unload-clock
(UNCK) input.
TI's c/ockedstyle FIFO also can receive asynchronous clocks for writing and reading data,
but the clock inputs are designed to be continuous, with the rising edge affecting data
transfers when separate enable signals are asserted. This characteristic allows a seamless
interface between the device and other high-speed buses or microprocessors with similar
control. The availability Of the free-running clock also provides the means to synchronize
the full and empty status flags as reliable control signals and reduce the amount of external
support logic. Each TI clocked FIFO has the empty flag synchronized to the read clock and
the full flag synchronized to the write clock with at least two flip-flop stages. Clocked FIFOs
produced in advanced CMOS technology can support clock frequencies up to 67 MHz. The
SN74ABT7819, produced in advanced BiCMOS technology, is capable of speeds up to 80
MHz. The SN7 4ABT7819 is also a bidirectional FI FO with two independent FI FO memories
combined on one chip to buffer data in opposite directions.
Memory organization of the FIFOs ranges in depth from 16 words to 16384 words and data
bit widths of 1, 4, 5, 8, 9, 18, 32, and 36. The under and deeper FIFOs offer a high level of
integration and board-space savings, where previously, multiple FIFOs had to be cascaded
to achieve the desired architecture. To accommodate the need to reduce package area as
data widths increase, many TI FIFO memories are offered in thin surface-mount packages.
The SSOP and TQFP packages with 25-mil, 0.5-mm, and 0.4-mm lead pitch, respectively,
can reduce the FIFO-dedicated board area by greater than 70% over PLCC packages.
TI continues to offer leading-edge solutions to customers' needs in both packaging
technology and device architecture. This is evidenced by the 120-pin TQFP with 16-mm x
16-mm area to house the 32- and 36-bit products. With features such as synchronous
retransmit, mailbox-bypass registers, byte swapping, and bus-width matching, these
devices provide a high level of integration in a compact area for applications such as
interfacing a digital signal processor (DSP) to a host processor and matching systems with
different memory organizations.

EPIC, EPIC-lIB, IMPACT, OEC, Widebus, and Multi-Q are trademarks of Texas Instruments Incorporated.

v
 PRODUCT STAGE STATEMENTS
Product stage statements are used on Texas Instruments data sheets to indicate the
development stage(s) of the product(s) specified in the data sheets.
If all products specified in a data sheet are at the same development stage, the appropriate
statement from the following list is placed in the lower left corner of the first page of the data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications perthe terms ofTexas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase
of development. Characteristic data and other specifications are subject to change without
notice.
PRODUCT PREVIEW information concerns products in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice.
If not all products specified in a data sheet are at the PRODUCTION DATA stage, then the first
statement below is placed in the lower left corner of the first page of the data sheet. Subsequent
pages of the data sheet containing PRODUCT PREVIEW information or ADVANCE
INFORMATION are then marked in the lower left-hand corner with the appropriate statement
given below:
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information
current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing
of all parameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase
of development. Characteristic data and other specifications are subject to change without
notice.
PRODUCT PREVIEW information concerns products in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice.

vi
 Contents
Section 1 - General Information • • • • • • • . • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 1-1
Alphanumeric Index ................................................................. 1-3
Product Overview ..•.•.....••................•.......•......•..•.........•.......... 1-5
Glossary ....•.........••.......•.........•..•..........••.......................... 1-7
Explanation of Function Tables .............•.........................................• 1-11
D Flip-Flop and Latch Signal Conventions .............................................. 1-13
Thermallnformation ...............................•.........•....................... 1-15

Section 2 - Telecom Single-Bit FIFOs ................................. 2-1

SN74ACT?226,SN74ACT2228
Dual 64 x 1, Dual 256 x 1 Clocked First-In, First-Out Memories ....................... 2-3
SN74ACT2227,SN74ACT2229
Dual 64 x 1, Dual 256 x 1 First-In, First-Out Memories .............................. 2-15

Section 3 - Reduced-Width FIFOs ......................... . . . . . . . . . .. 3-1

SN74ALS232B
16 x 4 Asynchronous First-In, First-Out Memory .................................... 3-3
SN74ALS234
64 x 4 Asynchronous First-In, First-out Memory .................................... 3-11
SN74ALS23~ .
64 x 4 Asynchronous First-In, Flrst-Out Memory ..•.•..•.....•........•............. 3-21
SN74S225
16 x 5 Asynchronous First-In, First-Out Memory .................................... 3-31
SN74ALS229B
16 x 5 Asynchronous First-In, First-Out Memory .................................... 3-41
SN74ALS233B
16 x 5 Asynchronous First-In, Flrst-out Memory •..•..........•.••.....••.........•. 3-49
SN74ALS235
64 x 5 Asynchronous First-In, First-out Memory .••................................. 3-57

Section 4 - 9-Blt Clocked/Strobed FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1

SN74ACT7807
2048 x 9 Clocked First-In, First-Out Memory .....................•.•.•....•........ 4-3
SN74ACT7808 .
2048 x 9 Strobed First-In, First-Out Memory .•.•.........•...•.•.....••...••..•.... 4-19

Section 5 - 8- and 9-Bit Asynchronous FIFOs ......................... 5-1

SN74ALS2238
32 x 9 x 2 Asynchronous Bidirectional First-In, First-Out Memory ..•..•.•..........•.. 5-3
SN74ALS2232A
64 x 8 Asynchronous First-In, First-Out Memory .........................•.....•.•.. 5-13
SN74ALS2233A
64 x 9 Asynchronous First-In, Flrst-Out Memory .•.....•.....•........•....•........ 5-21
SN74ACT7200L,SN74ACT7201LA,SN74ACT7202LA
256 x 9,512 x 9, 1024 x 9 Asynchronous First-In, First-Out Memories ....•.......••.•. 5-29
SN74ACT2235
1024 x 9 x 2 Asynchronous Bidirectional First-In, Flrst-Out Memory .....••...••.•••... 5-49
SN74ACT2236
1024 x 9 x 2 Asynchronous Bidirectional First-In, First-Out Memory ..•.....•.......... 5-61
SN74ACT7203L,SN74ACT7204L,SN74ACT7205L,SN74ACT7206L
2048 x 9, 4096 x 9, 8192 x 9, 16384 x 9 Asynchronous First-In, Flrst-Out Memories ..... 5-73

vii
 Section 6 - 9-81t Synchronous FIFOs ................................. 6-1
SN74ACT72211L,SN74ACT72221L,SN74ACT72231L,SN74ACT72241L
512 x 9,1024 x 9, 2048 x 9, and 4096 x 9 Synchronous First-In, First-Out Memories .... 6-3

Section 7 - 18-81t Clocked FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-1

SN74ACT7813
64 x 18 Clocked First-In, First-Out Memory ........................................ 7-3
SN74ACT7805
256 x 18 Clocked First-In, First-Out Memory ....................................... 7-17
SN74ACT7803
512 x 18 Clocked First-In, First-Out Memory ................•...................... 7-31
SN74ABT7819
512 x 18 x 2 Clocked Bidirectional First-In, First-Out Memory ...•.................... 7-45
SN74ACT7811
1024 x 18 Clocked First-In, First-Out Memory ...................................... 7-65
SN74ACT7881
1024 x 18 Clocked First-In, First-Out Memory ...................................... 7-81
SN74ACT7S82
2048 x 18 Clocked First-In, First-Out Memory ...................................... 7-97
SN74ACT7884
4096 x 18 Clocked First-In, First-Out Memory ...................................... 7 -113

Section 8 - 18-81t Strobed FIFOs ..................................... 8-1

SN74ACT7814
64 x 18 Strobed First-In, First-Out Memory ......................................... 8-3
SN74ACT7806
256 x 18 Strobed First-In, First-Out Memory ....................................... 8-15
SN74ACT7804
512 x 18 Strobed First-In, First-Out Memory ...........•........................... 8-27
SN74ABT7820
512 x 18 x 2 Strobed Bidirectional First-In, First-Out Memory ......................... 8-39
. SN74ACT7802
1024 x 18 Strobed First-In, First-Out Memory ...................................... 8-53

Sectlon9-Multi-QTM 18-8it FIFO ..................................... 9-1

SN74ACT53861
4096 x 18 Clocked Multlple-Queue (Multi-QTM) First-In, First-Out Memory
With Three Programmable-Depth Buffers and Cell-Based Flags ...................... 9-3

Section 10 - 3.3-V Low-Powered 18-81t FIFOs ......................... 10-1

SN74ALVC7803,SN74ALVC7805,SN74ALVC7813
512 x 18, 256 x 18, 64 x 18 Low-Powered Clocked First-In, First-Out Memories ........ 10-3
SN74ALVC7804,SN74ALVC7806,SN74ALVC7814
512 x 18, 256 x 18, 64 x 18 Low-Powered First-In, First-Oul Memories ................ 10-17

Section 11 - DSP 32- and 36-81t Clocked FIFOs ....................... 11-1

SN74ACT3631
512 x 36 Clocked First-In, First-Out Memory ....................................... 11-3
SN74ACT3841
1024 x 36 Clocked First-In, First-Out Memory ...................................... 11-29
SN74ACT3651
2048 x 36 Clocked First-In, First-Out Memory .....................•.•.........•.... 11-55

viii
Section 11 - DSP 32- and 36-Bit Clocked FIFOs (continued) ............ 11-1
SN74ACT3622
256 x 36 x 2 Clocked Bidirectional First-In, First-Out Memory ........................ 11-81
SN74ACT3638
512 x 32 x 2 Clocked Bidirectional First-In, First-Out Memory ........................ 11-107
SN74ACT3632
512 x 36 x 2 Clocked Bidirectional First-In, First-Out Memory .......................• 11-137
SN74ACT3642
1024 x 36 x 2 Clocked Bidirectional First-In, First-Out Memory ....................... 11-163

Section 12 -Internetworking 36-Bit Clocked FIFOs .................... 12-1

SN74ABT3613
64 x 36 Clocked First-In, First-Out Memory With Bus Matching and Byte Swapping ..... 12-3
SN74ABT3614
64 x 36 x 2 Clocked Bidirectional First-In, First-Out Memory
With Bus Matching and Byte Swapping ............................................ 12-35

Section 13 - High-Bandwidth Computing 36-Bit Clocked FIFOs ........ 13-1

SN74ABT3611
64 x 36 Clocked First-In, First-Out Memory ........................................ 13-3
SN74ABT3612
64 x 36 x 2 Clocked Bidirectional First-In, First-Out Memory ......................... 13-29

Section 14 - Military FIFOs .......................................... 14-1

Introduction ......................................................................... 14-3
SN54ABT7819
512 x 18 x 2 Clocked Bidirectional First-In, First-Out Memory ........................ 14-5
SN54ABT7820
512 x 18 x 2 Strobed Bidirectional First-In, First-Out Memory ......................... 14-25
SN54ACT7811
1024 x 18 Clocked First-In, First-Out Memory ...................................... 14-39
SN54ACT7881
1024 x 18 Clocked First-In, First-Out Memory ...................................... 14-55
SN54ABT3614
64 x 36 x 2 Clocked Bidirectional First-In, First-Out Memory
With Bus Matching and Byte Swapping ............................................ 14-71
SN54ACT3641
1024 x 36 Clocked First-In, First-Out Memory ...................................... 14-113

Section 15 - Application Reports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-1

FIFO Solutions for Increasing Clock Rates and Data Widths ............................... 15-5
FIFO Surface-Mount Package Information .............................................. 15-15
FIFO Memories: Fine-Pitch Surface-Mount Manufacturability .............................. 15-25
Metastability Performance of Clocked FIFOs ............ ; ............................... 15-35
FIFO Memories: Solution to Reduce FIFO Metastability ................................... 15-47
Multiple-Queue First-In, First-Out Memory SN74ACT53861 ............................... 15-53

ix
 Section 16 - Mechanical Data ........................................ 16-1
Ordering Instructions .•............................................................... 16-3
DL (R-PDSO-G**) ................................................................... 16-5
DV (R-PDSO-G28) .................................................................. 16-6
DW (R-PDSO-G**) .................................................................. 16-7
FK (S-CQCC-N**) ................................................................... 16-8
FN (S-PQCC-J**) ................................................................... 16-9
GA-GB (S-CPGA-P9 x 9) ... .. .. .. . . .. .. .. . . .. .. . . .. .. . .. . .. .. .. . .. . . .. .. . . .. . . . .. . . .. 16-10
GA-GB (S-CPGA-P11 x 11) ........................................................... 16-11
GA-GB (S-CPGA-P14 x 14) ..................•.......•................................ 16-12
N (R-PDIP-T**) ...................................................................... 16-13
N (R-PDIP-T**) ......................................................... , ............ 16-14
NP (R-PDIP-T28) ............•....................................................... 16-15
NT (R-PDIP-T**) .................................................................... 16-16
PAG (S-PQFP-G64) ................................................................. 16-17
PCB (S-PQFP-G120) ................................................................ 16-18
PH (R-PQFP-G80) .................................................................. 16-19
PM (S-PQFP-G64) .......•........................................•................. 16-20
PN (S-PQFP-G80) ................................................................... 16-21
PQ (S-PQFP-G***) .................................................................. 16-22
PZ (S-PQFP-G100) .................................................................. 16-23
RJ (R-PQCC-J32) ..........................•........................................ 16-24

x
I General Information

1-1
 Contents
Page
Alphanumeric Index ................................................... 1-3
C) Prod uct Overview ..•••••.•..•.......•................................. 1-5
CD Glossary ............................................................. 1-7
:::s
CD Explanation of Function Tables •.•.••...•..••••...•..•..•..•........... 1-11
OJ
--:::s o Flip-Flop and Latch Signal Conventions ............................•. 1-13
Thermal Information •....•••.......................................••.. 1-15
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1-2
 ALPHANUMERIC INDEX

DEVICE PAGE DEVICE PAGE

SN54ABT3614 ................................. 14-71 SN74ACT7803 .................................. 7-31
SN54ABT7819 .................................. 14-5 SN74ACT7804 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-27
SN54ABT7820 ...... . . . . . . . . . . . . . . . . . . . . . . . . . .. 14-25 SN74ACT7805 .................................. 7-17
SN54ACT3641 ................................ 14-113 SN74ACT7806 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-15
SN54ACT7811 ................................. 14-39 SN74ACT7807 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
SN54ACT7881 ................................. 14-55 SN74ACT7808 .................................. 4-19
SN74ABT3611 .................................. 13-3 SN74ACT7811 .................................. 7-65
SN74ABT3612 ................................. 13-29 SN74ACT7813 ................................... 7-3
SN74ABT3613 .................................. 12-3 SN74ACT7814 ................................... 8-3
SN74ABT3614 ................................. 12-35 SN74ACT7881 .................................. 7-81
SN74ABT7819 .................................. 7-45 SN74ACT7882 .................................. 7-97
SN74ABT7820 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-39 SN74ACT7884 ................................. 7-113
SN74ACT2226 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3 SN74ACT53861 .................................. 9-3
SN74ACT2227 .................................. 2-15 SN74ACT72211L ................................. 6-3
SN74ACT2228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3 SN74ACT72221 L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
SN74ACT2229 .................................. 2-15 SN74ACT72231 L ................................. 6-3
SN74ACT2235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .. 5-49 SN74ACT72241 L ................................. 6-3
SN74ACT2236 .................................. 5-61 SN74ALS229B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-41
SN74ACT3622 ................................. 11-81 SN74ALS232B ................................... 3-3
SN74ACT3631 .................................. 11-3 SN74ALS233B .................................. 3-49
SN74ACT3632 ................................ 11-137 SN74ALS234 ................................... 3-11
SN74ACT3638 ................................ 11-107 SN74ALS235 ................................... 3-57
SN74ACT3641 ................................. 11-29 SN74ALS236 ................................... 3-21
SN74ACT3642 ................................ 11-163 SN74ALS2232A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-13
SN74ACT3651 ................................. 11-55 SN74ALS2233A ................................. 5-21
SN74ACT7200L ................................. 5-29 SN74ALS2238 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
SN74ACT7201LA ............................... 5-29 SN74ALVC7803 ................................. 10-3
SN74ACT7202LA ............................... 5-29 SN74ALVC7804 ................................ 10-17
SN74ACT7203L ................................. 5-73 SN74ALVC7805 ................................. 10-3
SN74ACT7204L ................................. 5-73 SN74ALVC7806 ................................ 10-17
SN74ACT7205L ................................. 5-73 SN74ALVC7813 ................................. 10-3
SN74ACT7206L ................................. 5-73 SN74ALVC7814 ................................ 10-17
SN74ACT7802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-53 SN74S225 ..................................... 3-31

-!!J TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 1-3
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::J
C ~ iL ~ ::I!.5
ii
::I! ~ "-
II)
a: rna:
>.
III
III
::J
III
e
"-
:;
::I!
in
SN74ALVC7813
SN74ACT7814
64
64
18
18
13
15
r/
r/
r/
r/
r/
* r/
r/
r/
r/
:e
SN74ALVC7814 64 18 18 r/ r/ r/ r/
SN74ACT7805 256 18 12 r/ r/ r/
* r/ r/
SN74ALVC7805
SN74ACT7806
256
256
18
18
13
15
r/
r/
r/
r/
r/
* r/
r/
r/

"tI

~ SN74ALVC7806 256 18 18 r/ r/ r/ ""

r/

~-~ SN74ACT7803 512 18 12 r/ r/

"" * r/ r/

~~-..r SN74ALVC7803 512 18 13 r/ r/ r/

* r/ r/

~~d
SN74ACT7804 512 18 15 r/ r/ r/ r/

~t::~
SN74ALVC7804 512 18 18 r/ r/ r/ r/
SN74ABT7819 512 18 9 r/ r/ r/ r/ r/ r/
':~
SN74ABT7820 512 18 12 r/ r/ r/ r/
~l"l1

~~
SN74ACT7881 lK 18 11 r/ r/ r/ r/
SN74ACT7811 lK 18 15 r/ r/ r/ r/

~ SN74ACT7802 lK 18 30 r/ r/ r/

i SN74ACT7882
SN74ACT7884
2K
4K
18
18
11
11
r/
r/
r/
r/
r/
r/
r/
r/
SN74ACT53861 4K 18 11 r/ r/ r/ r/ r/ r/
SN74ACT3638 512 32 11 r/ r/ r/ r/ r/ r/ r/
SN74ABT3611 64 36 10 r/ r/ r/ r/ r/ r/ r/
SN74ABT3613 64 36 10 r/ r/ r/ r/ r/ r/ r/ r/ r/
SN74ABT3612 64 36 10 r/ r/ r/ r/ r/ r/ r/ r/
SN74ABT3614 64 36 10 r/ r/ r/ r/ r/ r/ r/ r/ r/
SN74ACT3622 256 36 11 r/ r/ r/ r/ r/ r/
SN74ACT3631 512 36 11 r/ r/ r/ r/ r/ r/ r/
SN74ACT3632 512 36 11 r/ r/ r/ r/ r/ r/
SN74ACT3641 lK 36 11 r/ r/ r/ r/ r/ r/ r/
SN74ACT3642 lK 36 11 r/ r/ r/ r/ r/ r/
SN74ACT3651 2K 36 11 r/ r/ r/ r/ r/ r/ r/

* Bidirectional configurable without additional logic

 GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS

INTRODUCTION
These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC
Council of the Electronic Industries Association (EIA) for use in the USA and by the International
Electrotechnical Commission (IEC) for international use.

operating conditions and characteristics (in sequence by letter symbols)

Ci Input capacitance
The internal capacitance at an input of the device
Co Output capacitance
The internal capacitance at an output of the device
Cpd Power dissipation capacitance
Used to determine the no-load dynamic power dissipation per logic function (see individual circuit pages):
PD = Cpd Vee 2 f + lee Vee

f max Maximum clock frequency

The highest rate at which the clock input of a bistable circuit can be driven through its required sequence
while maintaining stable transitions of logic level at the output with input conditions established that
should cause changes of output logic level in accordance with the specification
Icc Supply current
The current into' the Vee supply terminal of an integrated circuit
L\lcc Supply current change
The increase in supply current for each input that is at one of the specified TIL voltage levels rather than
o V or Vee
ICEX Output high leakage current
The maximum leakage current into the collector of the pulldown output transistor when the output is high
and the output forcing conditionVo = 5.5 V

II(hold) Input hold current

Input current that holds the input at the previous state when the driving device goes to a high-impedance
state
IIH High-level input current
The current into' an input when a high-level voltage is applied to that input
IlL Low-level input current
The current into' an input when a low-level voltage is applied to that input
loft Input/output power-off leakage current
The maximum leakage current int%ut of the input/output transistors when forcing the input/output to
4.5 V and Vee = 0 V
IOH High-level output current
The current into' an output with input conditions applied that, according to the product specification, will
establish a high level at the output.
IOL Low-level output current
The current into' an output with input conditions applied that, according to the product specification, will
establish a low level at the output.
'Current out of a terminal is given as a negative value.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 1-7
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS

IOZ Off-state (hlgh-Impedance-state) output current (of a 3-state output)

The current flowing into· an output having 3-state capability with input conditions established that,
according to the product specification, will establish the high-impedance state at the output
ta Access time
The time interval between the application of a specified input pulse and the availability of valid signals
at an output
tc Clock cycle time
Clock cycle time is 1/fmax .
tdls Disable time (of a 3-state or open-collector output)
The propagation time between the specified reference pOints on the input and output voltage waveforms
with the output changing from either of the defined active levels (high or low) to a high-impedance (off)
state
NOTE: For 3-state outputs, ~is = tpHZ or tpLZ. Open-collector outputs will change only if they are low
at the time of disabling, so ~is = tpLH.
ten Enable time (of a 3-state or open-collector output)
The propagation time between the specified reference points on the input and output voltage waveforms
with the output changing from a high-impedance (off) state to either of the defined active levels (high or
low)
NOTE: In the case of memories, this is the access time from an enable input (e.g., OE). For 3-state
outputs, ten =tpZH ortpZL. Open-collector outputs will change only ifthey are responding to data
that would cause the output to go low, so ten = tpHL.
th Hold time
The time interval during which a Signal is retained at a specified input terminal after an active transition
occurs at another specified input terminal
NOTES: 1. The hold time is the actual time interval between two signal events and is determined by the
system in which the digital circuit operates. A minimum value is specified that is the shortest
interval for which correct operation of the digital circuit is to be expected.
2. The hold time may have a negative value in which case the minimum limit defines the longest
interval (between the release of the signal and the active tranSition) for which correct operation
of the digital circuit is to be expected.
tpd Propagation delay time
The time between the specified reference points on the input and output voltage waveforms with the
output changing from one defined level (high or low) to the other defined level (tpd = tpHL or tpLH)
tpHL Propagation delay time, hlgh-ta-Iow level output
The time between the specified reference points on the input and output voltage waveforms with the
output changing from the defined high level to the defined low level
tpHZ Disable time (of a 3-state output) from high level
The time interval between the specified reference pOints on the input and the output voltage waveforms
with the 3-state output changing from the defined high level to the high-impedance (off) state
tpLH Propagation delay time, low-ta-hlgh level output
The time between the specified reference points on the input and output voltage waveforms with the
output changing from the defined low level to the defined high level

·Current out of a terminal is given as a negative value.

~1ExAs
INSTRUMENTS
1-8 POST OFFICE eox _ . DAlI..AS. TEXAS 75266
 GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS

tpLZ Disable time (of a 3-state output) from low level

The time interval between the specified reference points on the input and the output voltage waveforms
with the 3-state output changing from the defined low level to the high-impedance (off) state
tpZH Enable time (of a 3-state output) to high level
The time interval between the specified reference points on the input and output voltage waveforms with
the 3-state output changing from the high-impedance (off) state to the defined high level
tpZL Enable time (of a 3-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms with
the 3-state output changing from the high-impedance (off) state to the defined low level
tsu Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent active
transition at another specified input terminal
NOTES: 1. The setup time is the actual time interval between two signal events and is determined by
the system in which the digital circuit operates. A minimum value is specified that is the shortest
interval for which correct operation of the digital circuit is to be expected.
2. The setup time may have a negative value, in which case the minimum limit defines the
longest interval (between the active transition and the application of the other signal) for which
correct operation of the digital circuit is to be expected.
tw Pulse duration (width)
The time interval between specified reference points on the leading and trailing edges of the pulse
waveform
VIH High-level Input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to represent
the binary variables
NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which
operation of the logic element within specification limits is to be expected.
VIL Low-level Input voltage
An input voltage within the less positive (more negative) of the two ranges of values used to represent
the binary variables
NOTE: A maximum is specified that is the most-positive value of low-level input voltage for which
operation of the logic element within specification limits is to be expected.
VOH High-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification,
will establish a high level at the output
VOL Low-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification,
will establish a low level at the output
VIT+ Positive-going Input threshold level
The voltage level at a transition-operated input that causes operation of the logic element according to
specification as the input voltage rises from a level below the negative-going threshold voltage, VIT-
VIT_ Negative-going Input threshold level
The voltage level at a transition-operated input that causes operation of the logiC element according to
specification as the input voltage falls from a level above the positive-going threshold voltage, VIT+

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1-9
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS

definitions
asynchronous FIFO
Data writes are initiated by a low-level pulse on the write-enable input when the full flag is not asserted. Likewise,
data reads are initiated by a low-level pulse on the read-enable input when the empty flag is not asserted. The
empty and full flags are not synchronized to a particular clock and reflect the instantaneous comparison of the
read and write pointers.
clocked FIFO
Data is written by a low-to-high transition of a write clock when write-enable inputs are asserted and the
input-ready flag is not asserted. Likewise, data is read by a low-to-high transition of a read clock when
read-enable inputs are asserted and the output-ready flag is asserted. The input-ready flag is multistaged
synchronized to the write clock and the ouput-ready flag is multistaged synchronized to the read clock,
improving metastability.
strobed FIFO
Data is written on a low-to-high transition on the load-clock input when the full flag is not asserted. Likewise,
data is read on a low-to-high transition on the unload-clock input when the empty-flag is not asserted. The empty
and full flags are not synchronized to a particular clock and reflect the instantaneous comparison of the read
and write pOinters.
synchronous FIFO
The term synchronous refers to a port-control method and does not imply that data writes and reads must be
synchronous to one another. Data is written by a low-to-high transition of a write clock when write-enable inputs
are asserted and the full flag is not asserted. Likewise, data is read by a low-to-high transition of a read clock
when read-enable inputs are asserted and the .empty flag is not asserted. The empty flag is single-staged
synchronized to the read clock, and the full flag is single-staged synchronized to the write clock.

-!!11ExAs
INSTRUMENTS
1-10 POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
 EXPLANATION OF FUNCTION TABLES

The following symbols are used in function tables on TI data sheets:

H high level (steady state)
L low level (steady state)
i transition from low to high level

--
J.. transition from high to low level
value/level or resulting value/level is routed to indicated destination
value/level is re-entered
X irrelevant (any input, including transitions)
z off (high-impedance) state of a 3-state output
a ... h the level of steady-state inputs A through H respectively
Qo level of Q before the indicated steady-state input conditions were established
00 a
complement of Qo or level of before the indicated steady-state input
conditions were established
level of Q before the most recent active transition indicated by J.. or i
...JL one high-level pulse
""1..J one low-level pulse
Toggle each output changes to the complement of its previous level on each active
transition indicated by J.. or i
If, in the input columns, a row contains only the symbols H, L, and/or X, this means the indicated output is valid
whenever the input configuration is achieved and regardless of the sequence in which it is achieved. The output
persists so long as the input configuration is maintained.
If, inthe input columns, a row contains H, L, and/or X together with i and/or J.., this means the output is valid whenever
the input configuration is achieved but the transition(s) must occur following the achievement of the steady-state
levels. If the output is shown as a level (H, L, Qo, or 00), it persists so long as the steady-state input levels and the
levels that terminate indicated transitions are maintained. Unless otherwise indicated, input transitions in the opposite
direction to those shown have no effect at the output. (If the output is shown as a pulse,...JL or ""1..J , the pulse follows
the indicated input transition and persists for an interval dependent on the circuit.)

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 1-11
EXPLANATION OF FUNCTION TABLES

Among the most complex function tables are those of the shift registers. These embody most of the symbols used
in any of the function tables, plus more. Below is the function table of a 4-bit bidirectional universal shift register, e.g.,
type SN74194. .

FUNCTION TABLE
INPUTS OUTPUTS
MODE SERIAL PARALLEL
CLEAR CLOCK
A B D
QA QB Qc QD
S1 SO LEFT RIGHT C
L X X X X X X X X X L L L L
H X X L X X X X X X QAO QBO Oeo QDO
H H H t x x a b c d a b c d
H L H t X H H H H H H QAn QBn QCn
H L H t X L L L L L L QAn QBn QCn
H H L t H X X X X X QBn QCn QDn H
H H L t L X X X X X QBn QCn QDn L
H L L X X X X X X X QAO QBO Oeo QDO

The first line of the table represents a synchronous clearing of the register and says that if clear is low, all four outputs
will be reset low regardless of the other inputs. In the following lines, clear is inactive (high) and so has no effect.
The second line shows that so long as the clock input remains low (while clear is high), no other input has any effect
and the outputs maintain the levels they assumed before the steady-state combination of clear high and clock low
was established. Since on other lines of the table only the rising transition of the clock is shown to be active, the second
line implicitly shows that no further change in the outputs will occur while the clock remains high or on the high-to-Iow
transition of the clock.
The third line of the table represents synchronou~ parallel loading of the register and says that if S1 and SO are both
high then, without regard to the serial input, the data entered at A will be at output QA, data entered at B will be at
Qs, and so forth, following a low-to-high clock transition.
The fourth and fifth lines represent the loading of high- and low-level data, respectively, from the shift-right serial input
and the shifting of previously entered data one bit; data previously at QA is now at Qs, the previous levels of Qs and
Qc are now at Qc and QD, respectively, and the data previously at QD is no longer in the register. This entry of serial
data and shift takes place on the low-to-high transition of the clock when S1 is low and SO is high and the leVels at
inputs A through 0 have no effect.
The sixth and seventh lines represent the loading of high- and lOW-level data, respectively, from the shift-left serial
input and the shifting of previously entered data one bit; data previously at Qs is now at QA, the previous levels of
Qc and QD are now at Qs and Qc, respectively, and the data previously at QA is no longer in the register. This entry
of serial data and shift takes place on the low-to-high transition of the clock when S1 is high and SO is low and the
levels at inputs A through 0 have no effect.
The last line shows that as long as both inputs are low, no other input has any effect and, as in the second line, the
outputs maintain the levels they assumed before the steady-state combination of clear high and both mode inputs
low was established.
The function table functional tests do not reflect all possible combinations or sequential modes.

~1ExAs
INSTRUMENTS
1-12 POST OFFICE BOX 86S303 • DALlAS. TEXAS 75266
 D FLIP-FLOP AND LATCH SIGNAL CONVENTIONS

It is normal TI practice to name the outputs and other inputs of a D-type flip-flop or latch and to draw its logic symbol
based on the assumption of true data (D) inputs. Outputs that produce data in phase with the data inputs are called
Q and those producing complementary data are called O. An input that causes a Q output to go high or a 0 output
to go low is called preset (PRE). An input that causes a 0 output to go high or a Q output to go low is called clear
(CLR). Bars are used over these pin names (PRE and CLR) if they are active low.
The devices on several data sheets are second-source designs, and the pin name conventions used by the original
manufacturers have been retained. That makes it necessary to designate the inputs and outputs of the inverting
circuits 0 and Q.
In some applications, it may be advantageous to redesignate the data input from D to 0 or vice versa. In that case,
all the other inputs and outputs should be renamed as shown below. Also shown are corresponding changes in the
graphical symbols. Arbitrary pin numbers are shown.

1 1
PRE
C
2 " SC1 5
Q 2 " C1R 5

3 3 ~
o 10 6 10 6
4 4 Q
ClR '" R '" S

LATCH LATCH

1 1
PRE
ClK
2 " S C1 5
Q
CUi
ClK
2
.1'-
R
C1
5

3 3
o 10 6 o " 10 6
Q
4 4
ClR " R PRE " S
FLIP-FLOP FUP-FlOP

The figures show that when Q and 0 exchange names, the preset and clear pins also exchange names. The polarity
indicators (t:,.) on PRE and CLR remain, as these inputs are still active low, butthe presence or absence ofthe polarity
indicator changes at D (or 0), Q, and O. Pin 5 (Q or 0) is still in phase with the data input (D or 0); their active levels
change together.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75285 1-13
1-14
 THERMAL INFORMATION

In digital system design, consideration must be given to thermal management of components. The small size of the
small-outline package makes this even more critical. Figure 1 shows the thermal resistance of these packages for
various rates of air flow.
The thermal resistances in Figure 1 can be used to approximate typical and maximum virtual junction temperatures.
In general, the junction temperature for any device can be calculated using using the following equation:
TJ = RaJA X PT + TA

where:
TJ virtual junction temperature
RaJA thermal resistance, junction to free air
PT total power dissipation of the device
TA free-air temperature

JUNCTION-TO-AMBIENT THERMAL RESISTANCE

vs
AIR VELOCITY
o
§ 130.---'---~--~r---.----r---'
14-Pln 0 Package
120r---~--_+.~--r---~---r--~
HI· Pin 0 Package
110~--~~~~~r---~---+--~
2D-Pln OW Package

100 200 300 400 500 600

Air Velocity - ftImln

Figure 1

Derating curves for 21 O-mil shrink small-outline package are shown in Figures 2 through 5.

-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 1-15
THERMAL INFORMATION

DERATING CURVES FOR 210-MIL SHRINK SMALL-OUTLINE PACKAGE (DB)

1200 I I I I I
1200
8Pln 16 Pin
1100 Air Velocity - ;=
;= (linear m/sec)
-
E

0
c
I
1000
900
=0
E 1000
c
0
I
~ ~::. r=- - -- - - -
~=-:

:;Co
-r::- F$
0;;:
:.:
800 I 800 r--- .
.
'iii
is
700
-=is
r--.. .......
r--.. ........ 1-0..
0;;:
:--

~0
600
I 600
-r--..,
a. 500
- l"- I'-
- a. ........
r--.. ........ 1-0..
- -
E E Air Velocity
::I
E
';(
III
:::E
400

300
r- I'-
I"-
.::I
E
III
:::E
400 -
----
----
(linear m/sec)
=1
=0.75
.......
r--..
I 200 I 200 - --- =0.5
0.0
100
rf' - - =0.25

o o I I I =~ I
25 30 35 40 45 50 55 60 65 70 75 80 85 90 25 30 35 40 45 50 55 60 65 70 75 80 85 90
TA - Free-Air Temperature - ·c TA - Free-Air Temperature - ·C

Figure 2 Figure 3

1400 1400
20 Pin
I I I I I I 24 Pin I I I I I I
2200 Air Velocity - 2200 Air Velocity -
;= (linear m/sec)
;= (linear m/sec)
E
I
2000 - E
I
2000 -
c ---- =1 c ---- =1
1800 ---- =0.75 - 1800 ---- =0.75-
i'gj
0

t 1600 --- =0.5 _ 1600 --- =0.5 _

.
'iii
is 1400
- - =0.25
=0 - is 1400
- - =0.25
=0 -
! ! 1200

- --
1200
a. 1000
~ a. 1000
~~
":";:
E
::I
E
';(
III
:::E
I
800

600
400
~ ~ '::..-:-
- ;;::::: 1=:,-::: ":..:: ~
-. -Jo;::::
E

..
::I
E
III
:::E
I
800

600

400
I"- to-- f"":: F-t §;; ~...: ~
I"- - ; - . ~
.
r:::... ;:::,
. ~

0.0 0.0
200 200
o o
25 30 35 40 45 50 55 60 65 70 75 80 85 90 25 30 35 40 45 50 55 60 85 70 75 80 85 90
TA - Free-Air Temperature - ·C TA - Free-Air Temperature - ·C

Figure 4 Figure 5

~1ExAs
INSTRUMENTS
1-16 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-1
 TELECOM SINGLE-BIT FIFOS
Features Benefits

• O.8-j.lm CMOS process • High-performance, low-power process

• Dual independent FIFOs • Allow either a transmit and receive
configuration, two transmits, or two
receive operations
g • Separate inputs, outputs, resets, and
enables
• Greater design flexibility
C'D
(")
o • Synchronous IR and OR flags • Flag synchronization is done on chip.
3
_.
en •
•
Tl's advanced clocked interface
Empty, full, and aimost-fuil/aimost-empty
•
•
Support free-running clocks with enables
Multiple status flags enables greater
flags system control

-
_.
!!
"T1
oen
• -40°C/85°C characterization • Industrial temperature range for field
applications

2-2
 SN74ACT2226, SN74A CT2228
DUAL 64 x 1, DUAL 256 x 1
CLOCKED FIRST·IN FIRST·OUT MEMORIES
SCAS219B-

• Dual Independent FIFOs Organized as: OW PACKAGE

(TOP VIEW)
64 Words by 1 Bit Each - SN74ACT2226
256 Words by 1 Bit Each - SN74ACT2228
1HF 1ROCLK
• Free-Running Read and Write Clocks Can 1AF/AE 1ROEN
Be Asynchronous or Coincident on Each 1WRTCLK 3 lOR
FIFO 1WRTEN 4 10
• Input-Ready Flags Synchronized to Write 11R 2RESET
Clocks 10 Vee
• Output-Ready Flags Synchronized to Read GNO 7 20
Clocks 21R
• Half-Full and Almost-FuIl/Almost-Empty 2WRTEN
Flags 20R 2WRTCLK
2ROEN 11 2AF/AE
• Support Clock Frequencies up to 22 MHz
2ROCLK 2HF
• Characterized for Operation Over the
Industrial Temperature Range:
-40°C to 85°C
• Access Times of 20 ns
• Low-Power Advanced CMOS Technology
• Available in 24-Pin SOIC (OW) Package

description
The SN74ACT2226 and SN74ACT2228 are dual FIFOs suited for a wide range of serial-data buffering
applications including elastic stores for frequencies up to T2 telecommunication rates. Each FIFO on the chip
is arranged as 64 x 1 (SN74ACT2226) or 256 x 1 (SN74ACT2228) and has control signals and status flags for
independent operation. Output flags per FIFO include input ready (11R or 2IR), output ready (10R or 20R),
half full (1 HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).
Serial data is written into a FIFO on the low-to-high transition of the write-clock (1 WRTCLK or 2WRTCLK) input
when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (11R or 21R) output are both high.
Serial data is read from a FIFO on the low-to-high transition of the read-clock (1 RDCLK or 2RDCLK) input when
the read-enable (1 RDEN or 2RDEN) input and output-ready flag (1 OR or 20R) output are both high. The read
and write clocks of a FIFO can be asynchronous to one another.
Each input-ready flag (11R or 21R) is synchronized by two flip-flop stages to its write clock (1 WRTCLK or
2WRTCLK), and each output-ready flag (1 OR or 20R) is synchronized by three flip-flop stages to its read clock
(1 RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written
and read asynchronously.
A half-full flag (1 HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half
the depth of the FIFO. An almost-full/almost-empty flag (1 AF/AE or 2AF/AE) is high when eight or less bits are
stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data output
is not stored in the FIFO.
The SN74ACT2226 and SN74ACT2228 are characterized for operation from -40°C to 85°C.
For more information on this device family, see the application report FIFOs With a Word Width of One Bit in
the 1996 High-Performance FIFO Memories DeSigner's Handbook, literature number SCAA012A.

Copyright © 1995, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-3
SN74ACT2226, SN74ACT2228
DUAL 64 x 1, DUAL 256 x 1
CLOCKED FIRST·IN, FIRST·OUT MEMORIES
SCAS219B - JUNE 1992 - REVISED SEPTEMBER 1995

logic symbolst
<l>
FIFO 64 x 1
SN14ACT2226
8
1RESET
3
" RESET
INRDY
5
llR
lWRTCLK WRTCLK 1
4 HALF FULL lHF
lWRTEN WRTEN 2
24 ALMOST FULUEMPTY lAF/AE
lRDCLK RDCLK 22
OUTRDY lOR
lRDEN
23

6
,
I
RDEN
r 21
lD lQ

20
2RESET
15
" RESET
INRDY
17
21R
2WRTCLK WRTCLK 13
16 HALF FULL 2HF
2WRTEN WRTEN 14
12 ALMOST FULUEMPTY 2AF/AE
2RDCLK RDCLK 10

,
11 OUTRDY 20R
2RDEN RDEN
18
r 9
I
2D 2Q

<l>
FIFO 256 x 1
8 SN74ACT2228
1RESET
3
'" RESET
INRDY
5
llR
lWRTCLK WRTCLK 1
4 HALF FULL lHF
lWRTEN WRTEN 2
24 ALMOST FULUEMPTY lAF/AE
1RDCLK RDCLK 22
OUTRDY lOR
lRDEN
23

6
,
I
RDEN
r 21
lD 1Q

20 r-..
2RESET RESET 17
15 INRDY 21R
2WRTCLK WRTCLK 13
16 HALF FULL 2HF
2WRTEN WRTEN 14
12 ALMOST FULUEMPTY 2AF/AE
2RDCLK RDCLK 10

,
11 OUT RDY 20R
2RDEN RDEN

18
r 9
I
2D 2Q

t These symbols are in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.

~TEXAS
INSTRUMENTS
2-4 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT2226, SN74ACT2228
DUAL 64 x 1, DUAL 256 x 1
CLOCKED FIRST·IN, FIRST·OUT MEMORIES
SCAS219B - JUNE 1992 - REVISED SEPTEMBER 1995

SN74ACT2226 functional block diagram (each FIFO)

D

RDCLK Synchronous ~
rl Read ~
"
Location 1
Location 2
RDEN Read Control Pointer
Dual·Port
SRAM
64x 1
~ ~
WRTCLK Synchronous ~ Write
WRTEN Write Control Pointer Location 63

"-- r-
,.
Location 64

Register Q

AF/AE
Status
- r--- HF
Reset
'-- IR
Logic
OR

SN74ACT2228 functional block diagram (each FIFO)

D ,.
Location 1
RDCLK Synchronous ~
Read Control
~ Read
Pointer
~ Location 2
RDEN
Dual·Port
SRAM

~ ~
WRTCLK I 256 x 1
Synchronous
Write
WRTEN Write Control Pointer Location 255

"-- r-
,.
Location 256

Register Q

AF/AE
Status
- r--- HF
Reset
- Logic
IR
OR

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-5
SN74ACT2226, SN74ACT2228
DUAL 64 x 1, DUAL 256 x 1
CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS219B-JUNE 1992- REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME NO.
1AF/AE 2 Aimost-fuil/almost-emptyflag. AF/AE is high when the memory is eight locations or less from a full or empty state.
a
2AF/AE 14 AF/AE is set high after reset.
1D 6
I Data input
2D 18
,
GND 7 Ground
1HF 1 Half-full flag. HF is high when the numberof bits stored in memory is greater than or equal to half the FIFO depth.
a
2HF 15 HF is set low after reset.
Input-ready flag. IR is synchronized to the low-to-high transition ofWRTCLK. When IR is low, the FIFO is full and
11R 5
a writes are disabled. IR is set low during reset and is set high on the second low-to-high transition of WRTCLK
21R 17
after reset.
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FI Fa is empty
lOR 22
0 and reads are disabled. Ready data is present on the data output when OR is high. OR is set low during reset
2aR 10
and set high on the third low-te-high transition of RDCLK after the first word is loaded to empty memory.
1Q 21 Data outputs. After the first valid write to empty memory, the first bit is output on the third rising edge of RDCLK.
0
2Q 9 OR for the FIFO is asserted high to indicate ready data.
Read clock. RDCLK is a continuous clock and can be independent of any other clock on the device. A low-ta-high
1RDCLK 24
I transition of RDCLK reads data from memory when the FIFO RDEN and OR are high. OR is synchronous with
2RDCLK 12
the low-ta-high transition of RDCLK.
1RDEN 23 Read enable. When the RDEN and OR of a FIFO are high, data is read from the FIFO on the low-ta-high transition
I
2RDEN 11 of RDCLK.
Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-ta-high transitions of WRTCLK must
1RESET 8
I occur while RESET is low. This sets HF, IR, and OR low and AF/AE high. Before it is used, a FIFO must be reset
2RESET 20
after power up:
VCC 19 Supply voltage
Write clock. WRTCLK is a continuous clock and can be independent of any other clock on the device. A
1WRTCLK 3
I low-to-high transition of WRTCLK writes data to memory when WRTEN and IR are high. IR is synchronous with
2WRTCLK 15
the low-ta-high transition of WRTCLK.
1WRTEN 4
I Write enable. When WRTEN and IR are high, data is written to the FIFO on a low-la-high transition of WRTCLK.
2WRTEN 16

~1ExAs
INSTRUMENTS
2-6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT2226, SN74ACT2228
DUAL 64 x 1, DUAL 256 x 1
CLOCKED FIRST·IN, FIRST·OUT MEMORIES
SCAS219B - JUNE 1992 - REVISED SEPTEMBER 1995

Figure 1. FIFO Reset

-!!I TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265 2-7
SN74ACT2226, SN74ACT2228
DUAL 64 x 1, DUAL 256 x 1
CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS219B - JUNE 1992 - REVISED SEPTEMBER 1995

RESET
-------------------------------------------------------------1 0

~r-f1--,~r--fL
WRTCLK

WRTEN Ir------------------------~I--------~------~I--------Ir--01
--I I I I
I I I I
DQAASIB1@B2~B3@B4_ B:10. f. f ~ f ts?
RDCLK

I
~~A-,A
I I I I
ROEN I I I I I 1
------------------~I--------~I------~I------~I~----~I---O

0: ~"'-------L....---;-----1...-;.,--------1...---; ----L...--i

I
I
AF/AE

HF

IR
L
DATA BIT NUMBER BASED ON FIFO DEPTH
DATA BIT
DEVICE
A B C
SN74ACT2226 B33 B57 B65
SN74ACT2228 8129 8249 8257

Figure 2. FIFO Write

~TEXAS
INSTRUMENTS
2-8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT2226, SN74ACT2228
DUAL 64 x 1, DUAL 256 x 1
CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS219B - JUNE 1992 - REVISED SEPTEMBER 1995

............................................................................................................................- - 1
REm 0

WRTCLK

RDCLK

RDEN ....-+-...........

Q_.,....;;.B_1........>OD<
OR

AF/AE

HF

I R - i..................................

DATA BIT NUMBER BASED ON FIFO DEPTH

DATA BIT
DEVICE
A B C D E F
SN74ACT2226 833 834 856 857 864 865
SN74ACT2228 8129 8130 8248 8249 8256 8257

Figure 3. FIFO Read

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ....................................... -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI> Vecl ...........................•................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ........................................... ±50 mA
Continuous output current, 10 (VO =- 0 to Vecl ............................................. ±50 mA
Continuous current through Vee or GND ................................................. ±200 mA
Operating free-air temperature range, TA ........................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any othar conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided that the input and output current ratings are observed.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OAlLAS. TEXAS 75265 2-9
 SN74ACT2226, SN74ACT2228
DUAL 64 x 1, DUAL 256 x 1
.CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS219B - JUNE 1992 - REVISED SEPTEMBER 1995

recommended operating conditions

MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current Q outputs, Flags -8 mA
Qoutputs 16
IOL Low-level output current mA
Flags 8
TA Operating free-air temperature -40 85 ·C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYpt MAX UNIT
VOH VCC=4.5V, IOH=-8mA 2.4 V
IFlags VCC=4.5V, IOL-8 mA 0.5
V
VOL
I Qoutputs VCC=4.5V, IOL-16 mA 0.5
II VCC=5.5V, VI- VccorO ±5 ILA
IOZ VCC-5.5V, Vo = VCC orO ±5 jJA
ICC VI = VCC - 0.2 V or 0 400 jJA
AICC:I: VCC=5.5V, One input at 3.4 V, Other inputs at VCC or GND 1 mA
Ci VI=O, f.1 MHz 4 pF
Co VO-O, f= 1 MHz 8 pF
t All typical values are at VCC = 5 V, TA = 25·C.
:I: This is the supply .:urrent when each input is at one of the specified TIL voltage levels rather than 0 V or VCC.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 1 through 3)
MIN MAX UNIT
fclock Clock frequency 22 MHz
1WRTCLK, 2WRTCLK high or low 15
tw Pulse duration ns
1RDCLK, 2RDCLK high or low 15
10 before 1WRTCLKi and 20 before 2WRTCLKi 6
1WRTEN before 1WRTCLKi and 2WRTEN before 2WRTCLKi 6
tsu Setup time 1RDEN before 1RDCLKi and 2RDEN before 2RDCLKi 6 ns
1RESET low before 1WRTCLKi and 2RESET low before 2WRTCLKi§ 6
1RESET low before 1RDCLKi and 2RESET low before 2RDCLKi§ 6
10 aiter 1WRTCLKi and 20 aiter 2WRTCLKi 0
1WRTEN aiter 1WRTCLKi and 2WRTEN aiter 2WRTCLKi 0
th Hold time 1RDEN aiter 1RDCLKi and 2RDEN after 2RDCLKi 0 ns
1RESET low aiter 1WRTCLKi and 2RESET low aiter 2WRTCLKi§ 6
1RESET low aiter 1RDCLKi and 2RESET low aiter 2RDCLKi§ 6
§ ReqUirement to count the clock edge as one of at least four needed to reset a FI FO

~lExAs
INSTRUMENTS
2-10 POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
 SN74ACT2226, SN74ACT2228
DUAL 64 x 1, DUAL 256 x 1
CLOCKED FIRST-IN, FIR$T-OUT MEMORIES
SCAS219B - JUNE 1992 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 4)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
1WRTCLK,2WRTCLK,
fmax 22 MHz
or 1RDCLK, 2RDCLK
tpd 1RDCLKi, 2RDCLKi 1Q,2Q 2 20 ns
tpd 1WRTCLKi,2WRTCLKi 11R,21R 1 20 ns
tpd 1RDCLKi, 2RDCLKi 10R,20R 1 20 ns
1WRTCLKi,2WRTCLKi 3 20
tpd 1AF/AE,2AF/AE ns
1RDCLKi, 2RDCLKi 3 20
tpLH 1WRTCLKi,2WRTCLKi 2 20
1HF,2HF ns
tpHL 1RDCLKi, 2RDCLKi 3 20
tpLH 1AF/AE,2AF/AE 1 20
1RESET, 2RESET low ns
tpHL 1HF,2HF 1 20

PARAMETER MEASUREMENT INFORMATION

FruomdOuTtputt
n ar as =n T
Clock Input

I
I r----~:--r
I
----
3V

OV

VOH

Wp~ i. ~'----
RL=500Q CL=50pF Output

'PHL VOL
-- --
LOAD CIRCUIT VOLTAGE WAVEFORMS

Figure 4. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 2-11
SN74ACT2226, SN74ACT2228
DUAL 64 x 1, DUAL 256 x 1
CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS219B - JUNE 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS
SINGLE FIFO SUPPLY CURRENT
VB
CLOCK FREQUENCY

18 fl =112fclock -i---+----jf---::I
TA =75°C
16 CL=OpF

141----+--
121----+---r--~~~~-~

10f---+---r-~~7'

81----+--~~~+_--1--~

ff 61----+--7~"'---+_-_+---I
4f--~~~-r--+--~--~

2f-~~---r--+--~--~

O~-~---L--~-~--~
o 5 10 15 20 25
fclock - Clock Frequency - MHz
FigureS

calculating power dissipation

Data for Figure 5 is taken with one FIFO active and one FIFO idle on the device. The active FIFO has both writes
and reads enabled with its read clock (RDCLK) and write clock (WRTCLK) operating at the rate specified by
fclock' The data input rate and data output rate are half the fclock rate, and the data output is disconnected. A
close approximation to the total device power can be found by using Figure 5, determining the capacitive load
on the data output and determining the number of SN74ACT2226/2228 inputs driven by TTL high levels.
With ICC(I) taken from Figure 5, the maximum power dissipation (PT) of one FIFO on the SN74ACT2226 or
SN74ACT2228 can be calculated by:
PT = VCC x [ICC(I) + (N x ~Icc x dc)] + (Cl x VCc2 x fo)
where:
N number of inputs driven by TTL levels
~Icc increase in power supply current for each input at a TTL high level
dc duty cycle of inputs at a TTL high level of 3.4 V
Cl output capacitive load
fo switching frequency of an output

~1ExAs
INSTRUMENTS
2-12 POST OFFICE BOX 655303. DALlAS, TEXAS 75285
 SN74ACT2226, SN74ACT2228
DUAL 64 x 1, DUAL 256 x 1
CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS219B - JUNE 1992 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION

An example of concentrating two independent serial-data signals into a single composite data signal with the use of
an SN74ACT2226 or SN74ACT2228 device is shown in Figure 6. The input data to the FIFOs share the same average
(mean) frequency and the mean frequency of the SYS_CLOCK is greater than or equal to the sum of the individual
mean input rates. A single-bit FIFO is needed for each additional input data signal that is time-division multiplexed
into the composite signal.
The FI FO memories provide a buffer to absorb clock jitter generated by the transmission systems of incoming signals
and synchronize the phase-independent inputs to one another. FIFO half-full (HF) flags are used to signal the
multiplexer to start fetching data from the buffers. The state of the flags can also be used to indicate when a FIFO
read should be suppressed to regulate the output flow (pulse-stuffing control). The FIFO aimost-fuil/aimost-empty
flags (AF/AE) can be used in place of the half-full flags to reduce transmission delay.

SN74ACT2226
or
SN74ACT2228

+5V I
1HF
1WRTCLK 1RDCLK ~ READY_1
Serial {
Data ~ 1WRTEN 1RDEN SELECT_1
Stream 1D 1Q DATA_1
Composite
Time-Division
Data Stream
-
Serial {
Data
Stream ---- 2WRTCLK 2RDCLK
2WRTEN 2RDEN
Multiplexer
SELECT_2
2D
2HF
I
2Q
I DATA 2
READY_2

Figure 6. Time-Division Multiplexing Using the SN74ACT2226 or SN74ACT2228

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-13
2-14
 SN74ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST·IN, FIRST·OUT MEMORIES
SCAS220B - JUNE 1992 - I 1995

• Dual Independent FIFOs Organized as: ow PACKAGE

(TOP VIEW)
64 Words by 1 Bit Each - SN74ACT2227
256 Words by 1 Bit Each - SN74ACT2229
1HF 1 10E
• Free-Running Read and Write Clocks Can
1AF/AE 1RDCLK
Be Asynchronous or Coincident on Each
1WRTCLK 1RDEN
FIFO
1WRTEN lOR
• Input· Ready Flags Synchronized to Write 11R 10
Clocks 2RESET
• Output-Ready Flags Synchronized to Read Vee
Clocks Vee
• Half-Full and Almost·FuIl/Almost-Empty 1RESET 9 2D
Flags 20 21R
• Characterized for Operation Over the 20R 11 2WRTEN
Industrial Temperature Range: 2RDEN 2WRTCLK
-40°C to 85°C 2RDCLK 2AF/AE
20E 2HF
• Support Clock Frequencies up to 60 MHz
• Access Times of 9 ns
• 3·State Data Outputs
• Low-Power Advanced CMOS Technology
• Available in 28-Pin SOIC (OW) Package

description
The SN74ACT2227 and SN74ACT2229 are dual FIFOs suited for a wide range of serial-data buffering
applications including elastic stores for frequencies up to OC-1 telecommunication rates. Each FIFO on the chip
is arranged as 64 x 1 (SN74ACT2227) or 256 x 1 (SN74ACT2229) and has control signals and status flags for
independent operation. Output flags per FIFO include input ready (11R or 2IR), output ready (10R or 20R),
half full (1 HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).
Serial data is written into a FIFO on the low-to-high transition of the write-clock (1 WRTCLK or 2WRTCLK) input
when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (lIR or 21R) output are both high.
Serial data is read from a FIFO on the low-to-high transition of the read-clock (1 RDCLK or 2RDCLK) input when
the read-enable (1 RDEN or 2RDEN) input and output-ready flag (1 OR or 20R) output are both high. The read
and write clocks of a FIFO can be asynchronous to one another. A FIFO data output (1Q or 2Q) is in the
high-impedance state when its output-enable (1 OE or 20E) input is low.
Each input-ready flag (11R or 21R) is synchronized by two flip-flop stages to its write clock (1 WRTCLK or
2WRTCLK), and each output-ready flag (1 OR or 20R) is synchronized by three flip-flop stages to its read clock
(1 RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written
and read asynchronously.
A half-full flag (1 HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half
the depth of the FIFO. An almost-full/almost-empty flag (1 AF/AE or 2AF/AE) is high when eight or less bits are
stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data output
is not stored in the FIFO.
The SN74ACT2227 and SN74ACT2229 are characterized for operation from -40°C to 85°C.
For more information on this device family, see the application report FIFOs With a Word Width of One Bit in
the 1996 High-Performance FIFO Memories Designer's Handbook, literature number SCAA012A.

Copyright © 1995, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 2-15
SN74ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220B - JUNE 1992 - REVISED SEPTEMBER 1995

logic symbolst

C!>
FIFO 64x 1
9 SN74ACT2227
1RESET
lWRTCLK
3 " RESET
WRTCLK
INRDY
5
llR
1
4 HALF FULL lHF
lWRTEN WRTEN 2
27 ALMOST FULUEMPTY lAF/AE
lRDCLK RDCLK 25
28 OUTRDY lOR
10E ENl
lRDEN
26

6
.,
RDEN
L
1'1
24
lQ
lD

23 r-... RESET
2RESET
17
2WRTCLK WRTCLK 19
18 INRDY 21R
2WRTEN WRTEN 15
HALF FULL 2HF
13 16
2RDCLK RDCLK 2AF/AE
ALMOST FULUEMPTY
14 11

.,
20E EN2 OUTRDY 20R
12
2RDEN RDEN

20
L 10
2D 2'1 2Q

C!>
FIFO 256 x 1
9 SN74ACT2229
1RESET
3
" RESET
INRDY
5
llR
lWRTCLK WRTCLK 1
4 HALF FULL lHF
lWRTEN WRTEN 2
27 ALMOST FULUEMPTY lAF/AE
lRDCLK RDCLK 25
28 OUTRDY lOR
10E ENl
26
lRDEN

6
..,
RDEN
r 24
lD 1'1 lQ

23
2RESET
17
" RESET
2WRTCLK WRTCLK 19
18 INRDY 21R
2WRTEN WRTEN 15
HALF FULL 2HF
13 16
2RDCLK RDCLK 2AF/AE
ALMOST FULUEMPTY
14 11
20E EN2 OUTRDY 20R
2RDEN

2D
12

20
,RDEN
r 10
2'1 2Q

t These symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.

~lExAs
INSTRUMENTS
2-16 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220B - JUNE 1992 - REVISED SEPTEMBER 1995

SN74ACT2227 functional block diagram (each FIFO)

OE
D
t
Location 1
RDCLK
RDEN
Synchronous ~
Read Control ~ Read
Pointer ~ Location 2

Dual-Port
SRAM
64x 1
WRTCLK
Synchronous ~
Write Control
~ Write
Pointer
~
WRTEN Location 63
Location 64

~
c--
- -

Status
" H>--
Reglater Q
AF/AE
HF
- Reset Logic IR
OR

SN74ACT2229 functional block diagram (each FIFO)

OE
D
t
Location 1
RDCLK
RDEN
Synchronous ~
Read Control
~ Read
Pointer
~ Location 2

Dual-Port
SRAM
256 x 1
~ ~
WRTCLK
Synchronous ~ Write
WRTEN Write Control Pointer Location 255
Location 256

-
- -

Status
" H>--
Register Q
AF/AE
~
HF
'-- Reset Logic IR
--""
OR

'!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 2-17
SN14ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220B- JUNE 1992 - REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME NO.
1AF/AE 2 Aimost-fuil/almost-empty flag. AF/AE is high when the memory is eight locations or less from a full or empty
0
2AF/AE 16 state. AF/AE is set high after reset.
10 6
I Data input
20 20
GND 7,8 Ground
1HF 1 Half-full flag. HF is high when the number of bits stored in memory is greater than or equal to half the FI FO depth.
0
2HF 15 HF is set low after reset.
Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO is full
llR 5
0 and writes are disabled. IR is set low during reset and is set high on the second low-to-high transition of
21R 19
WRTCLK after reset.
lOE 28 Output enable. The data output of a FI FO is active when OE is high and in the high-impedance state when OE
I
20E 14 is low.
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is
lOR 25
0 empty and reads are disabled. Ready data is present on the data output when OR is high. OR is set low during
20R 11
reset and set high on the third low-to-high transition of RDCLK after the first word is loaded to empty memory.
10 24 Data outputs. After the first valid write to empty memory, the first bit is output on the third rising edge of RDCLK.
0
20 10 OR for the FI FO is asserted high to indicate ready data.
Read clock. RDCLK is a continuous clock and can be independent of any other clock on the device. A
lRDCLK 27
I low-to-high transition 01 RDCLK reads data from memory when the FIFO RDEN and OR are high. OR is
2RDCLK 13
synchronous with the low-to-high transition of RDCLK.
1RDEN 26 Read enable. When the RDEN and OR of a FIFO are high, data is read from the FIFO on the low-ta-high
I
2RDEN 12 transition of RDCLK.
Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK
lRESET 9
I must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high. Before it is used, a FIFO must
2RESET 23
be reset after power up.
Vee 21,22 Supply voltage
Write clock. WRTCLK is a continuous clock and can be independent of any other clock on the device. A
lWRTCLK 3
I low-to-high transition of WRTCLK writes data to memory when WRTEN and IR are high. IR is synchronous with
2WRTCLK 17
the low-to-high transition of WRTCLK.
1WRTEN 4
I Write enable. When WRTEN and IR are high, data is written tothe FIFO on a low-to-high transition of WRTCLK.
2WRTEN 18

~TEXAS
INSTRUMENTS
2-18 POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
 SN74ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220B - JUNE 1992 - REVISED SEPTEMBER 1995

WRTCLK

RDCLK

OE

IR~
Figure 1. FIFO Reset

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-19
SN74ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220B - JUNE 1992 - REVISED SEPTEMBER 1995

RESET - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0
1

~r---f1--,~~
WRTCLK

WRTEN Ir--------------------------~I--------+--------+I--------rl---01
---I

r. f
I I 1
1 1 1 1
DQS&SIB1@B2~B3@B4_ B~O= ~ Q I§
RDCLK
~~~J!L
RDEN
---------+-1----+-1
I . :. I : 1 1
----If--·-----!I-----+I-- 0

: :., : :
1 1 I I I 1

o:~ Q

OR __________________~I

AF/AE

HF

IR
L
DATA BIT NUMBER BASED ON FIFO DEPTH
DATA BIT
DEVICE
A B C
SN74ACT2227 933 957 965
SN74ACT2229 9129 9249 9257

Figure 2. FIFO Write

~1ExAs.
INSTRUMENTS
2-20 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220B - JUNE 1992 - REVISED SEPTEMBER 1995

RESET -----------------------------------------------------------1 0

WRTCLK

I I
W~EN~~__________~I---------------------------------------
D ~~
I
I
RDCLK

RDEN_+-__...... I I I I I
I I I I I
oE--T-----~I--------I~----~I~----~I--------~I----------~I-----1
I I I I I I 0

Q_-r-- B1___ 0 r3 :~~~~ :F

OR II II II I
~ ___
I I I
AF/AE --+-------------+-----......1 : 11------------------
HF I I
IR --i~ ____________....
DATA BIT NUMBER BASED ON FIFO DEPTH
DATA BIT
DEVICE
A B C D E F
SN74ACT2227 833 834 856 857 864 865
SN74ACT2229 8129 8130 8248 8249 8256 8257

Figure 3. FIFO Read

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265 2-21
SN74ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220B - JUNE 1992 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ....................................... -0.5 V to Vee + 0.5 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Input clamp current, 11K (VI < 0 or VI> Vecl ............................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vecl ........................................... ±50 mA
Continuous output current, 10 (VO = 0 to Vecl ............................................. ±50 mA
Continuous current through Vee or GND ................................................. ±200 mA
Operating free-air temperature range, TA ........................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
lunctional operation 01 the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions lor extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided that the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL LOW-level input voltage 0.8 V
IOH High-level output current Q outputs, Flags -8 mA
Qoutputs 16
IOL Low-level output current mA
Flags 8
TA Operating Iree-air temperature -40 85 ·e

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP:j: MAX UNIT
VOH Vee=4.5 V, IOH =-8mA 2.4 V
I Flags Vee = 4.5 V, IOL= 8 mA 0.5
V
VOL
I Qoutputs Vee = 4.5 V, IOL= 16mA 0.5
II Vee=5.5V, VI =Vee orO ±5 ~
loz Vee = 5:5 V, Vo=Vee orO ±5 ~
ICC VI = Vee - 0.2 V or 0 400 ~
Alee§ Vee=5.5V, One input at 3.4 V, Other inputs at Vee or GND 1 mA
ei VI = 0, 1= 1 MHz 4 pF
Co VO=O, 1= 1 MHz 8 pF
:t All tYPical values are at Vee = 5 V, TA = 25·e.
§ This is the supply current when each input is at one 01 the specified TIL voltage levels rather than 0 V or Vee.

~TEXAS
INSTRUMENTS
2-22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220B - JUNE 1992 - REVISED SEPTEMBER 1995

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 1 through 3)
MIN MAX UNIT
fclock Clock frequency 60 MHz
1WRTCLK, 2WRTCLK high or low 5
tw Pulse duration ns
1RDCLK, 2RDCLK high or low 5
1D before 1WRTCLKi and 2D before 2WRTCLKi 4.5

, tsu Setup time

1WRTEN before 1WRTCLKi and 2WRTEN before 2WRTCLKi
1RDEN before 1RDCLKi and 2RDEN before 2RDCLKi
4.5
4 ns
1RESET low before 1WRTCLKi and 2RESET low before 2WRTCLKit 6
1RESET low before 1RDCLKi and 2RESET low before 2RDCLKit 6
1D aiter 1WRTCLKi and 2D aiter 2WRTCLKi a
1WRTEN aiter 1WRTCLKi and 2WRTEN aiter 2WRTCLKi a
th Hold time 1RDEN aiter 1RDCLKi and 2RDEN after 2RDCLKi a ns
1RESET low after 1WRTCLKi and 2RESET low aiter 2WRTCLKit 6
1RESET low aiter 1RDCLKi and 2RESET low aiter 2RDCLKit 6
t Requirement to count the clock edge as one of at least four needed to reset a FIFO

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 50 pF (unless otherwise noted) (see Figure 4)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
1WRTCLK,2WRTCLK,
fmax 60 MHz
or 1RDCLK, 2RDCLK
tpd 1RDCLKi, 2RDCLKi 10,20 2 9 ns
tDd 1WRTCLKi,2WRTCLKi 11R,21R 1 8 ns
tpd 1RDCLKi, 2RDCLKi 10R,20R 1 8 ns
1WRTCLKi,2WRTCLKi 3 14
tpd 1AF/AE,2AF/AE ns
1RDCLKi,2RDCLKi 3 14
tpLH 1WRTCLKi,2WRTCLKi 2 12
1HF,2HF ns
tPHL 1RDCLKi, 2RDCLKi 3 14
tpLH 1AF/AE,2AF/AE 1 17
1RESET, 2RESET low ns
tPHL 1HF,2HF 1 18
len
10E,20E 10,20
a 8
ns
tdis a 8

-!11 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 2-23
SN74ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220B-JUNE 1992 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

Rl= R1 = R2
Clock Input
OV
R1

,
From Output Test Point
Under Test -----<t--_-....- - - - VOH
R2 Output

'PHL I,
I
1'----VOl
I
lOAD CIRCUIT VOLTAGE WAVEFORMS

Input ~1.5V -.r:::- 3V

tPZl-.J
~=~--OV
~ I
I I tPLZ -+J I+-
~
II ~3.5V

Output I
I
I I
--
*- 1.5 V

I +l J+-
--t..- VOL

r
tpHZ 0.3 V
tpZH~ ~ . I ~
I . . . . Y - - VOH
Output 1.5V ~V ~OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES

PARAMETER R1, R2 clt S1

tpZH Open
ten 5000 50pF
tpZL Closed
tpHZ Open
tdis 5000 50pF
tpLZ Closed
tpd 5000 50 pF Open
t Includes probe and test-ilxture capacitance
Figure 4. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
2-24 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220B-JUNE 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS
SINGLE FIFO SUPPLY CURRENT
vs
CLOCK FREQUENCY

40

35
~
I
30
~
a 25

i::s
II)
20
I
15
5:
0
_0 10
'I =1/2 'clock
5 f--:A'9---t---t---+ TA =75°C
CL=OpF
0
0 10 20 30 40 50 50

'clock - Clock Frequency - MHz

FigureS

calculating power dissipation

Data for Figure 5 is taken with one FIFO active and one FIFO idle on the device. The active FIFO has both writes
and reads enabled with its read clock (RDCLI<) and write clock (WRTCLI<) operating at the rate specified by
fclock. The data input rate and data output rate are half the fclock rate, and the data output is disconnected. A
close approximation to the total device power can be found by Figure 5, determining the capacitive load on the
data output and determining the number of SN74ACT2227/2229 inputs driven by TIL high levels.
With lee(!} taken from Figure 5, the maximum power dissipation (PT) of one FIFO on the SN74ACT2227 or
SN74ACT2229 can be calculated by:
PT = Vee x [Iee(f) + (N x t.lee x dc)] + (CL x Vee2 x fo)
where:
N number of inputs driven by TIL levels
t.lee increase in power supply current for each input at a TIL high level
. dc duty cycle of inputs at a TIL high level of 3.4 V
CL output capacitive load
fa switching frequency of an output

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 2-25
SN74ACT2227, SN74ACT2229
DUAL 64 x 1, DUAL 256 x 1
FIRST·IN, FIRST·OUT MEMORIES
SCAS220B - JUNE 1992 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION

An example of concentrating two independent serial-data signals into a single composite data signal with the use of
an SN74ACT2227 or SN74ACT2229 device is shown in Figure 6. The input data to the FIFOs share the same average
(mean) frequency and the mean frequency of the SYS_CII..OCK is greater than or equal to the sum of the individual
mean input rates. A single-bit FIFO is needed for each additional input data signal that is time-division multiplexed
into the composite signal.
The FIFO memories provide a buffer to absorb clock jitter generated by the transmission systems of incoming signals
and synchronize the phase-independent inputs to one another. FIFO half-full (HF) flags are used to signal the
multiplexer to start fetching data from the buffers. The state of the flags can also be used to indicate when a FIFO
read should be suppressed to regulate the output flow (pulse-stuffing control). The FIFO aimost-fuil/aimost-empty
flags (AF/AE) can be used in place of the half-full flags to reduce transmission delay.

SN74ACT2227
or
SN74ACT2229

+5V I
1HF
Serial { 1WRTCLK 1RDCLK ---4 READY_1
Data
Stream
---- 1WRTEN
10
1RDEN
1Q

2WRTCLK 2RDCLK -
SELECT_1
DATA_1
Time-Division
Multiplexer
Composite
Data Stream
Serial {
Data '--- 2WRTEN 2RDEN SELECT_2
Stream
20 2Q DATA_2
2HF
I I READY 2

Figure 6. Time-Division Multiplexing Using the SN74ACT2227 or SN74ACT2229

~TEXAS
INSTRUMENTS
2-26 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
I Reduced-WidthFIFOs

3-1
 REDUCED-WIDTH FIFOS
Features Benefits

• Frequencies up to 40 MHZ • Multiple frequencies for greater

system-performance flexibility
• 3-state outputs • Disable output from the data path
• Depths available from 16 to 64 words • Shallow depths for elastic store
• Package options include SOIC, PLCC, • Multiple package options for high-volume
and DIP production requirements
:D
CD
C.
c:
Q
c.
I

:e~
...
::T
!!
"T1
otn

3-2
 SN74ALS232B
16 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY

• Independent Asynchronous Inputs and OW OR N PACKAGE

{TOP VIEW)
Outputs
• 16 Words by 4 Bits
OE 16 Vee
• Data Rates From 0 to 40 MHz FULL 15 UNCK
• Fall-Through Time •.. 14 ns Typ LOCK 14 EMPTY
• 3-State Outputs DO 13 00
• Package Options Include Plastic 01 12 01
Small-Outline Packages (OW), Plastic Chip 02 11 02
Carriers (FN), and Standard Plastic 30o-mll 03 10 03
DIPs (N) GNO 9 RST

description
FNPACKAGE
{TOP VIEW)
This 64-bit memory use advanced low-power
Schottky technology and features high speed and
fast fall-through times. It is organized as 16 words I~5W()()~
~
by 4 bits each. u.oz;9';;)

A first-in, first-out (FIFO) memory is a storage 3 2 1 2019

LOCK 4 18 EMPTY
device that allows data to be written into and read DO 17 00
5
from its array at independent data rates. This NC 16 NC
6
FIFO is deSigned to process data at rates from 0 01 15 01
7
to 40 MHz in a bit-parallel format, word by word. 02 14 02
8
9 10 11 12 13
Data is written into memory on a low-to-high
transition at the load-clock (LOCK) input and is
read out on a low-to-high transition at the
C') Cl ()
ClzzCJ)O
C!:l
II-
C')

II:
unload-clock (UNCK) input. The memory is full
when the number of words clocked in exceeds by NC - No internal connection
16 the number of words clocked out. When the
memory is full, LOCK signals have no effect on the
data residing in memory. When the memory is
empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the FULL and EMPTY output flags. The FULL output is low when
the memory is full and high when it is not full. The EMPTY output is low when the memory is empty and high
when it is not empty.
A low level on the reset (RST) input resets the internal stack-control pointers and also sets EMPTY low and sets
FULL high. The Q outputs are not reset to any specific logic level. The first low-to-high transition on LOCK, after
either a RST pulse or from an empty condition, causes EMPTY to go high and the data to appear on the
Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting
with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does
not affect the FULL or EMPTY output flags. Cascading is easily accomplished in the word-width direction but
is not possible in the word-depth direction.
The SN74ALS2328 is characterized for operation from O°C to 70°C.

Copyright © 1993, Texas Instruments Incorporated

~ThXAS·
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3-3
SN74ALS232B
16 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS251 - FEBRUARY 1989 - REVISED SEPTEMBER 1993

logic symbolt

FIF016x4

9 CTR
RST b CT=O 2
3 (CT = 16) G1
LOCK 1(+/C2) 14
15 (CT = 0) G3
UNCK 3-

OE

00
1

4
.,
EN4

20
r
4.;;
13
QO
5 12
01 Q1
6 11
02 Q2
7 10
03 Q3

t This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but does not
show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled by a single counter
whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is O.
Pin numbers shown are for the DW and N packages.

~TEXAS
INSTRUMENTS
3-4 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS232B
16 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SCAS251- FEBRUARY 1989 - REVISED SEPTEMBER 1993

logic diagram (positive logic)

Ring
1
Counter
2
CTR
3
DIV16 4
5
6
7
8
~---'---------+~-d>+
9
10
Write 11
Address 12
13
CT = 1 14
15
16

Ring
Counter
1
2
CTR
3
DIV16 4
5
6
7
8
~-----------+++;>+ 9
10
RST _9=--____________.... Read 11
Address 12 RAM16x4
13
14 EN
t-------------~~~CT=1 15
16 1
1A1'6
16 i
r+-.L---I2A 16

DO~~~~
13 QO
D1 5 12 Q1
D2 6 11 Q2
D3 7 10
Q3

COMP
P=Q
P 14_
0-_______________ EMPTY

P=Q+1
I--+----L-...J
Q 0-_______________2_ FULL
P=Q-1 I-------------~R o------I__J

Pin numbers shown are for the DW and N packages.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-5
SN74ALS232B
16 x 4 ASYNCHRONOUS FIRST-IN, FIRST..OUT MEMORY
SCAS251 - FEBRUARY 1989 - REVISED SEPTEMBER 1993

timing diagram

.J,
LOCK
,

00-D3 ?§§§I:f§I Et ~~gn3~;l~ ISS

, \'1(1 W2 W3 Wi W2
Q f§I
W15 ~16
~
.
, , ,
UNCK
_f--+-----/
, , ,
QO-Q3 $!<_W_Ord_1_~ _ _ _ _w_o_rd_1_+-__ >CJOC
" 'Word2 Word 3 , , Word2 Word3 W... td4

I I I
'
I
I I,
',i
'I
' "
, U ,

I Load ,
, Wi , I
Initialize Unload Empty Full
Pointers W2

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee ............................................................... . . . . .. .. 7 V
Input voltage, VI ................................................................... . . . . . . .. 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated In the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

-!/} 1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ALS232B
16 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SCAS251 - FEBRUARY 1989 - REVISED SEPTEMBER 1993

recommended operating conditions (see Note 1)

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
Qoutputs -2.6
10H High-level output current mA
FULL, EMPTY -0.4
Qoutputs 24
10L Low-level output current mA
FULL, EMPTY 8
LDCK 0 40
fclockt Clock frequency MHz
UNCK 0 40
RSTlow 18
LDCKlow 15
tw Pulse duration LDCKhigh 10 ns
UNCKlow 15
UNCKhigh 10
Data before LDCKi 8
tsu Setup time ns
LDCK inactive before RSTi 5
Data after LDCKi 5
th Hold time ns
LDCK inactive after RSTi 5
TA Operating free-air temperature 0 70 ·C
tThe maximum possible clock frequency is 40 MHz. The maximum clock frequency when using a 50% duty cycle is 33.3 MHz.
NOTE 1: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs.
Any excessive noise or glitching on the clock inputs that violates limits for maximum VIL, minimum VIH, or minimum pulse duration can
cause a false clock or improper operation of the internal read and write pointers.

electrical characteristics over recommended operating free·air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP:j: MAX UNIT
VIK Vce =4.5V, 11=-18mA -1.2 V
Qoutputs VCC=4.5V, 10H =-2.6 mA 2.4 3.2
VOH V
FULL, EMPTY VCC = 4.5 V to 5.5 V, IOH =-0.4 mA VCC-2
IOL=12mA 0.25 0.4
Qoutputs VCC = 4.5 V
IOL=24 mA 0.35 0.5
VOL V
IOL=4mA 0.25 0.4
FULL, EMPTY VCC = 4.5 V
IOL=8 mA 0.35 0.5
10ZH VCC = 5.5 V, Vo = 2.7 V 20 J.tA
10ZL VCC =5.5 V, VO= 0.4 V -20 J.tA
II VCC = 5.5 V, VI =7V 0.1 mA
IIH VCC = 5.5 V, VI = 2.7V 20 J.tA
IlL VCC = 5.5 V, VI = 0.4 V -0.2 mA
10§ VCC =5.5 V, Vo = 2.25 V -30 -112 mA
ICC VCC = 5.5 V 80 125 mA
:I: All tYPical values are at VCC = 5 V, TA = 25·C.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3-7
SN74ALS232B
16 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS251 - FEBRUARY 1989 - REVISED SEPTEMBER 1993

switching characteristics (see Figure 1)

Vee=5V, vee = 4.5 V to 5.5 V,
CL=50pF, CL=50pF, ,
FROM TO R1 =5000. R1 =5000.
PARAMETER R2 = 5000. R2=5000, UNIT
(INPUT) (OUTPUT)
TA=25°C TA = MIN to MAXt
MIN TYP MAX MIN MAX
'max LDCK,UNCK, 50 40 MHz
LDCKt 14 23 6 30
tpd AnyQ ns
UNCKt 15 23 6 30
tpLH LDCKt 13 20 5 25
EMPTY ns
tPHL UNCKt 15 22 6 27
tPHL RST.L EMffi 15 21 5 26 ns
tpHL LDCKt FULL 15 22 6 27 ns
UNCKt 13 20 5 25
tPLH FULL ns
RST.L 16 23 7 28
ten OEt Q 5 12 1 14 ns
!dIs OE.L Q 5 12 1 16 ns
t
.. .. ..
For condilions shown as MIN or MAX, use the appropnate value specified under recommended operallng conditions .

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS232B
16 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS251 - FEBRUARY 1989 - REVISED SEPTEMBER 1993

PARAMETER MEASUREMENT INFORMATION

7V
SWITCH POSITION TABLE

S1
b Open
TEST
tpLH
51
Open
tpHL Open
R1 =5000 tpZH Open
From Output - -.....-~-41.--­ Test Point tPZL Closed
Under Test tPHZ Open
CL=50pF R2=5000 Closed
tpLZ
(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V

High-Level
Pulse ~ I I 0.3V

Timing
Input

tsu~th
t~3~ ___ 3.5 V

0.3 V
Low-Level
Pulse
~
l+--
I
tw

... v
~~.~V_
----+I
I
y:::- 3.5V

O.3V

~
Data 3.5 V VOLTAGE WAVEFORMS
Input 1.3V 1.3V PULSE DURATION
0.3 V
VOLTAGE WAVEFORMS

~~
SETUP AND HOLD TIMES 3'5V
Output
Control I ~~ 1.3V __ _

Input~ \..- - - - 3.5V .1 I 0.3V

(see Note B) 1.3 V i\ 1.3 V tpZL --.. I+-
I +--~~r-
~
I I. 0.3 V
tPLZ 3.5V
-l4---+I ~ tpHL
In-Phase
Output
tpLH
I
I
y I "\L-:;.; VOH
1.3 V I V '\.2:
Waveform 1
51 Closed
(see Note C) --L
I
I
1.3V I I oJ.
--~
VOL
__~I-J I VOL I tPHZ -./ I+- 0.3 V

tpHL~
I~~, ~tpLH
I
Waveform 2
._.. -+I. rt---t--;--=--
tpZH ~ I oJ.
VOH

~~~ __ SE:3~v
Out-of-Phase { !r.:: VOH
Output ' \ 1.3V T 1.3V 51 Open
(see Note C)
. , - - VOL

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ,:; 1 MHz, Zo = 50 0. tr ,:; 2 ns, tf ,:; 2 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3-9
3-10
 SN74ALS234
64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDASI 06B - OCTOBER 1986 - REVISED SEPTEMBER 1993

• Asynchronous Operation ow OR N PACKAGE

(TOP VIEW)
• Organized as 64 Words by 4 Bits
• Data Rates From 0 to 30 MHz OE Vcc
• 3-State Outputs IR SO
• Package Options Include Plastic SI OR
Small-Outline Packages (OW), Plastic 00 QO
J-Leaded Chip Carriers (FN), and Standard 01 Q1
Plastic 30o-mil DIPs (N) 02 Q2
03 Q3
description GNO RST

The SN74ALS234 is a 256-bit memory utilizing

advanced low-power Schottky IMPACpM
FNPACKAGE
technology. It features high speed with fast (TOP VIEW)
fall-through times and is organized as 64 words by
4 bits. illJ 0
!fOZ~CIl
°0
A first-in, first-out (FIFO) memory is a storage
device that allows data to be written into and read 3 2 1 20 19
SI 4 18 OR
from its array at independent data rates. The DO 5 17 QO
SN74ALS234 is deSigned to process data at rates NC 6 16 NC
from 0 to 30 MHz in a bit-parallel format, w.ord by 01 7 15 Q1
word. 02 8 14 Q2
9 10 11 12 13
Data is written into memory on the riSing edge of
the shift-in (SI) input. When SI goes low, the first
data word ripples through to the output (see
C') 0
OZZCllO
CD a:
C') OIl-
Figure 1). As the FIFO fills up, the data words
NC - No internal connection
stack up in the order they were written. When the
FIFO is full, additional shift-in pulses have no
effect. Data is shifted out of memory on the falling edge olthe shift-out (SO) input (see Figure 2). When the FIFO
is empty, additional SO pulses have no effect. The last data word remains at the outputs until a new word falls
through or reset (RST) goes low.
Status of the SN74ALS234 FIFO memory is monitored by the output-ready (OR) and input-ready (IR) flags.
When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFO
isempty.IR is high when the inputs are ready to receive more data.IR is lowwhen SI is high and stays low when
the FIFO is full.
When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high
during this time, the OR flag pulses high indicating valid data at the outputs (see Figure 3).
When the FIFO is full, data can be shifted in automatically by holding SI high and taking SO low. One propagation
delay after SO goes low, IR will go high. If SI is still high when IR goes high, data at the inputs are automatically
shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the
IR output (see Figure 4).

IMPACT is a trademark of Texas Instruments Incorporated.

Copyright © 1993, Texas Instruments Incorporated

~ThXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3-11
SN74ALS234
64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 06B - OCTOBER 1986 - REVISED SEPTEMBER 1993

description (continued)
The FIFO must be reset after power up with a low-level pulse on the master reset (RSn input. This sets IR high
and OR low signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (see
Figure 1). If SI is high when R"ST goes high, the input data is shifted in and IR goes low and remains low until
SI goes low. If SI goes low before RST goes high, the input data will not be shifted in and IR goes high. Data
outputs are nDninverting with respect to the data inputs and are at high impedance when the output-enable (OE)
input is high. OE does not affect the IR or OR.
The SN74ALS234 is characterized for operation from O°C to 70°C.

logic symbolt

FIFO 64 x4

CTR
3 14
SI 5+/C1 3CT>0 OR
L G2 (CT > 0) G4
15
so 4- 2
L G3 2CT<64 IR
(CT < 64) G5

~R
CT=O
9

00
1

4
.,
"- EN6

10 16V
r 13
QO
5 12
01 Q1
6 11
02 Q2
7 10
03 Q3

t This symbol is in accordance with ANSI/IEEE Standard 91-1984 and lEe Publication 617-12.

functional block diagram

4
00 -,:5-----1 13 QO
01 ---=6-----1 FIFO . 12 Q1
02 ~-----1 Input 11 Q2
03 ----<.7_ _---1 Stage
10 Q3

IR --=2____;1----1 ro:~:l_..!....l--jj15L SO

Sl ---,,-3--""L~:..J L~~I---,-,14,- OR
RST __9~______~~________~~________~__~

Pin numbers shown are for the OW and N packages.

~1ExAs
INSTRUMENTS
3-12 POST OFFICE BOX 655303 • DALlAS. TEXAS 75285
 SN74ALS234
64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 06B - OCTOBER 1986 - REVISED SEPTEMBER 1993

Sinaino Q4ea

~....... ..,
000
11 1
,---1.>>--.........+-----:-1
1
1

'+--~...., 1
1
1
1
1
1
L--++-.... ~_
1
1
1
1
~-1

f f
1 1

1
1
1
1
l...-~-4-+--
1
1
1
1
'-+--+.........-. t--
I
1
I
1
1
1
1
1
1
1

l...--<>-_--.l
I I I
IWo 0
e c c.......
e ..,
I~
'-. .r--'
Sindul elea

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-13
SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDAS1 06B - OCTOBER 1986 - REVISED SEPTEMBER 1993

timing diagram

SI

03-00

so

Q3-QO

IR

Clear Shift Out Full

Shift In W2
Wi Empty

t The last data word shifted out of the FIFO remains at the output until a new word falls through or a R5T pulse clears the FIFO.
:t: While the output data is considered valid only when the OR flag is high, the stored data remains at the outputs. Any additional words written into
the FIFO will stack up behind the first word and will not appear at the output until 50 is taken low.

-!!1TEXAS
INSTRUMENTS
3-14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDAS1 06B - OCTOBER 1986 - REVISED SEPTEMBER 1993

I
14-- tsu --+j
SI I i-I --:"1-....., 1-1__
~tsu-.!*-thi
03-00 ~ X,.I0:1. . - - - - i......
I:
-""'X,.I..,:::::::
!+ tPLH -+! 1 I+- tPHL -+! I+- tPLH -+I
I r
IR

OR
Full !
_ _ _-+r_tP_H_L-;-+!
I
I
I
I Empty
I
r---
!
tPLH ~i-----
I
I
I+- tpd --+I 11+_- - tpd --"'~I
Q3-QO
--------~~\.I /Ir------
------~------------~-----
NOTE: 50 is low.

Figure 1. Master Reset and Data-In Waveforms

SO I I
I : . - - tpLH -----.I
OR II --+-:--I r---
tpLH ~I r---tPHL~

IR Full
r
~ IcI(SOL.QX)

) ~ ~
Q3-QO
I
I+" ten ~tpd---1
tdls --: 1+"1 I
OE
--.J 1
NOTE: 51 is low.

Figure 2. Data-Out Waveforms

-!II TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265 3-15
SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDAS1 06B - OCTOBER 1986 - REVISED SEPTEMBER 1993

03-00
~~th-+j
tsu

SI
--~I ~I________________
I
I
SO - - '
r-
I
tpLH
I
-+j
r-twl
I

OR ...._____E_m_Pt_y________~1 ~I _________________
H td(QV-ORH)
Q3-QO --------I-nv-a-II-d------~)(~_______________________________
Figure 3. Data Fall-Through Waveforms

so

SI --'
~I tpLH -.IJ+- tw~

---I_
I I
IR ________F_U_II________~I ~1 _______F_UI_I________
03-00 ~'-_ _ _ _
Figure 4. Automatic Data-In Waveforms

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ............................................................ 7 V
Input voltage, VI ........................................................................... 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA ................................................. O°C to 70°
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

-!II TEXAS
INSTRUMENTS
3-16 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS234
64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDASI 06B - OCTOBER 1966 - REVISED SEPTEMBER 1993

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
Q outputs -2.6
10H High-level output current mA
IR and OR -0.4
Q outputs 24
10L Low-level output current mA
IR and OR 8
fclock Clock frequency SlorSO 0 30 MHz

Pulse duration
SlorSO I High or low 15
ns
tw
RSf I Low 15
Data 0
tsu Setup time before SI1" ns
RST I High (Inactive) 15
th Hold time, data after SI1" 17 ns
TA Operating free-air temperature 0 70 ·C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VIK VCC=4.5V, 11=-18mA -1.2 V
10H=-1 mA
AnyQ VCC- 4.5V
VOH IOH--2.6mA 2.4 3.2 V
IR,OR VCC-4.5V, 10H =-0.4 mA 2.7 3.4
10L= 12mA 0.25 0.4
AnyQ VCC-4.5V
IOL=24mA 0.35 0.5
VOL V
IOL=4mA 0.25 0.4
IR,OR VCC - 4.5 V
IOL=8mA 0.35 0.5
10ZH VCC =5.5 V, VO=2.7V 20 Jl.A
10ZL VCC-5.5V, Vo = 0.4 V -20 Jl.A
II VCC-5.5V, VI-7V 0.1 mA
IIH VCC = 5.5 V, VI -2.7V 20 Jl.A
IlL VCC=5.5V, VI-0.4 V -0.1 mA
10:1: VCC = 5.5 V, VO=2.25V -30 -112 mA
Low 100 145
ICC VCC-5.5V High 97 142 mA
Disabled 103 148
t All typical values are at VCC • 5 V, TA = 25·C.
:I: The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 665303 • DALlAS. TEXAS 75265 3-17
SN74ALS234
64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS106B - OCTOBER 1986 - REVISED SEPTEMBER 1993

switching characteristics (see Figure 5)

VCC=5V, Vcc = 4.5 V to 5.5 V,
CL=50pF, CL=50pF,
FROM TO R1 =5000, R1 =5000,
PARAMETER R2 =5000, R2 = 5000, UNIT
(INPUT) (OUTPUT)
TA=2SoC TA = MIN to MAxt
MIN TYP MAX MIN MAX
51 35 30
f max MHz
SO 35 30
tw:j: IR high 15 8 ns
tW§ OR high 19 8 ns
lcl(QV-ORH) Q valid before ORi 6 9 -5 12 ns

lcl(SOL-QX) Q valid after SO! 13 4 ns

tpd 51! Q 600 800 350 1000 ns
tpHL Sli 20 26 8 30
IR ns
tpLH 51! 16 21 6 25
tPLH II 51! OR 600 800 350 1000 ns
too SO! Q 13 17 4 22 ns
tPHL soi 23 27 7 3:3
OR ns
tpLH SO! 20 24 6 30
tPLH II SO! IR 600 800 350 1000 ns
tPHL OR 22 26 10 34
RSn ns
tpLH IR 17 21 6 27
tpHL RST! Q 14 17 5 19 ns
tdis OEi Q 7 13 2 15 ns
ten OE! Q 6 12 2 13 ns
..
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions .
:j: The IR output pulse occurs when the FIFO is full, 51 is high, and SO is pulsed (see Rgure 4).
§ The OR output pulse occurs when the FIFO is empty, SO is high, and 51 is pulsed (see Figure 3).
II Data throughput or fall-through times

-!!11ExAs
INSTRUMENTS
3-18 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ALS234
64 x 4 ASYNCHRONOUS FIRST-IN, FIRST·OUT MEMORY
SDAS1 06B - OCTOBER 1986 - REVISED SEPTEMBER 1993

PARAMETER MEASUREMENT INFORMATION

7V SWITCH POSITION TABLE

l Open
TEST
tpLH
S1
Open
tPHL Open
tpZH Open
From Output _ _.-_~.......>--_ Test Point tPZL Closed
Under Test Open
tPHZ
CL = 50pF R2=500Q tpLZ Closed
(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V

High-Level
Pulse ~ I I 0.3V

Timing
Input

tsu~th
t~3~ ___ 3.5 V

0.3 V
Low-Level
Pulse
~ 1 ~v
~~.~V_
14--
I
tw

J.I"":":':'"
---+I
I
3.5V

0.3 V

~
Data 3.5 V VOLTAGE WAVEFORMS
Input 1.3V 1.3V PULSE DURATION
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
Input - - - - 3.5 V
(see Note B) L 1.3 V \ . 1.3 V
--Ii I. 0.3 V
tPLH~ ~tPHL Waveform 1
In-Phase I 1/ I 'i.-:;.; VOH S1 Closed
Output I· T 1.3V I ~V (see Note C)
--~i-J I VOL
t I~~, ~ tpLH
PHL o---?I I
Waveform 2
Out-of-Phase 1
1.3 V FV
1.3O
V H
\ S10pen
Output . . __ VOL (see Note C)

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR S 1 MHz, Zo = 50 Q, tr S 2 ns, tf S 2 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.

Figure 5. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-19
SN74ALS234
64 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDAS1 06B - OCTOBER 1986 - REVISED SEPTEMBER 1993

APPLICATION INFORMATION

.---
-
IR
51
DC)
50
OR
QO
IR
51
00
50
OR
QO
. IR
51
00
50
OR
QO I--
50

- 01 Q1 01 Q1 01 Q1 r--
- 02 Q2 02 Q2 02 Q2 r--
- 03 Q3 03 Q3 03 Q3 r--

R5T R5T R5T

I 1 1

IR -r- IR 50 IR 50 IR 50 1------4

~
- 51 OR 51 OR 51 OR OR
- 00 QO 00 QO 00 QO i - -
- 01 Q1 01 Q1 01 Q1 i - -
- 02 Q2 02 Q2 02 Q2 ' - -
- 03 Q3 03 Q3 03 Q3 ' - -

R5T R5T R5T

I 1 1

IR 50 IR 50 IR 50 -
51 51 OR 51 OR 51 OR
- 00 QO 00 QO 00 QO -
- 01 Q1 01 Q1 01 Q1 -
- 02 Q2 02 Q2 02 Q2 -
- 03 Q3 03 Q3 03 Q3 -
R5T R5T R5T
I 1 1 ,

Figure 6. 192-Word by 12-Bit Expansion

~TEXAS
INSTRUMENTS
3-20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY

• Asynchronous Operation ow OR N PACKAGE

(TOP VIEW)
• Organized as 64 Words by 4 Bits
• Data Rates From 0 to 30 MHz NC Vcc
• 3-State Outputs IR SO
• Package Options Include Plastic SI OR
Small-Outline Packages (OW), Plastic DO 00
J-Leaded Chip Carriers (FN), and Standard 01 01
Plastic 300-mil DIPs (N) 02 02
03 03
description GND 9 RST
The SN74ALS236 is a 256-bit memory utilizing
advanced low-power Schottky IMPACT'M FNPACKAGE
technology. It features high speed with fast (TOP VIEW)
fall-through times and is organized as 64 words by
()() ()o
4 bits. g:;ZZ~CIl
A first-in, first-out (FIFO) memory is a storage 3 2 1 2019
device that allows data to be written into and read SI 4 18 OR
from its array at independent data rates. The DO 5 17 00
SN74ALS236 is designed to process data at rates NC 6 16 NC
from 0 to 30 MHz in a bit-parallel format, word by 01 7 15 01
word. 02 8 14 02
9 10111213
Data is written into memory on the rising edge of
the shift-in (SI) input. When SI goes low, the first C'"l Cl
ClZZCllO
o a:
C'"l ()II-
data word ripples through to the output (see
Figure 1). As the FIFO fills up, the data words NC - No internal connection
stack up in the order they were written. When the
FIFO is full, additional shift-in pulses have no
effect. Data is shifted out of memory on the falling
edge of the shift-out (SO) input (see Figure 2). When the FIFO is empty, additional SO pulses have no effect.
The last data word remains at the outputs until a new word falls through or reset (RST) goes low.
Status of the SN74ALS236 FIFO memory is monitored by the output-ready (OR) and input-ready (IR) flags.
When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFO
is empty. IR is high when the inputs are ready to receive more data. IR is low when SI is high and stays low when
the FIFO is full.
When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high
during this time, the OR flag pulses high indicating valid data at the outputs (see Figure 3).
When the FIFO is full, data can be shifted in automatically by holding SI high and taking SO low. One propagation
delay after SO goes low, IR will go high. If SI is still high when IR goes high, data at the inputs are automatically
shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the
IR output (see Figure 4).

IMPACT is a trademark of Texas Instruments Incorporated.

Copyright © 1993, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3-21
SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDASl 07A - OCTOBER 1986 - REVISED SEPTEMBER 1993

description (continued)
The FIFO must be reset after power up with a low-level pulse on the master reset (R8T) input. This sets IR high
and OR low signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (see
Figure 1). If 81 is high when R8T goes high, the input data is shifted in and IR goes low and remains low until
81 goes low. If 81 goes low before R8T goes high, the input data will not be shifted in and IR goes high. Data
outputs are noninverting with respect to the data inputs.
The 8N74AL8236 is characterized for operation from O°C to 70°C.

logic symbolt

FIF064x4

CTR
3 14
SI 5+/C1 3CT>0 OR
L G2 (CT > 0) G4
15
SO 4- 2
L G3 2CT<64 IR
(CT <64) G5

~
CT=O
9
R

4
'1 r 13
DO 10 I QO
5 12
01 Q1
6 11
02 Q2
7 10
03 Q3

t This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.

functional block diagram

4 13
DO 5 QO
01 FIFO 12
6 Q1
02 Input 11
7 Q2
03 Stage 10
Q3

1-1-4f---_1:.::5:-.- SO

SI ---=3'--_ _-1
L~~I------"'14'-- OR
RST_9~_ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _~_~

Pin numbers shown are for the DW and N packages.

~TEXAS
INSTRUMENTS
3-22 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDAS1 07A - OCTOBER 1986 - REVISED SEPTEMBER 1993

... C\lC')
000
I I I
I
I
I
I
'-t-~...., I
I
I
I
I
I
'---++-.-.~ -
I
I
I
I
j-l:
I
I

'f
I

~
'E
~
+---
I
I
I
I
t--
I
Q ;Z I
"S! 'E I
~ I
CI) ~
> I
0:: I
"iii I

-e
0
c..
E
_...1
I
I
I
en
CIS I I I
=s
u
"S!
8
'-y---I
cf'l8
Ii iii

~ s,ndUI~Ba

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-23
SN74ALS236
64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 07A - OCTOBER 1986 - REVISED SEPTEMBER 1993

timing diagram

SI

03-00

so

Q3-QO

t The last data word shifted out of the FIFO remains at the output until a new word falls through or a RST pulse clears the FIFO.
:I: While the output data is considered valid only when the OR flag is high, the stored data remains at the outputs. Any additional words written into
the FIFO will stack up behind the first word and will not appear at the output until SO is taken low.

~1ExAs
INSTRUMENTS
3-24 POST OFFICE BOX 666303 • DALLAS. TEXAS 75265
 SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDAS1 07A - OCTOBER 1986 - REVISED SEPTEMBER 1993

, ,
I I+---- tsu ~

51
I ~--~I--~ ~I----
~tSU--.l~thi
~ x. X~:======
:' ': ':
03-00
:.. tPLH +i I I+- tPHL +i I+- tPLH -.:
I II I r
IR

OR
Full !
_ _ _-+-r_tP_H_L+
,I Empty
i-ir r--
!
tPLH -----li--_ _ __
I
I
I+I~- - t p d --~

Q3-QO
14- tpd ~ .. ,
/,----
NOTE A: 80 is low.

Figure 1. Master Reset and Data·ln Waveforms

50
I I
I I : . - - tpLH --.J
I
OR I
I
tpLH . "I
I
I
I
~IPHL---+j
I t-
IR Full
!'
~ td(50L-QX)

Q3-QO )
< ~ ~
\+--t -4 pd
NOTE A: 81 is low.

Figure 2. Data-Out Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-25
SN74ALS236
64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 07A - OCTOBER 1986 - REVISED SEPTEMBER 1993

03-00
~[+--+I.-
Isu Ih -+j

SI
--~I ~I________________
I
I
SO~ I
I+- -.!~Iw~
IPLH I

OR ______E_m_p~
________~1 ~I _______________
H Id(QV.ORH)
---------In-v-al-Id------~)(~________________________________
Q3-QO

Figure 3. Data Fall-Through Waveforms

SO

SI~ ~I IPLH-.I
!+- Iw--+i
I I

03-00
IR

~~_ _ _ _
FU_II__________~I
__________ ~I

Figure 4. Automatic Data-In Waveforms

...J_
________ F_U_II_________

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ............................................................ 7 V
Input voltage, VI ........................................................................... 7 V
Operating free-air temperature range, TA ................................................. O°C to 70°
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

~TEXAS
INSTRUMENTS
3-26 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS236
64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 07A - OCTOBER 1986 - REVISED SEPTEMBER 1993

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voHage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
Q outputs -2.6
10H High-level output current rnA
IR and OR -0.4
Q outputs 24
10L Low-level output current rnA
IR and OR 8
fclock Clock frequency SlorSO 0 30 MHz

Pulse duration
SlorSO I High or low 15
ns
tw
RST I Low 15
Data 0
tsu Setup time before Sit ns
RST I High (inactive) 15
th Hold time, data after Sit 17 ns
TA Operating free-air temperature 0 70 ·e

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VIK Vee- 4.5V, 11=-18mA -1.2 V
IOH--1 rnA
AnyQ Vee - 4.5 V
VOH 10H =-2.6 rnA 2.4 3.2 V
IR,OR Vee- 4.5V, 10H =-0.4 rnA 2.7 3.4
IOL=12mA 0.25 0.4
AnyQ Vee = 4.5 V
IOL=24 rnA 0.35 0.5
VOL V
IOL-4mA 0.25 0.4
IR,OR Vee = 4.5 V
IOL=8mA 0.35 0.5
II Vee =5.5 V, VI-7V 0.1 rnA
IIH Vee = 5.5 V, VI =2.7V 20 IIA
IlL Vce = 5.5 V, VI- 0.4 V -0.1 rnA
10* Vee=5.5V, VO-2.25V -30 -112 rnA
Low 100 145
ICC Vee - 5.5 V rnA
High 97 142
t All typical values are at Vee = 5 V, TA _ 25·e.
* The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-27
SN74AlS236
64 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDAS1 07A - OCTOBER 1986 - REVISED SEPTEMBER 1993

switching characteristics (see Figure 6)

=
Vee 5 V, Vec = 4.5 V to 5.5 V,
=
el 50 pF, Cl =50 pF,
FROM TO R1 =500 a, R1 =500 a,
PARAMETER R2 = 500 a, R2 =500 a, UNIT
(INPUT) (OUTPUT)
TA = 25°e TA = MIN to MAXt
MIN TYP MAX MIN MAX
SI 35 30
f max MHz
SO 35 30
tw:l= IR high 15 8 ns
tw§ OR high 19 8 ns
td(QV-ORH) Q valid before ORi 6 9 -5 12 ns

td(SOL-QX) Q valid after SO! 13 4 ns

tpd SI! Q 600 800 350 1000 ns

tpHL Sli 20 26 8 30
IR ns
tPLH SI! 16 21 6 25
tPLH# SI! OR 600 800 350 1000 ns
tpd SO! Q 13 17 4 22 ns
tPHL soi OR
23 27 7 33
ns
tpLH SO! 20 24 6 30
tPLH# SO! IR 600 800 350 1000 ns
tpHL OR 22 26 10 34
RSH ns
tPLH IR 17 21 6 27
tPHL RST! Q 14 14 17 5 19 ns
.. shown as MIN or MAX, use the appropriate value specified under recommended operating conditions .
t For conditions
:1= The IR output pulse occurs when the FIFO is full, SI is high, and SO is pulsed (see Figure 4).
§ The OR output pulse occurs when the FIFO is empty, SO is high, and SI is pulsed (see Figure 3).
~ Data throughput or fall-through times

~TEXAS
INSTRUMENTS
3-28 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDASI 07A - OCTOBER 1986 - REVISED SEPTEMBER 1993

APPLICATION INFORMATION

... ...
-
IR
SI
so
OR ~
IR
SI
so
OR . IR
SI
so
OR
SO

- DO QO DO QO DO QO I--
- 01 Q1 01 Q1 01 Q1 I--
- 02 Q2 02 Q2 02 Q2 I--
- 03 Q3 03 Q3 03 Q3 r--

RST RST RST

I 1 1

...
IR
-G -
IR
SI
so
OR
IR
SI
so
OR .. IR
51
50 ~
OR
D- OR
- DO QO DO QO DO QO I--
- 01 Q1 01 Q1 01 Q1 I--
- 02 Q2 02 Q2 02 Q2 r--
- 03 Q3 03 Q3 03 Q3 I--

RST R5T RST

I 1 1

IR so IR 50 IR SO I - -
SI SI OR SI OR SI OR
- DO QO DO QO DO QO r--
- 01 Q1 01 Q1 01 Q1 r--
- 02 Q2 02 Q2 02 Q2 I--
- 03 Q3 03 Q3 03 Q3 f--

RST RST RST

I 1 1
Figure 5. 192·Word by 12·Bit Expansion

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-29
SN74ALS236
64 x 4 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDAS1 07A - OCTOBER 1986 - REVISED SEPTEMBER 1993

PARAMETER MEASUREMENT INFORMATION

7V
SWITCH POSITION TABLE

SI
l Open
TEST
tPLH
SI
Open
tpHL Open
tpZH Open
From Output _ _.......~__~I--_ Test Point tpZL Closed
Under Test Open
IpHZ
=
CL SO pF R2=soon tpLZ Closed
(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.SV

High-Level
Pulse ~ I I 0.3V

Timing
Input

tsu~th
t~3~ ___ 3.SV

0.3 V
Low-Level
Pulse
~
14--
I
tw

.... vv-:::-
~~.~V_
--+I
I
3.SV

0.3 V

~
Data 3.SV VOLTAGE WAVEFORMS
Input 1.3V 1.3V PULSE DURATION
0.3 V
VOLTAGE WAVEFORMS

~~
SETUP AND HOLD TIMES 3'SV
Output
Control I ~: 1.3V __ _

--rs
Input - - - - 3.S V .1 0.3V
(see Note B) L 1.3 V \ . 1.3 V
tPZL ..... ~ I
--.IJ I. 0.3 V l : - -§!-=i-i~
tPLZ 3.SV
IpLH~ ~tPHL
In-Phase
Output
I
I
y 1.3V
I
I
)L-:;.~
C V
VOH
Waveform 1
SI Closed
(see Note C)
I
I
1.3 V I I
-_ ...
--L VOL
...

--~I~ I VOL I -+I ~

~HL~
I~~, ~tpLH
I
Waveform 2
._. .
tPZH -.j ~
tPHZ

r~~-=-- VOH
I ...
0.3 V

---L~~ __ ~3~V
Out-of-Phase 1 1.3 V FV
1.3O
V H
\ S10pen
Output . . _ _ VOL (see Note C)

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ~ 1 MHz, Zo = SO n, tr ~ 2 ns. tf ~ 2 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.

Figure 6. Load Circuit and Voltage Waveforms

~ThxAs
INSTRUMENTS
3-30 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74S225
16 x 5 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY

• Independent Asychronous Inputs and NPACKAGE

Outputs (TOP VIEW)

• 16 Words by 5 Bits
ClKA vee
• DC to 1o-MHz Data Rate IR ClKS
• 3-State Outputs UNCKOUT ClR
• Packaged in Standard Plastic 30o-mll DIPs 00 4 OR
01 UNCKIN
description 02 00
03 7 01
This aO-bit active-element memory is a monolithic 04 02
Schottky-clamped transistor-transistor logic OE 03
(STIl) array organized as 16 words by 5 bits. A
GNO 11 04
memory system using the SN74S225 can easily
be expanded in multiples of 16 words or of 5 bits
as shown in Figure 2. The 3-state outputs
controlled by a single output-enable (DE) input
make bus connection and multiplexing easy.
A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array
at independent data rates. This FIFO is designed to process data at rates from dc to 10 MHz in a bit-parallel
format, word by word.
Reading or writing is done independently utilizing separate asynchronous data clocks. Data can be written into
the array on the low-to-high transition of either load-clock (ClKA, ClKS) input. Data can be read out of the array
on the low-to-high transition of the unload-clock (UNCK IN) input (normally high). Writing data into the FIFO can
be accomplished in one of two manners:
1. In applications not requiring a gated clock control, best results will be achieved by applying the clock
input to one of the clocks while tying the other clock input high.
2. In applications needing a gated clock, the load clock (gate control) must be high in order forthe FIFO to
load on the next clock pulse.
ClKA and ClKS can be used interchangeably for either clock gate control or clock input.
Status of the SN74S225 is provided by three outputs. The input-ready (IR) output monitors the status of the last
word location and signifies when the memory is full. This output is high whenever the memory is available to
accept any data. The unload-clock (UNCK OUT) output also monitors the last word location. This output
generates a low-logic-level pulse (synchronized to the internal clock pulse) when the location is vacant. The third
status output, output ready (OR), is high when the first word location contains valid data and UNCK IN is high.
When UNCK IN goes low, OR will go low and stay low until new valid data is in the first word position. The first
word location is defined as the location from which data is provided to the outputs.
The data outputs are non inverted with respect to the data inputs and are 3-state with a common control input
(DE). When DE is low, the data outputs are enabled to function as totem-pole outputs. A high logic level forces
each data output to a high-impedance state while all other inputs and outputs remain active.The clear (ClR)
input invalidates all data stored in the memory array by clearing the control logic and setting OR to a low logic
level on the high-to-Iow transition of a low-active pulse.
The SN74S225 is characterized for operation from O°C to 70°C.

Copyright © 1993. Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 6~5303 • DALLAS. TEXAS 75265 3-31
SN74S225
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDLS207 - SEPTEMBER 1976 - REVISED SEPTEMBER 1993

logic symbolt

.-.., FIF016x5 3
9
OE EN6 2 UNCKOUT
16 2
UNCKIN Z1 5,2 IR
L >3- CTR 1,3
17
OR
18
" CT=O CTc16 Q2

ClKA
1 -& > 2+
CT>O G3

19
ClKB C4
>2 11l.
Z5
4
r 16
DO 40 6V QO
5 15
01 Q1
6 13
02 Q2
7 12
03 Q3
8 11
04 Q4

t This symbol is in accordance with ANSI/IEEE Standard 91-1984 and lEe Publication 617-12.

-!JJ 1ExAs
INSTRUMENTS
3-32 POST OFFICE BOX 655303- DALlAS, TEXAS 75285
 functional block diagram

Words3-14

Word 15 1
Sameas2or15

Word 2
Word 1
(first word)

DO 4

J!l
:::J

.5
Q. io
~ SameasQO
c
01 .§.._~meas010 --~-Q1
for
~ 6 -----
o

!iz~
02 - - -
03 ~--
D4 ~--
t--_-'-13=_ Q2

I
~Q3
11 Q4
-
CD
X
~OE
UI
x --l
»
~f~ CLKA' ......... 0
-<
Z

!~~
CLKB .!!.. OR ()
:::I:
:a
~~
...
UNCK 3
OUT----I--e<t en
0
Z
0
r 0
~ en c:::

IR 2
L-+-_---'I I
~
I II II I I1II I I I I II I 1,-, 16 IN
UNCK
'"0
....
I
en
m
"....m
;::
m
0
:::!!
::::c
~
CLR
m
)J Z
....<0 -n
'"I ::::c
~
)J
m
<
a;
m 0
0
en
c:::
m -10
"....m
;::
3:Z
m ......
m 3:-Il>-
m
)J
0 0
% <0
co ::::c~
'" -<UI
'"
SN74S225
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDLS207 - SEPTEMBER 1976 - REVISED SEPTEMBER 1993

schematics of inputs and outputs

EQUIVALENT OF ALL INPUTS

EXCEPT DATA INPUTS

Vcc

Input

EQUIVALENT OF TYPICAL OF
DATA INPUTS ALL OUTPUTS

Vcc---"--- ----~~--Vcc

Input

Output

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ............................................................ 7 V
Input voltage, VI .......................................................................... 5.5 V
Off-state output voltage .................................................................... 5.5 V
Operating free-air temperature range, TA ................................................. O°C to 70°
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation 01 the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

~lExAs
INSTRUMENTS
3-34 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74S225
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDLS207 - SEPTEMBER 1976 - REVISED SEPTEMBER 1993

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
Q outputs -6.5
10H High-level output current mA
All other outputs -3.2
Q outputs 16
10L Low-level output current mA
All other outputs 8
CLKA or CLKS high 25
tw Pulse duration UNCKIN low 7 ns
CLR low 40
Data (see Note 2) -20
tsu Set up time before CLKA T or CLKST ns
CLR inactive 25
th Hold time after CLKA i or CLKSi 70 ns
TA Operating free-air temperature 0 70 ·C
NOTE 2: Data must be set up within 20 ns after the load clock positive transition.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VIK VCC = 4.75 V, 11=-18mA -1.2 V
Qoutputs VCC = 4.75 V, IOL=-6.5 mA 2.4 2.9
VOH V
All others VCC = 4.75 V, IOL=-3.2mA 2.4 2.9
Qoutputs VCC = 4.75 V, IOL=16mA 0.35 0.5
VOL V
All others VCC = 4.75 V, IOL = 8 mA 0.35 0.5
10ZH VCC = 5.25 V, Va =2.4 V 50 ~
10ZL VCC = 5.25 V, VO=0.5V -50 ~
II VCC = 5.25 V, VI = 5.5 V 1 mA
Data 40
IIH VCC = 5.25 V, VI =2.7V ~
All others 25
Data -1
IlL VCC = 5.25 V, VI = 0.5 V mA
All others -0.25
10S+ VCC = 5.25 V, VO=O -30 -100 rnA
ICC§ VCC = 5.25 V 80 120 mA
t All tYPical values are at VCC = 5 V, TA = 25·C.
+ Duration of the short circuit should not exceed one second.
§ ICC is measured with all inputs grounded and the output open.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-35
SN74S225
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDLS207 - SEPTEMBER 1976 - REVISED SEPTEMBER 1993

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
FROM TO
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
PNPUT) (OUTPUT)
ClKA 10 20
'max ClKB 10 20 MHz
Cl = 30pF
UNCK IN 10 20
tw UNCKOUT 7 14 ns
tdis OE AnyQ CL=5pF 10 25 ns
ten OE AnyQ 25 40 ns
tplH 50 75
UNCKIN AnyQ ns
tpHL 50 75
tPLH CLKAor ClKB OR 190 300 ns
tpLH 40 60
UNCK IN OR ns
tpHL 30 45
CLR OR CL = 30 pF 35 60
CLKAorCLKB 25 45
tPHl UNCKOUT ns
UNCK IN 270 400
CLKAor CLKB IR 55 75
UNCKIN 255 400
IR
tpLH CLR 16 35 ns
ORr AnyQ 10 20
t All tYPical values are at VCC = 5 V, TA = 25°C.

~1ExAs
INSTRUMENTS
3-36 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74S225
16 x 5 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDLS207 - SEPTEMBER 1976 - REVISED SEPTEMBER 1993

PARAMETER MEASUREMENT INFORMATION

7V
SWITCH POSITION TABLE

SI
~ Open
TEST SI
Open
tPLH
tPHL Open
tPZH Open
From Output - -....
Under Test
-----41..-- Test Point tpZL Closed
Open
tPHZ
=
CL SO pF R2=soon tpLZ Closed
(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.SV

Hlgh·Level
Pulse ~ I I 0.3 V

3.SV *- tw-+l

(~3~
Timing I I
3.SV
Input ___ Low·Level ~ 1 't V Jt::":'""
0.3V Pulse ~--.:.~V_ n.3V
tsu~th

~
Data 3.SV VOLTAGE WAVEFORMS
Input 1.3V 1.3V PULSE DURATION
0.3V
VOLTAGE WAVEFORMS

~
SET UP AND HOLD TIMES
\'1.3V 3.SV
Output
Control
~r--4~~---
I

---:s
InputJf \,- - - - 3.S V t .1 I£- 0.3 V
(see Note B) 1.3 V ~ 1.3 V PZL~ I'

I I ' 0.3V
l : - -~1-r-=-
tpLZ 3.SV
tPLH -J4---.+! ~ tpHL
I Wavelorm 1 II 1.3 V I I __ ...L.
I II 'i.I ~.; VVoH I-
In· Phase
Output I T 1.3V I
-"""1--' I
C VOL
SI Closed
(see Note C)
I tpHZ +I ~-L:~\
tpHL --J....--./ ~ IpLH
._.. ,
tpZH -+I ~
r~--;--::..
1 oJ.
- VOH
Wavelorm2

----L~~ __ ~3~V
Out·ol·Phase ,I 1.3 V FV
1.3O
V H S10pen
Output . , _ _ VOL (see Note C)

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR :5 1 MHz, Zo = 50 n, t r :5 2 ns, tf:5 2 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3-37
SN74S225
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDLS207 - SEPTEMBER 1976 - REVISED SEPTEMBER 1993

APPLICATION INFORMATION

~ rI...........--------~((r-----
~ jJ

ClKB
~~L....I ~
rI..........________~,,~,_____
~ )j

o S888883 Word 1 B888I Word 2 ~ Word 16

Word 3
Is low

UNCK~
IN

IR
-_.JI H
V r~
11
It

~Co
UNCK
OUT U rr-u
'S -, r--,.....___
0 OR
-I
--------., 1""'----, Irl__- - -
Q __ 1_w_o_rd_1_......,,''r'i_w_o_rd_1_ _ _......1 Word 2
..... ~I W10:d

load Unload Unload

Words 3-15 Word 1 Words 3-15

HH
Clear Load load Load Unload Unload
Word 1 Word 2 Word 16 Word 2 Word 16

Figure 2. Typical Waveforms for a 16-Word FIFO

~ThxAs
INSTRUMENTS
3-38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74S225
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDLS207 - SEPTEMBER 1976 - REVISED SEPTEMBER 1993

APPLICATION INFORMATION

(hlgh)- >CLKB (hlgh)- >CLKB (hlgh)- >CLKB

CLK
NC
CLKA OR
UNCK
OUT UNCK
IN
CLKA OR
UNCK
OUT UNCK
IN
CLKA OR
UNCK
OUT UNCK
IN
--D- OR

UNCKIN
- IR NC- IR NC- IR
DO QO DO QO DO QO
5-Blt{
Data
01
02
Q1
Q2
01
02
Q1
Q2
01
02
Q1
Q2 }
5-BII
Data
In 03 Q3 03 Q3 03 Q3 Out
04 Q4 04 Q4 04 Q4
CLR OE CLR OE CLR OE

1 1
IR -
h-
~ r----l ~
CLR OE
-
CLR OE
~-
CLR OE
(high) - t:> eLKB (hlgh)- f> CLKB (hlgh)- I>CLKB
CLKA OR CLKA OR CLKA OR :--
NC UNCK UNCK UNCK
OUTUNCK OUTUNCK OUT UNCK
IN IN IN
- IR NC- IR NC- IR
DO QO DO QO DO QO
5_Blt{ 01 Q1 01 Q1 01 Q1 5-Blt
Data
In
02 Q2 02 Q2 02 Q2 } Data
Oul
03 Q3 03 Q3 03 Q3
04 Q4 04 Q4 04 Q4

Figure 3. Expanding the SN74S225 FIFO (48 words of 10 bits shown)

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3-39
3-40
 SN74ALS229B
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
REVISED JUNE 1992

• Independent Asychronous Inputs and OW OR N PACKAGE

Outputs (TOP VIEW)

• 16 Words by 5 Bits OE 1 U 20 Vee

• Data Rates From 0 to 40 MHz 2 19 EMPTY+2
• Fall-Through Time ... 14 ns Typ FULL 3 18 UNCK
• 3-State Outputs LOCK 4 171 EMPTY
00 5 16 QO
• Package Options Include Plastic
Small-Outline Packages (OW), Plastic Chip 01 6 15 1 Q1
Carriers (FN), and Standard Plastic 30o-mil 02 7 14 Q2
DIPs (N) 03 8 13 Q3
04 9 12 Q4
description GNO [ 10 11 RST

This aO-bit memory uses advanced low-power

FNPACKAGE
Schottky technology and features high speed and (TOP VIEW)
fast fall-through times. It is organized as 16 words
by 5 bits. N ~
A FI FO memory is a storage device that allows I
...J~
:5:5 w
~
o~
data to be written into and read from its array at Lu..o::i?w
independent data rates. This FIFO is designed to
process data at rates from 0 to 40 MHz in a 3 2 1 20 19
LOCK 4 18 UNCK
bit-parallel format, word by word. 00 5 17 EMPTY
Data is written into memory on a low-to-high 01 6 16 QO
transition at the load clock (LOCK) input and is 02 7 15 Q1
read out on a low-to-high transition at the unload 03 8 14 Q2
9 10 11 12 13
clOCk (UNCK). The memory is full when the
number of words clocked in exceeds by 16 the
number of words clocked out. When the memory
is full, LOCK Signals have no effect. When the
memory is empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the FULL, EMPTY, FULL-2, and FULL+2 output flags. The FULL
output is low when the memory is full and high when it is not full. The FULL-2 output is low when the memory
contains 14 data words. The EMPTY output is low when the memory is empty and high when it is not empty.
The EMPTY+2 output is low when two words remain in memory.
A low level on the reset (RST) input resets the internal stack control pointers and also sets EMPTY low and sets
FULL, FULL-2, and EMPTY+2 high. The Q outputs are not reset to any specific logic level. The first low-to-high
transition on LOCK after either a RST pulse or from an empty condition causes EMPTY to go high and the data
to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs
are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input
is low. OE does not affect the output flags. Cascading is easily accomplished in the word-width direction but is
not possible in the word-depth direction.
The SN74ALS229B is characterized for operation from O°C to 70°C.

Copyright © 1992, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3-41
SN74ALS2298
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS090 - MARCH 1990 - REVISED JUNE 1992

logic symbolt

FIFO 16x5

CTR
11 3
." CT=O (Ch 16) G1 FULL
2
CT= 14 FULL-2
4 19
LOCK 1(+/C2) CT=2 EMPTV+2
18 17
UNCK 3- (CT = 0) G3 EMPTY

1
OE

5
,
EN4

r 16
DO 20 4\1 QO
6 15
01 Q1
7 14
02 Q2
8 13
03 Q3
9 12
04 Q4

t This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but does not
show the details of implementation; forthese, see the logic diagram. The symbol represents the memory as if it were controlled by a single counter
whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is O.
Pin numbers shown are for the DW and N packages.

~1ExAs
INSTRUMENTS
3-42 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS229B
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS090 - MARCH 1990 - REVISED JUNE 1992

logic diagram (positive logic)

Ring
1
Counter
2
CTR
3
4 0lV16
5
6
7
~--~--------++~3>+
8
9
10
Write 11
Address 12
13
CT = 1 14
15
16

Ring 1
Counter 2
CTR 3
0lV16 4
5
6
7
8
+ 9
10
11 Read 11
RST Address 12 RAM16x5
13
14 EN
CT = 1 15
16

5 16 QO
DO
6 15 Q1
01
7 14 Q2
02
8 13 Q3
03
9 12 Q4
04

16 16 COMP
P=Q
P 17
EMPTY
P=Q+2 S
Q 3
FULL
P=Q-2 R
2
FULL-2
19
EMPTY+2
Pin numbers shown are for the DW and N packages.

-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 ~3
SN74ALS229B
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS090 - MARCH 1990 - REVISED JUNE 1992

timing diagram

.J 1

LOCK 1

00-04

UNCK

QO-Q4

1 1 1 I I
I
~~I------+!------~~r~i------~----~----------
I

---IW
1

1I
II
I1 u-i f - -.....
..---+-1
1
1
1
1
I
I
I
I
1 I 1 1
1 I 1
I
1
1
1
1
1
W
1
1
1
I
I
I
LJ
I
~
Initialize 1 Unload Empty Empty+2 Full-2 Full
Pointers 1 W2
1
Load
W1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee ....................................................................... 7 V
Input voltage, VI ........................................................................... 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. DOC to 7Doe
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

~TEXAS
INSTRUMENTS
3-44 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS229B
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS090 - MARCH 1990 - REVISED JUNE 1992

recommended operating conditions (see Note 1)

MIN NOM MAX UNIT
Vee Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
Qoutputs -1.6
10H High-level output current rnA
Status flags -0.4
Q outputs 24
10L Low-level output current rnA
Status flags 8
LOCK 0 40
fclock Clock frequency MHz
UNCK 0 40
RSTlow 18
LOCK low 15
tw Pulse duration LOCK high 10 ns
UNCKlow 15
UNCKhigh 10
Oata before LOCKt 8
tsu Setup time RST (inactive) before LOCKt 5 ns
LOCK (inactive) before RSTt 5
th Hold time Oata aiter LOCKt 5 ns
TA Operating free-air temperature 0 70 ·C
..
NOTE 1: To ensure proper operation ofthls high-speed FIFO devlce,lt IS necessary to provide a clean signal to the LOCK and UNCK clock Inputs .
Any excessive noise or gl~ching on the clock inputs that violates the VIL, VIH, or minimum pulse duration limits can cause a false clock
or improper operation of the internal read and wr~e pOinters.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYpt MAX UNIT
VIK VCC=4.5V, 11=-18mA -1.2 V
Qoutputs VCC-4.5V, IOL=-2.6 rnA 2.4 3.2
VOH V
Status flags VCC = 4.5 V to 5.5 V, IOL--0.4mA VCC-2
VCC=4.5V, 10L- 12mA 0.25 0.4
Q outputs
VCC=4.5V, 10L= 24 rnA 0.35 0.5
VOL V
VCC-4.5 V, IOL-4mA 0.25 0.4
Status flags
VCC= 4.5 V, IOL=8mA 0.35 0.5
10ZH VCC-5.5V, VO-2.7V 20 IJA
10ZL VCC=5.5V, VO=0.4V -20 IJA
II VCC = 5.5 V, VI=7V 0.1 rnA
IIH VCC=5.5V, VI=2.7V 20 IJA
IlL VCC=5.5V, VI = 0.4 V -0.2 rnA
10:1: VCC=5.5V, Vo = 2.25 V -30 -112 rnA
ICC VCC=5.5V 85 140 rnA
t All tYPical values are at VCC = 5 V, TA = 25·C.
:I: The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265 3-45
SN74ALS229B
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST·OUT MEMORY
SDAS090 - MARCH 1990 - REVISED JUNE 1992

switching characteristics (see Figure 1)

Vee=4.5 V to 5.5 V,
el=50 pF,
FROM TO R1=500n,
PARAMETER
(INPUT) (OUTPUT) R2=5000, UNIT
TA=o·e to 70·e
MIN MAX
fmax LOCK, UNCK 40 MHz
lDCKt 6 30
tpd AnyQ ns
UNCKt 6 30
tpLH LDCKt 5 25
EMPTY ns
tPHL UNCKt 6 27
tpHL RST! EMPTY 5 26 ns
LDCKt 7 33
tpd EMPTY+2 ns
UNCKt 9 35
tPLH RST! EMPTY+2 9 33 ns
LDCKt 7 33
tpd FULL-2 ns
UNCKt 9 35
tpLH RST! FULL-2 9 33 ns
tPHL LDCKt FULL 6 27 ns
UNCKt 5 25
tpLH FULL ns
RSTJ. 8 31
ten OEt Q 2 15 ns
tdis OEJ. Q 1 15 ns

~TEXAS
INSTRUMENTS
3-46 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS229B
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS090 - MARCH 1990 - REVISED JUNE 1992

PARAMETER MEASUREMENT INFORMATION

7V
SWITCH POSITION TABLE

S1
b Open
TEST
tPLH
S1
Open
tPHL Open
R1 = soon tpZH Open
From Output
Under Test
--.-_.---.1--- Test Point tpZL Closed
tpHZ Open
CL=SOpF R2=soon tPLZ Closed
(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5V

High-Level
Pulse ~ I I 0.3 V

Timing
Input

tsu~th
t~3~ ___ 3.SV

0.3 V
Low-Level
Pulse
~
14--
I

~~.~V_
1 ...
tw

v
---+I
I
JI":'"::""
3.5 V

O.3V

~
Data 3.SV VOLTAGE WAVEFORMS
Input 1.3V 1.3V PULSE DURATION
0.3V
VOLTAGE WAVEFORMS

~~
SETUP AND HOLD TIMES 3'SV
Output
Control I ~~ 1.3V __ _
Input - - - - 3.S V .1 I 0.3 V
I+-
I +--~~r-=-
(see Note B) L 1.3 V ' \ . 1.3 V
tPZL .....
--II
~
I. 0.3 V
tpLZ 3.5 V
tpLH -l4--+! ~ tpHL Waveform 1 I 1.3V I I ..L.
In-Phase I 1/ I 'i,-:;.; VOH S1 Closed I --~
I T 1.3V I ~V
~ L ~~~V
Output (see Note C)
---r-j--J I VOL I tPHZ...j
-+I ~
t
PHL~
I~~, ~tpLH
j
Waveform 2
- .
tpZH I..L.
rr---t-~ -=-- VOH
----L~~ __ ~3:V
Out-of-Phase 1 1.3 V FV
1.3O
V H
\ S10pen
Output . . __ VOL (see Note C)

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ::; 1 MHz, Zo = 50 n. tr S 2 ns. tf S 2 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

~lEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-47
 SN74ALS233B
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

• Independent Asychronous Inputs and OW OR N PACKAGE

(TOPVIEWj
Outputs
• 16 Words by 5 Bits OE Vee
• Data Rates From 0 to 40 MHz FULL-1 EMPTY+1
• Fall-Through Time ... 14 ns Typ UNCK
• 3-State Outputs LOCK 4 EMPTY
• Package Options Include Plastic 00 00
Small-Outline Packages (OW), Plastic Chip 01 01
Carriers (FN), and Standard Plastic 300-mil 02 02
DIPs (N) 03 03
04
description GNO
This aO-bit memory uses advanced low-power
FN PACKAGE
Schottky technology and features high speed and (TOPVIEWj
a fast fall-through time. It is organized as 16 words
by 5 bits. '+
A FIFO memory is a storage device that allows ....J13 ~
:5:5UJ()~
data to be written into and read from its array at L.u.o-YUJ
independent data rates. This FIFO is designed to
process data at rates from 0 to 40 MHz in a 3 2 1 20 19
LOCK 4 18 UNCK
bit-parallel format, word by word. 00 5 17 EMPTY
Data is written into memory on a low-to-high 01 6 16 00
transition at the load clock (LOCK) input and is 02 7 15 01
read out on a low-to-high transition at the unload 03 8 14 02
910111213
clock (UNCK) input. The memory is full when the
number of words clocked in exceeds by 16 the
number of words clocked out. When the memory
"<t Cl II-
"<t C')
ClZ(l)CJCJ
(!:leI:
is full, LOCK signals have no effect. When the
memory is empty, UNCK signals have no effect.
Status ofthe FIFO memory is monitored by the FULL, EMPTY, FULL-1, and EMPTY+1 output flags. The FULL
output is low when the memory is full and high when it is not full. The FULL-1 output is low when the memory
contains 15 data words. The EMPTY output is low when the memory is empty and high when it is not empty.
The EMPTY+1 output is low when one word remains in memory.
A low level on the reset (RST) input resets the internal stack control pointers and also sets EMPTY low and sets
FULL, FULL-1, and EMPTY+1 high. The Q,outputs are not reset to any specific logic level. The first low-to-high
transition on LOCK, after either a RST pulse or from an empty condition, causes EMPTY to go high and the data
to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs
are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input
is low. OE does not affect the output flags. Cascading is easily accomplished in the word-width direction but is
not possible in the word-depth direction.
The SN74ALS2338 is characterized for operation from O°C to 70°C.

Copyright © 1992, Texas Instruments Incorporated

~~~~~~~~o~~1: s~~:r:~~sl~;~:~ :lle:~:~o~m~a:i
standard warranty. Production processing does not necessarily Include
testing of all parameter'S. -!/}TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3-49
SN74ALS233B
16 x 5 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SCAS253 - MARCH 1990 - REVISED JUNE 1992

logic symbolt

FIF016x5

CTR
11 3
"'- CT=O (CT = 16) G1 FULL
2
CT= 15 FULL-1
4 19
LOCK 1(+/C2) CT= 1 EMPTY+1
18 17
UNCK 3- (CT = 0) G3 EMPTY

1
OE

DO
5
, EN4

20
r 16
QO
4'\1
6 15
01 Q1
7 14
02 Q2
8 13
03 Q3
9 12
04 Q4

t This symbol is in accordance w~h ANSIIIEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but does not
show the details of implementation; for these. see the logic diagram. The symbol represents the memory as if it were controlled by a single counter
whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is O.
Pin numbers shown are for the DW and N packages.

~TEXAS
INSTRUMENTS
3-50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ALS233B
16 x 5 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SCAS253- MARCH 1990 - REVISED JUNE 1992

logic diagram (positive logic)

Ring
1
Counter
2
CTR
3
DIV16 4
5
6
7
B
tr---.---------+~_d~+
9
10
Write 11
Address 12
13
CT = 1 14
15
16

1 Ring
2 Counter
3 CTR
4 DIV 16
5
6
7
L-____________ B ~~~+

9
10
11 Read 11
RST----------------------~ Address 12 RAM16x5
13
14 EN
t-------------~~~CT=1 15
16 1A...L
16
16 1
2A16

~~~
16
QO
15
D1 Q1
14
D2 7 Q2
DBO § 6 13
D3 Q3
9 12
D4 Q4

COMP
P=Q
P 17
EMPTY
Q P=Q+2
3
FULL
P=Q-2
2
FULL-1

19
EMPTY+1
Pin numbers shown are for the OW and N packages.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303. DALLAS, TEXAS 75265 3-51
SN74ALS233B
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS253 - MARCH 1990 - REVISED JUNE 1992

timing diagram

~
I
LOCK I

00-04

UNCK

00-04

~~I------+i------~~~~i------~----~----------- I
I
I
I I I
I rl : .----+-1----.,1. I
L-J ,1'--....
i I
I I !---l I I I
I
I I I I
I I I
I
I
I
I
I
I
W
I
I
I
I
I
I
LJ
I
LJ
Initialize I Unload Empty Empty+1 Full-1 Full
Pointers I W2
I
Load
W1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee ....................................................................... 7 V
Input voltage, VI ........................................................................... 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. QOC to 7QoC
Storage temperature range............. ....... ... ........ .............. ..... . .... -65°C to 15QoC
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

~TEXAS
INSTRUMENTS
3-52 POST OFFICE BOX 655303. DALLAS. TEXAS 75265
 SN74ALS233B
16 x 5 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SCAS253- MARCH 1990 - REVISED JUNE 1992

recommended operating conditions (see Note 1)

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
Q outputs -1.6
10H High-level output current mA
Status flags -0.4
Qoutputs 24
10L Low-level output current mA
Status flags 8
LOCK 0 40
fclock Clock frequency MHz
UNCK 0 40
RSTlow 18
LOCK low 15
tw Pulse duration LOCK high 10 ns
UNCKlow 15
UNCKhigh 10
Oata before LOCK"!' 8
tsu Setup time RST (inactive) before LOCK"!' 5 ns
LOCK (inactive) before RST"!' 5
th Hold time Oata after LOCK"!' 5 ns
TA Operating free-air temperature 0 70 °C
NOTE 1: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LOCK and UNCK clock inputs.
Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse duration limits can cause a false clock
or improper operation of the internal read and write pOinters.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VIK VCC= 4.5 V, 11=-18mA -1.2 V
Qoutputs VCC = 4.5 V, 10H =-2.6mA 2.4 3.2
VOH V
Status flags VCC = 4.5 V to 5.5 V, 10H =-0.4mA VCC-2
VCC=4.5V, 10L= 12 mA 0.25 0.4
Qoutputs
VCC = 4.5 V, IOL=24 mA 0.35 0.5
VOL V
VCC = 4.5 V, IOL=4 mA 0.25 0.4
Status flags
VCC = 4.5 V, IOL=8 mA 0.35 0.5
10ZH VCC = 5.5 V, VO=2.7V 20 ~
10ZL VCC= 5.5 V, Vo = 0.4 V -20 ~
II VCC=5.5V, VI=7V 0.1 mA
IIH VCC=5.5V, VI =2.7V 20 ~
IlL VCC = 5.5 V, VI =0.4 V -0.2 mA
10* VCC=5.5V, Vo = 2.25 V -30 -112 mA
ICC VCC = 5.5 V 88 133 mA
t =
All typical values are at VCC = 5 V, TA 25°C.
:j: The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-53
SN74ALS233B
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS253- MARCH 1990- REVISED JUNE 1992

switching characteristics (see Figure 1)

Vee = 4.5 V to 5.5 V,
eL = 50 pF,
FROM TO R1 =5000,
PARAMETER UNIT
(INPUT) (OUTPUT) R2 = 5000,
TA = ooe to 700 e
MIN MAX
fmax lOCK, UNCK 40 MHz
LDCKi 6 32
tpd AnyQ ns
UNcKi 6 30
tpLH LDCKi 5 25
EMPTY ns
tpHL UNCKi 6 27
tpHL RST! EMPTY 5 25 ns
LDCKi 7 34
tpd EMPTY+1 ns
UNCKi 7 34
tpLH RST! EMPTY+1 8 31 ns
lOCKi 9 33
tpd FULL-1 ns
UNCKi 8 32
tpLH RST! FULL-1 11 32 ns
tpHL LDCKi FULL 6 27 ns
UNCKi 5 25
tpLH FULL ns
RST! 9 30
ten OEi Q 2 15 ns
tdis OE! Q 1 15 ns

~1ExAs
INSTRUMENTS
3-54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ALS233B
16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS253- MARCH 1990 - REVISED JUNE 1992

PARAMETER MEASUREMENT INFORMATION

7V
SWITCH POSITION TABLE

S1
b Open
TEST
tpLH
S1
Open
tPHL Open
R1 =5000 tPZH Open
From Output - -.....-e-~~­ Test Point tpZL Closed
Under Test Open
tPHZ
CL=50pF R2=5000
(see Note A) tPLZ Closed

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V

High-Level
Pulse ~ I I 0.3V
14-- tw ~
Timing
Input
i
__---Jq. ~3~
3.5 V

_ _ _ 0.3 V Low-Level ~1~V ~

I I
3.5 V

Pulse ~~.~V_ O.3V

Isu~th
Data ~~.;:-3.5V VOLTAGE WAVEFORMS
Input --I 1.3V ~ PULSE DURATION
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
InputJ, ~- - - - 3.5V
(see Note B) 1.3 V i\ 1.3 V
I I . .0.3V
tPLH --14---+1 ~ tpHL Waveform 1
In-Phase , 1/ ' 'S..~.; VOH S1 Closed
Output , T 1.3V' ~V (see Note C)
- - , - ,- . J , VOL
I~~, J+--+I- tpLH
tpHL~ ,
Waveform 2
Out-of-Phase 1 1.3 V Y;;VOH
1.3 V
\ S10pen
Output . . __ VOL (see Note C)

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR S 1 MHz, Zo = 50 0, tr S 2 ns, tf::; 2 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-55
3-56
 SN74ALS235 .
64 x 5 ASYNCHRONOUS FIRST·IN. FIRST·OUT MEMORY
SDAS108A - OCTOBER 1986 - REVISED SEPTEMBER 1993

• Asynchronous Operation OW OR N PACKAGE

(Top VIEW)
• Organized as 64 Words by 5 Bits
• Data Rates From 0 to 25 MHz OE Vcc
• 3-State Outputs HF AF/AE
• Package Options Include Plastic SO
Smail-Outline Packages (OW), Plastic OR
J-Leaded Chip Carriers (FN), and Standard 00
Plastic 300-mll DIPs (N) 01
02
description 03 03
04 04
The SN74ALS235 is a 320-bit memory utilizing GNO 11 RST
advanced low-power Schottky IMPACT"M
technology. It features high speed with fast
fall-through times and is organized as 64 words by FNPACKAGE
(TOP VIEW)
5 bits.
A first-in, first-out (FIFO) memory is a storage
device that allows data to be written into and read
from its array at independent data rates. The
SN74ALS235 is designed to process data at rates SI 43 2 1 20 1918 SO
from 0 to 25 MHz in a bit-parallel format, word by 00 5 17 OR
word. 01 6 16 00
Data is written into memory on the rising edge of 02 7 15 01
the shift-in (SI) input. When SI goes low, the first 03 8 14 02
9 10 11 12 13
data word ripples through to the output (see
Figure 1). As the FIFO fills up, the data words
stack up in the order they were written. When the
FIFO is full, additional shift-in pulses have no
effect. Data is shifted out of memory on the falling edge ofthe shift-out (SO) input (see Figure 2). When the FIFO
is empty, additional SO pulses have no effect. The last data word remains at the outputs until a new word falls
through or reset (RST) goes low.
Status of the SN74ALS235 FIFO memory is monitored by the output-ready (OR), input-ready (lR),
aimost-fuil/aimost-empty (AF/AE), and half-full (HF) flags. When OR is high, valid data is available at the
outputs. OR is low when SO is high and stays low when the FIFO is empty.IR is high when the inputs are ready
to receive more data.IR is low when SI is high and stays low when the FIFO is full. AF/AE is high when the FIFO
contains eight or less words (see Figure 5) or 56 or more words (see Figure 6). AF/AE is low when the FIFO
contains between nine and 55 words. HF is high when the FIFO contains 32 or more words and is low when
the FIFO contains 31 words or less (see Figure 7).
When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high
during this time, the OR flag pulses high indicating valid data at the outputs (see Figure 3).
When the FI FO is full, data can be shifted in automatically by holding SI high and taking SO low. One propagation
delay after SO goes low, IR will go high. If SI is still high when IR goes high, data at the inputs are automatically
shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the
IR output.

IMPACT is a trademark of Texas Instruments Incorporated.

Copyright © 1993. Texas Instruments Incorporated
:~:'~~:fo~1: .:r,rC:1:81;"CU~~':':l ,c:~::m~,:
standard warranty. Production processing does not necessarily Include
testing of all parameters. ~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-57
SN74ALS235
64 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDASl DBA - OCTOBER 1988 - REVISED SEPTEMBER 1993

description (continued)
The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR high
and OR low signifying that the FIFO is empty. Reselling the FIFO sets the outputs to a low logic level (see
Figure 1). If SI is high when RST goes high, the input data is shifted in and IR goes low and remains low until
SI goes low. If SI goes low before RST goes high, the input data will not be shifted in and IR goes high. Data
outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE)
input is high. OE does not affect the statUS-flag outputs (see Figure 2).
The SN74ALS235 is characterized for operation from ooe to 70°C.
logic symbolt

FIF064x5

CTR 17
4 3CT>0 OR
51 5 +/C1
L G2
(CT>0) G4
CTS8/CT~56
19
AF/AE
18
50 4- 2
L G3
CT~32
3
HF
2CT <64 IR
(CT <64) G5
~
CT=O
11

.,
R
1 r-.,
EN6
5
r 16
DO 10 -'6V QO
6 15
01 Q1
7 14
02 Q2
8 13
03 Q3
9 12
04 Q4

tThis symbol is in accordance with ANSI/IEEE Standard 91-1984 and lEG Publication 617-12.

~1ExAs
INSTRUMENTS
3-58 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS235
64 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 08A - OCTOBER 1986 - REVISED SEPTEMBER 1993

functional block diagram

16
5 QO
DO 15
6 Q1
01 FIFO FIFO 14
02
7
Input
f-----"- 65 x 5 Bit ~ Output 13
Q2
Q3
03
8 Stage r-------v' Register f------/ Stage 12
Q4
9
04 f-

IR
3
fJ
Input-
~ Control
1
Register-
~
J1
Output-
18
SO
Control Control
4 Logic i'V---v' Logic ['v----v' Logic 17
51 OR

)Y
Flag-
Control
Logic

11
.~
I
I 19
AF/AE
2
HF

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3-59
SN74ALS235
64 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 DBA - OCTOBER 1986 - REVISED.SEPTEMBER 1993

logic diagram (positive logic)

OE------------------------------------------------------------~.-1~
Word 64 Word 63

11: 03
Word 57 Word 56Word 55 Word 54 Word 33 Word 32 Word 31 Word 30

SI
2
SO

3
4
5
6
7

Continued on Next Page

~1ExAs
INSTRUMENTS
3-60 POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
 SN74ALS235
64 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS10BA- OCTOBER 1986 - REVISED SEPTEMBER 1993 ,

logic diagram (positive logic) (continued)

QO} Data
Q1
Q2 Outputs
Q3
Word 10 Word 9 Word 8

OR

3 HF
4
5
AF/AE
6 IR
7

timing diagram
is .11 r.

I I I I' Word 1 ' I Word 2 Word56 I I

IR~~~55 I I
! r-" i I
OR" ,1-----t-uL...r~n-u-
-r--j" 1---1 ~ II I I' I
AF/AE=1 I ~I I I~ ~I I j I
~II
HF =1 I
I
I \I I I
I
I
I
n I
I
II-I---+I-----~I\
'0--,.1_ _ __
..
I Shift In Almost Half Almost Empty Full
Clear W1 Empty+1 Full Full

*t
The last data word shifted out of the FIFO remains at the output until a new word fans through or a RST pulse clears the FIFO,
While the output data is considered valid only when the OR flag is high, the stored data remains at the output, Any additional words written into
the FIFO will stack up behind the first word and will not appear at the output until SO is taken low.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
SN74ALS235
64 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 08A - OCTOBER 1986 - REVISED SEPTEMBER 1993

RST 1
I
I+--Isu~

SI! i-I ---,..1-----1 "",1---

04-00 ~ su~
1 "'-- t *- th ---+i
-----.J

)(:
I
: X,..;---
I

!. tPLH -+I 1 14- tpHL -+I 14- tPLH -+I

IR Full ! 1 I i I r
_ _ _ _rl--tP_H_L-+I. .; 4 - - t p L H ~i-------
I+r
OR I I Empty ! .1
I
14- tpd ~ 11+4- - tpd ---+l~1
Q4-QO --------~\.I /I~------
-------~------------~-----
NOTE A: SO is low.

Figure 1. Master Reset and Data-In Waveforms

SO

i
OR
1 I

IR Full
'PLH~
Q4-QO

NOTE A: SI is low.

Figure 2. Data-Out Waveforms

~1ExAs
INSTRUMENTS
3-62 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS235
64 x 5 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDAS1 08A - OCTOBER 1986 - REVISED SEPTEMBER 1993

04- 00 m<L-----.J ~
I
I"PI+-
tsu th --+i
51 I I
~I------------------------------
I
I
~ tPLH -..II.- tw --J
I I
E_m_Pt_y________~1
OR _______ ~I _________________
H
I td(OV-ORH)
04-00 -------I-nV-al-ld---""X. . .______________
Figure 3. Data Fall-Through Waveforms

SO

51 ---.J j+-IPLH -+i

I+-- tw ---+I
I I
FU_II_ _ _ _ _ _ _ _~I
IR _________ ~1 ______ F_UI_I_______

04-00 ~""'_________.J~
Figure 4. Automatic Data-In Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS235
64 x 5 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDAS1 08A - OCTOBER 1986 - REVISED SEPTEMBER 1993

so
r- tPLH-t/

AF/AE _ _----.:-1------,~
If- tPHL""""I

SI
--------------------------~------~~I---------
Figure 5. Almost-Empty Waveforms

SI

AF/AE

Ie- tPHL--I
~
so ______________~__________~r-------~I_________
Figure 6. Almost-Full Waveforms

SI .-J
~tpLH -...I

HF --------------~I--------------------~~ I
If-- tPHL ---tI

so I I

Figure 7. Half-Full Waveforms

~·TEXAS
INSTRUMENTS
3--64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ALS235
64 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 08A - OCTOBER 1986 - REVISED SEPTEMBER 1993

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ............................................................ 7 V
Input voltage, VI ........................................................................... 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA ................................................. O°C to 70°
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under"absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
Qoutputs -2.6
IOH High-level output current mA
Flags -0.4
Qoutputs 24
IOL Low-level output current mA
Flags 8
fclock Clock frequency SlorSO 0 25 MHz

Pulse duration
SlorSO I High or low 15
ns
tw
RST I Low 15
Data 0
tsu Setup time before SIT ns
RST 1High (inactive) 15
th Hold time, data after Sli 17 ns
TA Operating free-air temperature 0 70 'C

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 3-65
SN74ALS235
64 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 D8A - OCTOBER 1986 - REVISED SEPTEMBER 1993

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VIK Vee=4.5 v, 11=-18mA -1.2 V
IOH =-1 mA
AnyQ Vee = 4.5 V
VOH IOH =-2.6mA 2.4 3.2 V
Flags Vee =4.5V, IOH =-0.4 mA 2.7 3.4
IOl=12mA 0.25 0.4
AnyQ Vee = 4.5 V
IOl=24 mA 0.35 0.5
VOL V
IOl=4 mA 0.25 0.4
Flags Vee=4.5V
10l = 8 mA 0.35 0.5
10ZH Vee = 5.5 V, VO=2.7V 20 JJA
10Zl Vee=5.5 V, Vo = 0.4 V -20 JJA
II Vee=5.5 V, VI =7V 0.1 mA
IIH Vee=5.5 V, VI =2.7V 20 JJA
III Vee=5.5V, VI =0.4 V -0.1 mA
10:1: Vee =5.5 V, VO= 2.25 V -30 -112 mA
low 112 165
ICC Vee = 5.5V High 105 160 mA
Disabled 115 170
t All tYPical values are at Vee = 5 V, TA = 25°C.
:I: The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.

~TEXAS
INSTRUMENTS
3-66 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS235
64 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 08A - OCTOBER 1986 - REVISED SEPTEMBER 1993

switching characteristics (see Figure 9)

Vcc = 5 V, Vcc =4.5 V to 5.5 V,
CL = 50 pF, CL=50pF,
FROM TO R1 = 500 n, R1 =500 n,
PARAMETER
(INPUT) (OUTPUT) R2 =500n, =
R2 500 n, UNIT
TA = 25°C TA = MIN to MAXt
MIN TYP MAX MIN MAX
51 30 25
f max MHz
SO 30 25
tw+ IR high 15 8 ns
tw§ OR high 19 8 ns

td(QV-ORH) Q valid before ORi 6 9 -5 12 ns

td(SOL-QX) Q valid after SO! 13 4 ns

tpd 51! Q 600 800 350 1000 ns

tpHL Sli 20 26 8 30
IR ns
tPLH 51! 16 21 6 25
tPLH Il 51! OR 600 800 350 1000 ns
tpHL 550 700 290 880
51! AF/AE ns
tpLH 85 115 40 150
tpLH 51! HF 340 410 180 510 ns
tpd SO! Q 13 17 4 22 ns
tpHL soi 23 27 7 33
OR ns
tpLH SO! 20 24 6 30
tPLH Il SO! IR 600 800 350 1000 ns
tPHL 550 700 290 880
sot AF/AE ns
tPLH 85 115 35 150
tpHL SO! HF 340 410 170 510 ns
tpHL RST! OR 22 26 10 34 ns
tpLH RSTi IR 12 18 5 22 ns
IR 12 18 5 22
tpHL RST! ns
Q 14 17 5 19
tdis OEi Q 7 13 2 15 ns
ten OE! Q 6 12 2 13 ns
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+ The IR output pulse occurs when the FIFO is full, 51 is high, and SO is pulsed (see Figure 4).
§ The OR output pulse occurs when the FIFO is empty, so is high, and 51 is pulsed (see Figure 3).
II Data throughput or fall-through times

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-67
SN74ALS235
64 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS1 08A - OCTOBER 1986 - REVISED SEPTEMBER 1993

APPLICATION INFORMATION

- HF AF/AE - - HF AF/AE - - HF AF/AE r--

.------
-
IR
SI
DO
so
OR
QO
IR
SI
DO
so
OR
QO
. IR
SI
DO
so
OR
QO r--
SO

- 01 Q1 01 Q1 01 Q1 r--
- 02 Q2 02 Q2 02 Q2 r--
- 03 Q3 03 Q3 03 Q3 r--
- 04 RST Q4 04 _
RST
Q4 04 RST Q4 r--
I 1 1

- HF AF/AE -....- HF AF/AE -....- HF AF/AE -

IR
---Q: -
IR
SI
so
OR
IR
SI
so
OR
.. IR
SI
so
OR
------4

=L}- OR
- DO QO DO QO DO QO -
- 01 Q1 01 Q1 01 Q1 -
- 02 Q2 D2 Q2 02 Q2 -
- 03 Q3 03 Q3 03 Q3 -
- 04 RST Q4 04 RS'f Q4 04 RS'f Q4 -
I 1 1

- HF AF/AE r-- - HF AF/AE r-- -

....
HF AF/AE -
IR so IR so IR so -
SI SI OR SI OR SI OR
- DO QO DO QO DO QO -
- 01 Q1 01 Q1 01 Q1 -
- 02 Q2 02 Q2 02 Q2 -
- 03 Q3 03 Q3 03 Q3 -
- 04 RST Q4 04 RST Q4 04 RST Q4 -
I 1 1 ~

Figure 8. 192-Word by 15-Blt Expansion

~1ExAs
INSTRUMENTS
3-68 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS235
64 x 5 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SDAS1 OBA - OCTOBER 19B6 - REVISED SEPTEMBER 1993

PARAMETER MEASUREMENT INFORMATION

7V
SWITCH POSITION TABLE

~ Open
TEST S1
Open
S1 tpLH
tPHL Open
R1 = 500n tPZH Open
From Output --"---~4"'-­ Test Point tpZL Closed
Under Test tpHZ Open
=
CL 50 pF R2=500n tPLZ Closed
(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5V

High-Level
Pulse ~ I I 0.3V

I+-- ----+i
__....Jt~3~ __ _
tw
Timing , . - - - - - 3.5 V I I
3.5V
Input Low-Level ~1"V ~
0.3 V Pulse ~~.~V_ 0.3 V
tsu~th

--.7~-:~­
Data 3.5V VOLTAGE WAVEFORMS
Input 1.3V ~ PULSE DURATION
0.3V
VOLTAGE WAVEFORMS

~~
SETUP AND HOLD TIMES 3'5V
Output
Control I ~: 1.3V __ _
Input - - - - 3.5 V .1 UV
(see Note B) L 1.3 V \ . 1.3 V
tPZL --.. i+- I

~
--Ii 1- 0.3 V I : __~~:~
tPLZ 3.5 V
tpLH~ ~tPHL
In-Phase I 1/ I \L~_; VOH
Waveform 1
S1 Closed
II 1.3V I I __ ..L.
'L

Output I T 1.3V I ~V (see Note C) --L VOL

--~I~ I VOL I tPHZ..j \4- 0.3 V
-+I ~
tpHL~
I~~, ~tpLH

Y;;
I
Waveform 2
._.. .
tpZH
r.t----t-~---=-
I ...i
- VOH

----L~~ __ SE:3~V
Out-of-Phase \
1
1.3 V 1.3 V VOH S10pen
Output _ . __ VOL (see Note C)

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ~ 1 MHz, Zo = 50 n, tr ~ 2 ns, tf ~ 2 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.

Figure 9. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 3-69
3-70
4-1
 9·BIT CLOCKED/STROBED FIFOS
Features Benefits

• O.8-llm CMOS process • Fast access times combined with low

power
• Support clock rates up to 67 MHZ • Supports high-performance systems
• Fast access times • Access times as low as 12 ns for
improved performance

•-
• High drive capabilities • -8-mA to 16-mA drive capability for
high-fanout and bus applications
I co • Depths from 32 to 2K words • Allows greater system optimization
I

_.
C:J • Output edge control (OECTM) circuitry
coupled with distributed Vee and GND
• Improved noise immunity and mutual
coupling effects
o
-
o
o
• Available in JEDEC reduced-height 64-pin
TQFP, PCMCIA Type I compliant
• Board-space savings of up to 23% over
32-pin PLCC option
~
--...
c.
en
o
C"
CD
c.
::!!
o"
en

4-2
 SN74ACT7807
2048 x 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200B - JANUARY 1991 - REVISED JULY 1995

• Free-Running Read and Write Clocks Can • Input-Ready, Output-Ready, and Half-Full
Be Asynchronous or Coincident Flags
• Read and Write Operations Synchronized • Cascadable In Word Width and/or Word
to Independent System Clocks Depth
• Input-Ready Flag Synchronized to Write • Fast Access Times of 12 ns With a 50-pF
Clock Load
• Output-Ready Flag Synchronized to Read • Data Rates From 0 to 67 MHz
Clock • 3-State Outputs
• 2048 Words by 9 Bits • Available in 44-Pin PLCC (FN),
• Low-Power Advanced CMOS Technology Space-Saving 64-Pin Thin Quad Flat (PM),
• Programmable Almost-FuIl/Almost-Empty and Reduced-Height 64-Pin Thin Quad Flat
Flag (PAG) Packages

description
The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at
rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect
to the data inputs. Expansion is easily accomplished in both word width and word depth.
The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous
or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9,
WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising
edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the
output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer
regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the
output buffer.
The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET must be asserted while at least four
WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the
IR, OR, and HF flags low and the AF/AE flag high. The FIFO must be reset upon power up.
The SN74ACT7807 is characterized for operation from O°C to 70°C.

Copyright © 1995, Texas Instruments Incorporated

~~~~~~~~:'o~:1: s~~r:r:::sl~:~~:~ glle:~~:~mC:~~
standard warranty. ProductJon processing does not necessarily Include
testing of all parameters. ~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4-3
SN74ACT7807
2048x9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200B - JANUARY 1991 - REVISED JULY 1995

FNPACKAGE
(TOP VIEW)

6 5 4 3 2 1 444342 41 40
3
3 Vee
3 02
10 3 03
3 GND
12 3 04
13 3 Vee
14 3 05
15 06
16 GND
17 2 07
18 19 20 21 2223 24 25 2627 28

PAG OR PM PACKAGE
(TOP VIEW)

oJ~>88 8 ~ ~ a>8>88 8 ~ ~o ~
~~~~OO~~~~~~~~~~G
NC 1. 48 NC
00 2 47 08
GND 3 46 Vee
GND 4 45 Vee
OE 5 44 RDCLK
NC 6 43 RDEN1
Vee 7 42 NC
Vee 8 41 RDEN2
RESET 9 40 OR
PEN 39 IR
GND 38 WRTEN2
GND 37 WRTEN1/DP9
AF/AE 36 WRTCLK
HF 35 GND
Vee 34 GND
Vee 33 NC
1718192021 22 2324 25 26 2728 29303132

Ne - No internal connection

~ThxAs
INSTRUMENTS
4-4 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7807
2048x9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200B - JANUARY 1991 - REVISED JULY 1995

logic symbolt

CI>
FIFO 2048 x9
SN74ACT7807
1
RESET
19
" RESET
WRTCLK
WRTCLK
20 22
WRTEN1/0P9 IN ROY IR
21 JWRTEN 5
WRTEN2 HALF FULL HF
26 4
ROCLK ROCLK ALMOST FULUEMPTY AF/AE
42 23
OE EN1 OUT ROY OR

ROEN1
25 T &""
L ROEN
24
ROEN2
PEN
2 -
" , PROGRAM ENABLE r
7 40
DO 0 0 QO
8 39
01 Q1
9 37
02 Q2
11 36
03 Q3
04
12
13
~ ~lV 34
32
Q4
05 Q5
15 31
06 Q6
16 29
07 Q7
17 28
08 8 8 Q8

t This symbol is in accordance w~h ANSI/IEEE Std 91-1984 and lEe Publication 617c 12.
Pin numbers shown are for the FN package.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265 4--5
SN74ACT7807
2048 x9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200B - JANUARY 1991 - REVISED JULY 1995

functional block diagram

OE

~J
00-08

- Location 1
ROCLK --< I - - -
ROEN1 -
ROEN2
-
--
Synchronous
Read
Control
I Read
Pointer
I
I
I
Location 2

I 2048 x 9 RAM

-
WRTCLK
WRTEN1/0P9
WRTEN2
--
--
~~
Synchronous
Write
Control I--
I
I
Write
Pointer
I
I Location 2047
Location 2048
I
~J
Register 00-08

Reset
Logic t Status-
Flag
Logic
OR
IR
HF
AFIAE

~TEXAS
INSTRUMENTS
4-6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7807
2048 x 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200B-JANUARY 1991- REVISED JULY 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME
Almost-fuIValmost-empty flag. Depth offset values can be programmed for AF/AE or the default value of 256 can be
AF/AE 0 used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains X or less
words or (2048 - Y) or more words. AF/AE is high after reset.
DO-D8 I Nine-bit data input port
HF 0 Half-full flag. HF is high when the FIFO memory contains 1024 or more words. HF is low after reset.
Input-readyflag.IR is synchronized tothe low-ta-high transition ofWRTCLK. When IR is low, the FIFO is full and writes
IR 0
are disabled. IR is low during reset and goes high on the second low-ta-high transition of WRTCLK after reset.
Output enable. When OE, RDEN1, RDEN2 and OR are high, data is read from the FIFO on a low-to-high transition
OE I
of RDCLK. When OE is low, reads are disabled and the data outputs are in the high-impedance state.
Output-ready flag. OR is synchronized to the low-ta-high transition of RDCLK. When OR is low, the FIFO is empty and
OR 0 reads are disabled. Ready data is present on aO-a17 when OR is high. OR is low during reset and goes high on the
third low-ta-high transnion of RDCLK after the first word is loaded to empty memory.
Program enable. After reset and before the first word is written to the FIFO, the binary value on DO-D8 and DP9 is
PEN I
latched as an AF/AE offset value when PEN is low and WRTCLK is high.
Nine-bn data output port. After the first valid write to empty memory, the first word is output on aO-a8 on the third
aO-a8 0 rising edge of RDCLK. OR is also asserted high at this time to indicate ready data. When OR is low, the last word read
from the FIFO is present on aO-a8.
Read clock. RDCLK is acontinuous clock and can be asynchronous or coincident to WRTCLK. A low-to-high transition
RDCLK I of RDCLK reads data from memory when RDEN1, RDEN2, OE, and OR are high. OR is synchronous tothe low-ta-high
transnion or RDCLK.
RDEN1, Read enables. When RDEN1, RDEN2, OE, and OR are high, data is read from the FIFO on the low-to-high transition
I
RDEN2 ofRDCLK.
Reset. To reset the FIFO, four low-ta-high transitions of RDCLK and four low-to-high transitions of WRTCLK must
RESET I
occur while RESET Is low. This sets HF, IR, and OR low and AF/AE high.
Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A low-to-high transition
WRTCLK I of WRTCLK writes data to memory when WRTEN1/DP9, WRTEN2, and IR are high. IR is synchronous to the
low-ta-high transition of WRTCLK.
Wrne enable/data pin 9. When WRTEN1/DP9, WRTEN2, and IR are high, data is written to the FIFO on a low-ta-high
WRTEN1/DP9 I transition ofWRTCLK. When programming an AF/AE offset value, WRTEN1/DP9 is used as the most significant data
bn.
Write enable. When WRTEN1/DP9, WRTEN2, and IR are high, data is written to the FIFO on a low-to-high transition
WRTEN2 I
ofWRTCLK.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 4-7
SN74ACT7807
2048 x 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200B - JANUARY 1991 - REVISED JULY 1995

offset values for AF/AE

The aimost-fuil/aimost-empty flag has two programmable limits: the almost-empty offset value (X) and the
almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written
to memory. If the offsets are not programmed, the default values of X = Y = 256 are used. The AF/AE flag is
high when the FIFO contains X or less words or (2048 - Y) or more words.
Program enable (PEN) should be held high throughout the reset cycle. PEN can be brought low only when IR
is high and WRTc:LK is low. On the following low-to-high transition of WRTCLK, the binary value on DO- D8 and
WRTEN1/DP9 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN
low for another low-to-high transition of WRTCLK reprograms Y to the binary value on DO-D8 and
WRTEN1/DP9 at the time of the second WRTCLK low-to-high transition. While the offsets are programmed,
data is not written to the FIFO memory regardless of the state ofthe write enables (WRTEN1/DP9, WRTEN2).
A maximum value of 1023 can be programmed for either X or Y (see Figure 1). To use the default values of
X = Y =256, PEN must be held high.

DO-D8~XandYX Y ~

IR _ _ _ _.....JI
WRTEN1/DP9 ~X~~~Y X YMSB Y
WRTEN2 \ " "_ _ _

Figure 1. Programming X and Y Separately

~1ExAs
INSTRUMENTS
4-8 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7807
2048 x 9
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS200B - JANUARY 1991 - REVISED JULY 1995

PEN ----------4--------------------------+----------------------- 1
0

WRTCLK

I I
WRTEN1/DP9 ~B(M6a~~
~'VVY\/'-I ~

I I
--------~I~-------I~--~I----------~I--------~------------ 1
OE I I I I 0
I I I I
I I! I
QO-Q8 Invalid

Define the AF/AE Flag Using the

Default Value of X = Y =256

Figure 2. Reset Cycle

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4-9
SN74ACT7807
2048x9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200B - JANUARY 1991 - REVISED JULY 1995

1
o
1
o

WRTCLK
~~~r-fl-
I I I I
WRTEN1/0P9
I I I I 1
I I I I o

WRTEN2
I i I I

00-08

ROCLK

1
ROEN1
o
I I : I I
ROEN2 1 I I I I
I I I I I
I I 1 I 1
OE
I I 1 I I 1
I I 1 I I o
I I I I: I:
QO-Q8
________lnv_a_lId______~><~------~------Tf-1------~------~--
1
OR

AF/AE

HF

IR
L
Figure 3. Write Cycle

~1ExAs
INSTRUMENTS
4-10 POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
 SN74ACT7807
2048 x 9
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS200B - JANUARY 1991 - REVISED JULY 1995

I I
WRTEN1/-rl I
O~ I - I

WRTEN2 --nI

I
I
I
I
00-081 W~049
1 I

ROCLK I ,-+-1---'I~~~r-Sl-fl-
I I
I 1 I I I
ROEN1 J I1 i
1
I
I
I
I
I
I
I 1 1 I I
~I------~i------~------~------~I __________~I----
ROEN2 --t-i_----' I 1 I I
I 1 I I
1 I I I
1 • 1 I
OE I I I I o
I I 1 I
QO-Q8 .....,;r--W_1__I>G:X....,..:_W3__\'r-~ +~9
1 1
OR I
1
1
1
AF/AE I
I
I
HF 1
I
1

IR 11.-_____--'
Figure 4. Read Cycle

-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 4-11
SN74ACT7807
2048x9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200B-JANUARY 1991 - REVISED JULY 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, VI ........................................................................... 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. ooe to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

'ACT7807-15 'ACT7807-20 'ACT7807-25 'ACT7807·40
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 0.8 V
IOH High-level output current Q outputs, flags -8 -8 -8 -8 mA
Q outputs 16 16 16 16
IOL Low-level output current mA
Flags 8 8 8 8
fclock Clock frequency 67 50 40 25 MHz
WRTCLK high or low 6 8 9 13
tw Pulse duration RDCLK high or low 6 8 9 13 ns
PEN low 6 9 9 13
DO-DS before
4 5 5 5
WRTCLKI
WRTEN1, WRTEN2
4 5 5 5
before WRTCLKI
OE, RDEN1, RDEN2
tsu Setup time 5 6 6 6.5 ns
before RDCLKI
Reset: RESET low
before first WRTCLKI 7 S S S
and RDCLKlt:
PEN before WRTCLKI 4 5 5 5
DO-DS after WRTCLKI 0 0 0 0
WRTEN1, WRTEN2
0 0 0 0
after WRTCLKI
OE, RDEN1, RDEN2
0 0 0 0
after RDCLKI

Hold time Reset: RESET low after

th ns
fourth WRTCLKI and 5 5 5 5
RDCLKI:I:
PEN high after
0 0 0 0
WRTCLK!
PEN low after
3 3 3 3
WRTCLKI
TA Operating free-air temperature 0 70 0 70 0 70 0 70 °c
..
:I: To permit the clock pulse to be utilized for reset purposes

"!/} TEXAS
INSTRUMENTS
4-12 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7807
2048x9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200B - JANUARY 1991 - REVISED JULY 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VOH VCC = 4.5 V, IOH =-8mA 2.4 V
IFlags VCC=4.5 V, IOL= 8 mA 0.5
V
VOL
IQoutputs VCC =4.5 V, IOL= 16 mA 0.5
II VCC =5.5V, VI =VCcorO ±5 IlA
IOZ VCC = 5.5 V, Vo =VCC orO ±5 !lA
ICC VCC = 5.5 V, VI = VCC - 0.2 V or 0 400 IlA
I WRTEN1/DP9 VCC =5.5 V, One input at 3.4 V, Other inputs at VCC or GND
2
mA
lIICC:t:
I Other inputs 1
Ci VI =0, 1= 1 MHz 4 pF
Co VO=O, 1= 1 MHz 8 pF
t All typical values are at VCC = 5 V, TA = 25°C.
:t: This is the supply current lor each input that is at one 01 the specified TTL voltage levels rather 0 V or V cc.

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 50 pF (unless otherwise noted) (see Figures 9 and 10)
FROM TO 'ACT7807-15 'ACT7807-20 'ACT7807-25 'ACT7807-40
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYPt MAX MIN MAX MIN MAX MIN MAX
WRTCLKor
Imax 67 50 40 25 MHz
RDCLK
tpd 3 9 12 3 13 3 18 3 25
RDCLKT AnyQ ns
tpd§ 8
tpd WRTCLKI IR 1 9 1 12 1 14 1 16 ns
too RDCLKI OR 1 9 2 12 2 14 2 16 ns
WRTCLKI 2 16 2 20 2 25 2 30
tpd AF/AE ns
RDCLKI 2 17 2 20 2 25 2 30
tpLH WRTCLKI 2 19 2 21 2 23 2 25
HF ns
tpHL RDCLKI 2 16 2 18 2 20 2 22
tpLH AF/AE 1 12 1 18 1 22 1 24
RESET low ns
tpHL HF 2 12 2 18 2 22 2 24
ten 2 10 2 13 2 15 2 18
OE AnyQ ns
tdis 1 11 1 13 1 15 1 18
t All typical values are at VCC = 5 V, TA = 25°C.
§ This parameter is measured with CL = 30 pF (see Figure 5).

operating characteristics, Vee = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF. I = 5 MHz

"!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4-13
SN74ACT7807
2048 x 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200B - JANUARY 1991 - REVISED JULY 1995

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME

vs
LOAD CAPACITANCE
typ + 8
VCC=SV
./
- RL=SOOQ
III
C
TA = 2SoC
/'"
.
E
I
typ+ 6

/
,/
i=

~
>-
typ+4 /
Q
c
0
/
~ V
..
CD typ + 2
Co
2
0-
/
I
"C
_Co typ
I
/
I
typ -2
o so 100 1S0 200 2S0 300

CL - Load Capacitance - pF

Figure 5

ACTIVE Icc
vs
FREQUENCY
200
I
180 I- TA = 2Soe L
160
Vee = S.S V
V ...
< 140
/ V
/ V /
E
I Vce=SV ~
0 120
9
~ 100 /~V
t;
< 80
~V
~V
I
Vee = 4.S V
e:
0 60
9
40 ~ V
20

o
o '"
10 20 30 40
f - Frequency - MHz
SO 60 70

Figure 6

~TEXAS
INSTRUMENTS
4-14 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7807
2048 x 9
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS200B- JANUARY 1991 - REVISED JULY 1995

TYPICAL CHARACTERISTICS

calculating power dissipation

With ICC(f) taken from Figure 6, the maximum power dissipation (PT) of the SN74ACT7807 can be calculated
by:
PT = VCC x [ICC(f) + (N x t.lcc x dc)] + E (CL x VCc2 x fo)
A more accurate power calculation based on device use and average number of data outputs switching can be
found by:
PT = VCC x [ICC(I) + (N x ~Icc x dc)] + E (Cpd x VCc 2 x fi) + E (CL x VCC2 x fo)
where:
ICC(I) = idle Icc maximum (see Figure 7)
N number of inputs driven by a TTL device
~ Icc = increase in supply current
dc duty cycle of inputs at a TTL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
fi data input frequency
fo data output frequency
6,------,,------,-------,,------,-------,-------,-------,
....- Vee=4.5V
___ Vee=5V
5
""'*- Vee = 5.5 V
TA =25°
<C
E 4
I
0
_0
CD 3
:§
I

0
~ 2

o~------~------~------~------~------~------~----~
o 10 20 30 40 50 60 70
f - Frequency - MHz

Figure 7. SN74ACT78071dle Icc With WRTCLK Switching,

Other Inputs at 0 or V cc - 0.2 V and Outputs Disconnected

-!!I TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 4-15
SN74ACT7807
2048 x 9
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS200B - JANUARY 1991 - REVISED JULY 1995

APPLICATION INFORMATION
CLOCK

WRTCLK
WRTEN1
SN74ACT7S07
WRTCLK
WRTEN1/0P9
ROCLK
OR
1 WRTCLK
WRTEN1/0P9
SN74ACT7S07
ROCLK
ROEN1
ROCLK
ROEN1
WRTEN2 WRTEN2 ROEN1 L WRTEN2 ROEN2 RDEN2
IR IR ROEN2 l IR OR OR
OE - 5 V OE OE

DO-OS DO-OS QO-QS DO-OS QO-QS QO-QS

Figure 8. Word-Depth Expansion: 4096 Words by 9 Bits

SN74ACT7807
WRTCLK WRTCLK ROCLK ROCLK
WRTEN WRTEN1/0P9 ROEN1 ROEN
WRTEN2 ROEN2

~
IR OR
OE OE

09-017 DO-OS QO-QS Q9-Q17

IR
-0- I--<
'--- >
SN74ACT7S07
WRTCLK ROCLK
D- OR

WRTEN1/0P9 ROEN1 - -
WRTEN2 ROEN2
IR OR
OE -
~O-OS DO-OS QO-QS QO-QS

Figure 9. Word-Width Expansion: 2048 Words by 18 Bits

~1ExAs
INSTRUMENTS
4-16 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7807
2048 x 9
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS200B-JANUARY 1991 - REVISED JULY 1995

PARAMETER MEASUREMENT INFORMATION

From Output
Under Test ~
Input -A
~L''''C 1 T
I
14- tpd~
CL'"''
Output _ _ _ _- J II
lOAD CIRCUIT TOTEM·POlE OUTPUTS

Figure 10. Standard CMOS Outputs (IR, OR, HF, AF/AE)

7V Input ~ ... v \ ;.~---::

l
S1
Rl= R1 = R2

R1
tpZl -.: it PLZ -.J ~
__,~,

lP
- ' , "'3.5 V
From Output ---.--il.---,-- Test
Under Test Point Output '\1.5V
'.
R2 , tpHZ -.I. - - . - VOL
1+ L 0.3 V

Output
tpZH -+I i '_{-=--:.
0.3 V
VOH

lOAD CIRCUIT
VOLTAGE WAVEFORMS

PARAMETER R1, R2 clt S1

I tpZH Open
ten 5000 50pF
tpZL Closed
I tPHZ Open
Ictis 5000 50pF
tpLZ Closed
tpd 5000 50pF Open
t Includes probe and test fixture capacitance

Figure 11. 3·State Outputs (Any Q)

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4-17
4-18
 SN74ACT7808
2048 X 9
STROBED FIRST·IN, FIRST·OUT MEMORY
SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995

• Load Clocks and Unload Clocks Can Be • Expansion Logic for Depth Cascading
Asynchronous or Coincident • Empty, Full, and Half-Full Flags
• 2048 Words by 9 Bits • Fall-Through Time of 20 ns Typ
• Low-Power Advanced CMOS Technology • Data Rates From 0 to 50 MHz
• Fast Access Times of 15 ns With a 50-pF • 3-State Outputs
Load
• Available in 44-Pin PLCC (FN),
• Programmable Almost-FuIl/Almost-Empty Space-Saving 64-Pin Thin Quad Flat (PM),
Flag and Reduced-Height 64-Pin Quad Flat
(PAG) Packages

description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7808 is a 2048-word by 9-bit FIFO designed for high speed and fast access times.
It processes data at rates up to 50 MHz and access times of 15 ns in a bit-parallel format.
Data is written into memory on a low-to-high transition at the load-clock (LOCK) input and is read out on a
low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked
in exceeds the number of words clocked out by 2048. When the memory is full, LOCK signals have no effect
on the data residing in memory. When the memory is empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and
aimost-fuil/aimost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the
memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF
output is high when the FI FO contains 1024 or more words and is low when it contains 1023 or less words. The
AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LOCK after reset can
be used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable
(PEN) is low. The AF/AE flag is high when the FIFO contains X or less words or (2048 - Y) or more words. The
AF/AE flag is low when the FIFO contains between (X + 1) and (2047 - Y) words.
A low level on the reset (RESET) input resets the internal stack pointers and sets FULL high, AF/AE high, HF
low, and EMPTY low. The Q outputs are not reset to any specific logic level. The FI FO must be reset upon power
up.
The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs.
It is important to note that the first word does not have to be unloaded. Data outputs are non inverting with respect
to the data inputs and are in the high-impedance state when the output-enable (OE) input is low. OE does not
affect the output flags.
Cascading is easily accomplished in the word-width and word-depth directions. When not using the FIFO in
depth expansion, cascade enable (CAS EN) must be tied high.
The SN74ACT7808 is characterized for operation from O°C to 70°C.

Copyright © 1995. Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4-19
SN74ACT7808
2048x9
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205B - FEBRUARY 1991- REVISED SEPTEMBER 1995

FNPACKAGE
(TOP VIEW)

6 5 4 3 2 1 444342 41 40
00 7 3 ~
01 8 3 Vee
~ 9 3 ~
GNO 10 3 Q3
03 11 3 GNO
04 12 3 Q4
05 13 3 Vee
Vee 14 3 Q5
06 15 Q6
07 16 GNO
08 17 2 Q7
1819202122232425262728

PAG OR PM PACKAGE
(TOPVIEWj

~~~~~W~~~~~~~~WG
NC 48 NC
1 •
QO 2 47 Q8
GNO 3 46 Vee
GNO 4 45 Vee
OE 5 44 UNCK
xo 6 43 CASEN
Vee 7 42 NC
Vee 8 41 FL
RESET 9 40 EMPTY
PEN 10 39 FULL
GNO 11 38 XI
GNO 12 37 OP9
AF/AE 13 36 LOCK
HF 14 35 GNO
Vee 15 34 GNO
Vee 16 33 NC
1718192021 2223242526272829303132

OO~(\JClClM'<tOIll oo(oI'-COO
Z Cl Cl Cl Z Z Cl Cl Z Cl 0 oCl Cl Cl Z
~~ »
Ne - No internal connection

~TEXAS
INSTRUMENTS
4-20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7808
2048 x 9
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205B- FEBRUARY 1991 - REVISED SEPTEMBER 1995

logic symbolt

CI>
FIFO 2048 x 9
SN74ACT7808
1 22
RESET "- RESET
FULL FULL
19 5
LOCK LOCK HALF FULL HF
26 4
UNCK UNCK ALMOST FULUEMPTY AF/AE
42 23
OE EN1 EMPTY EMPTY
2
PEN "- PROGRAM ENABLE
24 43
FL "- FIRST LOAD EXPANSION OUT XO
25
CASEN
21
'" CASCADE ENABLE

XI EXPANSION IN
20
OP9
.,
DATA PIN 9

r
7 40
00 0 0 QO
8 39
01 Q1
9 37
02 Q2
11 36
03 Q3
04
12
13
~ ~1V 34
32
Q4
05 Q5
15 31
06 Q6
16 29
07 Q7
17 28
08 8 8 Q8

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the FN package.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265 4-21
SN74ACT7808
2048 x 9
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995

functional block diagram

OE

00-08

J
Location 1
Read ~ Location 2
UNCK Pointer r-----v
I-+-
1 2048x9 RAM
T

LOCK Write
I ~
Pointer
r--
r-----v Location 2047
Location 2048

OP9

I
l ,I'
JI QO-Q8

'---

I Reset
Logic
r-
I Expansion
EMPTY

FULL
and
Status- HF
Flag
Logic AF/AE

XO

~TEXAS
INSTRUMENTS
4-22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7808
2048 x 9
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205B- FEBRUARY 1991 - REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME
Aimost-fuil/almost-emptyflag. Depth-offset values can be programmed for AF/AE or the default value of 256 can be used
AF/AE 0 for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains X or less words
or (2048 - Y) or more words. AF/AE is high after reset.
Cascade enable. When multiple SN74ACT7808 devices are depth cascaded, every device must have CASEN tied low.
CASENt I
CASEN must be tied high when a device is not used in depth expansion.
DO-D8 I Nine-bit data input port
DP9 I DP9 is used as the most significant bit when programming the AF/AE offset values.
EMPTY 0 Empty flag. EMPTY is low when the FIFO memory is empty. A FIFO reset also causes EMPTY to go low.
First load. When multiple SN74ACT7808 devices are depth cascaded, the first device in the chain must have its FL input
ITt I
tied low and all other devices must have their IT inputs tied high.
FULL 0 Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF 0 Half-full flag. HF is high when the FIFO memory contains 1024 or more words. HF is low after reset.
LDCK I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
OE I Output enable. When OE is low, DO-DB are in the high-impedance state.
Program enable. After reset and before the first word is written to the FIFO, the binary value on DO- 08 and DP9 is latched
PEN I
as an AF/AE offset value when PEN is low and LDCK is high.
00-08 0 Nine-bit data output port
RESET I Reset. A low level on RESET resets the FIFO and drives FULL and AF/AE high and HF and EMPTY low.
UNCK I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.
Xlt I Expansion input (XI) and expansion output (XO). When muttiple SN74ACT7BOB devices are depth cascaded, the XO
of one device must be connected to the XI of the next device in the chain. The XO of the last device in the chain is
xot 0 connected to the XI of the first device in the chain.
t See Figures 5 and 6 for application information on FIFO word-width and word-depth expansions, respectively.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 4-23
SN74ACT7808
2048x9
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205B - FEBRUARY 1991 -REVISED SEPTEMBER 1995

offset values for AF/AE

The aimost-fuli/almost-empty flag has two programmable limits: the almost-empty offset value (X) and the
almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written
to memory. If the offsets are not programmed, the default values of X =Y =256 are used. The AF/AE flag is
high when the FIFO contains X or less words or (204B - Y) or more words.
To program the offset values, program enable (PEN) can be brought low after reset only when LOCK is low. On
the following low-ta-high transition of LOCK, the binary value on ~O-DB and OP9 is stored as the almost-empty
offset value (X) and the almost-full offset value (Y). Holding PEN low for another low-to-high transition of LOCK
reprograms Y to the binary value on ~O-DB and OP9 at the time of the second LOCK low-to-high transition.
Writes to the FIFO memory are disabled while the offsets are programmed. A maximum value of 1023 can be
programmed for either X or Y (see Figure 1). To use the default values of X = Y = 256, PEN must be held high.

' __---'I
LOCK

00-08 ~ XandY X~_Y-----JX,--_ __

OP9 ~ XandYMSB X'--_Y_M_S_B_..JX"'-_ _ _ _ _- -

Figure 1. Programming X and Y Separately

~1ExAs
INSTRUMENTS
4-24 POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
 SN74ACT7808
2048 x 9
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995

w
I~
Ii ~
g
I
o 8I
8 Ii

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4-25
SN74ACT7808
2048 x 9
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee ................. , ........................................ -0.5 V to 7 V
Input voltage, VI ........................................................................... 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. ooe to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

'ACT7808-20 'ACT7808-25 'ACT7808-30 'ACT7808-40
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V
XI 3.S5 3.S5 3.S5 3.S5
VIH High-level input voltage V
Other inputs 2 2 2 2
VIL Low-level input voltage O.S O.S O.S O.S V
IOH High-level output current -S -S -S -8 mA
Q outputs 16 16 16 16
IOL Low-level output current mA
Flags 8 8 8 8
fclock Clock frequency 50 40 33.3 25 MHz
LOCK high or low S 9 11 13
UNCK high or low 8 9 11 13
tw Pulse duration ns
PEN low 9 9 11 13
RESET low 10 13 16 19
00- 08, OP9 before
5 5 5 5
LOCK!
tsu Setup time LOCK inactive ns
5 5 5 5
before RESET high
PEN before LOCK! 5 5 5 5
00- OS, OP9 after
0 0 0 0
LOCK!
LOCK inactive after
5 5 5 5
th Hold time RESET high ns
PEN low after LOCK! 4 4 4 4
PEN high after LOCK
0 0 0 0
low
TA Operating free-air temperature 0 70 0 70 0 70 0 70 'C

~TEXAS
INSTRUMENTS
4-26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7808
2048 x 9
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VOH VCC=4.5 V, IOH =-8mA 2.4 V
I Flags VCC=4.5 V, IOL=8 mA 0.5
V
VOL
IQ outputs VCC=4.5 V, IOL= 16 mA 0.5
II VCC=5.5 V, VI =VCCorO ±5 IJ.A
IOZ VCC=5.5 V, VO=VCC orO ±5 ~A

ICC VCC=5.5 V, VI=VCC-0.2VorO 400 ~

<lICC:!: VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GNO 1 mA
Ci VI = 0, 1= 1 MHz 4 pF
Co VO=O, 1= 1 MHz 8 pF
t All typical values are at V CC = 5 V, TA = 25'C.
:j: This is the increase in supply current lor each input, excluding XI, that is at one 01 the specified TTL voltage levels rather 0 V or V CC.

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 50 pF (unless otherwise noted) (see Figures 7 and 8)
FROM TO 'ACT7808-20 'ACT7808-25 'ACT7808-30 'ACT7808-40
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYPt MAX MIN MAX MIN MAX MIN MAX
Imax LOCK or UNCK 50 40 33.3 25 MHz
LOCKi 5 20 5 22 5 25 5 28
tpd
AnyQ 4.5 11 15 4.5 18 4.5 20 4.5 22 ns
UNCKi
tpd§ 10
tPLH LOCKi 4 15 4 17 4 19 4 21
UNCKi EMPTY 2 15 2 17 2 19 2 21 ns
tpHL
RESET low 2 16 2 18 2 20 2 22
tpHL LOCKi 4 15 4 17 4 19 4 21
UNCKi FULL 4 14 4 16 4 18 4 20 ns
tpLH
RESET low 2 18 2 20 2 22 2 24
LOCKi 2 16 2 18 2 20 2 22
tpd
UNCKi AF/AE 2 16 2 18 2 20 2 22 ns
tPLH RESET low 0 10 0 12 a 14 0 16
tPLH LOCKi 2 19 2 21 2 23 2 25
UNCKi HF 2 16 2 18 2 20 2 22 ns
tPHL
RESET low 2 12 2 14 2 16 2 18
tPLH UNCKi 2 11 2 13 2 15 2 17
XO ns
tpHL LOCKi 2 11 2 13 2 15 2 17
ten 1 10 1 12 1 14 1 16
OE AnyQ ns
tdis 1 9 1 11 1 13 1 15
ten XI high 3 13 3 15 3 17 3 19
AnyQ ns
tdis XOhigh 4 4 4 4
t All typical values are at VCC = 5 V, TA = 25°C.
§ This parameter is measured with CL = 30 pF (see Figure 3).

operating characteristics, Vee =5 V, TA =25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, 1= 5 MHz

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4-27
SN74ACT7808
2048x9
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME

vs
LOAD CAPACITANCE
typ + 8
VCC=5V .J'
f- RL=5OOQ
!
I
typ+6
TA=25°C /
G>
/
V
!>-
. typ+4 V
8c /
ia. typ+ 2
V
e
a..
/
I
"c:I
_0. typ If
/
I
typ -2 0
50 100 150 200 250 300

CL - Load capacitance - pF

FIgure 3

SUPPLY CURRENT
vs
CLOCK FREQUENCY
160
TA = 75°C
CL=OpF Vccl=5.5~ /
140
I _1_

oC 120
VCC=5V""\
/ /
/ ~/
E
I

~ 100

0
~

80
/ ~V
~
0.
~
II) 60 ~ ' / VCC= 4.5 V
,~
I V
s:
0 40
!:!
20
~
~
o
o 10 20 30 40 50 60 70 80
fclock - Clock Frequency - MHz

FIgure 4

~1ExAs .
INSTRUMENTS
4-28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7808
2048 x 9
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

calculating power dissipation

With ICC(f) taken from Figure 4, the maximum power dissipation (PT) of the SN74ACT7808 can be calculated
by:
PT = VCC x [ICC(f) + (N x tl.lcc x dc)] + :E (CL x VCc 2 x fa)
A more accurate power calculation based on device use and average number of data outputs switching can be
found by:
PT = VCC x [Icc + (N x tl.1cc x dc)] +:E (Cpd x Vcc 2 x fi) +:E (CL x Vcc 2 x fa)
where:
ICC power-down IcC maximum
N number of inputs driven by a TTL device
tl.lcc = increase in supply current
dc duty cycle of inputs at a TTL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
fi data input frequency
fa data output frequency

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4-29
SN74ACT7808
2048 x 9
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION

SN74ACT7B08
LOCK LOCK UNCK UNCK

FULL EMPTY

OE OE

09-017 ~O-DB QO-QB Q9-Q17

CASEN

SN74ACT7BOB
'--- > LOCK UNCK

FULL EMPTY - r---

OE -
~O-DB / DO -DB QO-QB QO-QB
CASEN

Figure 5. Word-Width Expansion: 2048 Words by 18 Bits

~TEXAS
INSTRUMENTS
4-30 POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
 SN74ACT7808
2048 x 9
STROBED FIRST-IN, FIRST·OUT MEMORY
SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION

depth cascading (see Figure 6)

The SN74ACT7808 provides expansion logic necessary for cascading an unlimited number of the FIFOs in
depth. CASEN must be low on all FIFOs used in depth expansion. FL must be tied low on the first FIFO in the
chain; all others must have FL tied high. The expansion-out (XO) output of a FIFO must be tied to the
expansion-in (XI) input of the next FIFO in the chain. The XO output of the last FIFO is tied to the XI input of
the first FIFO to complete the loop. Data buses are common to each FIFO in the chain. A composite EMPTY
and FULL signal must be generated to indicate boundary conditions.

OE

IL IL IH L I H IL
FL CASEN FL CASEN FL CASEN

SN74ACT7S0S SN74ACT7S0S SN74ACT7S0S

- XI XO XI XO XI XO -
'--- RESET OE - - RESET OE r-- '-- RESET OE -
r-- DO-Dsao-as - !"'"- DO-Dsao-as ~
9
~ DO-Dsao-as
- 9
r- p.LDCK.-:: - p.LDCK .::=. r - - p.LDCK .::=.
9 UNCK 9 UNCK 9 UNCK

FULL EMPTY FULL EMPTY FULL EMPTY

~ ~
DO-OS
9
'" 9 '" 9
ao-as

UNCK
LOCK

---p
- t:: ~
:]
~

Figure S. Depth Cascading to Form a SK x 9 FIFO

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 4-31
SN74ACT7808
2048 x 9
STROBED FIRST-IN, FIRST·OUT MEMORY
SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

From Output Inpul-A

Under Test ~
RL =500 0 1 T= CL 50 pF
I
14- tpd~

-- --
Output _ _ _---J
I'
LOAD CIRCUIT TOTEM·POLE OUTPUTS

Figure 7. Standard CMOS Outputs (XO, EMPTY, FULL, AF/AE, HF)

S1
7V

l RL =R1 =R2
Input ~,5Y
tPZL --.II I~PLZ
\ ~5~---::
~rl I~
R1
----;1..,. I I I '" 3.5 V
I. -JLI
From Output _-*_ ___.>---,...-- Test
Under Test Point Output
I ". 1.5V
I -I- VOL
R2 I tpHZ -+I 1+ L 0.3 V
tpZH -+I!+- I ~
I -- VOH
Output
-f:--
0.3 V
"'---"'OV
LOAD CIRCUIT
VOLTAGE WAVEFORMS

PARAMETER R1, R2 CLt S1

~
Open
ten 5000 50pF
tpZL Closed

~
Open
tdis 5000 50pF
tpLZ Closed
tpd 5000 50pF Open
t Includes probe and test fixture capacitance
Figure 8. 3·State Outputs (Any Q)

~lEXAS
INSTRUMENTS
4-32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I 8- and 9-Bit Asynchronous FIFOs

5-1
 8· AND 9·BIT ASYNCHRONOUS FIFOS
Features Benefits

• Multiple-speed sort options • Design flexibility

• Depth from 256 to 4K words • Optimize depth for specific application
• Fast data-access time of 15 ns • Increased system performance
• Bit-width and word-depth expandable • Allows interface to larger and deeper data
paths
• Empty, full, and half-full flags • Multiple status flags to ease design efforts
• Compatible to 720x pinout • Drop-in replaceable to existing layouts
and designs
• TI has established an alternate source • Standardization that comes from a
common-product approach

5-2
 SN74ALS2238
32 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL
FIRST·IN, FIRST·OUT MEMORY

• Independent Asychronous Inputs and NPACKAOE

Outputs croP VIEW)

• Bidirectional RS'i'A RSTB

• 32 Words by 9 Bits OAF OBF
• Programmable Depth BO
• Data Rates from 0 to 40 MHz A1 B1
A2 B2
• Fall-Through Time .•. 22 ns Typ
GNO 6 GNO
• 3-State Outputs A3 B3
A4 B4
description
AS 9 B5
This 576-bit memory uses advanced low-power A6 10 31 B6
Schottky IMPACT-)(TM technology and features GNO 11 GNO
high speed and fast fall-through times. It consists Vee 12 Vee
of two FIFOs organized as 32 words by 9 bits A7 13 28 B7
each. A8 14 27 B8
LOCKA 15 26 LOCKB
. A FIFO memory is a storage device that allows
data to be written into and read from its array at FOlIA 25 FULLB
independent data rates. These FIFOs are UNCKB UNCKA
designed to process data at rates from 0 to 40 EMJ5'i'YB EMPTYA
MHz in a bit-parallel format, word by word. SAB SBA
GAB GBA
The SN74ALS2238 consists of bus-transceiver
circuits, two 32 x 9 FIFOs, and control circuitry
arranged for multiplexed transmission of da~ FNPACKAGE
(TOP VIEW)
directly from the data bus or from the internal FIFO
memories. Enables GAB and GBA are provided to
control the transceiver functions. The SAB and
SBA control pins are provided to select whether
real-time or stored data is transferred. The 6 5 4 3 2 1 44 43 42 41 40 B2
circuitry used for select control eliminates the 7 39
typical decoding glitch that occurs in a multiplexer 8 38 ~~~
during the transition between stored and real-time 37 B3
data. A low level selects real-time data and a high 10 36 B4
selects stored data. Eight fundamental 11 35
bus-management functions can be performed as 12 34 :
shown in Figure 1. ~:: GNO
Data on the A or B data bus, or both, is written into 15 31 Vee
the FIFOs on a low-ta-high transition at the load 16 30 B7
clock (LOCKA or LOCKB) input and is read out on 17 29 B8
a low-to-high transition at the unload clock 18 19 20 21 22232425262728
~ < <
(UNCKA or UNCKB) input. The memory is full
when the number of words clocked in exceeds, by
the defined depth, the number of words clocked
04:
I~ ~ Ii: ~ ~ ~ ml ~
i! ~ == ~
ClJ !cC
51< i!~ 59
~
ClJ ClJ

~ w w
When the memory is full, LOCK signals have no effect on the data residing in memory. When the memory is
empty, UNCK signals have no effect.

IMPACT-X is a trademark of Texas Instruments Incorporated.

Copyright C 1990, Texss InstrumentS Incorpora1ed

~1ExAs
INSTRUMENTS
POST OFFICE BOX 856303 • DALLAS. TEXAS 75265
SN74ALS2238
32 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL
FIRST-IN, FIRST-OUT MEMORY
SOAS 182 - APRI L 1990

description (continued)
Status of the FIFO memories is monitored by the FULLA, FULLB, EMPTYA, and EMPTYB output flags. The
FULLA and FULLB are definable full flags. A high-to-Iowtransition on OAF stores the binary value of AO through
A4 into a register for use as the value of X. A high-to-Iow transition on OBF stores the binary value of BO through
B4 into a register for use as the value of Y. In this way, the depth of either FIFO can be defined to be one to
32 words deep. The value of X and Y must be defined after power up or the stored value of X and Y will be
ambiguous. The FULLA and FULLB outputs are low when their corresponding memories are full and high when
the memories are not full.
The EMPTYA and EMPTYB outputs are low when their corresponding memories are empty and high when they
are not empty. The status flag outputs are always active.
A low-level pulse on the RSTA or RS'f'B inputs resets the control pointers on FIFO A or FIFO B and also sets
EMPTYA low and FULLA high or EMPTYB low and FULLB high. The outputs are not reset to any specific logic
levels. With OAF at a low level, a low-level pulse on RSTA sets FIFO A to a depth of 32 - X, where X is the value
stored above. With OAF at a high level, a low level pulse on RSTAsets FIFO A to a depth of 32 words. The depth
of FIFO B is set in a similar manner. The first low-to-high transition on LOCKA or LOCKB, either after a reset
pulse or from an empty condition, will cause EMPTYA or EMPTYB to go high and the data to appear on the
Q outputs. It is important to note that the first word does not have to be unloaded. Cascading is easily
accomplished in the word-width direction, but is not possible in the word-depth direction.
The SN74ALS2238 is characterized for operation from O°C to 70°C.

logic symbolt
<I>
FIFO

SBA
22
19
o}
1 MODE
32x9x2
SN74ALS2238
SAB
20
GAB ENl
21
GBA EN2
1 "- RESET A 40
RSTA RESET B /1 RSTB
OAF 2 39
'" OEF A FULL OEFB FULL 'A OBF
15 26
LOCKA LOCKA LOCKB LOCKB
24 17
UNCKA UNCKA UNCKB UNCKB
18 25
FULLA FULLA FULLB FULLB
23 18
EMPTYA
3
,EMPTYA EMPTYB
I'"
38
EMPTYB

AO 0 0 BO
4 37
Ai Bl
5 36
A2 B2
7 34
A3 B3
8 33
A4
A5
9 \7~~\7 32
B4
B5
10 31
A6 B6
13 28
A7 B7
14 27
A8 8 8 B8

t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the N package.

~lExAs
INSTRUMENTS
5-4 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS2238
32 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL
FIRST·IN, FIRST·OUT MEMORY
SDAS182-APAIL 1990

logic diagram (positive logic)

19
SAB

1 ~
SBA
22
"" --/
I Ln
-- <l>
FIFOB k1 40
RSTB
32x9
L-1 39
18 OBF
EMPTYB 25
26 FULLB
17
UNCKB

21
,..----------.,
I i
.., r 38
LOCKB

Q 0 BO
GBA ! I I
I I
II -.!
r---r-"
L __
lOne of_ __
Nine _ _ _ _ _ .JI
Channels

To Other Channels

20
GAB
<l>

RSTA
1 r-...
FIFO A
32x9
I
2 r-...
OAF
16 23 EMPTYA
FULLA
15 24
LOCKA
.., r
UNCKA

r~I
3 Q
AO 0
I I
I I
Ii I I
L-=.2!!!!~~n!.~=~J
To Other Channels

Pin numbers shown are for the N package.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-5
SN74ALS2238
32x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL
FIRST-IN, FIRST-OUT MEMORY
SDAS182-APRI.L 1990

BusA BusB BU8A BU8B

SAB SBA GAB GBA SAB SBA GAB GBA

L X H L X X L L

Bus A BU8B BU8A BU8B

SAB SBA GAB GBA SAB SBA GAB GBA

X L L H H L H H

BU8A BusB BU8A BusB

SAB SBA GAB GBA SAB SBA GAB GBA

H X H L L H H H

BU8A BU8A BusB

BU8B

SAB SBA GAB GBA SAB SBA GAB GBA

X H L H H H H H

Figure 1. Bus-Management Functions

~1ExAs .
INSTRUMENTS
5-6 POST OFFICE BOX 1155303 • DAUAS. TEXAS 75265
 timing diagram for FIFO At

RSTA -I ------ -----y

I ,
DAF " ~nttc;r:NV\NVVV\N?
~XYXyy)~ II
.
~
~xxxxx~
I I
I I
~ rll---------
LDCKA
I
I
AO-A8 Don't care
I
(3 I
'"-t I
~~I II ~I.
UNCKA

~~ ~ rSl-
I I
i~;;I I QO-Q8
ID1iiUi@X W1 ~~;;Jil2SX W1 ~~
~~~
F=l'I'J
I
I
. I
I
I
I
Co)
I\:)

III X
i~ EMPTYA I I CO
I I I
I I I X
I\:)
'" I I I
»
~ • FULLA
II II L-J ~
:!!Z
Deplh Set 10 Default (32) Load X Into Depth Reglster:t: Depth Sello 32 - X ::z:JO
(/)::J:
t Operation of FIFO B is identical to that of FIFO A. -;-I::z:J
-0
:t: X includes AO through A4 only. A5 through A8 are ignored. _ZZ
-nO
-c:
::z:J(/)
~2!
"'OO(/)
!i!c:-Z
~-I~"""
~s::ot
l>m::::!r-
jJ s:: 0 (/)
;= 0 Z I\:)
;;;::z:J»~
~ 8 -< r- (X)
SN74ALS2238
32 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL
FIRST-IN, FIRST-OUT MEMORY
SDAS182-APRIL 1990

SELECT·MODE CONTROL TABLE

CONTROL OPERATION
SAB SBA A BUS BBUS·
L L Real-time B to A bus Real-time A to B bus
L H FIFO B to A bus Real-time A to B bus
H L Real-time B to A bus FIFO A to B bus
H H FIFO B to A bus FIFO A to B bus

OUTPUT-ENABLE CONTROL TABLE

CONTROL OPERATION
GAB GBA ABUS BBUS
H H A bus enabled B bus enabled
L H A bus enabled Isolation/input to B bus
H L Isolationlinput to A bus B bus enabled
L L Isolation/ input to A bus Isolation/input to B bus

programming procedure for depth of FIFO At

Program:
Step 1. With RSTA at a high level, take OAF from a high level to a low level. The high-to-Iow transition on
OAF stores the binary value of AO-A4 for use as the value of X in defining the depth of FIFO A.
Step 2. With OAF held low, pulse the RSTA signal low. On the low-Io-high transition of RSTA, FIFO A is set
to a depth of 32 - X, where X is the value of AO-A4 stored above.
Step 3. To redefine the depth of FIFO A to 32 words, hold OAF at a high level and pulse the RSTA signal low.
t The programming procedures used to define the depth of FIFO B are the same as the procedure above.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted):!:
Supply voltage, Vee ............................................................... -0.5 V to 7 V
Input voltage: Control inputs ................................................................ 7 V
I/O ports .................................................................... 5.5 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Maximum junction temperature .................................................... :....... 150°C
:t: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

~TEXAS
INSTRUMENTS
5-8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ALS2238
32 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL
FIRST-IN, FIRST-OUT MEMORY
SDAS182-APRIL 1990

recommended operating conditions (see Note 1)

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
A or B ports -15
IOH High-level output current rnA
Status flags -0.4
A or B ports 24
IOL Low-level output current rnA
Status flags 8
LDCKA or LDCKB 0 40
fclock Clock frequency MHz
UNCKA or UNCKB 0 40
RSTA or RSTB low 17
LDCKA or LDCKB low 12.5
LDCKA or LDCKB high 10
tw Pulse duration ns
UNCKA or UNCKB low 12.5
UNCKA or UNCKB high 10
DAF or DBF high 10
Data before LDCKA or LDCKB1' 7
Define depth: D4-DO before DAF or DBFJ- 6
tsu Setup time Define depth: DAF or DBFJ- before RSTA or RSTB1' 45 ns
Define depth (32): DAF or DBF high before RSTA or RSTB1' 32
LDCKA or LDCKB (inactive) before RSTA or RSTB1' 5
Data after LDCKA or LDCKB1' 3
Define depth: D4-DO after DAF or DBF.J. 4
th Hold time Define depth: DAF or DBF low after RSTA or RSTB1' 0 ns
Define depth (32): DAF or DBF high after RSTA or RSTB1' 0
LDCKA or LDCKB (inactive) after RSTA or RSTB1' 5
TA Operating free-air temperature 0 70 DC
NOTE 1: To ensure proper operation of this high-speed FIFO device. it is necessary to provide a clean signal to the LDCKA or LDCKB and UNCKA
or UNCKB clock inputs. Any excessive noise or glitching on the clock inputs (which violates the VIL. VIH. or minimum pulse duration
limits) can cause a false clock or improper operation of the internal read and write pointers.

~ThXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-9
SN74ALS2238
32 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL
FIRST-IN, FIRST-OUT MEMORY
SDASl82-APRIL 1990

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VIK VCC =4.5 V, 11--18mA -1.2 V
Status flags VCC - 4.5 V to 5.5 V, 10H --O.4mA VCC-2
VCC-4.5V, IOH--2mA VCC-2
VOH V
A or B ports VCC-4.5V, IOH--3mA 2.4 3.2
VCC-4.5V, 10H --15mA 2
VCC=4.5V, 10L= 12 mA 0.25 0.4
AorB-ports
VCC=4.5V, IOL-24mA 0.35 0.5
VOL V
VCC-4.5V, IOL-4mA 0.25 0.4
Status flags
VCC-4.5V, IOL=8mA 0.35 0.5
OAF, OBF, RSTA, RSTB, GAB, GBA, SAB,
0.1
II SBA,LDCKA,LDCKB,UNCKA,UNCKB VCC-5.5V, VI_7V mA
AorBports 0.2
OAF, DBF, RSTA, RSTB, GAB, GBA, SAB,
20
SBA,LOCKA,LOCKB,UNCKA,UNCKB
IIH VCC-5.5V, VI=2.7V !IA
AorB ports; 40
DAF, DBF, RSTA, RSTB, GAB, GBA, SAB,
-0.2
IlL SBA,LCKA,LDCKB,UNCKA,UNCKB VCC=5.5V, VI = 0.4 V mA
A or B ports; -0.4
A or B ports; -20 -130
10§ VCC = 5.5 V, VO-2.25V mA
Status flags -15 -100
ICC VCC=5.5V 190 350 mA
t All typical values are at VCC = 5 V, TA = 25°C.
; For I/O ports, the parameters IIH and IlL include the offstate output current.
§ The output conditions have been chosen to produce a current that closely approximates one hall of the true short-circuit output current, lOS.

~1ExAs
INSTRUMENTS
5-10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75266
 SN74ALS2238
32 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL
FIRST·IN, FIRST·OUT MEMORY
SDAS182 - APRIL 1990

switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(see Figure 2)
CL=50pF,
FROM TO R1 = 500n,
PARAMETER R2=500n UNIT
PNPUT) (OUTPUT)
MIN TYPt MAX
f max LOCK, UNCK 40 MHz
LOCKAi,LOCKBi 7 22 33
tpd B,A ns
UNCKAi, UNCKBi 7 20 29
tpLH LOCKAi, LOCKBi 5 12 22
EMPTYA, EMPTYB ns
tpHL UNCKAi, UNCKBi 5 12 22
tpHL RSTM,RSTB,j, EMPTYA, EMPTYB 5 12 22 ns
tpHL LOCKAi, LDCKBi FULLA,FULLB 5 12 22 ns
UNCKAi, UNCKBi 5 12 23
tpLH FULLA, FULLB ns
RSTM,RSTB,j, 6 15 28
SAB,SBM 2 11 18
tpd B,A ns
!VB 2 8 15
ten GBA, GAB A,B 2 6 15 ns
tdis GBA,GAB A,B 1 5 12 ns
t All tYPical values are at VCC = 5 V, TA = 25°C.
:j: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-11
SN74ALS2238
32 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL
FIRST-IN, FIRST-OUT MEMORY
SDAS182-APRIL 1990

PARAMETER MEASUREMENT INFORMATION

7V SWITCH POSITION TABLE

l Open
TEST
tPLH
S1
Open
tpHL Open
tpZH Open
From Output --.----<__--41--- Test Point tPZL Closed
Under Test tPHZ Open
=
CL SOpF R2=soon tpLZ Closed
(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.SV

High-Level
Pulse ~ I I 0.3 V
~ tw----+l
Timing
Input
_ _ _..I.

tsu~th
t~3~ __ _ 3.SV

0.3 V Low-Level
Pulse
~1"'V ~
~~.~V_
I I
3.SV

0.3 V

Data ~~~-3.SV VOLTAGE WAVEFORMS

Input ~1.3V ~ PULSE DURATION
0.3 V
VOLTAGE WAVEFORMS

~~
SETUP AND HOLD TIMES 3'SV

Output 1.3 V 1.3 V

Control 1
Input - - - -- 3.S V tPZL ~ I+- 1----- 0.3V
(see Note B) L 1.3 V \ . 1.3 V
-+i 1+ tpLZ
--'i I. 0.3 V
1 1

tpLH~
1 Y ~tpHL
1 1- -
Waveform 1 i\:~-n~"V
I Ph
nOut~: 1 1.3V 1 \2:,v VOH S1 Closed
(see Note C) ,......if-=-:::~ VOL
-""""I-J 1 VOL 1 tPHZ -.l \+- 0.3 V
I_~, 1+--+1- tPLH tpZH -+I ~ 1 ...i
~I ~-
tPHL --I4--i'I 1
Waveform2 VO"
Out-ol·Phase ,I 1.3 V FV
1.3O
V H S10pen 1.3 V L.- 0.3 V
Output . . __ VOL (see Note C) _ _ _ _ _ _ OV

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY.TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, Zo = 50 n, tr S 2 ns, tf S 2 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.

Figure 2. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
5-12 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS2232A
64 x 8 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

• Independent Asynchronous Inputs and NT PACKAGE

Outputs (TOP VIEW)

• 64 Words by 8 Bits FiST 1 24 OE

• Data Rates From 0 to 40 MHz 00 2 23 00
• Fall-Through Time ••• 20 ns Typical 01 3 22 01
02 4 02
• 3-State Outputs 03 03
VCC GNO
description 04 7 04
This 512-bit memory uses advanced low-power 05 8 05
Schottky IMPACT-XTM technology and features 06 9 06
high speed and fast fall-through times. It is 07 07
organized as 64 words by 8 bits. FULL 11 EMPTY
LOCK UNCK
A FIFO memory is a storage device that allows
......_ - - '
data to be written into and read from its array at
FNPACKAGE
independent data rates. The function is used as a (TOP VIEW)
buffer to couple two buses operating at different
clock rates. This FI FO is designed to process data ~ol~owo
cc
~
a: zO 00
at rates from 0 to 40 MHz in a bit-parallel format,
word by word. 4321282726
025 0 25
Data is written into memory on a low-to-high 03 6 24
transition of the load clock (LOCK) input and is VCC 7 23
read out on a low-to-high transition of the unload NC 8 22
clock (UNCK) input. The memory is full when the 04 9 21
05 10 20
number of words clocked in exceeds by 64 the
06 11 19
number of words clocked out. When the memory 12 13 14 15 16 17 18
is full, LOCK signals have no effect on the data
residing in memory. When the the memory is
empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the NC - No internal connection
FULL and EMPTY output flags. The FULL output
is low when the memo~and high when the
memory is notfull. The EMPTY output is low when
the memory is empty and high when it is not
empty.
A low level on the reset (RST) Input resets the internal stack control pointers and also sets EMPTY low and FULL
high. The outputs are not reset to any specific logic levels. The first low-to-high transition on LOCK, either after
a RST pulse or from an empty condition, causes EMPTY to go high and the data to appear on the Q outputs.
The first word does not have to be unloaded. Data outputs are non inverting with respect to the data inputs and
are at a high-impedance state when the output-enable (OE) input is low. The OE input does not effect either
the FULL or EMPTY output flags. Cascading is easily accomplished in the word-width direction, but is not
possible in the word-depth direction.
The SN74ALS2232A is characterized for operation from O°C to 70°C.

IMPACT-X is a trademark of Texas Instruments Incorporated.

Copyright @ 1990. Texas Instruments Incorporated

~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5--13
SN74ALS2232A
64 x 8 ASYNCHRONOUS FIRST-IN, FIRST~OUT MEMORY
SCAS248- FEBRUARY 1988- REVISED MARCH 1990

logic symbolt

FIFO 64 x 8

1 11

12
" CT=O (CT = 64) G1

LOCK 1(+/C2)
13 14
UNCK 3- (CT = 0) 03

24
OE

2
,EN4
r 23
DO 20 4V QO
3 22
01 Q1
4 21
02 Q2
5 20
03 Q3
7 18
D4 Q4
8 17
05 Q5
9 16
06 Q6
10 15
07 Q7

t This symbol is in accordance with ANSIIIEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but does not
show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled by asingle counter
whose content is the number of words stored at the time. Output data Is invalid when the counter content (CT) is o.
Pin numbers shown are for the NT package.

~1ExAs
INSTRUMENTS
5-14 PQST OFFICE BOX 655303 • DA~LAS. TEXAS 75265
 SN74ALS2232A
64 x 8 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SCAS248 - FEBRUARY 1988 - REVISED MARCH 1990

logic diagram (positive logic)

24

--
OE
I
I ..........
_ j l Writ.

~
DECODE
Low LATCH
12
LOCK Cl ~C·CTRDIV8
.
8 PL :J:
CT=1 1-7 1PL 0-
<XI
8 ....
... ..!!.
l Hlah
CTRDIV8
EN1
8 PH
C1 0-

"
0-

1PH
po 1.
CT=1
R ••d
DECODE
RAM

.
Low LATCH
CTRDIV8 64x8
EN
13 QL
.:.:..
UNCK C2
20
- - CT=1 1-7
8 ....
8
1QL
.
:J:
g
...a
Q 44
1A1/64

2A1/64

- I
lEN1
Hlah
CTRDIV8
8 QH
C1

a"
- CO

1QH

RST
1
2
po 1.
CT=1
..., r-
00 lA,3D 2AV -B... QO
3 22
D1 Q1
02
4 -ll. Q2
5 ~ Q3
03 18
7
04 8 Q4
05 9 ---1!... Q5
06 -.!L Q6
10 --1L Q7
07
8
8
8
8

~ .,.."-:~:'~
~ "-
1
r--
P=Q

~
QL PL=QL-1
-R
CT;;::56
>--OR 11
-LJ FU
~PH
Hlah I
- -8
i..-

QH
COMP P H = Q P
PH=QH-1
PH=QH.1
- -
R
R
S
CT<8

-LJ - 14
E

Pin numbers shown are for the NT package.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-15
SN74ALS2232A
64 x 8 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS248 - FEBRUARY 1988 - REVISED MARCH 1990

timinig diagram

RST~

t8J'_
I
LOCLK I
---;.----.
00-07 ~ BS ~ t888&~in2~*mggs ~ ~?2
1 W2 W3 W1 W2 W63 W64
I I .
UNCK I I +I +I +I I
I I 1L..-...1~1

QO-Q7 «ili~a[(~ Word 1

I
EMPTY i II I
I
I I
W
Initialize Load Unload Empty Full
Pointers W1 W2

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) .................. II . II............ ....... .. ... . . ...... . .. .. 7 V
Input voltage .............................................................................. 7 V
Voltage applied to a disabled 3-state output ....................... ,.......................... 5.5 V
Operating free-air temperature range, TA ............................................. O°C to 70°C
Storage temperature range ............. II ....... II ....... II ... II . . . . . . . . . . . . . . . .. - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

~TEXAS
INSTRUMENTS
5-16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ALS2232A
64 x 8 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS248 - FEBRUARY 1988 - REVISED MARCH 1990

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
Q outputs -2.6
10H High-level output current mA
FULL, EMPTY -0.4
Qoutputs 24
10L Low-level output current mA
FULL, EMPTY 8
fclock Clock frequency LOCK, UNCK 0 40 MHz
RSTlow 25
LOCK low 13
tw Pulse duration LOCK high 12 ns
UNCK low 13
UNCKhigh 12
tsul Setup time, data before LOCK! 5 ns
tsu2 Setup time, RST high (inactive) before LOCK! 5 ns
th Hold time, data after LOCK! 5 ns
TA Operating free-air temperature a 70 °c

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP* MAX UNIT
VIK VCC=4.5 V, 11=-18mA -1.2 V
Q outputs VCC=4.5 V, 10H =-2.6 mA 2.4 3.2
VOH V
FULL, EMPTY VCC = MIN to MAX, 10H =0.4 mA VCC-2
10L= 12 mA 0.25 0.4
Q outputs VCC=4.5 V
IOL=24 mA 0.35 0.5
VOL V
10L = 4 mA 0.25 0.4
FULL, EMPTY VCC=4.5 V
10L = 8 mA 0.35 0.5
10ZH VCC = 5.5 V, Vo = 2.7 V 20 1IA
10ZL VCC=5.5V, Vo = 0.4 V -20 1IA
II VCC=5.5 V. VI =7V 0.1 mA
IIH VCC=5.5V, VI =2.7V 20 1IA
CLKs -0.2
IlL VCC=5.5V. VI = 0.4 V mA
Others -0.1
Qoutputs -20 -130
10§ Vce = 5.5 V, Vo = 2.25 V mA
FULL, EMPTY -20 -112
ICC Vce = 5.5 V 175 270 mA
.. shown as MIN or MAX, use the appropriate value specified
t For conditions .. under recommended operating conditions .
:j: All typical values are at VCC = 5 V, TA = 25°C.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.

~ThXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-17
SN74ALS2232A
64 x 8 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS248 - FEBRUARY 1988 - REVISED MARCH 1990

switching characteristics (see Figure 1)

Vcc = 5 V, Vcc = 4.5 Vto 5.5 V,
eL = 50 pF, CL=50pF,
FROM TO R1 = 500n, R1 = 500n,
PARAMETER R2=500n, R2= 500 n, UNIT
(INPUT) (OUTPUT)
TA = 25°e TA = ooe to 70 0 e
MAX TYP MAX MIN MAX
fmax LDCK, UNCK 40 MHz
LDCKI 18 26 30
tpd AnyQ ns
UNCKI 18 24 27
tpLH LDCKI 12 16 18
EMPTY ns
tpHL UNCKI 12 17 20
tpHL RSTJ. EMPTY 12 17 20 ns
tpHL LDCKI FULL 16 21 22 ns
UNCKI 10 15 18
tpLH FULL ns
RSTJ. 13 19 23
ten OEI Q 11 15 17 ns
tdis OEJ. Q 11 17 19 ns

~TEXAS
INSTRUMENTS
5-18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ALS2232A
64 x 8 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS248 - FEBRUARY 1988 - REVISED MARCH 1990

PARAMETER MEASUREMENT INFORMATION

7V
SWITCH POSITION TABLE

~ Open
TEST
tpLH Open
S1

tPHL Open
tpZH Open
From Output
Under Test
--.-----<e----....-- Test Point tPZL Closed
Open
tPHZ
CL=50pF R2=500n tPLZ Closed
(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V

High-Level
Pulse ~ I I 0.3V

~ tw--+i
3.5V I I
'~3~
Timing
3.5V
Input ___ Low-Level ~1"V ~
0.3 V Pulse ~~.~V_ O.3V
tsu~th

~
Data 3.5 V VOLTAGE WAVEFORMS
Input 1.3V 1.3V PULSE DURATION
0.3V
VOLTAGE WAVEFORMS

~~
SETUP AND HOLD TIMES 3'5V

Output 1.3 V 1.3 V

Control I
Input - - - - 3.5V tpZL ---.I i+" I- - - - - 0.3 V
(see Note B) .L 1.3 V \ . 1.3 V

~ I --~~r-=-
-/l I. 0.3 V
: tPLZ 3.5V
tPLH -i+--foI i+----+I-- tPH L Waveform 1 II 1.3V I I __ ..L.'L
I 1/ I 'i.I -:;.; VVoH S1 Closed
In-Phase
Output
---rl-J
I T 1.3V I C I VOL
(see Note C)
I tpHZ~ ~-L:~\
I _~, J+---+I-
I
tPLH tpZH -+I I+- I ...i _ _ VOH

~~c-
tpHL~

Out-of-Phase 1.3 V Y;; 1.3 V VOH

Waveform2
S1 Open 1.3 V 1:- 0.3 V
Output
" . . __ VOL (see Note C) _ _ _ _ _ _ OV

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR :5 1 MHz, Zo = 50 n, tr :5 2 ns, tf:5 2 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-19
5-20
 SN74ALS2233A
64 x 9 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY

• Independent Asynchronous Inputs and NPACKAGE

Outputs (TOP VIEW)

• 64 Words by 9 Bits OE
• Data Rates From 0 to 40 MHz 00
• Fall-Through Time ... 20 ns Typical 26 01
• 3-State Outputs 25 02
24 03
description 23 GNO
22 04
This 576-bit memory uses advanced low-power 05
21
Schottky IMPACT-X ™ technology and features
20 06
high speed and fast fall-through times. It is
07 07
organized as 64 words by 9 bits.
08 11 08
A FIFO memory is a storage device that allows AF/AE HF
data to be written into and read from its array at FULL EMPTY
independent data rates. The function is used as a LOCK UNCK
buffer to couple two buses operating at different
clock rates. This FIFO is designed to process data
at rates from 0 to 40 MHz in a bit-parallel format, FNPACKAGE
word by word. (TOP VIEW)

Data is written into memory on a low-to-high

transition of the load clock (LOCK) input and is
N,.. 0l~
ccca:OOO
W 0,..
read out on a low-to-high transition of the unload 4 321 28 2726
03 5 25 02
clock (UNCK) input.The memory is full when the 0
number of words clocked in exceeds by 64 the Vcc 6 24 03
number of words clocked out. When the memory 04 7 23 GNO
05. 8 22 04
is full, LOCK signals have no effect on the data
residing in memory. When the the memory is 06 9 21 05
empty, UNCK signals have no effect. 07 10 20 06
08 11 19 07
Status of the FI FO memory is monitored by the 12 1314 15 16 1718
FULL, EMPTY, aimost-fuil/aimost-empty (AF/AE),
and half-full (HF) output flags. The FULL output is
low when the memory is full and high when the
memory is not full. The EMPTY output is low when
the memory is empty, and high when it is not
empty. The AF/AE flag is high when the FIFO contains eight or less words or 56 or more words. The AF/AE flag
is low when the FIFO contains between nine and 55 words. The HF flag is high when the FIFO contains 32 or
more words and is low when the FIFO contains 31 words or less.
A low level on the reset (RST) input resets the internal stack control pointers and also sets EMPTY low and FULL
high. The outputs are not reset to any specific logic levels. The first low-to-high transition on LOCK, either after
a RST pulse or from an empty condition, causes EMPTY to go high and the data to appear on the Q outputs.
The first word does not have to be unloaded. Data outputs are non inverting with respect to the data inputs and
are at a high-impedance state when the output-enable (DE) input is low. The OE input does not effect either
the FULL or EMPTY output flags. Cascading is easily accomplished in the word-width direction, but is not
possible in the word-depth direction.
The SN74ALS2233A is characterized for operation from O°C to 70°C.

IMPACT-X is a trademark of Texas Instruments Incorporated.

Copyright © 1990.·Texas Instruments Incorporated

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-21
SN74ALS2233A
64 x 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS249 - FEBRUARY 1988 - REVISED MARCH 1990

logic symbolt

FIF064x9
17
CTR CT~32 HF
1 r-..
CT=O 12
CTS8/CT~56 AF/AE
14 13
LOCK 1(+/C2) (CT= 64)G1 FULL
15 16
UNCK 3- (CT=0)G3 EMPTY

OE

00
2
28

,
EN4

20 4V
r 27
QO
3 26
01 Q1
4 25
02 Q2
5 24
03 Q3
7 22
04 Q4
8 21
05 Q5
9 20
06 Q6
10 19
07 Q7
11 18
08 Q8

t This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but does not
show the details of Implementation; for these, see the logic diagram. The symbol represents the memory as if It were controlled by asingle counter
whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is O.

~1ExAs
INSTRUMENTS
5-22 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ALS2233A
64 x 9 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SCAS249 - FEBRUARY 1988 - REVISED MARCH 1990

logic diagram (positive logic)

28
OE

I -- L W,ItA

LOCK
14

4D
C1
- 1 ~/TRDIV8
Low

PL
DECODE
LATCH

..."
8 :I:
CT=1 1-7 1PL II;
8_
..!:.
Il High
CTRDIV8
EN1
8 PH
C1

1PH
oJ

1.
CT=1
Read
DECODE
Low LATCH RAM
64 x9
~:CTRDIV8 EN

. i!:..
15 • 8 QL
UNCK C2 :I: 1A 1164
2D
CT= 1 1- ~1-+-1 1QL
51 64
Q
2A 1164
oJ
C1 a
It Hlah a"
- C3
CTRDIV8 QH
EN1 8
1QH
1.
RST
1
CT.1 ..., r-
2 1A.3D 2A'V 27
DO QO
3 26
01 Q1
02
4
~ Q2
03
5
~ Q3
7 22
04 8 21
Q4
05 Q5
06
9
~ Q6
07 10
~ Q7
~ Q8
11
08
8
8
8
8

L LQw
PL COMP PL=QL
- 1
I
P=Q

-- ~ ~{y.
PL.QL.1
QL PL=QL-1 f----r\ 11
FU
: I ;:::- 12
J AFIAE

Hlah
~ ::{} ~,! - 16
EM PTY

~ -
""- PH COMP PH • QH
PH=QH-1
PH=QH.1 R

-
17
QH PH=QH.4
- -
R
S
HF

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-23
 UJ en
~ 0 0"1
timing diagram > ~z
UJ
X ......
~
'"I co;
RST --t "mm
JJ
c
:t>r-
en en
-<N
I > ZN
lOCK~~~~rflfl,---_ _ __ ~
<0
(')~
:::J::t>
ex>
co :a
I: I I I I I 0
DO-08 WW18W2~W8HW8~W31BW32~w55RW56~w..BW84~€ogl§.8J,e~ JJ
m
:5
Z
0
I I iii i UJ
m
0
;:
c:
en
UNCK I
I
I
I
I
I
I
I
I
I
I
I 1IlL....IIl.~r-='"I lLrI l~<,J"I lLrI l~<,-II lLrI l~T.J
. Il Il
'-I l -
>
JJ
0
I
"
S;
I I I I I I I I <0 en

: ~~~~~
'7'
~
~-
QO-oo=$* : 71 : '"0
_Z

~2!~ "
~~
I I I
II
I
II II
I
L
I S;
en

i~g
~~~
EMPTYJj

FUll
I
I
I
I
I
I
I
I
w.i- I - - -_ _ _ _ _ _ _ _--+
'7'
0
c:
-I
3:
~ l'l'HIl I I I m
~~ I I I I I 3:
~(iJ AF/AE : I I I I 0
:a
m
HF
I
II
I I
I
II I
I I I
I II
I I
-<

I I I I
Initialize I Almost Half Almost I Unload Empty
Pointers Empty+ 1 Full Full I W2
I I
load Full
W1
 SN74ALS2233A
64 x 9 ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORY
SCAS249 - FEBRUARY 1988 - REVISED MARCH 1990

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ............................................................ 7 V
Input voltage .............................................................................. 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA ............................................. ooe to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only. and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GNO.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
Qoutputs -2.6
IOH High-level output current mA
Flag outputs -0.4
Q outputs 24
IOL Low-level output current mA
Flag outputs 8
fclock Clock frequency LOCK, UNCK 0 40 MHz
RSTlow 25
LOCK low 13
tw Pulse duration LOCK high 12 ns
UNCKlow 13
UNCKhigh 12
tsu1 Setup time, data before LOCKi 5 ns
tsu2 Setup time, RST high (inactive) before LOCKi 5 ns
th Hold time, data after LOCKi 5 ns
TA Operating free-air temperature 0 70 'c

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-25
SN74ALS2233A
64 x 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS249- FEBRUARY 1988- REVISED MARCH 1990

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT
VIK Vee =4.5V, 11=-18mA -1.2 V
Q outputs Vee =4.5 V, 10H =-2.6mA 2.4 3.2
VOH V
Flag outputs Vee = MIN to MAX, 10H =0.4 mA Vee- 2
10l= 12 mA 0.25 0.4
Q outputs Vee=4.5 V
IOl=24 mA 0.35 0.5
VOL V
IOl=4 mA 0.25 0.4
Flag outputs Vee =4.5 V
10l = 8 mA 0.35 0.5
10ZH Vee =5.5 V, Vo = 2.7 V 20 !lA
10Zl Vee = 5.5 V, Vo = 0.4 V -20 !lA
II Vee = 5.5 V, VI =7V 0.1 mA
IIH Vee = 5.5 V, VI = 2.7 V 20 !lA
elKs -0.2
III Vee = 5.5 V, VI = 0.4 V mA
Others -0.1
Q outputs -20 -130
10§ Vee =5.5 V, Vo = 2.25 V mA
Flag outputs -20 -112
lee Vee =5.5 V 175 290 mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j: All typical values are at Vee = 5 V, TA = 25°e.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.

~1ExAs
INSTRUMENTS
5-26 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALS2233A
64 x 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS249 - FEBRUARY 1988 - REVISED MARCH 1990

switching characteristics (see Figure 1)

VCC=5V. Vcc = 4.5 V to 5.5 V.
CL=50pF. CL = 50 pF.
FROM TO R1 = 500n. R1 = 500 n.
PARAMETER R2 =500n. R2=500n. UNIT
(INPUT) (OUTPUT)
TA = 25'C TA = O'C to 70'C
MIN TYP MAX MIN MAX

'max LOCK. UNCK 40 MHz

LDCK1' 18 26 30
tpd Any 0 ns
UNCKi 18 24 27
tpLH LDCKi 12 16 18
EMPTY ns
tpHL UNCKi 12 17 20
tpHL RSf.L. EMPTY 12 17 20 ns
tPHL LDCKi FULL 16 21 22 ns
UNCKi 10 15 18
tPLH FULL ns
RST.L. 13 19 23
tpLH 22 27 30
LDCKi AF/AE ns
tpHL 19 25 28
tPLH 22 27 30
UNCKT AF/AE ns
tpHL 17 23 26
tpLH RST.L. AF/AE 12 16 18 ns
tpLH LDCKi 22 27 30
HF ns
tPHL RST.L. 28 32 35
tpHL UNCK1' HF 16 22 25 ns

len OEi 0 11 15 17 ns
!dis OE.L. 0 11 17 19 ns

:illExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-27
SN74ALS2233A
64 x 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SCAS249 - FEBRUARY 1988 - REVISED MARCH 1990

PARAMETER MEASUREMENT INFORMATION

SWITCH POSITION TABLE

TEST S1
tpLH Open
tPHL Open
tpZH Open
From Output _~__....._ ...._ Test Point tpZL Closed
Under Test tPHZ Open
CL=50pF R2 = 500 Cl tpLZ Closed
(see Note A)

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V

High-Level
Pulse 0.3 V

Timing 3.5 V
Input
_ _ _oJ,.. 1~3~ __ _ 0.3 V Low-Level
Pulse
3.5 V

0.3 V
tsu~th
Date ~. ct~-~--- 3.5V
Input .....f 1•3V ~ 0.3 V
VOLTAGE WAVEFORMS

~~
SETUP AND HOLD TIMES 3'5V
Output 1.3 V 1.3 V
Control 1
Input.J ~- - - - 3.5V tPZL...,.I I+- 1----- 0.3V
(see Note B) 1.3 V i\ 1.3 V
I --~~r-=
~
I I. 0.3 V
: tpLZ 3.5 V
tpLH~ ~tpHL
Waveform 1 1 1.3 V 1 I ..L.
In-Phase 1 1/. 1 { -:;.; VOH S1 Closed 1 --~
Output 1 T 1.3V 1 ~V
(see Note C) ~ tpHZ -+I ~- L :~\
--r-I--' 1 VOL

~~ - 1.:1
I.~, ~tpLH

Out-ot-Phase'
Output
tpHL~
{
' \ 1.3 V
.
1

T v:::
1.3 V
.. - - VOL
VOH
(see Note C) _ _ _ _ _ _
\E:':OH OV

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE .OUTPUTS

NOTES: A. CL Includes probe and jig capacitance.

B. All inpul pulses are supplied by generalors having Ihe following characterislics: PRR S 1 MHz, Zo = 50 0, Ir S 2 ns, If S 2 ns.
C. Waveform 1 is for an output wilh internal condHions such that the output is low except when disabled by the output control.
Waveform 2 is for an outpul wilh Internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

~1ExAs
INSTRUMENTS
5-28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA
256 x 9,512 x 9,1024 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS221 A - FEBRUARY 1993 -

• Reads and Writes Can Be Asynchronous DV OR NP PACKAGE

or Coincident (TOP VIEW)

• Organization: W
- SN74ACT7200L - 256 x 9
Vee
08 04
- SN74ACT7201LA -512 x 9
05
- SN74ACT7202LA -1024 x 9
06
• Fast Data Access Times of 15 ns 07
• Read and Write Frequencies up to 40 MHz FLIRT
• Bit·Width and Word· Depth Expansion RS
• Fully Compatible With the
EF
IDT7200/7201/7202 XO/HF
07
• Retransmit Capability 06
• Empty, Full, and Half·Full Flags 05
• TTL·Compatible Inputs 04
• Available in 28-Pin Plastic DIP (NP), GNO R
Small·Outline (DV), and 32·Pin Plastic
J·Leaded Chip·Carrier (RJ) Packages RJPACKAGE
(TOP VIEW)
description
The SN74ACT7200L, SN74ACT7201 LA, and
SN74ACT7202LA are constructed with dual-port 4 3 2 1 32 31 30
SRAM and have internal write and read address 5 0 29 06
counters to provide data throughput on a first-in, 6 28
first-out (FIFO) basis. Write and read operations 7 27
are independent and can be asynchronous or 8 26
coincident. Empty and full status flags prevent 25
underflow and overflow of memory, and 10 24
depth-expansion logic allows combining the 23
storage cells of two or more devices into one 12 22
FIFO. Word-width expansion is also possible. 13 21
1415 16 171819 20
Data is loaded into memory by the write-enable
(W) input and unloaded by the read-enable (R)
input. Read and write cycle times of 25 ns
(40 MHz) are possible with data access times of NC - No internal connection
15 ns.
These devices are particularly suited for providing a data channel between two buses operating at
asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in data-
acquisition systems, temporary storage elements between buses and magnetic or optical memories, and
queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus
a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for
retransmitting previously read data when a device is not used in depth expansion.
The SN74ACT7200L, SN74ACT7201 LA, and SN74ACT7202LA are characterized for operation from O°C
to 70°C.

Copyright © 1995. Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-29
SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA
256 x 9, 512 x 9,1024 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS221A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

SN74ACT7200L logic symbolt

FIF0256x9
<t>
SN74ACT7200L
22 r-- 2,4 CT =0 (RST)
RS 8
1
W 6 (WR PNTR) 2(CT =255) G6

7
C i',
!> 6 C1
G2
4(CT
(CT
=255) G6
=256) G6 t=!
XI (EXPAND) 21
23 i',
(CT =0) G5
FLIRT (1ST LOAD)
L, 2,4 (REXMIT) (EXPAND)
20
XO/HF
15
W
e
i', CT> 128
5 (RO PNTR)
5EN3
G4

DO
6
.,
10
(CT =WR PNTR - RO PNTR)
r
3'7
9
QO
5 10
01 Q1
4 11
02 Q2
3 12
03 Q3
27 16
04 Q4
26 17
·05 Q5
25 18
06 Q6
24 19
07 Q7
2 13
08 Q8

t This symbol is in accordance with ANS!/lEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the DV and NP packages.

"!!1 TEXAS
INSTRUMENTS
5-30 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 x 9,512 x 9,1024 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS221 A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

SN74ACT7201 LA logic symbolt

FIFO 512 x9
<l>
SN74ACT7201 LA
22
1
"- 2,4 CT =0 (RST) 8
6(WR PNTR) 2(CT =511) G6

7
C po
G2
6C1 4(CT
(CT
=511) G6
= 512) G6 ~
Xi "- (EXPAND) 21
23
"- (1ST LOAD)
(CT =0) G5
FL/RT
L:, 2,4 (REXMIT) (EXPAND)
20
XO/HF
15
W
e
f',
"5 (RD PNTR) CT > 256
gEN3
G4

DO
6
.,
1D
(CT =WR PNTR - RD PNTR)
3<;7
r 9
QO
5 10
D1 Q1
4 11
D2 Q2
3 12
D3 Q3
27 16
D4 Q4
26 17
D5 Q5
25 18
D6 Q6
24 19
D7 Q7
2 13
D8 Q8

t This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-31
SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA
256 x 9, 512 x 9, 1024 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

SN74ACT7202LA logic symbolt

FIFO 1024 x 9
cI>
SN74ACT7202LA
22
1
I'.
2,4 CT =0 (RST) 8
6 (WR PNTR) 2(CT =1023) G6

7
C >
G2
6C1 4(CT
(CT
=1023) G6
=1024) G6 tJ
XI
23 '" (EXPAND) (CT =0) G5 21

FLIRT
'"
Lr::,
(1ST LOAD)
2,4 (REXMIT)
20
(EXPAND)
15 U
e, '" 5EN3
5 (RDPNTR)

G4
(CT =WR PNTR - RD PNTR)
CT>512

6
r 9
DO 10 3\7 QO
5 10
01 Q1
4 11
02 Q2
3 12
03 Q3
27 16
04 Q4
26 17
05 Q5
25 18
06 Q6
24 19
07 Q7
2 13
08 Q8

t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the DV and NP packages.

~TEXAS
INSTRUMENTS
5-32 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7200L,SN74ACT7201LA,SN74ACT7202LA
256x9,512x9,1024x9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A- FEBRUARY 1993 - REVISED SEPTEMBER 1995

functional block diagram

9
00-08 Location 1
Location 2

w I
I
Write
Control
1
I
.. I
I
Write
Pointer
~
256x90r
512x90r
1024 x 9
+-1 Read
Pointer
I
i ..
RAMt

9
00-08

I
I
Reset
Logic
I
I
0
Status-
Flag

H Read
I Control
I
1
r Logic

,I.
Expansion
XO/HF
Logic

t 256 x 9 for SN74ACT7200L; 512 x 9 for SN74ACT7201 LA; 1024 x 9 for SN74ACT7202LA
RESET AND RETRANSMIT FUNCTION TABLE
(single-device depth; single-or multiple-device width)

INPUTS INTERNAL TO DEVICE OUTPUTS

FUNCTION
RS FURT XI READ POINTER WRITE POINTER EF FF XO/HF
L X L Location zero Location zero L H H Reset device
H L L Location zero Unchanged X X X Retransmit
H H L Increment if EF high Increment if FF high X X X Read/write

RESET AND FIRST-LOAD FUNCTION TABLE

(multiple-device depth; single-or multiple-device width)

INPUTS INTERNAL TO DEVICE OUTPUTS

FUNCTION
RS FURT XI READ POINTER WRITE POINTER EF FF
L L t Location zero Location zero L H Reset first device
L H t Location zero Location zero L H Reset all other devices
H X t X X X X Read/write
t XI IS connected to XO/HF of the prevIous deVice m the daiSY cham (see Figure 15).

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-33
SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA
256 x 9,512 x 9,1024 x 9
ASYNCHRONOUS FIRST-IN, FIRST·OUT MEMORIES
SCAS221 A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME
00-08 I Data inputs
Empty-flag output. EF is low when the read pointer is equal to the write pointer, inhibiting any operation initiated by a read
EF 0 cycle. When the FIFO is empty, a data word can be read automatically at aO-a8 by holding R low when loading the data
word with a low-level pulse on W.
Full-flag output. FF is low when the write pointer is one location less than the read pointer, indicating that the device is
full and inhibiting any operation initiated by a write cycle. FF goes low when the number of writes after reset exceeds the
FF 0 number of reads by 256 for the SN74ACT7200L, 512 for the SN74ACT7201 LA, and 1024 for the SN74ACT7202LA.
When the FIFO is full, a data word can be written automatically into memory by holding IN low while reading out another
data word with a low-level pulse on R.
First-Ioadlretransmit input. FLIRT performs two separate functions. When cascading two or more devices for word-depth
expansion, FLIRT is tied to ground on the first device in the daisy chain to indicate that it is the first device loaded and
unloaded; it is tied high on all other devices in the depth-expansion chain.
A device is not used in depth expansion when its expansion (xi) input is tied to ground. In that case, FLIRT acts as a
FLIRT I retransmit enable. A retransmit operation is initiated when FURT is pulsed low. This sets the internal read pointer to the
first location and does not affect the write pointer. Rand IN must be at a high logic level during the low-level FLIRT
retransmit pulse. Retransmit should be used only when less than 256/512/1024 writes are performed between resets;
otherwise, an attempt to retransmit can cause the loss of unread data. The retransmit function can affect XO/HF
depending on the relative locations of the read and write pointers.
GND Ground
aO-a8 0 Data outputs. aO-a8 are in the high-impedance state when R is high or the FIFO is empty.
Read-enable input. A read cycle begins on the falling edge of R if EF is high. This activates aO-a8 and shifts the next
data value to this bus. The data outputs return to the high-impedance state as R goes high. As the last stored word is
R I
read by the falling edge ofR, EF transitions low but aO-a8 remain active until R returns high. When the FIFO is empty,
the internal read pointer is unchanged by a pulse on R.
Reset input. A reset is performed by taking RS low. This initializes the internal read and write pointers to the first location
RS I and sets EF low, FF high, and HF high. Both R and IN must be held high for a reset during the window shown in Figure 7.
A reset is required after power up before a write operation can take place.
VCC Supply voltage
Write-enable input. A write cycle begins on the falling edge of W if FF is high. The value on 00- 08 is stored in memory
IN I
as IN returns high. When the FIFO is full, FF is low, inhibiting IN from performing any operation on the device.
Expansion-in input. XI performs two functions. XI is tied to ground to indicate that the device is not used in depth
Xi I expansion. When the device is used in depth expansion, Xi is connected to the expansion-out (XO) output olthe previous
device in the depth-expansion chain.
Expansion-outlhalf-full-flag output. XO/HF performs two functions. When the device is not used in depth expansion (I.e.,
when Xi is tied to ground), XO/HF indicates when half the memory locations are filled. After half of the memory is filled,
the falling edge on IN for the next write operation drives XO/HF low. XO/HF remains low until a rising edge of R reduces
XO/HF 0 the number of words stored to exactly half of the total memory.
When the device is used in depth expansion, XO/HF is connected to Xi of the next device in the daisy chain. XO/HF drives
the daisy chain by sending a pulse to the next device when the previous device reaches the last memory location.

~ThxAs
INSTRUMENTS
5-34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA
256 x 9,512 x 9,1024 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221 A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range (any input), VI .................................................... -0.5 V to 7 V
Continuous output current, 10 .............................................................. 50 mA
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
lunctional operation 01 the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions lor extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
IXI 2.6
VIH High-level input voltage V
IOther inputs 2
Vil low-level input voltage 0.8 V
IOH High-level output current -2 mA
IOl low-level output current 8 mA
TA Operating Iree-air temperature 0 70 'C

electrical characteristics over recommended operating free-air temperature range, Vee =5.5 V
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH VCC =4.5 V, IOH =-2 mA 2.4 V
VOL VCC=4.5 V, IOl = 8 mA 0.4 V
IOZH VO=VCC, R<!VIH ±10 ~
IOZl Vo = 0.4 V. R<!VIH ±10 ~
II VI = 0 to 5.5 V -1 1 ~
ta= 15 and 25 ns 125~
ICC1:!: mA
ta = 35 and 50 ns 50 80
ta= 15 and 25 ns 15
ICC2 :i: Fl, IN, RS, and FlIRT at VIH mA
ta = 35 and 50 ns 5 8
t a =15and25ns 0.5
ICC3:!: VI = VCC-0.2 V mA
ta = 35 and 50 ns 0.5
Ci§ VI =0, TA = 25'C, 1= 1 MHz 8 pF
C o§ VO=O, TA = 25'C, 1= 1 MHz 8 pF
:I: ICCI = supply current; ICC2 = standby current; ICC3 = power-down current. ICC measurements are made with outputs open (only capacitive
loading).
§This parameter is sampled and not 100% tested.
~ Tested at Iclock = 20 MHz

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-35
SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA
256 x 9, 512 x 9, 1024 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A- FEBRUARY 1993- REVISED SEPTEMBER 1995

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
,ACT7200L-15 'ACT7200L-25 'ACT7200L-50
'ACT7201LA-35t
'ACT7201LA-15 'ACT7201LA-25 'ACT7201 LA-50
FIGURE ,ACT7202LA-35t UNIT
'ACT7202LA-15 ' ACT7202LA-25 ' ACT7202LA-50
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency, R or W 40 28.5 22.2 15 MHz
tc(R) Cycle time, read 1 (a) 25 35 45 65 ns
tc(W) Cycle time, write 1 (b) 25 35 45 65 ns
tc(RS) Cycle time, reset 7 25 35 45 65 ns

tc(RT) Cycle time, retransmit 4 25 35 45 65 ns

twIRL) Pulse duration, R low 1(a) 15 25 35 50 ns
tw(WL) Pulse duration, W low 1(b) 15 25 35 50 ns
tw(RH) Pulse duration, R high 1(a) 10 10 10 15 ns
tw(WH) Pulse duration, W high 1(b) 10 10 10 15 ns
tw(RT) Pulse duration, FLIRT low 4 15 25 35 50 ns
tw(RS) Pulse duration, RS low 7 15 25 35 50 ns
tw(XIL) Pulse duration, XI low 10 15 25 35 50 ns
tw(XIH) Pulse duration, XI high 10 10 10 10 10 ns
tsu(D) Setup time, data before wi 1(b),6 11 15 18 30 ns
Setup time, Rand W high
tsu(RT) 4 15 25 35 50 ns
before FLIRTH
Setup time, Rand W high
tsu(RS) 7 15 25 35 50 ns
before RsH
Setup time, XI low
tsu(XI-R) 10 10 10 10 15 ns
before "RJ
Setup time, XI low
tsu(XI-W) 10 10 10 10 15 ns
beforeWJ,

th(D) Hold time, data after wi 1(b),6 0 0 0 5 ns

th(E-R) Hold time, R low after EFi 5,11 15 25 35 50 ns
th(F-W) Hold time, W low after FFi 6, 12 15 25 35 50 ns
Hold time, Rand W high
th(RT) 4 10 10 10 15 ns
after FLlRTi
Hold time, Rand W high
th(RS) 7 10 10 10 15 ns
afterRSi
t Released In RJ package only
:j: These values are characterized but not currently tested.

~TEXAS
INSTRUMENTS
5-36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 x 9,512 x 9,1024 x 9
ASYNCHRONOUS FIRST-IN, FIRST·OUT MEMORIES
SCAS221A- FEBRUARY 1993 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 13)
'ACT7200L-15 'ACT7200L-25 'ACT7200L-50
'ACT7201 LA-35t
'ACT7201LA-15 'ACT7201 LA-25 ,ACT7202LA-35t 'ACT7201 LA-50
PARAMETER FIGURE 'ACT7202LA-15 ' ACT7202LA-25 ' ACT7202LA-50 UNIT

MIN MAX MIN MAX MIN MAX MIN MAX

Access time, RJ, or EFi to l{a),3,
ta 15 25 35 50 ns
data out valid 5
Valid time, data out valid
tv{RH) 1(a) 5 5 5 5 ns
after "Ai
Enable time, RJ, to Q
ten{R-QX) 1(a) 5 5 10 10 ns
outputs at low impedance+
Enable time, Wi to Q
ten{W-QX) outputs at low 5 5 5 5 15 ns
impedance+§
Disable time, Ri to Q
tdis{R) outputs at high 1 (a) 15 18 20 30 ns
impedance+
Pulse duration, FF high in
tw{FH) 6 15 25 30 45 ns
automatic write mode
Pulse duration, EF high in
tw{EH) 5 15 25 30 45 ns
automatic read mode
Propagation delay time,
tpd{W-F) 2 15 25 30 45 ns
WJ,to FFlow
Propagation delay time,
tpd{R-F) 2,6,12 15 25 30 45 ns
"Ai to FF high
Propagation delay time,
tpd{RS-F) 7 25 35 45 65 ns
RSJ, to FF high
Propagation delay time,
tpd{RS-HF) 7 25 35 45 65 ns
RSJ, to XO/HF high
Propagation delay time,
tpd{W-E) 3,5,11 15 25 30 45 ns
Wi to EFhigh
Propagation delay time,
tpd{R-E) 3 15 25 30 45 ns
"AJ,to EF low
Propagation delay time,
tpd{RS-E) 7 25 35 45 65 ns
RSJ,to EF low
Propagation delay time,
tpd{W-HF) 8 25 35 45 65 ns
WJ, to XO/HF low
Propagation delay time,
tpd{R-HF) 8 25 35 45 65 ns
"Ai to XO/HF high
Propagation delay time,
tpd{R-XOL) 9 15 25 35 50 ns
"AJ, to XO/HF low
Propagation delay time,
tpd(W-XOL) 9 15 25 35 50 ns
WJ, to XO/HF low
Propagation delay time,
tpd(R-XOH) 9 15 25 35 50 ns
"Ai to XO/HF high
Propagation delay time,
tpd{W-XOH) 9 15 25 35 50 ns
Wi to XO/HF high
Propagation delay time,
tpd{RT-FL) 4 25 35 45 65 ns
FLIRTJ, to HF, EF, FF valid
t Released In RJ package only
+ These values are characterized but not currently tested.
§ Only applies when data is automatically read (see Figure 5)

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-37
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 x 9, 512 x 9,1024 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS221 A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

!41~--- tc(R) ---".J.4:~f-- twIRL) ---I

1 1 1 1
1 1 I4f4--....·*-1 1 1
_--~I-
~ la --.I:1
:.- tw(RH)

ta --.I
1
1
1,...---------------
It
1-----

~ I)t '\
ten(R-QX) I~ ~ -1
I :.- 14--- ---1
tv(RH) I tdls(R)

QO-Q8 _________ ~~ ~_a_lId ~~ ~_II_d ~~i-----

__ _____ __ ___

(a) READ

~4- _ - - - - t c(W) ----~.I1

.
1
1 1
J4---- tw(WL) - -•• t . - I tw(WH) ~
1 1 1

W- ,
1
l'1 1
'\'-__--JI
j+ tsu(D) -¥- th(D) +1

DO -D8 - - - - - - - ( Valid )1-1 ---~(\.._ _ Va_lI_d _---i»)..---

(b) WRITE

Figure 1. Asynchronous Waveforms

1 1 1
Last Write 1 Ignored 1 First Read 1 Additional Reads
1 Write 1 1
R ---+-------+1---11-.."--{ ! V
I I 1 I
w \~ /1
1,-._ _ _1 i\..J ,
I
1 II
_--+-_I~___·I I I tpd(W-F) tpd(R-F) ---i<I1~1----~·1 ~I_____________
'\ I I )I I
Figure 2. Full-Flag Waveforms

~TEXAS
INSTRUMENTS
5-38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 x 9,512 x 9,1024 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS221 A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

1 1
1 Ignored 1 Additional Writes
Last Read 1 Read 1 First Write

w---+----------~!------~~r-~------~~
1 1 1
1 1 1
'K ~~:I----+:~------------------------
1 1
14 .1 tpd(RoE) 1 1 1'44~>---...+-1 tpd(WoE)
1 1 1 1 1 1
EF ---+--+-i- ' " ' \ : : ,,---------
i ~--~i------~i------~---J
i~ta-+l 1 1
i l l
~O-DB --~----__~------~I------~----------------------
Figure 3. Empty-Flag Waveforms

W, R ~ i }'-_________________________
: j+- tsu(RT) .:4 th(RT) ----I
XO/HF, EF, F F r - - - - - - - - - - y , - a l - l d - F - l a - g- - - - - -

I
14 tpd(RToFL) ~
I
NOTE A: The EF, FF, and XO/HF status flags are valid after completion of the retransmit cycle.

Figure 4. Retransmit Waveforms

-!II TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-39
SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA
256 x 9,512 x 9,1024 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221 A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

w \ t
," !4--- Ih(E·R) .,,
I I y~-----

,1 ,1

EF ____________________ ~!______~ ~~-------------------

, I.- Iw(EH) -+i
Ipd(W·E) ,4
,
.,4 ., I
la
len(W.QX) ~ 14- 1

QO-Q8-------------------~~---~-a-lId--~)~-------------
Figure 5. Automatic-Read Waveforms

R~~_ _--,(
I ' ,
I !4-- Ih(F.W) .,
w :! ~~-----------

Ipd(R.F) -,14-4--~., ,
I , ,

t \1 '~I-------
r-- --t; 'I
- - - - - - - - - - - - - - ' 1-
Iw(FH)
~ l h(D) j4-
DO_D8 ______________________________;<lr-~-al-ld-~)~-------------

1
i4- Isu(D) ----+i
Figure 6. Automatic-Write Waveforms

~1ExAS
INSTRUMENTS
5-40 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 x 9,512 x 9,1024 x 9
ASYNCHRONOUS FIRST-IN, FIRST·OUT MEMORIES
SCAS221 A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

1 ..-
i41
- - - - - - - te(RS) ----------+i
.1
1 1
114
..- - - - - - tw(RS) ------+t
·1 1
1 1
RS~
I~----------------------~ 1
1 1
1
1
1
1 1
1
W
1 1
1
1
1
'\1
1 1
1 1
R 1 1

---+iooII---~f-
1 1
: tsu(RS) -14i
.. ·1" ·1 th(RS)

EF

14---- tpd(RS-E) .,

XO/HF.FF~
1
~ tpd(RS-HF) -----1 I

J+-- tpd(R5-F) .1
Figure 7. Master-Reset Waveforms

Half Full or Less i More Than Half Full 1

1
Half Full or Less

I
W
\ 1
I tpd(R-HF)
1
1
.1
1 I"

r
1 1
1 1
R 1
1
.1
\ 1
1
1
14 tpd(W-HF) 1 1
1 I 1
1
XO/HF I
1 '\ 1
I Y
Figure 8. Half-Full Flag Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-41
SN74ACT7200L,SN74ACT7201LA,SN74ACT7202LA
256x9,512x9,1024x9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS221A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

Write to Last
Iii Physical Location

",~,
,
I tpd(W-XOH) ~ 1\
Read From Last
Physical Location I
XO/HF
j4-----+!--
-\L
\
, tpd(W-XOL)

r""

;
.~---I.*""' tpd(R-XOL) ~t4---..~t-
\J
" ' \ .
Y , tpd(R-XOH)

Figure 9. Expansion-Out Waveforms

~ tw(XIL) ---t~~,~ tw(XIH) ----1

Xl } " -_ _ ...Jy "1"------'/
,. ., tsu(Xl-WJ ,

Iii
-----~, Write to First
Physical Location
1-4"----------------------
,

ii4.--I.*-',- tsu(XI-R)

-------------\',.,.';---\I Read From First

R "\ Physical Location
/
Figure 10, Expansion-In Waveforms

Iii \'---_____1
tpd(W-E) -f~4---+!~
JI----
EF 1'1
------------------------------------~,
J4- th(E-R) +l
R r~-

Figure 11. Minimum Timing for an Empty-Flag Coincident-Read Pulse

-!!1 TEXAS
INSTRUMENTS
5-42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 x 9, 512 x 9, 1024 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS221A- FEBRUARY 1993- REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

Figure 12. Minimum Timing for a Full-Flag Coincident-Write Pulse

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265 5-43
SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA
256 x 9,512 x 9, 1024 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS221 A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

SV

?
? 11000
From Output
Under Test - - . - - - - - .

< 6800 -::=-

;:or: 30 pF
(see Note A)

LOAD CIRCUIT

Timing
Input
1.
----'4 ~ ~ ___
3V
GND
High-Level
Input ---1f_~~.~-
,.~. ~
3V
GND

tsu~th I+- tw ~
I I·
Data, ~ -:- ;:, - 3 V
~
I 3V
Enable ~ 1.SV ~ Low-Level 1.S V 1.S V
Input GND Input _ _ _ _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

3V
Output L
Enable ---I': 1.S V
1 GND
~ i4-tPLZ
Low-Level
Output
II
1
_-+...JI
- - - -.......-.:

I4--tPZH
=3V

VOL
Input --X'l.SV \~S~ - - ::0
I tpd --j4--+i ~ tpd
High-Level
VOH
.--_~ 1- _ VOH
Output 1 1
1 1 =OV
In-Phase
Output
_ _---J.
!l.SV ~'\.:.:..
1.SV
VOL
~ l4-tPHZ

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 13. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
5-44 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 x 9,512 x 9,1024 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS221 A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION
Combining two or more devices to create one FIFO with a greater number of memory bits is accomplished in two
different ways. Width expansion increases the number of bits in each word by connecting FIFOs with the same depth
in parallel. Depth expansion uses the built-in expansion logic to daisy-chain two or more devices for applications
requiring more than 256, 512, or 1024 words of storage. Width expansion and depth expansion can be used together.

width expansion
Word-width expansion is achieved by connecting the corresponding input control to multiple devices with the
same depth. Status flags (EF, FF, and HF) can be monitored from anyone device. Figure 14 shows two FIFOs
in a width-expansion configuration. Both devices have their expansion-in (XI) inputs tied to ground. This
disables the depth-expansion function of the device, allowing the first-load/retransmit (FURT) input to function
as a retransmit (RT) input and the expansion-outlhalf-full (XO/HF) output to function as a half-full (HF) flag.

depth expansion
The SN74ACT7200Ll7201 LA/7202LA is easily expanded in depth. Figure 15 shows the connections used to
depth expand three SN74ACT7200Ll7201 LA/7202LA devices. Any depth can be attained by adding additional
devices to the chain. The SN74ACT7200Ll7201 LA/7202LA operates in depth expansion under the following
conditions:
• The first device in the chain is designated by tying FL to ground.
• All other devices must have their FL inputs at a high logic level.
• XO of each device must be tied to XI of the next device.
• External logic is needed to generate a composite FF and EF. All FF outputs must be ORed together and
all EF outputs must be ORed together.
• RT and HF functions are not available in the depth-expanded configuration.

combined depth and width expansion

Both expansion techniques can be used together to increase depth and width. This is done by first creating
depth-expanded units and then connecting them in a width-expanded configuration (see Figure 16).

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-45
SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA
256 x 9, 512 x 9,1024 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A- FEBRUARY 1993 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION
SN74ACT7200L/7201LA/7202LA

18 00-08 QO-Q8 18
00-018 00-08 QO-Q8 QO-Q18
....... 9 9 ",
Vi Vi
R R EF

FLIRT FF
RS XO/HF
Xi
l
SN74ACT7200L/7201LA/7202LA

09-018 Q9-Q18
00-08 QO-Q8
9 9
Vi
R EF

FLIRT FF
RS XO/HF
Xi
l .
Figure 14. Word-Width Expansion: 256151211024 Words x 18 Bits

~lExAs
INSTRUMENTS
5-46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA
256 x 9,512 x 9,1024 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS221 A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION
SN74ACT7200L/7201LA/7202LA

9 9 9 9
00-08 00-08 QO-Q8 QO-Q8
W W
R R XO/HF
RS EF
FURT FF
,..-- Xi

SN74ACT7200L/7201LA/7202LA

9 9
00-08 QO-Q8
W
~
R XO/HF f - - ~
RS EF I
VCC FURT FF
- Xi
I ~
--.-/

SN74ACT7200L/7201LA/7202LA

9 9
00-08 QO-Q8
W

R XO/HF -
RS EF
FURT FF
1- r--- Xi

,
Figure 15. Word-Depth Expansion: 768/1536/3072 Words x 9 Bits

-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-47
SN74ACT7200L,SN74ACT7201LA,SN74ACT7202LA
256 x 9, 512 x 9, 1024 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A - FEBRUARY 1993 - REVISED SEPTEMBER 1996

APPLICATION INFORMATION
QO-Q17 QO-Q26

9~_Q17
18
9 9f= 27
QO-Qa 9 Q18-Q26

'ACT7200L, 'ACT7200L, 'ACT7200L,

'ACT7201LA, or 'ACT7201LA, or 'ACT7201LA, or
'ACT7202LA 'ACT7202LA 'ACT7202LA
W,R,RS
Oepth- Oepth- Oepth-
Expansion Expansion Expansion
Block Block Block

27
j 00-08
18
j 09-017 9 018-026

00-026 09-026

Figure 16. Word·Depth Plus Word·Width Expansion

~TEXAS
INSTRUMENTS
5-48 POST OFFICE BOX 865303 • DALLAS. TEXAS 75265
 SN74ACT2235
1024 x 9 x 2
ASYNCHRONOUS BIDIRECTIONAL FIRSl FIRST·OUT MEMORY

• Independent Asynchronous Inputs and FNPACKAGE

Outputs (TOP VIEW)

• Low-Power Advanced CMOS Technology 0««1II1I10

~~oZIIlIIl««ZO~
««(!)(!)I1)I1)(!)(!)1II1I1
• Bidirectional
• 1024 Words by 9 Bits Each 6 5 4 3 2 1 44 4342 41 40
A3 7 39 B2
• Programmable Almost-FuIl/Almost-Empty A4 8 38 B3
Flag B4
Vee 9 37
• Empty, Full, and Half-Full Flags A5 10 36 Vee
• Access Times of 25 ns With a 5O-pF Load A6 11 35 B5
• Data Rates From 0 to 50 MHz A7 12 34 B6
A8 13 33 B7
• Fall-Through Times of 22 ns Max B8
GND 14 32
• High Output Drive for Direct Bus Interface AF/AEA 15 31 GND
• Available in 44-Pin PLCC (FN), HFA 16 30 AF/AEB
Space-Saving 64-Pin Thin Quad Flat (PM), LDCKA 17 HFB
18192021 22 23 24 25 26 27 2829
and Reduced-Height 64-Pln Thin Quad Flat
(PAG) Packages
Ij~I~I~lgl~I~I~
::l0 ~Ij ~
0a:(1) 0 0...0::l0
u.~~ a: ::!:~u.g
UJ UJ

PAG OR PM PACKAGE
(TOP VIEW)
() o 0««1II1I1 0 0 ()
$'~<~aaffiffi~(§aa~[ij ~$'
~~~~OOW~~~~M~~~W~

Vee 48 NC
1•
A3 2 47 Vee
A4 3 46 B3
Vee 4 45 B4
GND 5 44 GND
GND 6 43 GND
A5 7 42 Vee
A6 8 41 B5
Vee 9 40 B6
Vee 10 39 VCC
A7 11 38 B7
A8 12 37 B8
GND 13 36 GND
GND 14 35 GND
AF/AEA 15 34 AF/AEB
HFA 16 33 HFB
17 18 192021 2223242526272829 3031 32

NC - No internal connection

Copyright © 1995, Texas Instruments Incorporated

~~o~~~~:o~~ :=:~~81;;'t,rr:::.:l ~:':tC:m':~
standard warranty. Proiluctlon processing does nOI n......~ly Include
testing 01 all parameters. -!II TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265 5-49
SN74ACT2235
1024x9x2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148C- DECEMBER 1990- REVISED SEPTEMBER 1995

description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT2235 is arranged as two 1024 by 9-bit FIFOs for high speed and fast access times.
It processes data at rates from 0 to 50 MHz with access times of 25 ns in a bit-parallel format.
The SN74ACT2235 consists of bus-transceiver circuits, two 1024 x 9 FI FOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable (GAS
and GSA) inputs are provided to control the transceiver functions. The select-control (SAS and SSA) inputs are
provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates
the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.
Figure 1 shows the eight fundamental bus-management functions that can be performed with the
SN74ACT2235.
The SN74ACT2235 is characterized for operation from O°C to 70°C.
For more information on this device family, see the application report 1K x 9 x 2 Asynchronous FIFOs
SN74ACT2235 and SN74ACT2236 in the 1996 High-Performance FIFO Memories DeSigner's Handbook,
literature number SCAA012A.
logiC symbolt
CI>
FIFO
44 1024x9x2
SAB
SN74ACT2235
1 :}MOOE
SBA
43
GAB EN1
2
GBA EN2
22 23
RSTA
21
" ReaetA RESETB l-1
24
RSTB
OAF
17
" OEFAFLAG OEFBFLAG l-1
28
OBF
LOCKA LOCKA LOCKB LOCKB
26 19
UNCKA UNCKA UNCKB UNCKB
18 27
FOlIA FULLA FULLB FULLB
25 20
EMPTYA EMPTYA EMPTYB EMPTYB
15 ALMOST-FULU 30
AF/AEA ALMOST-FULU AF/AEB
16 ALMOST-EMPTY A ALMOST-EMPTY A
29
HFA
,
HALF-FULL A HALF-FULLB
r
HFB

4 41
AO 0 0 BO
5 40
A1 B1
6 39
A2 B2
7 38

~ ~
A3 B3
8 37
A4 B4
10 35
A5 B5
11 34
A6 B6
12 '.'-33
A7 B7
13 32
A8 8 8 B8

tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the FN package.

~1ExAs
INSTRUMENTS
5-50 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT2235
1024x9x2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148C- DECEMBER 1990- REVISED SEPTEMBER 1995

logic diagram (positive logic)

SAB

I ~
SBA '" --"
HFB
I ~ ct>
FIFOB
1024 x 9 RSTB
AF/AEB DBF
EMPTYB FULLB
UNCKB LDCKB
'1 .-'"

~
GBA
Q D BO

r-
I I
I

!
L.One
__ of_
Nine
__ Channels
_ _ _ _ _ .J I
To Other Channels

GAB

ct> I
RSTA FIFO A HFA
1024x 9
DAF AF/AEA
FULLA h. EMPTYA
LDCKA
, UNCKA

r(~I
r
AO D Q

I I
I ~!
t i I
IL _
-One of Nine Channels I
_ _ _ _ _ _ _ _ _ .J

To Other Channels

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 5-51
SN74ACT2235
1024x9x2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCASl48C- DECEMBER 1990- REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
110 DESCRIPTION
NAME NO.
Almost fulValmost empty flags. The aimost-fuil/aimost-empty A flag (AF/AEA) is defined by the
AF/AEA, almost-fuIValmost-emptyoffset value for FIFO A (X). AF/AEA is high when FIFO A contains X or less
15,30 0
AF/AEB words or 1024-X words. AF/AEA is low when FIFO A contains between X + 1 or 1023 - X words.
The operation of the aimost-fuillaimost-empty B flag (AF/AEB) Is the same as AF/AEA for FIFO B.
AO-AS 4-8,10-13 1/0 A data Inputs and outputs
32-35,
BO-B8 1/0 B data inputs and outputs
37-41
Define-flag inputs. The high-to-Iow transRion of OAF stores the binary value on AO-A8 as the
OAF,OBF 21,24 I almost-fuIValmost-empty offset value for FIFO A (X). The high-to-Iow transRion of OBF stores the
binary value of BO-B8 as the aimost-fuillaimost-empty offset value for FIFO B (Y).
EMPTYA, Emptyflags. EMPTYA and EMPTYB are low when their corresponding memories are empty and high
20,25 0
EMPTYB when they are not empty.
FULLA, Full flags. FULLA and FULLB are low when their corresponding memories are full and high when they
18,27 0
FULLB are not full.
Half-full flags. HFA and HFB are high when their corresponding memories contain 512 or more words
HFA, HFB 16,29 0
and low when they cOntain 511 or less words.
Load clocks. Data on AO-AS is written into FIFO A on a low-to-high transition of LOCKA. Data on
LOCKA,
17,28 I BO-B8 is written into FIFO B on a low-to-high transition of LOCKB. When the FIFOsarefull, LOCKA
LOCKB
and LOCKB have no effect on the data residing in memory.
Output enables. GAB, GBA control the transceiver functions. When GBA is low, AO-A8 are in the
GAB,GBA 2,43 I
high-impedance state. When GAB is low, BO-B8 are in the high-impedance state.
Reset. A reset is accomplished in each direction by taking RSTA and RSTB low. This sets EMPTYA,
RSTA, RSTB 22,23 I
EMPTYB, FULLA, FULLB, and AF/AEB high. Both FIFOs must be reset upon power up.
Select-control inputs. SAB and SBA select whether real-time or stored data Is transferred. A low level
SAB, SBA 1,44 I selects real-time data and a high level selects stored data. Eight fundamental bus-management
functions can be performed as shown in Figure 1.
Unload clocks. Data in FIFO A is read to BO-B8 on a low-to-hlgh transRion of UNCKB. Data In FIFO
UNCKA,
19,26 I B is read to AO-A8 on a low-to-high transRlon of UNCKB. When the FIFOs are empty, UNCKA and
UNCKB
UNCKB have no effect on data residing in memory.

programming procedure for AF/AEA

The aimost-fuil/almost-empty flags (AF/AEA, AF/AEB) are programmed during each reset cycle. The
aimost-fuil/aimost-empty offset value FIFO A (X) and for FIFO B (Y) are either a user-defined value or the default
values of X = 256 and Y = 256. Below are instructions to program AF/AEA using both methods. AF/AEB is
programmed in the same manner for FIFO B.
user-defined X
Take OAF from high to low. This stores AD thru AS as X.
If RSTA is not already low, take RSTA high.
With OAF held low, take RSTA high. This defines AF/AEA using X.
To retain the current offset for the next reset, keep OAF low.
default X
To redefine AF/AE using the default value of X =256, hold OAF high during the reset cycle.

~1ExAs
INSTRUMENTS
5-52 POST OFFICE BOX 665303 • DAUAS. TEXAS 76265
 timing diagram for FIFO At

RSTA

OAF
.J
1
I ~€O;'!i+~
LJ
II~
+ I 1'*
LOCKA

AO-A8
~rf1rf1~rfl
~ ~I~:_I
~tt~v:~~~C
I I
III
I::
V:~rd=~€O£'£~~~ x I
I I
. l>
~
Z
I I I I I I I I o
UNCKAII I I I Inn n n nil
~ I I I I I I i YH
Yr-; YT---/ YT--1 1""'----+-1-1-1.........- -
::::a::::
:::u
o
I I I I I I I I I I I I oz
1~4r QO _ Q8
3 Invalid
: Word11 I I~~ Word ord Word rd Word ~
Word Word Word I I valid
oc:
en
I-3:t::~
' . _ 2 257 258 513 514 768 769 1024

I I I I I I m

!~
EMPTYA ---W I
I
I
I
I
I ~_-+I_-r_-
I
I
c
:::u
m
I I I ~
~CiJ
iii
8l
FULLA II
I
U II
I
000
§?z
~l>
~r-

H~ I I ?::!!
c:::u
I
I
:
I
~en
~ ..
mz
111-
:D_
I I

.
AF/AEA
I I i::!!
I I Set Flag to f:::u
I IEmpty + XlFull- X :Den
~
I I fRO en
Set Flag to Empty + 2561 Empty + 256 Full - 256 Full- 256 Half Full Empty + 256 Empty Load X into cc: .... Z
Full - 256 (default) Half Full Full Flag Register
fR-to
.,,~~~
......
(0 ~ X ~ 511) iri;:o,,~l>
s:mX 0
t Operation of FIFO B is identical to that of FIFO A. !113:.-. -t
:DO-~
:j: Last valid data stays on outputs when FIFO goes empty due to a read. ~ X ~
III :::u
~
(0)
"'-<~UI
SN74ACT2235
1024 x 9 x 2
ASYNCHRONOUS BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS148C- DECEMBER 1990- REVISED SEPTEMBER 1995

BusA BusB BusA BusB

SAB SBA GAB GBA SAB SBA GAB GBA

L X H L X X L L

BusA BusB BusA BusB

SAB SBA GAB GBA SAB SBA GAB GBA

X L L H H L H H

BusA BusB Bus A BusB

SAB SBA GAB GBA SAB SBA GAB GBA

H X H L L H H H

BusA
Bus A BusB
BusB

SAB SBA GAB GBA SAB SBA GAB GBA

X H L H H H H H

Figure 1. Bus-Management Functions

SELECT·MODE CONTROL TABLE

~ThxAS
INSTRUMENTS
5-54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT2235
1024 x 9 x 2
ASYNCHRONOUS BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS148C- DECEMBER 1990 - REVISED SEPTEMBER 1995

CONTROL OPERATION
SAB SBA A BUS BBUS
L L Real-time B to A bus Real-time A to B bus
L H FIFO B to A bus Real-time A to B bus
H L Real-time B to A bus FIFO A to B bus
H H FIFO B to A bus FIFO A to B bus

OUTPUT-ENABLE CONTROL TABLE

CONTROL OPERATION
GAB GBA A BUS BBUS
H H A bus enabled B bus enabled
L H A bus enabled Isolation/input to B bus
H L Isolation/input to A bus B bus enabled
L L Isolation/input to A bus Isolation/input to B bus

Figure 1. Bus-Management Functions (Continued)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range. Vee .......................................................... -0.5 V to 7 V
Input voltage: Control inputs .................................................................. 7 V
I/O ports ............................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled 3-s:ate output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. TA ............................................... O°C to 70°C
Storage temperature range. Tstg .................................................... -65°C to 150°C
Maximum junction temperature. TJ ......................................................... 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-55
SN74ACT2235
1024 x 9 x 2
ASYNCHRONOUS BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS148C - DECEMBER 1990 - REVISED SEPTEMBER 1995

recommended operating conditions

'ACT2235-20 'ACT2235-30 'ACT2235-40 'ACT2235-60
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 0.8 V
A or B ports -8 -8 -8 -8
IOH High-level output current mA
Status flags -8 -8 -8 -8
A or B ports 16 16 16 16
IOL Low-level output current mA
Status flags 8 8 8 8
LDCKA or LDCKB 50 33 25 16.7
fclock Clock frequency MHz
UNCKA or UNCKB 50 33 25 16.7
RSTA or RSTB low 20 20 25 25
LDCKA or LDCKB low 8 10 14 20
LDCKA or LDCKB high 8 10 14 20
tw Pulse duration ns
UNCKA or UNCKB low 8 10 14 20
UNCKA or UNCKB high 8 10 14 20
DAF or DBF high 10 10 10 10
Data before LDCKA or
4 4 5 5
LDCKBt
Define AF/AE: DO-D8
5 5 5 5
before DAF or DBFt
Define AF/AE: DAF or
DBFt before RSTA or 7 7 7 7
tsu Setup time RSTBt ns
Define AF/AE (default):
DAF or DBF high before 5 5 5 5
RSTA or RSTBt
RSTA or RSTB inactive
(high) before LDCKA or 5 5 5 5
LDCKBt
Data after LDCKA or
1 1 2 2
LDCKBt
Define AF/AE: DO-D8
0 0 0 0
after DAF or DBFt

Hold time Define AF/AE: OAF or ns

th
DBF low after RSTA or 0 0 0 0
RSTBt
Define AF/AE (default):
DAF or DBF high after 0 0 0 0
RSTA or RSTBt
TA Operating free-air temperature 0 70 a 70 0 70 0 70 ·C

~lExAs
INSTRUMENTS
5-56 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT2235
1024x9x2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148C- DECEMBER 1990 - REVISED SEPTEMBER 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VOH VCC =4.5 V, 10H =-8 mA 2.4 V
I Flags VCC =4.5 V, IOL=8 mA 0.5
V
VOL
Ilia ports VCC = 4.5 V, 10L= 16 mA 0.5
II VCC=5.5 V, VI=VCcorO ±5 IlA
10Z VCC =5.5 V, VO= VCC orO ±5 IlA
ICCt VI = VCC - 0.2 V or 0 10 400 IlA
AICC§ VCC=5.5 V, One input at 3.4 V, Other inputs at VCC or GNO 1 mA
Ci VI =0, f = 1 MHz 4 pF
Co VO=O, f = 1 MHz 8 pF
t All tYPical values are at VCC = 5 V, TA = 25'C.
:j: ICC tested with outputs open.
§ This is the supply current when each input is at one of the specified TIL voltage levels rather than 0 V or VCC.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figures 4 and 5)
FROM TO 'ACT2235-20 'ACT2235-30 'ACT2235-40 'ACT2235-60
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYPt MAX MIN MAX MIN MAX MIN MAX
LOCK 50 33 25 16.7
f max MHz
UNCK 50 33 25 16.7
tpd LOCKI', LOCKBI B or A 8 22 8 22 8 24 8 26 ns
UNCKAI,
tpd BorA 12 17 25 12 25 12 35 12 45 ns
UNCKBI
EMPTYA,
tpLH LOCKI, LOCKBI 4 15 4 15 4 17 4 19 ns
EMPTYB
UNCKAI, EMPTYA,
tPHL 2 17 2 17 2 19 2 21 ns
UNCKBI EMPTYB
EMPTYA,
tpHL RSTAJ., RSTBJ. 2 18 2 18 2 20 2 22 ns
EMPTYB
tpHL LOCKI, LOCKBI FULLA, FULLB 4 15 4 15 4 17 4 19 ns
UNCKAI,
tpLH FULLA, FULLB 4 15 4 15 4 17 4 19 ns
UNCKBI
tPLH RSTAJ., RSTBJ. FULLA, FULLB 2 15 2 15 2 17 2 19 ns
tpLH RSTAJ., RSTBJ. AF/AEA, AF/AEB 2 15 2 15 2 17 2 19 ns
tpLH LOCKI, LOCKBI HFA, HFB 2 15 2 15 2 17 2 19 ns
UNCKAI,
tpHL HFA, HFB 4 18 4 18 4 20 4 22 ns
UNCKBI
tpHL RSTAJ., RSTBJ. HFA, HFB 1 15 1 15 1 17 1 19 ns
tpd SABor SBAIf BorA 1 11 1 11 1 12 1 14 ns
tpd AorB BorA 1 11 1 11 1 12 1 14 ns
tpd LOCKI, LOCKBI AF/AEA, AF/AEB 2 18 2 18 2 20 2 22 ns
UNCKAI,
tpd AF/AEA, AF/AEB 2 18 2 18 2 20 2 22 ns
UNCKBI
ten GBAorGAB AorB 2 11 2 11 2 13 2 15 ns
tdis GBAorGAB AorB 1 9 1 9 1 11 1 13 ns
t All tYPical values are at VCC = 5 V, TA = 25'C.
If These parameters are measured with the internal output state of the storage register opposite to that of the bus input.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-57
SN74ACT2235
1024 x 9 x 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148C - DECEMBER 1990 - REVISED SEPTEMBER 1995

operating characteristics, Vee =5 V, TA =25°C

PARAMETER TEST CONDITIONS TYP UNIT

Power dissipation capacitance per 1K bits

I Outputs enabled CL = 50 pF, f=5MHz
71
pF
Cpd
I Outputs disabled 57

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME POWER DISSIPATION CAPACITANCE
vs vs
LOAD CAPACITANCE SUPPLY VOLTAGE

VCC~5V Vce =5V

- TA = 25°C
RL=500n /
/
~
'a.
I
11 = 5 MHz
TA = 25°C V
./
~ typ+1
V S ,/
,/
V 1o typ ./
/
/' a V
1 ,/
V ~ typ-1
/'
/ ,/
1/ II typ-2
,/
/ o
"8-

typ -2
/ typ-3
o 50 100 150 200 250 300 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5
eL - Load Capacitance - pF Vee - Supply Voltage - V

Figure 2 Figure 3

calculating power dissipation

The maximum power dissipation (PT) can be calculated by:
PT = Vce x [Icc + (N x l1lee x dc)] + :E(Cpd x Vee2 x Ii) + :E(CL x Vee2 x 10 )
where:
Icc = power-down ICC maximum
N = number of inputs driven by a TTL device
l1lcc = increase in supply current
dc = duty cycle 01 inputs at a TTL high level 013.4 V
Cpd = power dissipation capacitance
CL = output capacitive load
Ii = data input frequency
10 = data output Irequency

~TEXAS
INSTRUMENTS
5-58 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT2235
1024 x 9 x 2
ASYNCHRONOUS BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS148C- DECEMBER 1990- REVISED SEPTEMBER 1995

From Output
Under Test
=nI
RL=5000
PARAMETER MEASUREMENT INFORMATION

Input
~
L
tpd --ioII1"1--~~
I
\ ~~---
I.
I
14
I
~tpd
3V
GND

Output
_ _ _ _.J
I I , . - - -......~t---
1.5 V
3V
OV

LOAD CIRCUIT TOTEM· POLE OUTPUTS

Figure 4. Standard CMOS Outputs (FULL, AF/AE, EMPTY)

7V
3V
Input \ 1 . 5 V j1.5V
RL = R1 = R2 51 1-------- OV
I
tpZL-+1 I... -+1 i+-tPLZ
R1 i 1 1
1 ~3.5V

b~~~
From Output Test 1 1
Under Test Point Output \1.5V 1
1
1 VOL
I
tpHZ --+I I+- t
t----'-
CL R2 I 1
tPZH --+I I+-

Output 11.5V
----3 VOH
O.3V
~ov
~

LOAD CIRCUIT VOLTAGE WAVEFORMS

PARAMETER R1, R2 CLt 51

tpZH Open
ten 5000 50 pF
tpZL Closed
tpHZ Open
tdis 5000 50 pF
tpLZ Closed
tpd - 50 pF Open
t Includes probe and test·fixture capacitance
Figure 5. 3-State Outputs (AO-A8, BO-B8)

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-59
5-60
 SN74ACT2236
1024 x 9 x 2
ASYNCHRONOUS BIDIRECTIONAL FIRSl FIRST·OUT MEMORY

• Independent Asynchronous Inputs and • Access Times of 25 ns With a 50·pF Load

Outputs • Data Rates From 0 to 50 MHz
• Low·Power Advanced CMOS Technology • Fall·Through Times of 23 ns Max
• Bidirectional • High Output Drive for Direct Bus Interface
• 1024 Words by 9 Bits Each • 3·State Outputs
• Programmable Almost·FuIl/Almost·Empty • Available In 44·Pln PLCC (FN) Package
Flag
• Empty, Full, and Half·Full Flags
FNPACKAGE
(TOP VIEW)

Cl «co Cl
C\I ... 0 z Q; co « IW Z 0 ...
«««(!)ClcncnO(!)COCO
6 5 4 3 2 1 44 434241 40
7 39 82
8 38 83
9 37 84
10 36 Vee
11 35 85
12 34 86
13 33 87
14 32 88
15 31 GND
16 30 AF/AE8
17 29 HF8
181920 21 222324 25262728

13~1~1~1~1~1~1~
u..~~ a:
gl~ ~
~~u..9
W W

description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT2236 is arranged as two 1024 by 9-bit FIFOs for high speed and fast access times.
It processes data at rates from 0 to 50 MHz with access times of 25 ns in a bit·parallel format.
The SN74ACT2236 consists of bus-transceiver circuits, two 1024 x 9 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable OE and
DIR inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates
the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.
Figure 1 shows the five fundamental bus-management functions that can be performed with the SN74ACT2236.
The SN74ACT2236 is characterized for operation from O°C to 70°C.
For more information on this device family, see the application report 1K x 9 x 2 Asynchronous FIFOs
SN74ACT2235 and SN74ACT2236 in the 1996 High-Performance FIFO Memories Designer's Handbook,
literature number SCAA012A.

Copyright © 1995, Texas Instruments Incorporated

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-61
SN74ACT2236
1024x9x2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCASl49A - APRIL 1990 - REVISED SEPTEMBER 1995

logic symbolt

4l
FIFO
1024x9x2
SN74ACT2236
44
SAB
1 : } MODE
SBA
43
L"
OE 3EN1 [BA)
3EN2[AB)
2 r-.
OIR G3 23
22 r-. RESETB
.A
RSTB
RSTA RESET A
21 24
I"-
OEFAFLAG OEFBFLAG A OBF
OAF 26
17 LOCKB
LOCKA LOCKA LOCKB
26 19
UNCKA UNCKB UNCKB
UNCKA 27
16 FULLB FULLB
FILLA FULLA 20
25 EMPTYB EMPTYB
EMPTYA EMPTYA
15 30
AF/AEA ALMOST·FULU ALMOST·FULU AF/AEB
16 ALMOST·EMPTY A ALMOST·EMPTY B 29
HFA ~ALF.FULLA HALF.FULL~ \ HFB

4 41
AO 0 1V 2V 0 BO
5 40
Ai B1
6 39
A2 B2
7 36

~~
A3 B3
8 37
A4 B4
10 35
A5 B5
11 34
A6 B6
12 33
A7 B7
13 32
A8 8 8 B8

t This symbol is in accordance with ANSIIIEEE Std 91·1984 and lEe Publication 617·12.

~1ExAs
INSTRUMENTS
5-62 POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
 SN74ACT2236
1024x9x2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995

logic diagram (positive logic)

SAB

I D
I '" Lrp
SBA

'--' <l>
HFB FIFOB RSTB
AF/AEB 1024 x 9 OBF
EMPTYB FULLB
UNCKB
., r
LOCKB

~:
Q 0 BO
I I

I --r-b
L __
lOne of_ __
Nine _ _ _ _ _ .JI
Channels

To Other Channels

OIR

?=r -d]
<l>
RSTA HFA
FIFO A
OAF 1024 x 9 AF/AEA
FULLA EMPTYA
LOCKA
., ,. r--------- -.,
UNCKA

AO 0 Q i H-
I I
! II
i I
L_=~~~~e~~~e~J
To Other Channels

-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-{l3
SN74ACT2236
1024x9x2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A- APRIL 1990- REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
Almost full/almost empty flags. The almost-full/almost-empty A flag (AF/AEA) is defined by the
AF/AEA, almost-full/almost-emptyoffset value for FIFO A (Xl. AF/AEA is high when FIFO A contains X or less
15,30 0
AF/AEB words or 1024-X words. AF/AEA is low when FIFO A contains between X + 1 or 1023 - X words.
The operation of the almost-full/almost-empty B flag (AF/AEBl is the same as AF/AEA for FIFO B.
AD-AS 4-S, 10-13 I/O A data inputs and outputs
32-35,
BO-BS I/O B data inputs and outputs
37-41
Oefine-f1ag inputs. The high-to-Iow transition of OAF stores the binary value on AD-AS as the
OAF,OBF 21,24 I almost-full/almost-empty offset value for FI FO A (Xl. The high-to-Iow transition of OBF stores the
binary value of BO-BS as the almost-fuIValmost-empty offset value for FIFO B (Yl.
EMPTYA, Empty flags. EMPTYA and EMPTYB are low when their corresponding memories are empty and high
20,25 0
EMPTYB when they are not empty.
FULLA, Full flags. FULLA and FULLB are low when their corresponding memories are full and high when they
18,27 0
FULLB are not full.
Half-full flags. HFA and HFB are high when their corresponding memories contain 512 or more
HFA, HFB 16,29 0
words, and low when they contain 511 or less words.
Load clocks. Oata on AO-AS is written into FIFO A on a low-to-high transition of LOCKA. Oata on
LOCKA,
17,2S I BO-BS is written into FIFO B on a low-to-high transition of LOCKB. When the FIFOs are full, LOCKA
LOCKB
and LOCKB have no effect on the data residing in memory.
Enable inputs. OIR and OE control the transceiver functions. When OE is high, both AD-AS and
BO-BS are in the high-impedance state and can be used as inputs. With OE low and OIR high, the
OIR,OE 2,43 I
A bus is in the high-impedance state and B bus is active. When both OE and OIR are low, the A bus
is active and the B bus is in the high-impedance state.
Reset. A reset is accomplished in each direction by taking RSTA and RSTB low. This sets EMPTYA,
RSTA,RSTB 22,23 I
EMPTYB, FULLA, FULLB, and AF/AEB high. Both FIFOs must be reset upon power up.
Select-control inputs. SAB and SBA select whether real-time or stored data is transferred. A low level
SAB,SBA 1,44 I selects real-time data, and a high level selects stored data. Eight fundamental bus-management
functions can be performed as shown in Figure 1.
Unload clocks. Oata in FIFO A is read to BO-BS on a low-to-high transition of UNCKB. Oata in FIFO
UNCKA,
19,26 I B is read to AO-AS on a low-to-high transition of UNCKB. When the FIFOs are empty, UNCKA and
UNCKB
UNCKB have no effect on data residing in memory.

programming procedure for AF/AEA

The aimost-fuil/almost-empty flags (AF/AEA, AF/AEB) are programmed during each reset cycle. The
aimost-fuil/almost-empty offset value FIFO A (X) and for FI FO B (V) are either a user-defined value or the default
values of X = 256 and V = 256. Below are instructions to program AF/AEA using both methods. AF/AEB is
programmed in the same manner for FIFO B.
user-defined X
Take OAF from high to low. This stores AD thru A8 as X.
If RSTA is not already low, take RSTA high.
With OAF held low, take RSTA high. This defines the AF/AEA flag using X.
To retain the current offset for the next reset, keep OAF low.
default X
To redefine the AF/AE flag using the default value of X = 256, hold OAF high during the reset cycle.

~TEXAS
INSTRUMENTS
5-64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 timing diagram for FIFO At

R~~ ~
I II~
OAF I ~~O;'r~+~ W~
LOCKA ~~~~r-fl III
_
~~i_1
AO-A8~tt~~~;ijt~~C ~r::~€0~'£~~~ xIII
I
I
I I I
»
~
I I I I I I I I z
(')
UNCKAII I I I Inn n n nil
~
o I I I I I I i ~H Yr-; Yr-j YT"-1 1 -t-I-----
1.............
:::E:
:a
o
~z4r
3 11 :1: I I~I~I I~I ~I * II
~ ~

i~~
QO _ Q8 Invalid Word 1 WOrd Ord Word Word WOrd
~
WOrd Word Invalid c:
. . • 2 257 258 513 514 768 789 1024 "t......,.-_ _ en
I I I UJ

~~~ EMPTYA -+J

! I
I

II
I
I
I I I
I

p----+---+---
6
$
m

~~ I ~
I
I
FULLA. U
I I I
I
I I
I
I
I
oz

HFA
I
I I
I I
I
I
I
I
:
C/l»
S1r-
C/l"TI
i$
II
I I :ren
>-;-1
I ~I____I_ _~~-+ "0_
;!lz
AF/AEA I I I r_
u>"TI
~$
I I I Set Flag to
I I I IEmpty + XlFull-X ~~
S •
I I I I fflO en
Set Flag to Empty + 256/ Empty + 256 Full - 256 Full - 256 Half Full Empty + 256 Empty Load X Into cc: .... z
Full- 256 (default) Half Full Full Flag Register
ffl-to ......
"O,.~~
(0 S X S 511) iil;:.~»
;:m x (')
1Ri: ..... -t
*t
Operation of FIFO B is identical to that of FIFO A.
Last valid data stays on outputs when FIFO goes empty due to a read.
:JJO-~
- X ~
~ ~:a-<
'"
(0)
~O)
SN74ACT2236
1024x9x2
ASYNCHRONOUS BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995

BusA BusB BusA BusB

SAB SBA DIR OE SAB SBA DIR OE

L X H L X X X H

BusA Bus B BusA BusB

SAB SBA DIR OE SAB SBA DIR OE

X L L L H X H L

BusA BusB

SAB SBA DIR OE

X H L L

Figure 1. Bus-Management Functions

~TEXAS
INSTRUMENTS
5-66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT2236
1024 x9x2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995

SELECT-MODE CONTROL TABLE

CONTROL OPERATION
SAB SBA A BUS BBUS
L L Real-time B to A bus Real-time A to B bus
L H FIFO B to A bus Real-time A to B bus
H L Real-time B to A bus FIFO A to B bus
H H FIFO B to A bus FIFO A to B bus

OUTPUT-ENABLE CONTROL TABLE

CONTROL OPERATION
DIR OE A BUS BBUS
X H Input Input
L L Output Input
H L Input Output

Figure 1. Bus-Management Functions (Continued)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage: Control inputs .................................................................. 7 V
I/O ports ................................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range, TA .......................... . . . . . . . . . .. . . . . . . .. .. O°C to 70°C
Storage temperature range, Tstg .................................................... -65°C to 150°C
Maximum junction temperature, TJ .....,.................................................... 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage tothe device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-67
SN74ACT2236
1024 x 9 x 2
ASYNCHRONOUS BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS149A- APRIL 1990- REVISED SEPTEMBER 1995

recommended operating conditions

'ACT2236-20 'ACT2236-30 'ACT2236-40 'ACT2236-60
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 2 V
VIL Low-level input voltage O.S O.S O.S O.S V
High-level output cur- A or B ports -S -S -S -S
IOH mA
rent Status flags -S -S -S -S
A or B ports 16 16 16 16
IOL Low-level output current mA
Status flags S S S S
LDCKA or LDCKB 50 33 25 16.7
fclock Clock frequency MHz
UNCKA or UNCKB 50 33 25 16.7
RSTA or RSTB low 20 20 25 25
LDCKA or LDCKB low S 10 14 20
LDCKA or LDCKB high S 10 14 20
tw Pulse duration ns
UNCKA or UNCKB low S 10 14 20
UNCKA or UNCKB high S 10 14 20
DAF or DBF high 10 10 10 10
Data before LDCKA or
4 4 5 5
LDCKBl'
Define AF/AE: DO-DS
5 5 5 5
before DAF or DBFJ,
Define AF/AE: DAF or
DBFJ, before RSTA or 7 7 7 7
tsu Setup time RSTBl' ns
Define AF/AE (default):
DAF or DBF high before 5 5 5 5
RSTA or RSTBl'
RSTA or RSTB inactive
(high) before LDCKA or 5 5 5 5
LDCKBl'
Data after LDCKAor
1 1 2 2
LDCKBl'
Define AF/AE: DO-DS
0 0 0 0
after DAF or DBFJ,

Hold time Define AF/AE: DAF or ns

th
DBF low after RSTA or 0 0 0 0
RSTBl'
Define AF/AE (default):
DAF or DBF high after 0 0 0 0
RSTA or RSTBl'
TA Operating free-air temperature 0 70 0 70 0 70 0 70 °c

~TEXAS
INSTRUMENTS
5-6S POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT2236
1024 x 9 x 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VOH VCC =4.5V, 10H=-SmA 2.4 V
I Flags VCC = 4.5 V, 10L= SmA 0.5
V
VOL
1110 ports VCC =4.5V, 10L= 16 mA 0.5
II VCC = 5.5 V, VI = VCC orO ±5 !iA
10Z VCC =5.5V, Vo=VccorO ±5 !iA
ICC:!: VI = VCC - 0.2 V or 0 10 400 !iA
§ I DIR, OE One input at 3.4 V, Other inputs at VCC or GND
2
mA
VCC = 5.5 V,
AICC lather inputs 1
Ci VI =0, f= 1 MHz 4 pF
Co Vo=O, f= 1 MHz 8 pF
t All tYPical values are at VCC = 5 V, TA = 25°C.
:!: ICC tested with outputs open.
§ This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 50 pF (unless otherwise noted) (see Figures 4 and 5)
FROM TO 'ACT2236-20 'ACT2236-30 'ACT2236-40 'ACT2236-60
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYpt MAX MIN MAX MIN MAX MIN MAX
LDCK 50 33 25 16.7
f max MHz
UNCK 50 33 25 16.7
too LDCKi, LDCKBi BorA 8 23 8 23 8 25 8 27 ns
UNCKAi,
tpd BorA 10 17 25 10 25 10 35 10 45 ns
UNCKBi
EMPTYA,
tpLH LDCKi, LDCKBi 4 15 4 15 4 17 4 19 ns
EMPTYB
UNCKAi, EMPTYA,
tpHL 2 17 2 17 2 19 2 21 ns
UNCKBi EMPTYB
EMPTYA,
tPHL RSTA1,RSTBl 2 18 2 18 2 20 2 22 ns
EMPTYB
tpHL LDCKi, LDCKBi FULLA, FULLB 4 15 4 15 4 17 4 19 ns
UNCKAi,
tpLH FULLA, FULLB 4 15 4 15 4 17 4 19 ns
UNCKBi
tpLH RSTA1,RSTBl FULLA, FULLB 2 15 2 15 2 17 2 19 ns
tpLH RSTAl, RSTBl AF/AEA, AF/AEB 2 15 2 15 2 17 2 19 ns
tPLH LDCKi, LDCKBi HFA, HFB 2 15 2 15 2 17 2 19 ns
UNCKAi,
tpHL HFA, HFB 4 19 4 19 4 21 4 23 ns
UNCKBi
tPHL RSTAl, RSTBl HFA,HFB 1 15 1 15 1 17 1 19 ns
tpd SAB orSBAIf B or A 1 11 1 11 1 13 1 15 ns
tpd Aor B B or A 1 11 1 11 1 13 1 15 ns
tpd LDCKi, LDCKBi AF/AEA, AF/AEB 2 19 2 19 2 21 2 23 ns
UNCKAi,
tpd AF/AEA, AF/AEB 2 19 2 19 2 23 2 23 ns
UNCKBi
ten DIR,OE AorB 2 12 2 12 2 14 2 16 ns
!dis DIR,OE A or B 1 10 1 10 1 12 1 14 ns
t All tYPical values are at VCC = 5 V, TA = 25°C.
If These parameters are measured with the internal output state of the storage register opposite to that of the bus input.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • PALLAS. TEXAS 75265 5-69
SN74ACT2236
1024 x 9 x 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST·OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995

operating characteristics, VCC =5 V, TA =25°C

PARAMETER TEST CONDITIONS TYP UNIT

Power dissipation capacitance per 1K bits

I Outputs enabled CL = 50 pF, f = 5 MHz
71
pF
Cpd
I Outputs disabled 57

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME POWER DISSIPATION CAPACITANCE
vs vs
LOAD CAPACITANCE SUPPLY VOLTAGE
typ+2
VCC~5V VCC=5V
r- TA =25°C V" ,,/
IL
a. 11 = 5 MHz
RL =5000 TA = 25°C
In typ+6 / 8
I
Iyp + 1
./
I:
V I:
,,/
t
I
G)
E
/ /"
V
;;. typ + 4 ~ typ
/
.l!!
~ /
I:
0
:;a. V
I:
,g typ+2 / 'iii
In lyp-1 ./
V
I
11.
I typ /
/ Ci

!
11.
I lyp-2
V
,,/

J. / "a.
0
I
typ -2 typ -3
o 50 100 150 200 250 300 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5
CL - Load Capacitance - pF VCC - Supply Voltage - V

Figure 2 Figure 3

calculating power dissipation

The maximum power dissipation (PT) can be calculated by:
PT = Vec x [ICC + (N x ~Ice x dc)] + :E(Cpd x VCC2 x fi) + :E(CL x VCC2 x fa)
where:
Icc = power-down Icc maximum
N = number of inputs driven by a TTL device
~lcC = increase in supply current
dc = duty cycle of inputs at a TTL high level of 3.4 V
Cpd = power dissipation capacitance
CL = output capacitive load
fi = data input frequency
fa = data output frequency

~TEXAS
INSTRUMENTS
5-70 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT2236
1024 x 9 x 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

Input L \ -:;:~--- 3V

Fr~~d~~::=n ---11 I· GND

RL=500n T CL=50pF
tpd --t4I~-~~
:
-
I
14
I
~tpd

-- - -
Output
_ _ _ _..I
I I ,.---~~t-
1.5V
3V
OV

LOAD CIRCUIT TOTEM· POLE OUTPUTS

Figure 4. Standard CMOS Outputs (All Flags)

3V
Input \ 1 . 5 V j1.5V
1-------- OV
I Vcc
1
tpzL ....1
1
I+-
I
....1 I+-tPLZ
I I =vcc

-r-i r:~~~~
I I
Output \1.5V I
From Output RL I
S1 1 I VOL
Under Test
I tPHZ --+I I+-t
T
-::
CL 1S2 Output
tpZH -+i 14-
11.5V
I

t O.3V J
t... VOH

":" =OV

LOAD CIRCUIT VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PARAMETER RL CLt S1 S2
tpZH Open Closed
ten 500n 50pF
tpZL Closed Open
tpHZ Open Closed
'dis 500n 50pF
tpLZ Closed Open
tpd ortt - 50pF Open Open
t Includes probe and test·fixture capacitance

Figure 5. 3-State Outputs (AO-AS, BO-BS)

-!!11ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-71
5-72
 SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST·OUT MEMORIES
I

• Reads and Writes Can Be Asynchronous DV OR NP PACKAGE

(TOP VIEW}
or Coincident
• Organization: VCC
- SN74ACT7203L - 2048 x 9 04
- SN74ACT7204L - 4096 x 9 05
- SN74ACT7205L-8192x9 06
- SN74ACT7206L -16383 x 9
07
• Fast Data Access Times of 15 ns 00 FLIRT
• Read and Write Frequencies up to 40 MHz XI RS
• Bit-Width and Word-Depth Expansion FF EF
• Fully Compatible With the IDT7203/7204 00 9 XO/HF
01 07
• Retransmit Capability 02 06
• Empty, Full, and Half-Full Flags 03 05
• TTL-Compatible Inputs 08 04
• Available In 28-Pln Plastic DIP (NP), Plastic GNO R
Smail-Outline (DV), and 32-Pln Plastic
J-Leaded Chip-Carrier (RJ) Packages RJPACKAGE
(TOP VIEW}
description t')co C) 0...,. Ltl
0013: z ~O 0
These devices are constructed with dual-port
SRAM and have internal write and read address 4 3 2 1 3231 30
02 5 0 29 06
counters to provide data throughput on a first-in, 28 07
first-out (FIFO) basis. Write and read operations 27
7 NC
are independent and can be asynchronous or
8 26
coincident. Empty and full status flags prevent
25
underflow and overflow of memory, and
10 24
depth-expansion logic allows combining the
23 XO/HF
storage cells of two or more devices into one
FIFO. Word-width expansion is also possible. 12 22 07
06
Data is loaded into memory by the write-enable
(W) input and unloaded by the read-enable (R)
input. Read and write cycle times of 25 ns
(40 MHz) are possible with data access times of
NC - No internal connection
15 ns.
These devices are particularly suited for providing a data channel between two buses operating at
asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in .
data-acquisition systems, temporary storage elements between buses and magnetic or optical memories, and
queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus
a parity bit or packet-framing information. The read pOinter can be reset independently of the write pointer for
retransmitting previously read data when a device is not used in depth expansion.
The SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, and SN74ACT7206L are characterized for operation
from O·C to 70·C.

Copyright <C> 1995, Texas Instruments Incorporated

~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-73
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9, 4096 x 9, 8192 x 9, 16384 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

SN74ACT7203L logic symbolt

FIF02048x9
cp
SN74ACT7203L
22 "- 2,4 CT = 0 (RST)
RS
1 8
W 6(WR PNTR) 2(CT = 2047) 06

7
C I>
02
6C1

"- (EXPAND)
4(CT = 2047) 06
(CT = 2048) 06 t1
Xi 21
23 (CT= 0) 05
FLIRT "- (1ST LOAD)
G 2,4 (REXMIT) (EXPAND)
20
15
W
e .,"-
5EN3
04
5(RDPNTR)

(CT = WR PNTR - RD PNTR)

CT> 1024

6
r 9
DO 10 3V QO
5 10
01 Q1
4 11
02 Q2
3 12
03 Q3
27 16
04 Q4
26 17
05 Q5
25 18
06 Q6
24 19
07 Q7
2 13
08 Q8

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the DV and NP packages.

~TEXAS
INSTRUMENTS
5-74 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9, 4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

SN74ACT7204L logic symbolt

FIFO 4096 x 9
<t>
SN74ACT7204L
22 r--
1
2,4 CT =0 (RST) 8
6(WR PNTR) 2(CT =4095) G6
C P. 6 C1
G2
4(CT
(eT
=4095) G6
=4096) G6 ~
7 r--.
Xi (EXPAND) 21
23
"- (1ST LOAD)
(eT =0) G5
FLIRT
L, 2,4 (REXMIT) (EXPAND)
20
15 r--. ~

e
5 (RDPNTR) eT > 2048
5EN3
G4

DO
6
.,
10
(eT =WR PNTR - RD PNTR)
3'7
r 9
QO
5 10
01 Q1
4 11
02 Q2
3 12
03 Q3
27 16
04 Q4
26 17
05 Q5
25 18
06 Q6
24 19
07 Q7
2 13
08 Q8

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-75
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9, 4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

SN74ACT7205L logic symbolt

FIFO 8192 x 9
<I>
SN74ACT7205L
22 r--
RS
1
2,4 CT =0 (RST) 8
W 6 (WRPNTR) 2(CT =8191) G6

7
t= r--
>
G2
6C1

(EXPAND)
'!(CT=8191) G6
(CT =8192) G6 t=f
21
23 r--
(CT =0) G5
(1ST LOAD)
G 2,4 (REXMIT) (EXPAND)
20
XO/HF
15
W
e
-i"- S (RD PNTR) CT>4096
5EN3
G4

6
, (CT =WR PNTR - RD PNTR)
i 9
DO 10 3<;7 QO
5 10
01 Q1
4 11
02 Q2
3 12
03 Q3
27 16
04 Q4
26 17
05 Q5
25 18
06 Q6
24 19
07 Q7
2 13
08 Q8

t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the DV and NP packages.

~TEXAS
INSTRUMENTS
5--76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9, 4096 X 9, 8192 X 9, 16384 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A- FEBRUARY 1993 - REVISED SEPTEMBER 1995

SN74ACT7206L logic symbolt

FIFO 16384 x 9
~
SN74ACT7206L
22
AS
1
" 2,4 CT =0 (RST)
8
W 6(WRPNTR) 2(CT = 18383) G6

7
C P.
G2
6C1 4(CT = 16383) G6
(CT = 16384) G6 ~
Xi
23
" (EXPAND)
(CT =0) G5
21

FLIRT " (1ST LOAD)

L..t:. 2,4 (REXMIT) (EXPAND)
20
XO/HF
15
W
e, " 5(RDPNTR)
5EN3
G4
(~ =WR PNTR -
CT >8192

RD PNTR)

6
r 9
DO 1D 3V QO
5 10
D1 Q1
4 11
D2 Q2
3 12
D3 Q3
27 16
D4 Q4
26 17
D5 Q5
25 18
D6 Q6
24 19
D7 Q7
2 13
D8 Q8

t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the DV and NP packages.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 s-n
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9,4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

functional block diagram

9
00-08 Location 1
Location 2

w I Write
I Control I
I I
I
Write
Pointer
r---...
2048 x 9 or
4096 x 9 or
8192x90r
16384 x 9
H Read
Pointer
I
t ..
RAMt
~
9
QO-Q8

I
Reset
Logic
I
I
J
~ Status-
Flag

~ Read
Control
I
I
r Logic

I
I
Expansion
XO/HF
Logic

t 2048 x 9 for SN74ACT7203L; 4096 x 9 for SN74ACT7204L; 8192 x 9 for SN74ACT7205L; 16384 x 9 for SN74ACT7206L
RESET AND RETRANSMIT FUNCTION TABLE
(single-device depth; single-or multiple-device width)

INPUTS INTERNAL TO DEVICE OUTPUTS

FUNCTION
RS FURT XI READ POINTER WRITE POINTER EF FF XO/HF
L X L Location zero Location zero L H H Reset device
H L L Location zero Unchanged X X X Retransmit
H H L Increment if EF high Increment if FF high X X X Read/write

RESET AND FIRST-LOAD FUNCTION TABLE

(multiple-device depth; single-or multiple-device width)

INPUTS INTERNAL TO DEVICE OUTPUTS

FUNCTION
RS FLIRT XI READ POINTER WRITE POINTER EF FF
L L :j: Location zero Location zero L H Reset first device
L H :j: Location zero Location zero L H Reset all other devices
H X :j: X X X X Read/write
:j:XIIS connected to XO/HF of the prevIous device In the daisy chain (see Figure 15).

~TEXAS
INSTRUMENTS
5-78 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9,4096 x 9,8192 x 9, 16384 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME
DO-D8 I Data inputs
Empty-flag output. EF is low when the read pointer is equal to the write pointer, inhibiting any operation initiated by a read
EF 0 cycle. When the FIFO is empty, a data word can be read automatically at aO-a8 by holding R low when loading the data
word with a low-level pulse on W.
Full-flag output. FF is low when the write pointer is one location less than the read pointer, indicating that the device is
full and inhibiting any operation initiated by a write cycle. FF goes low when the number of writes after reset exceeds the
FF 0 number of reads by 2048 for the SN74ACT7203L, 4096 for the SN74ACT7204L, 8192 for the SN74ACT7205L, and
16384 for the SN74ACT7206l. When the FIFO is full, a data word can be written automatically into memory by holding
VIi low while reading out another data word with a lOW-level pulse on R.
First-load/retransmit input. FURT performs two separate functions. When cascading two or more devices for word-depth
expansion, FLIRT is tied to ground on the first device in the daisy chain to indicate that it is the first device loaded and
unloaded; it is tied high on all other devices in the depth-expansion chain.
A device is not used in depth expansion when its expansion-in (Xi) input is tied to ground. In that case, FURT acts as
FLIRT I a retransmit enable. A retransmit operation is initiated when FLIRT is pulsed low. This sets the internal read pointer to
the first location and does not affect the write pointer. R and VIi must be at a high logic level during the low-level FLIRT
retransmit pulse. Retransmit should be used only when less than 2048/4096 writes are performed between resets;
otherwise, an attempt to retransmit can cause the loss of unread data. The retransmit function can affect XO/HF
depending on the relative locations of the read and write pointers.
GND Ground
aO-a8 0 Data outputs. aO-a8 are in the high-impedance state when R is high or the FIFO is empty.
Read-enable input. A read cycle begins on the falling edge of R if EF is high. This activates aO-a8 and shifts the next
data value to this bus. The data outputs return to the high-impedance state as R goes high. As the last stored word is
R I
read by the falling edge ofR, EFtransitions low but aO-a8 remain active until R returns high. When the FIFO is empty,
the internal read pointer is unchanged by a pulse on R.
Reset input. A reset is performed by taking RS low. This initializes the internal read and write pointers to the first location
RS I and sets EF low, FF high, and HF high. Both R and VIi must be held high for a reset during the window shown in Figure 7.
A reset is required after power up before a write operation can take place.
VCC Supply voltage
Write-enable input. A write cycle begins on the falling edge of W if FF is high. The value on DO-D8 is stored in memory
VIi I
as VIi returns high. When the FIFO is full, FF is low inhiMing VIi from performing any operation on the device.
Expansion-in input. XI performs two functions. XI is tied to ground to indicate that the device is not used in depth
Xi I expansion. When the device is used in depth expansion, Xi is connected to the expansion-out (XO) output of the previous
device in the depth-expansion chain.
Expansion-outlhalf-full-flag output. XO/HF performs two functions. When the device is not used in depth expansion (Le.,
when Xi is tied to ground), XO/HF indicates when half the memory locations are filled. After half of the memory is filled,
the falling edge on VIi for the next write operation drives XO/HF low. XO/HF remains low until a rising edge of R reduces
XO/HF 0 the number of words stored to exactly half of the total memory.
When the device is used in depth expansion, XO/HF is connected to Xi olthe next device in the daisy chain. XO/HF drives
the daisy chain by sending a pulse to the next device when the previous device reaches the last memory location.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265 5-79
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9,4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A- FEBRUARY 1993 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range (any input), VI .................................................... -0.5 V to 7 V
Continuous output current, 10 .............................................................. 50 mA
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. DoC to 70°C
Storage temperature range, Tstg .................................................. -55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under '"recommended operating conditions'" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
IXI 2.6
VIH High-level input voltage V
I Other inputs 2
Vil low-level input voltage 0.8 V
IOH High-level output current -2 mA
IOL low-level output current 8 mA
TA Operating free-air temperature 0 70 °C

electrical characteristics over recommended operating free-air temperature range, Vee = 5.5 V
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VOH VCC=4.5 V, IOH =-2 mA 2.4 V
VOL VCC = 4.5 V, IOl=8mA 0.4 V
IOZH VO=VCC, R;;"VIH ±10 IlA
IOZl VO= 0.4 V, R;;"VIH ±10 vA
II VI = Ot05.5 V -1 1 IlA
ICC1:j: fclock = 20 MHz 120 mA
ICC2:j: R, W, RS, and FURT at VIH 12 mA
ICC3:j: VI =VCC-0.2V 2 mA
Ci§ VI =0, TA = 25°C, f = 1 MHz 10 pF
C o§ VO=O, TA = 25°C, f = 1 MHz 10 pF
:j: ICC1 = supply current; ICC2 = standby current; ICC3 = power-down current. ICC measurements are made with outputs open (only capacitive
loading).
§ This parameter is sampled and not 100% tested.

~1ExAs
INSTRUMENTS
5-80 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9, 4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
'ACT7203L-15 ' ACT7203L-25 'ACT7203L-50
'ACT7204L-15 'ACT7204L-25 'ACT7204L-50
FIGURE 'ACT7205L-15 ' ACT7205L-25 'ACT7205L-50 UNIT
'ACT7206L-15 'ACT7206L-25 'ACT7206L-50
MIN MAX MIN MAX MIN MAX
fclock Clock frequency, R or W 40 28.5 15 MHz
te(R) Cycle time, read 1(a) 25 35 65 ns
tc(W) Cycle time, write 1(b) 25 35 65 ns
tc(RS) Cycle time, reset 7 25 35 65 ns
tc(RT) Cycle time, retransmit 4 25 35 65 ns
tw(Rl) Pulse duration, R low 1(a) 15 25 50 ns
tw(Wl) Pulse duration, W low 1(b) 15 25 50 ns
tw(RH) Pulse duration, R high 1(a) 10 10 15 ns
tw(WH) Pulse duration, W high l(b) 10 10 15 ns
tw(RT) Pulse duration, FLJRT low 4 15 25 50 ns
tw(RS) Pulse duration, RS low 7 15 25 50 ns
tw(XILl Pulse duration, XI low 10 15 25 50 ns
tw(XIH) Pulse duration, XI high 10 10 10 10 ns
tsu(D) Setup time, data before Wi l(b),6 11 15 30 ns
tsu(RT) Setup time, Rand W high before FLiRTit 4 15 25 50 ns
tsu(RS) Setup time, Rand W high before Rsit 7 15 25 50 ns
tsuCXI-Rl Setup time, XI low before RJ- 10 10 10 15 ns
tsuCXI-W) Setup time, XI low before wJ- 10 10 10 15 ns
th(D) Hold time, data after wi l(b),6 0 0 5 ns
th(E-R) Hold time, R low after EFi 5,11 15 25 50 ns
th(F-W) Hold time, W low after FFt 6, 12 15 25 50 ns
th(RT) Hold time, Rand W high after Fl/RTi 4 10 10 15 ns
th(RS) Hold time, Rand W high after Rsi 7 10 10 15 ns
t These values are characterized but not currently tested.

~1EXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-81
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, .SN74ACT7206L
2048 x 9,4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 13)
'ACT7203L·15 'ACT7203L·25 'ACT7203L-50
'ACT7204L·15 'ACT7204L·25 'ACT7204L-50
PARAMETER FIGURE 'ACT7205L·15 'ACT7205L·25 'ACT7205L·50 UNIT
'ACT7206L·15 'ACT7206L·25 'ACT7206L·50
MIN MAX MIN MAX MIN MAX
ta Access time, RJ. or EFi to data out valid 1(a),3,5 15 25 50 ns
tv(RH) Valid time, data out valid after Ri 1(a) 5 5 5 ns
Enable time, RJ. to Q outputs at
ten(R-QX) 1(a) 5 5 10 ns
low impedancet
Enable time, Wi to Q outputs at
ten(W-QX) 5 5 5 15 ns
low impedancett
Disable time, Ri to Q outputs at
tdis(R) 1(a) 15 18 30 ns
high impedancet
Pulse duration, FF high in
tw(FH) 6 15 25 45 ns
automatic-wrHe mode
Pulse duration, EF high in
tw(EH) 5 15 25 45 ns
automatic-read mode
tpd(W-F) Propagation delay time, WJ. to FF low 2 15 25 45 ns
tpd(R-F) Propagation delay time, Ri to FF high 2,6,12 15 25 45 ns
tpd(RS-F) Propagation delay time, RSJ. to FF high 7 .25 35 65 ns
Propagation delay time, RSJ. to XO/HF
tpd(RS-HF) 7 25 35 65 ns
high
tpd(W-E) Propagation delay time, Wi to EF high 3,5,11 15 25 45 ns
tpd(R-El Propagation delay time, RJ. to EF low 3 15 ' 25 45 ns
tpd(RS-E) Propagation delay time, RSJ. to EF low 7 .25 35 65 ns
Propagation delay time, WJ. to XOIHF
tpd(W-HF) 8 25 35 65 ns
low
Propagation delay time, Ri to XO/HF
tpd(R-HF) 8 25 35 65 ns
high
Propagation delay time, RJ. to XO/HF
tpd(R-XOL) 9 15 25 50 ns
low
Propagation delay time, WJ. to XO/HF
tpd(W-XOL) 9 15 25 50 ns
low
Propagation delay time, Ri to XO/HF
tpd(R-XOH) 9 15 25 50 ns
high
Propagation delay time, Wi to XO/HF
tpd(W-XOH) 9 15 25 50 ns
high
Propagation delay time,
!Pd(RT-FL) 4 25 35 65 ns
FURTJ. to HF, EF, FF valid
t These values are charactenzed but not currently tested.
:j: Only applies when data is automatically read

~TEXAS
INSTRUMENTS
5-82 POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
 SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9, 4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

I.~ twIRL) ---'I

1....- _ - tc(R) _ _ _.......
I I
I I I I
I I 14 ~tw(RH) I I
fc--ta~: ~ta~:
R- . . . .\ i k--'\ i '1-------
I I 1
ten(R-QX) .~: I j4- tw(RH) ~: : 14--- tdls(R) ~

QO-Q8 ---------~~ __v_a_lId_____ ~~--~-II-d---~~1 -----

(a) READ

~ tc(W) .:
I I
14 tw(WL) ~i4- tw(WH) ~
I I 1

w - , , ' - -_ _ ---J{' '\10..-_ _---11

1 I
jC- tsu(O) . . th(O) -ti1
DO -08 __________......( Valid »)-1 ------«\-___v_a_lId____...I)>----

(b) WRITE

Figure 1. Asynchronous Waveforms

I I I
I Ignored I I
Last Write First Read Additional Reads
I Write I I
I
R I IV IV
I
I I
I I
I
W
'\ I
Il\.J I
I
I
I..
14 ~ tpd(W-F) I tpd(R-F) ~
I I I I
FF
\ I
I I
Figure 2. Full-Flag Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-83
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9, 4096 x 9, 8192 x 9,16384 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

I I
Last Read
I Ignored I Additional Writes
I Read I First Write

W---+----------~i------~~~~---------~
I I I
I I I
~ ~-I~:---+:~----------------
I I

EF
"-
I
---+-+:----..\:
I
I+-ta~
~
I
tpd(R-E) I
I

~---ri--------~i

I
I
I
:______
I
i4~-I---""~01-
I

~---J
,r----------
I
tpd(W-E)

i I I
00-08 --~------~------~I------~----------------------
Figure 3_ Empty.Flag Waveforms

W,R ~
·"~~~~JI
I
:
'x1\-
I~------------------
: ~ tsu(RT) ~ th(RT) ~
XO/HF, EF, FF~----------v:-al-Id-F-Iag---------

I :
jill tpd(RT-FL) .1
NOTE A: The EF, FF, and XO/HF status flags are valid after completion of the retransmit cycle.

Figure 4. Retransmit Waveforms

~TEXAS
INSTRUMENTS
5-84 POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9,4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST·IN, FIRST-OUT MEMORIES
SCAS226A- FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

w \'--_--J{
1
i+-- th(E-R) -----.:
1
1
1
i y~-------

I I
1 1
1 1,..-_.....
f '\
EF
---------+-!-----' ~
tpd(W-E) j'4
1

.[4
tw(EH) ..

~ ta
I'------------
ten(W-QX) ~ I+- 1
I I __---~
QO-Q8 ----------~ Valid )>-------
Figure 5_ Automatic-Read Waveforms

R~ {
1 104--- th(F-W) ~
w
1
1
1
i
y~---------
----------------~----~I----------~·I
I
14----~~-
1411 tpd(R-F) 1
1 1

----------------~l ~~!----------
FF

~tw(FH) ~ 1

~ I4- t h(D)
DO-D8----------------~(~-V-al-id--~)~1_ _ _ _ _ __
I I
j4-- tsu(O) ~

Figure 6. Automatic-Write Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5-85
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9, 4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

~
14
le(RS)
tw(RS) -----~.I
----1-----..:.: 1
~ ~ l'~--~:--------
_______________________JI
RS j\
I
. 1

1 1
1 ! 1
~~~~~~~~~~~

W
1 1
:
1
1\I~----------

R i i
1 1 1 1
1 tsu(RS) -t4r4--".1144--"'~+-- th(RS)

EF

14-- tpd(RS-E) ~

XO/HF.FF~
1 1
14--- tpd(RS-HF) ~
14--- tpd(RS-F) ~
Figure 7. Master·Reset Waveforms

Half Full or Less 1 More Than Half Full 1 Half Full or Less
1 1
1
W
\1 / 1
1
I
14
1 ~ tpd(R-HF)

1 1
R 1
1
.1
\ Y1 1
I
~ tpdCW-HF) 1 1
I 1
1
XO/HF
'\ 1
I )I
Figure 8_ Half·Full Flag Waveforms

~TEXAS
INSTRUMENTS
5-86 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9,4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

Write to Last
W Physical Location

1 1~ Read From Last

1 ) Physical Location L
1 tpd(W-XOH) --j4---+I 1 fI
~ ~14--t•.;-.: tpd(R-XOL)
XO/HF - "
tpd(W-XOL)

r'; '\
1

Figure 9. Expansion-Out Waveforms

1.
4.1----t.0I-1

)t
tpd(R-XOH)

~ '.",ILI + '."""1 ,~
X1 } ...._ _ _ ..J)!---~) } . . .___ --.J
1
I.. .1 tsu(XI-W) 1

---"" 1 Write to First 1-1-1- - - - - - - - - - - - -

W Physical Location 1
~i4--"~f- tsu(XI-RI
1

I
';''1-,- - - " Read From First
"\ Physical Location

Figure 10. Expansion-In Waveforms

W \"--_ _ _ _1
tpd(W-E) H
EF _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J AI~----------
1
1

..- - - t
141 •.;-.: th(E-R)
R 1
Figure 11. Minimum Timing for an Empty-Flag Coincident-Read Pulse

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-87
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9,4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

R \ I I
tpd(R-F) i'4 ~
FF A'~-----------

w~~~~~~~~~~~
114-
j
.. - -....;-1 th(F-W)

Figure 12. Minimum Timing for a Full-Flag Coincident-Write Pulse

~1ExAs
INSTRUMENTS
5-88 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9,4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

SV

11000
From Output
Under Test - - e - - - -__

6800 30pF
(see Note A)

LOAD CIRCUIT

-If~~.~-
Timing _of 3V High-Level 3V
Input ______ Jr ~ ~ __ _
J~ GND Input ..~. ~ GND

tsu~th ~ tw ---+I
I I
Data, ~ :-..-:; - 3V
Enable ~1.SV ~ Low-Level ~ 1.SV ~ 3V
Input GND Input ~ ~~.:... _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

3V
Output
Enable -.Il.L1.S V GND
~ l-4-tPLZ
=3V
Low-Level I I ---.....,..... 3V
Output I
--t-.JI
I
I VOL
Input ~1.5V )..~S~--
GND
---.I ~tPZH ~tpd
VOH tpd --t4--+I
High-Level I
Output

~
I I
I I
l-4-tpHZ
=OV
In-Phase
Output 11.5 V
~
VOH

VOL

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 13. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-89
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9, 4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION

Combining two or more devices to create one FIFO with a greater number of memory bits is accomplished in two
different ways. Width expansion increases the number of bits in each word by connecting FIFOs with the same depth
in parallel. Depth expansion uses the built-in expansion logic to daisy-chain two or more devices for applications
requiring more than 2048, 4096,8192, or 16384 words of storage. Width expansion and depth expansion can be used
together.

width expansion
Word-width expansion is achieved by connecting the corresponding input control to multiple devices with the
same depth. Status flags (EF, FF, and HF) can be monitored from anyone device. Figure 14 shows two FIFOs
in a width-expansion configuration. Both devices have their expansion-in (XI) inputs tied to ground. This
disables the depth-expansion function of the device, allowing the first-load/retransmit (FURT) input to function
as a retransmit (RT) input and the expansion-outlhalf-full (XO/HF) output to function as a half-full (HF) flag.

depth expansion
The SN74ACT7203L17204U7205U7206L are easily expanded in depth. Figure 15 shows the connections
used to depth expand three SN74ACT7203L172041'7205L17206L devices. Any depth can be attained by
adding additional devices to the chain. The SN74ACT7203L17204L17205U7206L operate in depth expansion
under the following conditions:
• The first device in the chain is designated by connecting FL to ground.
• All other devices have their FL inputs at a high logic level.
• XO of each device must be connected to XI of the next device.
• External logic is needed to generate a composite FF and EF. All FF outputs must be ORed together,
and all EF outputs must be ORed together.
• RT and HF functions are not available in the depth-expanded configuration.

combined depth and width expansion

Both expansion techniques can be used together to increase depth and width. This is done by creating
depth-expanded units and then connecting them in a width-expanded configuration (see Figure 16).

~TEXAS
INSTRUMENTS
5-90 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9, 4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION
SN74ACT7203L/7204U7205U7206L

18 00-08 QO-Q8 18
00-018 00-08 QO-Q8 QO-Q18
......... 9 9 ",
W W
R R EF

RT FLIRT FF
RS RS XO/HF

Xi
l
SN74ACT7203L/7204L17205U7206L

09 - 018 Q9-Q18
00-08 QO-Q8
9 9
W
R EF

FLIRT FF
RS XO/HF

Xi
1
Figure 14. Word-Width Expansion: 2048/4096 Words x 18 Bits

-!!I TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-91
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9,4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION
SN74ACT7203L/7204U7205U7206L

9 9 9 9
00-08 00-08 QO-Q8 QO-Q8

W W
R R XO/HF

RS EF
FLIRT FF

r--- XI

SN74ACT7203L/7204U7205U7206L

9 9
00-08 QO-Q8

W
'----';:) ~
R XO/HF I---- --./
RS EF I
VCC FLIRT FF

- XI
I ~
--
f

SN74ACT7203L/7204U7205U7206L

9 9
00-08 QO-Q8

W
R XO/HF -
RS EF
FLIRT FF

f - XI

Figure 15. Word·Depth Expansion: 6144/12288124576/49152 Words x 9 Bits

~ThxAs
INSTRUMENTS
5-92 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 x 9,4096 x 9,8192 x 9,16384 x 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION
QO-Q17 QO-Q26

"r 18 (If'" 27

9 QO-Q8 9 Q9-Q17 9 Q18-Q26

'ACT7203L 'ACT7203L 'ACT7203L

or or or
'ACT7204L 'ACT7204L 'ACT7204L
or or or
W,R,RS 'ACT7205L 'ACT7205L 'ACT7205L
or or or
'ACT7206L 'ACT7206L 'ACT7206L
Oepth- Oepth- Oepth-
Expansion Expansion Expansion
Block Block Block

9 00-08 9 09-017 9 018-026

27 ./ 18 ./
00-026 09-026

Figure 16. Word-Depth Plus Word-Width Expansion

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5-93
5-94
I9-Bit Synchronous FIFOs

6-1
 9·BIT SYNCHRONOUS FIFOS
Features Benefits

• Data I/O employs synchronous control • Allows for simultaneous read and write
architecture
• Multiple-speed sort options • Designflexibility
• Depth from 512 to 4K words • Optimize depth for specific application
• Write and read cycle times of 15 ns • Increased system performance
• Bit-width expandable • Allows interface to larger data-path
architectures
• Empty, full, programmable-empty, and • Multiple status flags to ease design efforts
programmable-full flags
• Compatible to 722X1 pinout • Drop-in replaceable to existing layouts
and designs
• TI has established an alternate source • Standardization that comes from a
common-product approach

en
'<
:l
(")

...
::r
o
:l
o
c
en
::!l
"o
en

6-2
 SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9,2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST·IN FIRST·OUT MEMORIES

• Read and Write Clocks Can Be RJPACKAGE

Asynchronous or Coincident (TOP VIEW)

• Organization: C\JC')-.rLOCO t--co

ClClClClClClCl
- SN74ACT72211L - 512 x 9
- SN74ACT72221L -1024 x 9
- SN74ACT72231 L - 2048 x 9 o
- SN74ACT72241 L - 4096 x 9
• Write and Read Cycle Times of 15 ns
• Bit-Width Expandable Vee
• Empty and Full Flags 10 QS
Q7
• Programmable Almost-Empty and
12 Q6
Almost-Full Flags With Default Offsets
of Empty+7 and Full-7, Respectively 13 21 05
1415 16 17 18 19 20
• TTL-Compatible Inputs
• Fully Compatible With the
IlLlJ.. IlLl..aaaaa
0l.. ~ C\J C') -.r

IOT72211 172221/72231172241
• Available in 32-Pin Plastic J-Leaded
Chip Carrier (RJ)

description
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are constructed with
CMOS dual-port SRAM and are arranged as 512, 1024, 2048, and 4096 9-bit words, respectively. Internal write
and read address counters provide data throughput on a first-in, first-out (FIFO) basis. Full and empty flags
prevent memory overflow and underflow, and two programmable flags (almost full and almost empty) are
provided.
The SN7 4ACT72211 L, SN74ACT72221 L, SN74ACT72231 L, and SN74ACT72241 L are synchronous FIFOs,
which means the data input port and data output port each employ synchronous control. Write-enable (WEN1,
WEN2/LO) signals allow the low-to-high transition of the write clock (WCLK) to store data in memory, and
read-enable (REN1, REN2) signals allow the low-to-high transition of the read clock (RCLK) to read data from
memory. WCLK and RCLK are independent of one another and can operate asynchronously or be tied together
for single-clock operation.
The empty-flag (EF) output is synchronized to RCLK and the full-flag (FF) output is synchronized to WCLK to
indicate absolute boundary conditions. Write operations are prohibited when FF is low, and read operations are
prohibited when EF is low. Two programmable flags, programmable almost empty (PAE) and programmable
almost full (PAF), can both be programmed to indicate any measure of memory fill. After reset, PAE defaults
to empty+7 and PAF defaults to full-7. Flag-offset programming control is similar to a memory write with the
use of the load (WEN2/LO) signal.
These devices are suited for providing a data channel between two buses operating at asynchronous or
synchronous rates. Applications include use as rate buffers for graphics systems and high-speed queues for
communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus a parity bit
or packet-framing information.
The SN74ACT72211 L, SN74ACT72221 L, SN74ACT72231 L, and SN74ACT72241 L are characterized for
operation from O°C to 70°C.

Copyright © 1993, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6-3
SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 X 9,2048 X 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

functional block diagram

OE
LO

00-08

~J
Input Register

~j.
I Offset
Registers
I
RCLK
REN1
Synchronous
Read
Control
rl Read
Pointer
I ,...
REN2
Oual·Port
SRAM
512x90r
WCLK
WEN1
WEN2
-
-
Synchronous
Write
Control
rl Write
Pointer
J-+ 1024 x9 or
2048x9 or
4096x9 t

---1 Reset
Logic
I l;
Output Register

II
.
QO-Q8
I
Status-
Flag
Logic
l-..+

t 512 x 9 for the SN74ACT72211 L: 1024 x 9 for the SN74ACT72221 L: 2048 x 9 for the SN74ACT72231 L: 4096 x 9 for the SN74ACT72241 L

~TEXAS
INSTRUMENTS
6-4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9, 1024 X 9, 2048 X 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222- FEBRUARY 1993 - REVISED JUNE 1993

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME NO.
6-1,
DO-D8 I Data inputs
32-30
Empty-flag. When memory is empty, EF is low and further data reads are ignored by the device. When EF is
EF 14 0
high, the memory is not empty and data reads are allowed. EF is synchronized to RCLK by one flip-flop.
Full-flag. When memory is full, FF is low and data writes are inhibited. FF is synchronized to WCLK by one
FF 15 0
flip-flop.
GND 9 Ground
OE 13 I Output-enable. aO-a8 are in the high-impedance state when OE is high. aO-a8 are active when OE is low.
Programmable almost-empty-flag. PAE is low when the FIFO is almost empty based on the value in its offset
PAE 8 0
register. The default value for the register is empty + 7. PAE is synchronized to RCLK by one flip-flop.
Programmable almost-full-flag. PAF is low when the FIFO Is almost full based on the value in its offset register.
PAF 7 0
The default value for the register is full -7. PAF is synchronized to WCLK by one flip-flop.
aO-a8 16-24 0 Data outputs
Read-clock. A data read is performed by the low-to-high transition of RCLK when RENl and REN2 are
RCLK 11 I
asserted and EF is high.
REN1, 10, Read-enable. Data is read from the FIFO on a low-ta-high transition of RCLK when RENl and REN2 are low
I
REN2 11 and EF is high.
Reset. When RS is set low, the read and write pOinters are initialized to the first RAM location and the FIFO
RS 29 I is empty. FF and PAF are set high, and EF and PAE are set low. Each bit in the data output register is set low
by a device reset. The FIFO must be reset after power up before data is written.
VCC Supply voltage
Write-clock. Data is written by the low-to-high transition ofWCLK when WENl and WEN2ILD are asserted and
WCLK 27 I
FF is high.
WritEHlnable 1. WENl is the only write enable terminal if the device is configured to have programmable flags.
Data is written on a low-ta-high transition of WCLK when WENl is low and FF is high. If the FIFO is not
WENl 28 I
configured for programmable flags, data is written on a low-te-hightransition of WCLK when WENt and WEN2
are asserted and FF is high.
Write-enable 2110ad. This is a dual-purpose input. The FIFO can have either two write enables or
programmable flags. To use WEN2ILD as a WEN2, WEN2ILD must be held high at reset. When WEN2 and
WEN2ILD 26 I WENl are asserted and FF is high, a low-te-high transition of WCLK writes data. To use WEN2/LD as the LD
terminal, it must be held low at reset. In this case, LD is asserted low to write or read the programmable offset
registers.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 6-5
SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9,2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

detailed description
device reset
A reset is performed by taking the reset (RS) input low. This initializes both the write and read pOinters to the
first memory location. After a reset, the full flag (FF) and programmable almost-full flag (PAF) are high and the
empty flag (EF) and programmable almost-empty flag (PAE) are low. Each bit in the data output register
(QO-Q8) is set low, and the flag offset registers are loaded with the default offset values. A FIFO must be reset
after power up before a write cycle is allowed.
The logic level on the dual-purpose input write enable 2/load (WEN2/LD) during reset determines its function.
If WEN2/LD is high when RS returns high at the end of the reset cycle, the input is a second write enable (see
FIFO writes and reads) and the programmable flags (PAF, PAE) can only use the default values. If WEN2/LD
is low when RS returns high at the end of the reset cycle, the input is the load (LD) enable for writing and reading
flag offset registers (see flag programming).
FIFO writes and reads
Data is written to memory by a low-to-high transition of write clock (WCLK) when write enable 1 (WEN 1) is low,
WEN2/LD is high, and FF is high. This stores DO-D8 data in the dual-port SRAM and increments the write
pointer.
If no reads are performed after reset (RS = VILl, FF is set low upon the completion of 512 writes to the
SN74ACT72211, 1024 writes to the SN74ACT72221, 2048 writes to the SN74ACT72231, and 4096 writes to
the SN74ACT72241. Attempted write cycles are ignored when FF is low. FF is set high by the first low-to-high
transition of WCLK after data is read from a full FIFO. FF and PAF are each synchronized to the low-to-high
transition of WCLK by one flip-flop.
If a device is configured to have two write enables (see device reset), data is read by the low-to-high transition
of read clock (RCLK) when both read enables (REN1, REN2) are low and EF is high. WEN2/LD must also be
high if the device is configured to have programmable flags. A read from the FIFO puts RAM data on QO-Q8
and increments the read pointer in the same sequence as the write pointer. New data is not shifted to the output
register while either one or both of the read enables are high.
EF and PAE are each synchronized to the low-to-high transition of RCLK by one flip-flop. When the device is
empty, the write and read pointers are equal and EF is set low. Attempted read cycles are ignored while EF is
set low. EF is set high by the first low-to-high transition of RCLK after data is written to an empty FIFO.
WCLK and RCLK can be asynchronous or coincident to one another. Writing data to FIFO memory is
independent of reading data from FIFO memory and vice versa.
flag programming
When WEN2/LD is held low during a device reset (RS = VILl, the input is the load (LD) enable for flag offset
programming. In this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained
in the SN74ACT72211 L/-72221L1-72231 L/-72241 L for writing or reading data.
When the device is configured for programmable flags and both WEN2/LD and WEN1 are low, the first
low-to-high transition of WCLK writes data from the data inputs to the empty offset least significant bit (LSB)
register. The second, third, and fourth low-to-high transitions of WCLK store data in the empty offset most
significant bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD
and WEN1 are low. The fifth low-to-high transition of WCLK while WEN2/LD and WEN1 are low writes data to
the empty LSB register again. Figure 1 shows the register sizes and default values for the various device types.
It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written;
then, by bringing the WEN2/LD input high, the FIFO is returned to normal read and write operation. The next
time WEN2/LD is brought low, a write operation stores data in the next offset register in sequence.

~TEXAS
INSTRUMENTS
6-6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9, 1024 x 9, 2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

flag programming (continued)

The contents of the offset registers can be read to the data outputs when WEN2/LD is low and both REN 1 and
REN2 are low. Low-to-high transitions of RCLK read the register contents to the data outputs. Writes and reads
should not be performed simultaneously on the offset registers (see Figure 1 and Table 1).

SN74ACT72211L -512 x 9-Blt SN74ACT72221L -1024 x 9-Blt

8 7 o 8 7 o
Empty Offset (LSB) Register Empty Offset (LSB) Register
Default Value =007h Default Value =007h
8 o

8 7 o
Full Offset (LSB) Register Full Offset (LSB) Register
Default Value =007h Default Value =007h
8 o
(MSB)
00

SN74ACT72231 L - 2048 x 9-Blt SN74ACT72241 L - 4096 x 9-Blt

Empty Offset (LSB) Register Empty Offset (LSB) Register

Default Value =007h Default Value =007h
8 2 o 8 3 o
(MSB) (MSB)
000 0000

7
Full Offset (LSB) Register Full Offset (LSB) Register
Default Value =007h Default Value =007h
8 2 o 8 3 o
(MSB)
0000

Figure 1. Offset Register Location and Default Values

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 6-7
SN7.4ACT72211L, SN7.4ACT72221L, SN7.4ACT72231L, SN7.4ACT722.41L
512 x 9,102.4 x 9, 20.48 x 9, AND .4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

flag programming (continued)

Table 1. Writing the Offset Registers

LD WEN1 WCLKt SELECTION

0 0 i
Empty""" (tSB']
Empty offset (MSB)
Full offset (LSB)
Full offset (MSB)
0 1 i No operation
1 0 i Write into FIFO
1 1 i No operation
t The same selection sequence applies to reading from
the registers. RENl and REN2 are enabled and a read
is performed on the low-ta-high transition of RCLK.

programmable flag (PAE, PAF) operation

Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) and programmable almost-full flag (PAF) states are determined by their
corresponding offset registers and the difference between the read and write pointers.
The number formed by the empty offset least significant bit register and empty offset most significant bit register
is referred to as n ahd determines the operation of PAE. PAE is synchronized to the low-to-high transition of
RCLK by one flip-flop and is low when the FIFO contains n or fewer unread words. PAE is set high by the
low-to-high transition of RCLK when the FIFO contains (n + 1) or greater unread words.
The number formed by the full offset least significant bit register and full offset most significant bit register is
referred to as m and determines the operation of PAF. PAF is synchronized to the low-to-high transition of WCLK
by one flip-flop and is set low when the number of unread words in the FI FO is greater then or equal to (512 - m)
for the SN74ACT72211L, (1024- m) for the SN74ACT72221L, (2048 - m) for the SN74ACT72231L, and
(4096 - m) for the SN74ACT72241 L. PAF is set high by the low-to-high transition of WCLK when the number
of available memory locations is greater than m (see Table 2).

Table 2. Status Flags

NUMBER OF WORDS IN FIFO OUTPUTS
SN74ACT72211L SN74ACT72221L SN74ACT72231 L SN74ACT72241 L FF PAF PAE EF
0 0 0 0 H H L L
1 tont 1 tont 1 to nt 1 to nt H H L H
(n + l)to (n + 1) to (n+ l)to (n + l)to
H H H H
[512-(m+l)) [1024-(m+l)] [2048 - (m + 1)) [4096-(m + 1)]
(512 - m):J: to 511 (1024 - m):J: to 1023 (2048 - m):J: to 2047 (4096 - m):J: to 4095 H L H H
512 1024 2048 4096 L L H H
t n _ empty offset (default value = 7)
:J: m = full offset (default value _ 7)

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9, 1024 x 9, 2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

EF.PAE~
~
14--- tpd(RS-O) ~
FF.PAF~
!.-- tpd(R5-0) ~
00-08 :---------~~~~':..---------
NOTES: A. Holding WEN2/LD high during reset makes it act as a second write enable. Holding WEN2/LD low during reset makes it act as a
load enable for the programmable flag offset registers.
B. After reset, the outputs are low if OE is low and at the high-impedance level if OE is high.
C. The clocks (RCLK, WCLK) can be free running during reset.

Figure 2. Reset Timing

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6-9
SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9, 2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS222- FEBRUARY 1993- REVISED JUNE 1993

WCLK

00-08

WEN2
(If applicable)

\ _____1 \-----1

NOTE A: tsk1 is the minimum time between a rising RCLK edge and a subsequent rising WCLK edge for FF to change logic levels during the
currerit clock cycle. lithe time between the riSing edge of RCLK and the subsequent rising edge of WCLK is less than tsk1. then FF may
not change its logic level until the next WCLK rising edge.

Figure 3. Write-Cycle Timing

~TEXAS
INSTRUMENTS
6-10 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9,2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

I.. te ~
14-- tw(CLKH) +- tw(CLKL) -----l
RCLK J '\ l~~\'--_--JI
tsu(EN) ~ I+- th(EN) i
REN1,REN2 ~!CfI No Operation i~..........____________
14------ tpd(R-EFJ ----.1 [4-- tpd(R-EF) ----'1
1 1 1 1
1 ~ 1 1~------
1 ~~____~I~________~.
L
1-
- ta
1
~I
1

00-08 _ _ _ _ _ _ ~~-v-a-lI-d-Da..L..:-a-""\)>-I------------
ten --.I [4--
-----~\ tpd(OE-O) -----'1
1
1,.----1!--------------
14-- tdls ~

I-: ~ ..,,- No" AJ

WCLK
\,-------,y \,-------,1
\~------------------------
WEN2 /
-----'
NOTE A: tsk1 is the minimum time between a rising WCLK edge and a subsequent rising RCLK edge for EF to change logic levels during the
current clock cycle. If the time between the rising edge of WCLK and the subsequent rising edge of RCLK is less than tskl , then EF may
not change its logic level until the next RCLK rising edge.

Figure 4. Read-Cycle Timing

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6-11
SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9,2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS222 - FEBRUARY 1993- REVISED JUNE 1993

WCLK
I
K tsu(O)

00-08 'O'~~~~,...,..~WO (1st valid wrlteX

I ~
Wi
____- J
X
~
W2
______J
X W3
~-------
X
~14~-~:- tsu(EN)

I
I I
WEN2
(if applicable)
&1 14j4----1~ tsk1 (see Note A)

RCLK

I I I
_______________IP_d(_~_E_F)_~:~~~~~~)tr--~i----------!~--------------
I I
I I
REN1, I I
REN2 _L_o_w__________________________~I------~1 ___________
i I
!4- ta -+I j+- ta -+II
_,..,..,..,..,~ I ,.....___~ ,--_______

QO-Q8 ----------.....,.I---....,~ WO X'--___ W_1____

len ~ ~ :
------------.~ tpd(OE-Q) ~
OE '-

NOTE A: tsk1 is the minimum time between a rising WCLK edge and a subsequent rising RCLK edge for EF to change during the current clock
cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tsk1 , then EF may not change state until
the next RCLK edge.

Figure 5. Flrst-Data-Word-Latency Timing

~·TEXAS
INSTRUMENTS
6-12 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9, 1024 x 9, 2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

~ No Write ---I ~ No Write

I
-.1
I
WCLK

00-0&
I
~ ~ I.. ~ I,. ~I

y-
tpd(W-FF) tpd(W-FF) tpd(W-FF)
I I
I I
FF I
I
I
I '\ I
I
I
I
WEN1
\ I
I
I
I
J
WEN2
(If applicable)
I
I
I
I

,
I
RCLK
I I
tsu(EN)
~ ~.. ~ th(EN) tsu(EN)
I" ~~ ~ th(EN)
REN1,
REN2
II '\ II I
~ ta ~ I
I
OE Low I I
I I
I J4- ta -.I
I I
QO-Q& Data In Output Register Data Read Next Data Read

NOTE A: tsk1 is the minimum time between a rising RCLK edge and a subsequent rising WCLK edge for FF to change logic levels during the
current clock cycle. lithe time between the rising edge of RCLK and the subsequent rising edge of WCLK is less than tsk1, then FF may
not change its logic level until the next WCLK rising edge.

FIgure 6. Full-Flag TImIng

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6-13
SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9, 2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

WCLK

DO-OS

tsU(EN) ~~ th(EN) tsu(EN) :4 .14 .: Ih(EN)

I 1 Ir-----------------~~
WEN1 ~ i;f ~ !fiI
I 1 I I 1
WEN2
(if applicable)
? II
I \1
1
1
"-
~----------------~~
@
1 1
I'{
1
I" 14
RCLK

tpd(R-EF) -'4~-~
~ ~ .1
1
tpd(R-EF) tpd(R-EF) ~
1
1
1 '\ !
\~------~------------------
Low

---.I j4- ta

QO-QS
------------------------~Ir_------------------------
Data In Output Register O_ata X. ._______________
__R_ea_d_________

NOTE A: tsk1 is the minimum time between a rising WCLK edge and a subsequent rising RCLK edge for EF to change logic levels during the
current clock cycle. If the time between the rising edge of WCLK and the subsequent rising edge of RCLK is less than tsk1. then EF may
not change its logic level until the next RCLK rising edge.

Figure 7. Empty-Flag Timing

-!/} ThXAS
INSTRUMENTS
6-14 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9,2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

Iw(CLKH)

WCLK

Isu(EN) 14.~ ~ Ih(EN) i

----~~~ 1 ~~~--~:----------------~~-------

1 ! 1 i
~\,,;:~-....!t__-------+_---
WEN2
(If applicable)
_ _......£.IN..:..'-J :
Ipd(W-AF) 14
(Full - m) Words In FIFO
[Full- (m + 1)] Words In FIFO
(see Nole B)
(see Nole A)
.i4---.r Ipd(W-AF)
RCLK

Isu(EN) I.i! .14 .1 Ih(EN)

--------------------~~ :~~----
NOTES: A. PAF offset = m
B. (512 - m) words for SN74ACT72211 L. (1024 - m) words for SN74ACT72221 L. (2048 - m) words for SN74ACT72231 L. (4096 - m)
words for SN74ACT72241 L
C. tsk2 is the minimum time between a rising RCLK edge and the subsequent rising WCLK edge for PAF to change its logic level during
that clock cycle. If the time between the rising edge of RCLK and the subsequent rising edge of WCLK is less than tsk2. then PAF
may not change its logic level until the next WCLK rising edge.
D. If a write is performed on this rising edge of the write clock. there will be [Full- (m -1)] words in the FIFO when PAF goes low.

Figure 8. Programmable Almost-Full Flag Timing

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 6-15
SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9, 2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

tw(CLKH)
WCLK

tsu(EN) I.- + ~ th(EN)

~:~~------------------------------------
I I I
WEN2
(If applicable)
!1?'
t:@"
II ~
~
----~~~ I ~~---------------------------------------
I : See Note A
PAE ____ n_W_o_rd_s_ln_F_I_FO~:----------Jif (n + 1) Words In FIFO
tpd(R-AE)
L
--1+-_----+1.1
I.. .1 (see Note C)
I I
RCLK

tsU(EN) I.. ~.. .I th(EN)

~~~~----------------------------------~~~ : ~~r--------------
NOTES: A. PAE offset = n
B. tsk2 is the minimum time between a rising WCLK edge and the subsequent rising RCLK edge for PAE to change its logic level during
that clock cycle. If the time between the rising edge of WCLK and the subsequent rising edge of RCLK is less than tsk2. then PAE
may not change its logic level until the next RCLK rising edge.
C. If a write is performed on this rising edge of the write clock. there will be [Empty + (n -1)J words in the FIFO when PAE goes low.

Figure 9. Programmable Almost-Empty Flag Timing

~TEXAS
INSTRUMENTS
6-16 POST OFfiCE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9,2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222- FEBRUARY 1993 - REVISED JUNE 1993

tw(ClKH) ---14-----.014--..,
WClK

00-07

PAE PAE PAF PAF

Offset Offset Offset Offset
(lSB) (MSB) (lSB) (MSB)

Figure 10. Write-Offset-Registers Timing

tw(ClKH)

RClK

----,~~
~I
:A
tsu(EN) 1l1li .1l1li ~ th(EN)

tsu(EN) -*-+i
------.~I:""':""" :
1
I+- ta--.I
----------------~Ir_------~ r------~ r_------~
QO-Q7 Data In Output Register PAE Offset (lSB) PAE Offset (MSB) PAF Offset (lSB)

PAF Offset (MSB) J

Figure 11. Read-Offset-Registers Timing

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6-17
SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9,2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range, any input, VI (see Note 1) ......................................... -0.5 V to 7 V
Continuous output current, 10 ............................................................. ±50 mA
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range under bias ............................................. -55°C to 125°C
Storage temperature range. . . .............. .. ....... ........ .... .. ...... .... .. ... -55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current -2 mA
IOL Low-level output current 8 mA
TA Operating free-air temperature 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VOH High-level output voltage VCC = 4.5 V, IOH =-2 mA 2.4 V
VOL Low-level output voltage VCC = 4.5 V, IOL= 8 mA 0.4 V
II Input current VCC = 5.5 V, VI=VCCorOV ±1 ~
IOZ High-impedance output current VCC = 5.5 V, Vo=VccorOV ±10 ~
Ci:!: Input capacitance VI = 0, f = 1 MHz 10 pF
Co:!: Output capacitance VO=O, f = 1 MHz, OE~VIH 10 pF
SN74ACT72211 L 140§
ICC~ Active supply cu rrent fclock = 20 MHz SN74ACT72221 L, SN74ACT72231 L, mA
160#
SN74ACT72241 l
:j: Specified
"
by design but not tested
§ ICC measurements are made with outputs open (only capacitive loading). Typical ICC = 65 + (fclockx 1.1/MHz) + (fclockx Cl x 0.03/MHz-pF) mA
(CL = external capacitive load).
~ The ICC limits are valid for tc = 15,20,25, and 50 ns.
# ICC measurements are made with outputs open (only capacitive loading). Typical ICC = 80 + (Iclock x 2.1/MHz) + (fclock x CL x 0.03/MHz-pF) mA
(Cl = external capacitive load).

~TEXAS
INSTRUMENTS
6-18 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9, 2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 2 through 13)
'ACT72211L·15 'ACT72211 L·20 'ACT72211L·25 'ACT72211L·50
'ACT72221 L·15 'ACT72221 L·20 'ACT72221 L·25 'ACT72221 L·50
'ACT72231L·15 'ACT72231 L·20 'ACT72231 L·25 'ACT72231 L·50 UNIT
'ACT72241L·15 'ACT72241L·20 'ACT72241L·25 'ACT72241 L·50
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency, RClK or WClK 66.7 50 40 20 MHz
tc Clock cycle time, RClK or WClK 15t 20 25 50 ns
Pulse duration, RClK or WClK
tw(ClKH) 6 8 10 20 ns
high
tw(ClKl) Pulse duration, RClK or WClK low 6 8 10 20 ns
tw(RS) Pulse duration, RS low 15 20 25 50 ns
tsu(O) Setup time, 00-08 before RClKi 4 5 6 10 ns
Setup time, WEN1, WEN2:j:, and
tsu(EN) lO§ before WClKi; REN 1, REN2, 4 5 6 10 ns
and lO§ before RClKi
Setup time, REN1, REN2, WEN1,
tsu(RS) 15 20 25 50 ns
and WEN2/l0 before RS high
th(O) Hold time, 00- 08 after RClKi 1 1 1 2 ns
Hold time, WEN1, WEN2+, and
th(EN) lO§ after WClKi; REN1, REN2, 1 1 1 2 ns
and LD§ after RClKi
Hold time, REN1, REN2, WEN1,
th(RS) 15 20 25 50
and WEN2/l0 after RS high
Skew time between RClKi and
WClKi to allow EF or FF to
tsk1 6 8 10 15 ns
change logic levels during the
current clock cycle
Skew time between RClKi and
WClKi to allow PAF or PAE to
tsk2 28 35 40 45 ns
change logic levels during the
current clock cycle
t Valid for PAE or PAF program values as follows:
S 63 bytes from the respective boundary for the SN7 4ACT72211 l;
s 511bytes from the respective boundary for the SN74ACT72221 U-72231 U-72241 l;
minimum tc is 20 ns for program values greater than those indicated above.
:j: Applicable when the device is configured with two write-enable inputs (WEN2/l0 = WEN2).
§ Applicable when the device is configured to have programmable flags (WEN2/l0 =lO).

-!llExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 6-19
SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9, 2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 2 through 13)
'ACT72211L-15 'ACT72211L-20 'ACT72211L·25 'ACT72211L-50
'ACT72221 L-15 'ACT72221 L-20 'ACT72221 L-25 'ACT72221 L-50
PARAMETER 'ACT72231L-15 'ACT72231L-20 'ACT72231 L-25 'ACT72231L-50 UNIT
'ACT72241L-15 'ACT72241L-20 'ACT72241L-25 'ACT72241L-50
MIN MAX MIN MAX MIN MAX MIN MAX
Access time, RCLKI to QO-Q8
ta 2 10 2 12 3 15 3 25 ns
valid
Propagation delay time, OE low to
tpd(OE-Q) 3 8 3 10 3 13 3 28 ns
QO-Q8valid
Propagation delay time, RCLKI to
tpd(R-EF) 10 12 15 30 ns
EF low or high
Propagation delay time, WCLKI to
tpd(W-FF) 10 12 15 30 ns
FF low or high
Propagation delay time, RCLKI to
tpd(R-AE) 10 12 15 30 ns
PAE low or high
Propagation delay time, WCLKI to
tpd(W-AF) 10 12 15 30 ns
PAF low or high
Propagation delay time, RS low to
tpd(RS-O) FF and PAF high and EF, PAE, and 15 20 25 50 ns
QO-Q810w
Enable time, OE low to QO-Q8 at
ten 0 0 0 0 ns
the low-impedance levelt
Disable time, OE high to QO-Q8 at
tdis 3 8 3 10 3 13 3 28 ns
the high-impedance levelt
t These values are charactenzed but not tested.

~TEXAS
INSTRUMENTS
6-20 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9, 1024 x 9, 2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

APPLICATION INFORMATION

width-expansion configuration
Word width is increased by connecting the corresponding input control signals of multiple devices. Composite
empty and full flags should be created by monitoring all devices in width expansion. Almost-full and
almost-empty status can be obtained from anyone device. Figure 12 shows an 18-bit-wide data path formed
by using two SN74ACT72211 Ll72221 Ll72231 Ll72241 L devices.
In Figure 12, read enable 2 (REN2) is grounded and read enable 1 (REN1) acts as the only read control. The
write enable 21load (WEN2/LD) input of only one device is set low at reset to configure the device for
programmable flags and to have it act as a load control for reading and writing the programmable flag offset
registers.

SN74ACT72211L/72221L/72231L/72241L

RS RS RCLK RCLK
WCLK WCLK REN1 REN1
WEN1 WEN1 REN2
LO WEN2ILO l
PAF PAF PAE PAE
FF EF
9 9
~O-DB QO-Q8
~O-DB QO-QB

FF SN74ACT72211L/72221L/72231L/72241L EF

RS RCLK
00-017 ~ WCLK REN1
~ QO-Q11
WEN1 REN2
5V WEN2ILO J-
FF EF
9 9
DO-DB QO-QB
09-017 Q9-Q17
Figure 12. Word-Width Expansion for 512/1024/2048/4096 x 18 FIFO

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 6-21
SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 x 9,1024 x 9,2048 x 9, AND 4096 x 9
SYNCHRONOUS FIRST·IN, FIRST·OUT MEMORIES
SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993

PARAMETER MEASUREMENT INFORMATION

5V

11000
From Output
Under Test ---+-------
Input
6800 :::::::- 30pF
.-- --- (see Note A)

In-Phase
Output

LOAD CIRCUIT VOLTAGE WAVEFORMS

3V
~~.~-
Timing

Input
1.
---J.4 ~ ~ - - -
3V

GND
High-Level
Input -----Ii 1.0 V ~
GND
l+- tw ~
tsu~th I I
Data
Input
~ct--- 3V
1.5 V 1.5 V
Low-Level ~ 1.5 V ~ 3V
GND
Input ~ _:.. ~ _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

NOTE A: Includes probe and jig capacitance

Figure 13. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
6-22 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-1
 18·BIT CLOCKED FIFOS
Features Benefits

• Members of Texas Instruments Widebus™ • Combine wider data-path capability with

family reduced board space area
• Advanced BiCMOS process • Fast access time for improved system
cycle time and performance
• 0.8-J.1m CMOS process • Fast access times combined with low
power
• TI's advanced clocked interface • Supports free-running clocks with enables
• Support clock rates up to 80 MHZ • Supports high-performance systems
• Fast access times • Access times as low as 9 ns for improved
performance
• High drive capabilites • Drive capability as high as -12 mA to
24 mA for high fanout and bus
applications
• Depths from 64 to 4K words • Multiple depths to optimize system
applications
• Latched input and output registers • Allows for fast access times and reduced
setup and hold times
Q
o
(')
• Grey-code flag architecture • Eliminates race conditions
• First-word fallthrough • Eases system interface requirements
~
c. • Programmable AF/AE flag • Increases design flexibility
!! • Multistage flag synchronization • Increases reliability by increasing mean
"otn time between failures (MTBF)
• Output edge control (OECTM) circuitry • Improved reliability
• Distributed Vee and GND • Improved noise immunity and mutual
coupling effects
• Fine-pitch package options • Significantly reduce critical board space
• EIAJ 80-pin TQFP packages • Board-space savings of up to 70% over
68-pin PLCC option

7-2
 SN74ACT7813
64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
-JANUARY 1991 - REVISED APRIL 1992

• Member of the Texas Instruments DLPACKAGE

Wldebus ™ Family (TOP VIEW)

• Free-Running Read and Write Clocks Can RESET OE1

Be Asynchronous or Coincident 017 Q17
• Read and Write Operations Synchronized Q16
to Independent System Clocks 015 Q15
• Input-Ready Flag Synchronized to Write 014 GNO
Clock Q14
• Output-Ready Flag Synchronized to Read Vee
Clock 011 Q13
010 Q12
• 64 Words by 18 Bits
• Low-Power Advanced CMOS Technology
Vee Q11
09 Q10
• Half-Full Flag and Programmable 08 Q9
Almost-FuIl/Almost-Empty Flag GNO GNO
• Bidirectional Configuration and Width 07 Q8
Expansion Without Additional Logic 06 Q7
• Fast Access Times of 12 ns With a 50-pF 05 Q6
Load and All Data Outputs Switching 04 Q5
Simultaneously 03 Vee
02 Q4
• Data Rates From 0 to 67 MHz
01 Q3
• Pin Compatible With SN74ACT7803 and
DO Q2
SN74ACT7805
HF GNO
• Packaged in Shrink Small-Outline 300-mil PEN Q1
Package (DL) Using 25-mil Center-to-Center AF/AE QO
Spacing WRTCLK ROCLK
WRTEN2 ROEN
description
WRTEN1
The SN74ACT7813 is a 64-word x 18-bit FIFO IR
suited for buffering asynchronous data paths at
67-MHz clock rates and 12-ns access times. Its
56-pin shrink small-outline package (DL) offers
greatly reduced board space over DIP, PLCC, and conventional SOIC packages. Two devices can be configured
for bidirectional data buffering without additional logic. Multiple distributed Vcc and GND pins along with TI's
patented output edge control (OECT ") circuit dampen simultaneous switching noise.
The write clock (WRTCLK) and read clock (RDCLK) should be free running and can be asynchronous or
coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low,
and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low
and OR is high. The first word written to memory is clocked through to the output buffer regardless of the RDEN,
OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four
WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FI FO initializes
the IR, OR, and HF flags low and the AF/AE flag high. The FIFO must be reset upon power up.
The SN74ACT7813 is characterized for operation from DOC to 7DoC.

Widebus and OEe are trademarks of Texas Instruments Incorporated.

Copyright © 1992, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-3
SN74ACT7813
64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS199 - JANUARY 1991 - REVISED APRIL 1992

logic symbolt

<I>
1 FIFO 64x 18
RESET "- RES.:r
SN74ACT7813
25
WRTCLK WRTCLK
27
WRTEN1 28
26 IN ROY IR
WRTEN2 " tJWRTEN 22
32 HALF-FULL HF
ROCLK ROCLK 24
56 ALMOST FULUEMPTY AF/AE
OE1 "- 29
30 OUT ROY OR
OE2 "- [:JEN1
~ r-a
"- ROEN
31
" I""-
23 b
..,
PROGRAM ENABLE
r
21 33
00 0 0 QO
20 34
01 Q1
19 36
02 Q2
18 37
03 Q3
17 38
04 Q4
16 40
05 Q5
15 41
06 Q6
14 42
07 Q7
12 43
08 Q8
09
11
9 ~ ~1V 45
46
Q9
010 Q10
8 47
011 Q11
7 48
012 Q12
6 49
013 Q13
5 51
014 Q14
4 53
015 Q15
3 54
016 Q16
2 55
017 17 17 Q17

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.

-!JJ lExAs
INSTRUMENTS
7-4 POST OFFICE BOX 655303 • OALLAS. TEXAS 75266
 SN74ACT7813
64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS199 - JANUARY 1991 - REVISED APRIL 1992

functional block diagram

-ri Output
Control II
I

~J
DO-017

'-- Location 1
ROCLK
-
Synchronous
Read
Control
I Read
Pointer
I
I
Location 2

ROEN
I 64x18RAM

WRTCLK -f--< ~ Synchronous I

WRTEN1 - f -
WIn'EN2 -r- ~
Write
Control f- I Write
Pointer I Location 83
Location 84
I
~J
Register QO-Q17

Status-
Li Reset
Logic I
I
Flag
Logic
OR
IR
HF
AF/AE

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265 7-5
SN74ACT7813
64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS199 - JANUARY 1991 - REVISED APRIL 1992

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
Aimost-full/almost-empty flag. Depth offset values can be programmed for AF/AE, or the default
AF/AE 24 0 value of 8 can be used for both the almost-empty offset (Xl and the almost-full offset (V). AF/AE is
high when memory contains X or less words or (64 - V) or more words. AF/AE is high after reset.
21-14,12-11,
DO-D17 I The 18-bit data input port
9-2
HF 22 0 Half-full flag. HF is high when the FIFO memory contains 32 or more words. HF is low after reset.
Input-ready flag. IR is synchronized to the low-to-high transRion of WRTCLK. When IR is low, the
IR 28 0 FIFO is full and wrHes are disabled.IR is low during reset and goes high on the second low-to-high
transition of WRTCLK after reset.
Output enables. When OE1, OE2, and RDEN are low and OR is high, data is read from the FIFO
OE1,OE2 56,30 I on a low-to-high transition of RDCLK. When either OEl or OE2 is high, reads are disabled and the
data outputs are in the high-impedance state.
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the
FIFO is empty and reads are disabled. Ready data is present on 00-017 when OR is high. OR is
OR 29 0 low during reset and goes high on the third low-to-high transition of RDCLK after the first word is
loaded to empty memory.
Program enable. After reset and before the first word is written to the FIFO, the binary value on
PEN 23 I
DO-D4 is latched as an AF/AE offset value when PEN is low and WRTCLK is high.
33-34, 36-38, The 18-bit data output port. After the first valid write to empty memory, the first word is outpul on
00-017 40-43,45-49, 0 00-017 on the third riSing edge of RDCLK. OR is also asserted high at this time to indicate ready
51,53-55 data. When OR is low, the last word read from the FIFO is present on 00-017.
Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A
RDCLK 32 I low-to-high transHion of RDCLK reads data from memory when OE1, OE2, and RDEN are low and
OR is high. OR Is synchronous to the low-to-high transition or RDCLK.
Read enable. When RDEN, OE1, and OE2 are low and OR Is high, data is read from the FIFO on
RDEN 31 I
the low-to-high transition of RDCLK.
Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of
RESET 1 I
WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high.
Write clOCk. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A
WRTCLK 25 I low-to-high transHion of WRTCLK writes data to memory when WRTEN2 is low, WRTENl is high,
and IR is high. IR is synchronous to the low-to-high transition of WRTCLK.
WRTEN1, Write enables. When WRTENl is high, WRTEN2 is low, and IR is high, data is written to the FIFO
27,26 I
WRTEN2 on a low-to-high transition of WRTCLK.

~1ExAs
INSTRUMENTS
7-6 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7813
64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS199 -JANUARY 1991 - REVISED APRIL 1992

WRTCLK

1 1

WRTEN1

_vvvvvvv~
00-017 Don't Care

1 1 'VVINVV\X 1 1
1 1
RDCLK 1 1 12 3 4 1 1

~
v~~
I I I
:
-------------yyyyy+y I

~
___
'''lJlJ'''~X~
.
I
~on'tCare
~ ~_____
I
I
I

~ :
1 I! ! i
QO-Q17 Invalid

AF/AE

Define the AF/AE Flag Using

the Default Value of X =Y =8

Figure 1. Reset Cycle

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-7
SN74ACT7813
64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS199 - JANUARY 1991 - REVISED APRIL 1992

1
o
1
o

WRTCLK

1
WRTEN1 I I I I o
I I I· I
I I I I
W~EN2 --,L.. ______________________~I------~I ______~I------~I--
I I I I
I I I I
00-017 SS@Wl®W2®W3lAAw4.W~+2ld ~3 .w+~~
I. I I
+
I
RS

ROCLK

I I I
~~~r-ffi-
OE1
I I I 1
________________~I--------~I------~I------_+------_+--- o
I I I
I I I 1
I I I o
I I I
I I I
OE2 _________________~I--------~I------~I------~------~---
I I I o
I I II
OO~7 ~~ X ~
----------------~i ~------------~I------~------~--
OR ________________........ I
AF/AE
I
HF ________________________________~I

IR
L
Figure 2. Write Cycle

~1ExAs
INSTRUMENTS
7-8 POST OFFICE BOX 665303 • DALLAS, TEXAS 75265
 SN74ACT7813
64 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS199-JANUARY 1991- REVISED APRIL 1992

------------------------------------------------------------- 1
RESET 0

------------------------------------------------------------- 1
PEN 0

WRTCLK-fLfl~~~~r----fl-Sl-
1 1
WRTEN1 ~ :
1 1
1 1 1
WRTEN2 1 !
o
1 1

00-0171 +5
1 1

ROCLK 1 41 - ---'.~~~r--fL.fL
1
1 1
1
OE1 1 1
1
1 o
1 I
1 1
1 1
ROEN
I I
I 1
I 1
OE2
I I
I 1
I
QO-Q17 WI
>GX : W3 ~ W(Y+1)

OR I
1
1
I
AF/AE 1

I
1
HF 1
1
I
IR 1 ..._____ ---1

Figure 3. Read Cycle

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-9
SN74ACT7813
64 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS199-JANUARY 1991- REVISED APRIL 1992

offset values for AF/AE

The aimost-fuillaimost-empty flag has two programmable limits: the almost-empty offset value (X) and the
almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written
to memory. If the offsets are not programmed, the default values of X = Y = 8 are used. The AF/AE flag is high
when the FIFO contains X or less words or (64 - Y) or more words.
Program enable (PEN) should be held high throughout the reset cycle. PEN can be brought low only when IR
is high and WRTCLK is low. On the following low-to-high transition of WRTCLK, the binary value on DO-D4 is
stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another
low-to-high transition of WRTCLK reprograms Y to the binary value on DO-D4 at the time of the second
WRTCLK low-to-high transition. When the offsets are being programmed, writes to the FIFO memory are
disabled regardless of the state of the write enables (WRTEN1, WRTEN2). A maximum value of 31 can be
programmed for either X or Y (see Figure 4). To use the default values of X = Y = 8, PEN must be held high.

WRTCLK

DO-D4

IR I
WRTEN1

WRTEN2_

Figure 4. Programming X and Y Separately

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, VI ........................................................................... 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range .............................. , .. ................. ..... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

~TEXAS
INSTRUMENTS
7-10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7813
64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS199-JANUARY 1991- REVISED APRIL 1992

recommended operating conditions

'ACT7813-15 'ACT7813-20 'ACT7813-25 'ACT7813-40
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 0.8 V
IOH High-level output current Q outputs, Flags -8 -8 -8 -8 rnA
Q outputs 16 16 16 16
IOL Low-level output current rnA
Flags 8 8 8 8
fclock Clock frequency 67 50 40 25 MHz
WRTCLK high or low 6 7 8 12
tw Pulse duration RDCLK high or low 6 7 8 12 ns
PEN low 8 9 9 12
DO-D17 before
4 5 5 5
WRTCLKi
WRTEN1, WRTEN2
4 5 5 5
before WRTCLKi
OE1,OE2
5 5 6 6
tsu Setup time before RDCLKi ns
RDEN before RDCLKi 4 5 5 5
Reset: RESET low
before first WRTCLKi 5 6 6 6
and RDCLKit
PEN before WRTCLKi 5 6 6 6
DO-D17 after
0 0 0 0
WRTCLKi
WRTEN1, WRTEN2
0 0 0 0
after WRTCLKi
OE1, OE2, RDEN
0 0 0 0
afterRDCLKi
th Hold time Reset: RESET low ns
after fourth WRTCLKi 2 2 2 2
and RDCLKit
PEN high
0 0 0 0
after WRTCLK,j,
PEN low after
2 2 2 2
WRTCLKi
TA Operating free-air temperature 0 70 0 70 0 70 0 70 ·C
t To permit the clock pulse to be utihzed for reset purposes

~ThXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-11
SN74ACT7813
64 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS199 -JANUARY 1991 - REVISED APRIL 1992

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VOH VCC= 4.5 V, IOH =-8mA 2.4 V
I Flags VCC=4.5V, IOL=8 mA 0.5
V
VOL
IQ outputs VCC= 4.5 V, IOL= 16 mA 0.5
II VCC = 5.5 V, VI =VccorO ±5 IlA
IOZ VCC = 5.5 V, Vo =VCC orO ±5 IlA
ICC VI=VCC-0.2VorO 400 IlA
aICC:I: VCC=5.5V, One input at 3.4 V, Other inputs at VCC or GND 1 mA
Ci VI=O, f= 1 MHz 4 pF
Co VO=O, f= 1 MHz 8 pF
t All tYPical values are at VCC = 5 V, TA = 25°C.
:I: This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (see Figures 9 and 10)
FROM TO 'ACT7813-15 'ACT7813-20 'ACT7813-25 'ACT7813-40
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYPt MAX MIN MAX MIN MAX MIN MAX
WRTCLKor
f max 67 50 40 25 MHz
RDCLK
tpd 4 9.5 12 4 13 4 15 4 20
RDCLKi AnyQ ns
tpd§ 8.5
tpd WRTCLKi IR 3 8.5 3 11 3 13 3 15 ns
tpd RDCLKi OR 3 8.5 3 11 3 13 3 15 ns
WRTCLKi 7 16.5 7 19 7 21 7 23
tpd AF/AE ns
RDCLKi 7 17 7 19 7 21 7 23
tPLH WRTCLKi 7 15 7 17 7 19 7 21
HF ns
tpHL RDCLKi 7 15.5 7 18 7 20 7 22
tPLH AF/AE 2 9 2 11 2 13 2 15
RESET low ns
tPHL HF 2 10 2 12 2 14 2 16
ten 2 8.5 2 11 2 11 2 11
OE1,OE2 AnyQ ns
tdis 2 9.5 2 11 2 14 2 14
§ ThiS parameter IS measured with a 30-pF load (see Figure 5).

operating characteristics, Vee =5 V, TA =25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance Outputs enabled CL = 50 pF, f = 5 MHz

~TEXAS
INSTRUMENTS
7-12 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7813
64 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS199 -JANUARY 1991 - REVISED APRIL 1992

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
typ + 8
VccL5V
./
r- TA = 25°C
RL=500n
V
II)
typ+6 /
c
I
CD
/
E
j::
>-
co
typ +4
/
/
Qj
Q /
c
0
:; typ +2 1/
t»
co
Q.
2
/
Q.
I
'C typ L
!l-
I
/
typ-2
o 50 100 150 200 250 300

CL - Load Capacitance - pF

Figure 5

SUPPLY CURRENT
vs
CLOCK FREQUENCY
200 I
TA = 75°C
180 CL = 0 pF VCC = 5.5 V
I
V
160
c(
E 140
VCC=5V~
V l/
C
I

~::> 120
/ rY / '
0 100 / 't'/ /
>-
0.
Q.
::> 80
/ / // VCC = 4.5 V

~~
1/1
I
60
S
0
~ 40 ~~
20

0
,
~p

o 10 20 30 40 50 60 70

fclock - Clock Frequency - MHz

Figure 6

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-13
SN74ACT7813
64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS199-JANUARY 1991 - REVISED APRIL 1992

TYPICAL CHARACTERISTICS

calculating power dissipation

With ICC(f) taken from Figure 6, the maximum power dissipation (Pr) based on all data outputs changing states
on each read can be calculated using:
Pr = VCC x [ICC(f) + (N x t.ICC x dc)] + :E(CL x VCc2 x fo)
A more accurate power calculation based on device use and average number of data outputs switching can be
found using:
Pr = VCC x [Icc + (N x t.ICC x dc)] + :E(Cpd x Vcc2 x fi) + :E(CL x VCC2 x fo)
where:
Icc power-down ICC maximum
N number of inputs driven by a TTL device
t. Icc increase in supply current
dc duty cycle of inputs at a TTL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
fi data input frequency
fo data output frequency

~TEXAS
INSTRUMENTS
7-14 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7813
64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS199 -JANUARY 1991 - REVISED APRIL 1992

APPLICATION INFORMATION

SN74ACT7813
CLOCK A WRTCLK ROCLK CLOCKB
W/RA WRTEN1 OE1 W/RB

CSA WRTEN2 ROEN CSB

OE2 U
18/
00-017 QO-Q17 BO-B17

SN74ACT7813
l....-
f> ROCLK WRTCLK
- OE1 WRTEN1
ROEN WRTEN2
L OE2

18/
AO-A17 QO-Q17 00-017

Figure 7. Bidirectional Configuration

SN74ACT7813
WRTCLK WRTCLK ROCLK ROCLK
WRTEN1 WRTEN1 ROEN

WRTEN2
IR
OE1
&
OR

OE2
36/
00-035 00-017 QO-Q17

D- OR

?
-
IR
-D '--

'----
SN74ACT7813
>WRTCLK ROCLK
' - - - WRTEN1 ROEN
WRTEN2 OE1
IR OR - r--
OE2 -
36/
00-017 QO-Q17 QO-Q35

Figure 8. Word·Width Expansion: 64 x 36 Bits

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-15
SN74ACT7813
64 x 18 CLOCKED FIRST-IN, FIRST·OUT MEMORY
SCAS199- JANUARY 1991- REVISED APRIL 1992

From Output
Under Test

RL
=nT
=500 a
PARAMETER MEASUREMENT INFORMATION

CL =50 pF
Input

tpd
L
---'1
- ,.1.-
I'
....
_1
~
\ ~~---
I·
I
14 ~
I
tpd
3V
GND

I r----'"'\:::T
--
I I
Output
I 3V
1.5V
-- -- _ _ _ _oJ OV

LOAD CIRCUIT TOTEM·POLE OUTPUTS

Figure 9. Standard CMOS Outputs (IR, OR, HF, AF/AE)

, . . . . - - - 3V

Input 1.5V 1.5 V

I Q. ____ OV
tPZL--.I ~ I
I I tpLZ -+i ,....
~
II =3.5V

Output II I I __ 1.5 V .L
L
R1
- - T - VOL
From Output
Under Test ----..,.-->--.....- Test Point
tPZH
I
--.J I+-
tpHZ +I ~ L 0.3 V
I .J. - -
R2 , VOH

Output _ _ -oJ! 1.5 V ~ V=0 V

LOAD CIRCUIT VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PARAMETER R1, R2 CLf S1

tpZH Open
ten 500 a 50pF
tpZL Closed
tpHZ Open
tdis 500 a 50 pF
tpLZ Closed
tpd 500 a 50pF Open
t Includes probe and test-fixture capacitance

Figure 10. 3-State Outputs (Any Q)

~lEXAS
INSTRUMENTS
7-16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7805
256 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY

• Member of the Texas Instruments DLPACKAGE

(TOP VIEW)
Widebus™ Family
• Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident RESET 1 OE1
017 Q17
• Read and Write Operations Synchronized 016 Q16
to Independent System Clocks Q15
015
• Input-Ready Flag Synchronized to Write 014 GNO
Clock Q14
• Output-Ready Flag Synchronized to Read Vee
Clock Q13
• 256 Words by 18 Bits Q12
• Low-Power Advanced CMOS Technology Vee Q11
09 11 Q10
• Half-Full Flag and Programmable 08 Q9
Almost-FuIl/Almost-Empty Flag
GNO GNO
• Bidirectional Configuration and Width 07 Q8
Expansion Without Additional Logic 06 Q7
• Fast Access Times of 12 ns With a 50-pF 05 Q6
Load and All Data Outputs Switching 04 Q5
Simultaneously 03 Vee
• Data Rates From 0 to 67 MHz 02 Q4
• Pin Compatible With SN74ACT7803 and 01 Q3
SN74ACT7813 DO Q2
HF GNO
• Packaged in Shrink Small-Outline 300-mil
PEN Q1
Package (DL) Using 25-mil Center-to-Center
AF/AE QO
Spacing
WRTCLK ROCLK
description WRTEN2 ROEN
WRTEN1 OE2
The SN74ACT7805 is a 256-word x 18-bit clocked IR OR
FIFO suited for buffering asynchronous data
paths at 67-MHz clock rates and 12-ns access
times. Its 56-pin shrink small-outline package (DL)
offers greatly reduced board space over DIP, PLCC, and conventional SOIC packages. Two devices can be
configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GN D pins along
with TI's patented Output Edge Control (OEC™) circuit dampen simultaneous switching noise.
The write clock (WRTCLK) and read clock (RDCLK) should be free running and can be asynchronous or
coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low,
and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1 , and OE2 are low
and OR is high. The first word written to memory is clocked through to the output buffer regardless of the RDEN,
OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four
WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes
the IR, OR, and HF flags low and the AF/AE flag high. The FIFO must be reset upon power up.
The SN74ACT7805 is characterized for operation from O°C to 70°C.

Widebus and OEe are trademarks of Texas Instruments Incorporated.

Copyright © 1992, Texas Instruments Incorporated
~~o~~~~~~~o~:1: s~~rw:~~sl~e~~~:~!r: g,' ~:~~:~m:~
standard warranty. Production processing does not necessarily Include
testing 01 all parameters. ~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-17
SN74ACT7805
256 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS201 - MARCH 1991 - REVISED APRIL 1992

logic symbolt

<l>
1 FIFO 256 x 18
RESET
25
" RESET SN74ACT7805
WRTCLK WRTCLK
27
WRTENl
26 f'.- JWRTEN
WRTEN2 28
32 IN ROY IR
ROCLK ROCLK 22
HALF·FULL HF
56 t-- 24
OEl ALMOST FULUEMPTY AF/AE
30 t-- =:JENl 29
OE2 OUT ROY OR
~~
t-- ROEN
31 f'.-
23

21
f'.-
,
I--
PROGRAM ENABLE
r
33
DO 0 0 QO
20 34
01 Ql
19 36
02 Q2
18 37
03 Q3
17 38
04 Q4
16 40
05 Q5
15 41
06 Q6
14 42
07 Q7
12 43
08 Q8

~ ~1V'
11 45
09 Q9
9 46
010 Q10
8 47
011 Ql1
7 48
012 Q12
6 49
013 Q13
5 51
014 Q14
4 53
015 Q15
3 54
016 Q16
2 55
017 17 17 Q17

t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.

~TEXAS
INSTRUMENTS
7-18 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7805
256 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS201 - MARCH 1991 - REVISED APRIL 1992

functional block diagram

~tl Output
II
Control
I

~l
00-017

Location 1
-
~

RDCLK

- -
r--
'----
Synchronous
Read
Control ---.- I Read
Pointer
I
I
Location 2

I 256 x 18RAM

WRTCLK Synchronous
Write
WRTEN1 -- I"--i Write
I
I Pointer I
WRTEN2 Control I-- Location 255
Location 256
I
_U
Register QO-Q17

Status-
~ I OR
Reset Flag
Logic IR
Logic
I HF
AF/AE

~ThxAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-19
SN74ACT7805
256 x 18 CLOCKED FIRST-IN,FIRST-OUT MEMORY
SCAS201-MARCH 1991- REVISED APRIL 1992

Terminal Functions
TERMINAL
VO DESCRIPTION
NAME NO.
Almost-fuIValmost-empty flag. Depth offset values can be programmed for AF/AE, or the default
value of 32 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE
AF/AE 24 0 is high when memory contains X or less words or (256 - Y) or more words. AF/AE is high after
reset.
00-017 21-14,12-11,9-2 I 16-bit data input port
HF 22 0 Half-full flag. HF is high when the FIFO memory contains 126 or more words. HF is low after reset.
Input-ready flag.IR is synchronized to the low-te-high transition ofWRTCLK. When IR is low, the
IR 26 0 FIFO is full and writes are disabled. IR is low during reset and goes high on the second low-te-high
transition of WRTCLK after reset.
Output enables. When OE1, OE2, and ROEN are low and OR is high, data is read from the FIFO
OE1, OE2 56,30 I on a low-te-high transition of ROCLK. When either OEl or 0E2 is high, reads are disabled and
the data outputs are in the high-impedance state.
Output-ready flag. OR is synchronized to the low-te-high transition of ROCLK. When OR is low,
the FIFO is empty and reads are disabled. Ready data is present on QO-Q17 when OR is high.
OR 29 0 OR is low during reset and goes high on the third low-te-high transition of ROCLK after the first
word is loaded to empty memory.
Program enable. After reset and before the first word is written to the FIFO, the binary value on
PEN 23 I
00-06 is latched as an AF/AE offset value when PEN is low and WRTCLK is high.
33-34, 36-38, 16-blt data output port. After the first valid write to empty memory, the first word Is output on
QO-Q17 40-43,45-49,51, 0 QO-Q17 on the third rising edge of ROCLK. OR is also asserted high atthistimeto indicate ready
53-55 data. When OR is low, the last word read from the FIFO is present on QO-Q17.
Read clock. ROCLK is a continuous clock and can be asynchronous or coincident to WRTCLK.
ROCLK 32 I A low-to-high transition ofROCLK reads data from memory when OE1, OE2, and ROEN are low
and OR is high. OR is synchronous to the low-to-high transition or ROCLK.
Read enable. When ROEN, OE1, and OE2 are low and OR is high, data Is read from the FIFO
ROEN 31 I
on the low-to-high transition of ROCLK.
Reset. To reset the FIFO, four low-te-high transitions of ROCLK and four low-to-high transitions
RESET 1 I
of WRTClK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high.
Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to ROCLK.
WRTCLK 25 I A low-to-high transition of WRTCLK writes data to memory when WRTEN2 is low, WRTEN1 is
high, and IR is high. IR is synchronous to the low-to-high transition of WRTCLK.
WRTEN1, Write enables. When WRTENl is high, WRTEN2 is low, and IR is high, data is written to the FIFO
27,26 I
WRTEN2 on a low-te-high transition of WRTCLK.

~1ExAs
INSTRUMENTS
7-20 POST OFFICE SOX 655303 • DALlAS. TEXA3 75265
 SN74ACT7805
256 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS201 - MARCH 1991 - REVISED APRIL 1992

WRTCLK

I I

00-017 .)l!~~
I I I I
I I
RDCLK I 1 I2 3 4 I I
I I
- I
OE1 Don't Care I
vyyyy y

QO-Q17 Invalid

AF/AE ~n't Care I

- - ryvyy:..- I
I I
~3:~~~"O~"O~~~~~:OO::~,o::v~'" I
HF Don't Care
yyyvyyy_ I

Define the AF/AE Flag Using the

==
Default Value of X Y 32

Figure 1. Reset Cycle

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-21
SN74ACT7805
256 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS201 - MARCH 1991 - REVISED APRIL 1992

1
o
1
o

WRTCLK

1
WRTEN1 o
I I I I
I I I I
I I I I

00-017 <SO<g @jW1 W2

:
~ tAA W3
; I
W4 =
--'~--------------------~I------~:~----~I~----~I~
I
W~+2) ~
I
W1'29

I
~w+-Y)q W~57 re
I I
ROCLK
~~r-fTL.-;r-flL
I I I
I I I
I I I 1
I I i o
I I I
I
I
:I i
I o
I I I
I I I
I I I o
: : I I
QO-Q17
_______lnv_a_"d______~«~----~;------~t-1----~------~:---
OR I :
AF/AE

HF

IR
L
Figure 2. Write

~TEXAS
INSTRUMENTS
7-22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7805
256 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS201 - MARCH 1991 - REVISED APRIL 1992

1
o
1
o

WRTCLK

1 1
WRTEN1 ~ I
1 1
1 1 1
WRTEN2 I I
o
1 1

00-017) Wf57

1 1

ROCLK 1 ---..,1 r--fl--,~~r-fl-fl-

1
1
1 1
OE1 I 1
1 I o
1 1
1 1
ROEN 1 1
1 1
1 1
OE2 I I
1 1
I
QO-Q17 WI
>G:X : W3 +57

OR I
1
1
1
AF/AE 1

1
1
HF 1
1
1

IR 1 ..._____---'
Figure 3. Read

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALUlS, TEXAS 75265 7-23
SN74ACT7805
256 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS201 - MARCH 1991- REVISED APRIL 1992

offset values for AF/AE

The aimost-fuil/aimost-empty flag has two programmable limits: the almost-empty offset value (X) and the
almost-full offset value (Y). They can be programmed after the FI FO is reset and before the first word is written
to memory. If the offsets are not programmed, the default values of X = Y = 32 are used. The AF/AE flag is high
when the FIFO contains X or less words or (256 - Y) or more words.
Program enable (PEN) should be held high throughout the reset cycle. PEN can be brought low only when IR
is high and WRTCLK is low. On the following low-to-high transition of WRTCLK, the binary value on 00-06 is
stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another
low-to-high transition of WRTCLK reprograms Y to the binary value on 00-06 at the time of the second
WRTCLK low-to-high transition. When the offsets are being programmed, writes to the FIFO memory are
disabled regardless of the state of the write enables (WRTEN1, WRTEN2). A maximum value of 127 can be
programmed for either X or Y (see Figure 4). To use the defa41t values of X = Y = 32, PEN must be held high.

WRTCLK 3

00-06

IR I
WRTEN1

WRTEN2~
Figure 4. Programming X and Y Separately

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, VI ........................................................................... 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under"absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

~TEXAS
INSTRUMENTS
7-24 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7805
256 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS201 - MARCH 1991 - REVISED APRIL 1992

recommended operating conditions

'ACT7805-15 'ACT7805-20 'ACT7805-25 'ACT7805-40
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 0.8 V
IOH High-level output current Q outputs, Flags -8 -8 -8 -8 mA
Q outputs 16 16 16 16
IOL Low-level output current mA
Flags 8 8 8 8
fclock Clock frequency 67 50 40 25 MHz
WRTCLK high or low 6 7 8 12
tw Pulse duration RDCLK high or low 6 7 8 12 ns
PEN low 8 9 9 12
DO-D17 before
4 5 5 5
WRTCLKi
WRTEN1, WRTEN2
4 5 5 5
before WRTCLKi
OE1,OE2
5 5 6 6
before RDCLKi
tsu Setup time RDEN before RDCLKi 4 5 5 5 ns
Reset: RESET low
before first WRTCLKi 5 6 6 6
and RDCLKit
PEN before WRTCLKi 5 6 6 6
Define AF/AE: PEN
5 6 6 6
before WRTCLKi
DO-D17) after
0 0 0 0
WRTCLKi
WRTEN1, WRTEN2
0 0 0 0
after WRTCLKi
OE1, OE2, RDEN
0 0 0 0
th Hold time after RDCLKi ns
Reset: RESET low
after fourth WRTCLKi 2 2 2 2
and RDCLKit
Define AF/AE: PEN
2 2 2 2
after WRTCLKi
TA Operating free-air temperature 0 70 0 70 0 70 0 70 ·C
..
t To permit the clock pulse to be utilized for reset purposes

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-25
SN74ACT7805
256 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS201 - MARCH 1991 - REVISED APRIL 1992

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VOH VCC = 4.5 V, IOH=-8mA 2.4 IV
I Flags VCC=4.5 V, IOL=8 mA 0.5
VOL V
I Qoutputs VCC = 4.5 V, IOL=16mA 0.5
II VCC=5.5V. VI = VCC orO ±5 ~
IOZ VCC= 5.5 V, Vo = Vce orO ±5 ~
ICC VI=VCC-0.2VorO 400 ~
6ICC:l: VCC=5.5V, One input at 3.4 V, Other inputs at Vee or GND 1 mA
Ci VI = 0, f= 1 MHz 4 pF
Co VO=O, f= 1 MHz 8 pF
t All typical values are at Vce = 5 V, TA = 25°C.
:l: This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figures 9 and 10)
FROM TO 'ACT7805-i5 'ACT7805-20 'ACT7805-25 'ACT7805-40
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYPt MAX MIN MAX MIN MAX MIN MAX
WRTCLKor
fmax 67 50 40 25 MHz
RDCLK
tpd 4 9.5 12 4 13 4 15 4 20
RDCLKT AnyQ ns
tpd§ 8.5
tpd WRTCLKi IR 3 8.5 3 11 3 13 3 15 ns
tDd RDCLKi OR 3 8.5 3 11 3 13 3 15 ns
WRTCLKi 7 16.5 7 19 7 21 7 23
tpd AF/AE ns
RDCLKi 7 17 7 19 7 21 7 23
tPLH WRTCLKi 7 15 7 17 7 19 7 21
HF ns
tPHL RDCLKi 7 15.5 7 18 7 20 7 22
tpLH AF/AE 2 9 2 11 2 13 2 15
RESET low ns
tpHL HF 2 10 2 12 2 14 2 16
ten 2 8.5 2 11 2 11 2 11
OE1, OE2 AnyQ ns
tdis 2 9.5 2 11 2 14 2 14
§ This parameter IS measured with a 30-pF load (see Figure 5).

operating characteristics, Vee = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance per FIFO channel Outputs enabled CL =50 pF, f = 5 MHz

~lEXAS
INSTRUMENTS
7-26 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7805
256 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS201- MARCH 1991 - REVISED APRIL 1992

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
typ +8
VCC ~5V ./
-TA=25°C
RL=500Q V
I/)
typ+6 /
c
I
CI)
/
E
j::
>- typ+4
/
.!!! ~
2l /

~
c
0
typ + 2 /
Cl
to
C.
e /
D.
I V
..
'0
C.
typ
/
typ-2
/
o 50 100 150 200 250 300

CL - Load Capacitance - pF

Figure 5

SUPPLY CURRENT
vs
CLOCK FREQUENCY
200 I
TA = 75°C
180 CL = 0 pF VCC=5.5V ~
./
160
«
E 140
VCC=5V~
V ./

~
I

120
/ IY . /
::I
0 100 / / /
>-
C.
c.
::I 80
V/ // VCC = 4.5 V
en
I
e: 60 h V
0
0 40 £. ~
20
0
,.~'P'
o 10 20 30 40 50 60 70

1c lock - Clock Frequency - MHz

Figure 6

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-27
SN74ACT7805
256 x 18 CLOCKED FIRST-IN, FIRST·OUT MEMORY
SCAS201 - MARCH 1991 - REVISED APRIL 1992

TYPICAL CHARACTERISTICS

calculating power dissipation

With ICC(f) taken from Figure 6, the maximum power dissipation (PT) based on all data outputs changing states
on each read can be calculated using:
PT = Vcc x [ICC(!) + (N x illcc x de)] + E(CL x Vcc2 x fo)
A more accurate power calculation based on device use and average number of data outputs switching can be
found using:
PT = Vcc x [IcC + (N x illCC x de)] + E(Cpd x Vcc 2 x fi) + E(CL x Vcc2 x 10 )
where:
Icc power-down Icc maximum
N number of inputs driven by a TTL device
il Icc increase in supply current
dc duty cycle 01 inputs at a TTL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
Ii data input frequency
fo data output frequency

~TEXAS
INSTRUMENTS
7-28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7805
256 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS201 - MARCH 1991 - REVISED APRIL 1992

APPLICATION INFORMATION

SN74ACT7805
CLOCK A WRTCLK RDCLK CLOCKB
WiRA WRTEN1 OE1 WiRB

CSA WRTEN2 RDEN CSB

OE2 ~

18/
00-017 QO-Q17 BO-B17

SN74ACT7805
- ~ ROCLK WRTCLK
' - - - OE1 WRTEN1
ROEN WRTEN2
L OE2

18/
AO-A17 QO-Q17 00-017

Figure 7. Bidirectional Configuration

SN74ACT7805
WRTCLK WRTCLK ROCLK ROCLK
WRTEN1 WRTEN1 ROEN

WRTEN2
IR
OE1
OR
r&
OE2
36/
00-035 00-017 QO-Q17

D- OR

IR
L
- SN74ACT7805
'-- P. WRTCLK ROCLK
'--- WRTEN1 ROEN
WRTEN2 OE1
IR OR r- -
OE2 r-
36/
00-017 QO-Q17 QO-Q35

Figure 8. Word·Width Expansion: 256 x 36 Bits

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-29
SN74ACT7805
256 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS201 - MARCH 1991 - REVISED APRIL 1992

PARAMETER MEASUREMENT INFORMATION

Input~ \1.~--- 3V
FromOutput=n
Under Test

RL=500Q T CL=50pF
tpd 14 ~
I
I
14 ~tpd
I
I I GND

-- --
Output
................J
I - -
I ,.----'\~t-
1.5V
3V

OV

LOAD CIRCUIT TOTEM·POLE OUTPUTS

Figure 9. Standard CMOS Outputs (IR, OR, HF, AF/AE)

,...........- 3V

Input 1.5V 1.5V

I Q.. ____ OV
7V tpZL~ ~ I
I I -+i I+-
~
tpLZ

~
RL = R1 = R2 rl ~3.5V
S1
Output I I I __ L 1.5V
I - - T - VOL
From Output
Under Test ----<1-...........-.....-
Test Point I tpHZ+I I+- L 0.3 V
R2
tpZH -.r ~ IL
I . . . J - - VOH
Output _ _ --J! 1.5V ~V ~OV
LOAD CIRCUIT VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES

PARAMETER R1, R2 CLt S1

tpZH Open
len 500 a 50pF
tpZL Closed
tpHZ Open
'dis 500 a 50pF
tpLZ Closed
tpd 500 a 50pF Open
t Includes probe and test·flxture capacitance
Figure 10. 3-State Outputs (Any Q)

~1ExAs
INSTRUMENTS
7-30 POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
 SN74ACT7803
512 x 18
FIRST·OUT MEMORY

• Member of the Texas Instruments DLPACKAGE

Widebus ™ Family (TOP VIEW)

• Free-Running Read and Write Clocks Can

OE1
Be Asynchronous or Coincident
Q17
• Read and Write Operations Synchronized Q16
to Independent System Clocks Q15
• Input-Ready Flag Synchronized to Write 014 GNO
Clock 013 51 Q14
• Output-Ready Flag Synchronized to Read 012 7 50 Vee
Clock 011 49 Q13
48 Q12
• 512 Words by 18 Bits
Q11
• Low-Power Advanced CMOS Technology
Q10
• Half-Full Flag and Programmable 08 Q9
Almost-FuIl/Almost-Empty Flag GNO GNO
• Bidirectional Configuration and Width 07 Q8
Expansion Without Additional Logic 06 Q7
• Fast Access Times of 12 ns With a 50-pF 05 41 Q6
Load and All Data Outputs Switching 04 40 Q5
Simultaneously 03 39 Vee
• Data Rates From 0 to 67 MHz 02 38 Q4
01 37 Q3
• Pin Compatible With SN74ACT7805 and
00 36 Q2
SN74ACT7813
HF 35 GNO
• Available in Shrink Small-Outline 30Q-mil PEN 34 Q1
(DL) Package Using 25-mil Center-to-Center 33
AF/AE QO
Spacing
WRTCLK 32 ROCLK
WRTEN2 31 ROEN
description
WRTEN1 30 OE2
The SN74ACT78D3 is a 512-word x 18-bit FIFO IR 29 OR
suited for buffering asynchronous data paths at
67-MHz clock rates and 12-ns access times. Its
56-pin shrink small-outline package (DL) offers
greatly reduced board space over DIP, PLCC, and conventional SOIC packages. Two devices can be configured
for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins along with TI's
patented output-edge-control (OEC™) circuit dampen simultaneous switching noise.
The write clock (WRTCLK) and read clock (RDCLK) should be free running and can be asynchronous or
coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low,
and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low
and OR is high. The first word written to memory is Clocked through to the output buffer regardless of the RDEN,
OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four
WRTCLKand four RDCLK riSing edges occur to clear the synchronizing registers. Resetting the FIFO initializes
the IR, OR, and HF flags low and the AF/AE flag high. The FIFO must be reset upon power up.
The SN74ACT78D3 is characterized for operation from DOC to 7DoC.

Widebus and OEe are trademarks of Texas Instruments Incorporated.

Copyright © t995. Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-31
SN74ACT7803
512 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS191A-MARCH 1991 -REVISED JULY 1995

logic symbolt

<I>
1 FIFO 512 x 18
RESET
25
" RESET SN74ACT7803

WRTCLK WRTCLK
27
WRTEN1 28
26 J'-, tJWRTEN IN ROY IR
WRTEN2 22
32 HALF-FULL HF
ROCLK ROCLK 24
56 ALMOST FULUEMPTY AF/AE

~EN1
"- 29
OE1 OUT ROY OR
30 "-
OE2
~7
31
" ROEN

" I--
23
.,
" PROGRAM ENABLE r
33
21
DO 0 0 QO
20 34
01 Q1
19 36
02 Q2
18 37
03 Q3
17 38
04 Q4
16 40
05 Q5
15 41
06 Q6
14 42
07 Q7
12 43
08 Q8
09
11
9 ~ ~1V 45
46
Q9
010 Q10
8 47
011 Q11
7 48
012 Q12
6 49
013 Q13
5 51
014 Q14
4 53
015 Q15
3 54
016 Q16
2 55
017 17 17 Q17

t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.

~1EXAS
INSTRUMENTS
7-32 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7803
512 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS191A-MARCH 1991- REVISED JULY 1995

functional block diagram

---<t---
- .-
Output
Control I
I
00-017

-
jJ
Location 1
ROCLK -i f--
'--
Synchronous
Read
f--+-
I Read
Pointer
I
I
Location 2

ROEN - f-- Control

I 512x18RAM

WRTCLK -r-

~
Synchronous
I Write
WRTEN1 -r-
WRTEN2 - f -
Write
Control ~ I-- I Pointer I Location 511
Location 512
I
~J
Register QO-Q17

Status-
- OR
'--- Reset
Logic I
I
Fisg
Logic IR
HF
AF/AE

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75285 7-33
SN74ACT7803
512 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS191A-MARCH 1991 - REVISED JULY 1995

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
Aimost-fuli/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default
AF/AE 24 0 value of 64 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is
high when memory contains X or less words or (512 - Y) or more words. AF/AE is high after reset.
2-9,11-12,
00-017 I The 18-bit data input port
14-21
HF 22 0 Half-full flag. HF is high when the FIFO memory contains 256 or more words. HF is low after reset.
Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the
IR 28 0 FIFO is full and writes are disabled. IR is low during reset and goes high on the second low-to-high
transition of WRTCLK after reset.
Output enables. When OE1, OE2, and ROEN are low and OR is high, data is read from the FIFO on
OE1, OE2 56,30 I a low-to-high transition of ROCLK. When either OEl or OE2 is high, reads are disabled and the data
outputs are in the high-impedance state.
Output-ready flag. OR is synchronized to the low-te-high transition of ROCLK. When OR is low, the
FIFO is empty and reads are disabled. Ready data is present on aO-a17 when OR is high. OR is
OR 29 0
low during reset and goes high on the third low-to-high transition of ROCLK after the first word is
loaded to empty memory.
Program enable. After reset and before the first word is written to the FI FO, the binary value on
PEN 23 I
00-07 is latched as an AF/AE offset value when PEN is low and WRTCLK is high.
33-34,36-38, The 18-bit data output port. After the first valid write to empty memory, the first word is output on
aO-a17 40-43,45-49, 0 aO-a17 on the third rising edge of ROCLK. OR is also asserted high at this time to indicate ready
51,53-55 data. When OR is low, the last word read from the FIFO is present on aO-a17.
Read clock. ROCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A
ROCLK 32 I low-te-high transition of ROCLK reads data from memory when OE1, OE2, and ROEN are low and
OR is high. OR is synchronous to the low-te-high transition of ROCLK.
Read enable. When ROEN, OE1, and OE2 are low and OR is high, data is read from the FIFO on
ROEN 31 I
the low-to-high transition of ROCLK.
Reset. To reset the FIFO, four low-to-high transitions of ROCLK and four low-te-high transitions of
RESET 1 I
WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high.
Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A
WRTCLK 25 I low-to-high transition of WRTCLK writes data to memory when WRTEN2 is low, WRTENl is high,
and IR is high. IR is synchronous to the low-to-high transition of WRTCLK.
WRTEN1, Write enables. When WRTENl is high, WRTEN2 is low, and IR is high, data is written to the FIFO
27,26 I
WRTEN2 on a low-to-high transition of WRTCLK.

~TEXAS
INSTRUMENTS
7-34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7803
512 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS191A-MARCH 1991- REVISED JULY 1995

WRTCLK

I I
WRTEN1

00-017

ROCLK

I I! I
QO-Q17 Invalid

i I I
OR~~yd8~
~ .

AF/AE~ I
I
'eI~oe"oeDoeOnoe1oeCaoe"roeeoe"5<loel
II
HF ~yvvyyyy~ I
I

Define the AF/AE Flag Using the

==
Default value of X Y 64

Figure 1. Reset Cycle

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75266 7-35
SN74ACT7803
512 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS191A - MARCH 1991 - REVISED JULY 1995

1
o
1
o

WRTCLK
~~~~
I I I I 1
WRTEN1 I I I I o
I I I I
I I II
---, I I I I
WRTEN2 ~-----------------------TI------~I------~'------~'~-
I I I I
00-017 2SAA WI ® WI gsa wal@ W4 W~+2) d
wdS7 .w+-~. W~13 RS dJ
I . I I I
ROCLK

I I I
r-ftL--,~~~
_________________~I--------~I-------4I------_+------_+-- o
1
OE1
I I I
I I I
I I I 1
I I I o
I I I
I I I 1
OE2 I I I
----------------~I--------~I-------+I------~------~-- o
I I I
QO-Q17 _______'_nv_sl_ld______ --fX'-______.:._______ 1______
w'!'": ~------_r_-

OR ________________ ~ :I II
I I
A~E ------------~II I I
I
HF ________________________________~I

IR
L
Figure 2. Write Cycle

~TEXAS
INSTRUMENTS
7-36 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7803
512 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS191A- MARCH 1991 - REVISED JULY 1995

....................................................................................................................- - - 1
RESET 0

........................................................- -........................................................- - - 1
PEN 0

WRTCLK

I I
WRTEN1 ~ i
I I
I I 1
WRTEN2 I I
o
I I
00-0171 Wf13
I I
ROCLK I ~I---I,~r-fl--,~~
I
I I
I 1
OE1 I o
I i
I I
I I
ROEN
I I
I I
I I
OE2
i I
I I
I
QO-Q17 W1
>GX >3 +13
OR i
I
I
I
AF/AE I
I
I
HF I
I
I
IR 1 . . _____ ----1

Figure 3. Read Cycle

~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-37
SN74ACT7803
512 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS191A- MARCH 1991 - REVISED JULY 1995

offset values for AF/AE

The aimost-fuil/almost-empty flag has two programmable limits: the almost-empty offset value (X) and the
almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written
to memory. If the offsets are not programmed, the default values of X =Y =64 are used. The AF/AE flag is high
when the FIFO contains X or less words or (512 - Y) or more words.
Program enable (PEN) should be held high throughout the reset cycle. PEN can be brought low only when IR
is high and WRTCLK is low. On the following low-to-high transition of WRTCLK, the binary value on 00- 07 is
stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another
low-to-high transition of WRTCLK reprograms Y to the binary value on 00-07 at the time of the second
WRTCLK low-to-high transition. When the offsets are being programmed, writes to the FIFO memory are
disabled regardless of the state of the write enables (WRTEN1, WRTEN2). A maximum value of 255 can be
programmed for either X or Y (see Figure 4). To use the default values of X = Y = 64, PEN must be held high.

WRTCLK

00-07

IR I
WRTEN1

WRTEN2~
Figure 4. Programming X and Y Separately

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, VI ........................................................................... 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

~TEXAS
INSTRUMENTS
7-38 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7803
512 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS191A- MARCH 1991 - REVISED JULY 1995

recommended operating conditions

'ACT7803-15 'ACT7803-20 'ACT7803-25 ' ACT7803-40
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 0.8 V'
IOH High-level output current Q outputs, Flags -8 -8 -8 -8 mA
Q outputs 16 16 16 16
IOL Low-level output current mA
Flags 8 8 8 8
fclock Clock frequency 67 50 40 25 MHz
WRTCLK high or low 6 7 8 12
tw Pulse duration RDCLK high or low 6 7 8 12 ns
PEN low 8 9 9 12
DO- D17 before
4 5 5 5
WRTCLKi
WRTEN1. WRTEN2
4 5 5 5
before WRTCLKi
OE1,OE2
5 5 6 6
tsu Setup time before RDCLKi ns
RDEN before RDCLKi 4 5 5 5
Reset: RESET low
before first WRTCLKi 5 6 6 6
and RDCLKit
PEN before WRTCLKi 5 6 6 6
DO - D 17 after
0 0 0 0
WRTCLKi
WRTEN1. WRTEN2
0 0 0 0
after WRTCLKi
OE1, OE2, RDEN
0 0 0 0
after RDCLKi
th Hold time Reset: RESET low ns
after fourth WRTCLKi 2 2 2 2
and RDCLKit
PEN high
0 0 0 0
after WRTCLKJ.
PEN lowaller
2 2 2 2
WRTCLKi
TA Operating free-air temperature 0 70 0 70 0 70 0 70 'c
..
t To permit the clock pulse to be utilized for reset purposes

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-39
SN74ACT7803
512 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCASI91A-MARCH 1991-REVISEDJULY 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP't MAX UNIT
VOH VCC=4.5V, IOH=-8mA 2.4 V

VOL
I Flags VCC = 4.5 V, IOL-8mA 0.5
V
I o outputs VCC-4.5V, IOL-16mA 0.5
II VCC = 5.5 V, VI=VccorO ±5 jlA
IOZ VCC-5.5V, Vo=VccorO ±5 jlA
ICC VI = VCC-0.2VorO 400 jlA
AICC* VCC-5.5V, One input at 3.4 V, Other inputs at VCC or GND 1 rnA
Ci VI=O, 1= 1 MHz 4 pF
Co VO-O, 1-1 MHz 8 pF
t All typical values are at VCC - 5 V, TA - 25·C.
* This is the supply current lor each input that is at one 01 the specified TTL voHage levels rather than 0 V or VCC.

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 50 pF (unless otherwise noted) (see Figures 9 and 10)
FROM TO 'ACT7803-15 'ACT7803-20 'ACT7803-25 'ACT7803-40
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYPt MAX MIN MAX MIN MAX MIN MAX
WRTCLKor
Imax 67 50 40 25 MHz
RDCLK
tpd 4 9.5 12 4 13 4 15 4 20
RDCLKi Any 0 ns
tpd§ 8.5
tpd WRTCLKi IR 3 8.5 3 11 3 13 3 15 ns
tpd RDCLKi OR 3 8.5 3 11 3 13 3 15 ns

t~d WRTCLKi AF/AE 7 16.5 -7 19 7 21 7 23 ns

tpd RDCLKi AF/AE 7 17 7 19 7 21 7 23 ns
tpLH WRTCLKi 7 15 7 17 7 19 7 21
HF ns
tPHL RDCLKi 7 15.5 7 18 7 20 7 22
tpLH AF/AE 2 9 2 11 2 13 2 15
RESET low ns
tPHL HF 2 10 2 12 2 14 2 16
ten 2 8.5 2 11 2 11 2 11
OO,OE2 Any 0 ns
tdis 2 9.5 2 11 2 14 2 14
§ ThiS parameter IS measured With a 30-pF load (see Figure 5).

operating characteristics, Vee =5 V, TA =25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance Outputs enabled CL-50pF, 1=5MHz

~1ExAs
INSTRUMENTS
7-40 POST OFFICE BOX 655303 • PALLAS. TEXAS 75265
 SN74ACT7803
512 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS191A- MARCH 1991 - REVISED JULY 1995

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
typ + 8
VCC~ 5V ~
-TA=25°C
V
.. typ + 6
RL = 500 g
/
I:
I
CD
/
E
j::
>- typ +4
/
.!!! /
CD
C /
I:
0
~
/
..
CI
II.
typ + 2

/
e
II.
I
'0 typ V
-II.
/
/
typ-2
o 50 100 150 200 250 300

CL - Load Capacitance - pF

Figure 5

SUPPLY CURRENT
vs
CLOCK FREQUENCY
200 I
TA = 75°C
180 CL= OpF
VCC=5.5V ~ /
160
<
E 140
VCC=5V --.......
V ./
C
I

~:::I 120
/ IY /
0
>-
100 L L '/
Q.
II.
:::I 80
V/ / VCC = 4.5 V
til

E
I
60 h- ~
0
E 40 ~~
20
0
,~W
o 10 20 30 40 50 60 70

fclock - Clock Frequency - MHz

Figure 6

-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-41
SN74ACT7803
512 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS191A-MARCH 1991- REVISED JULY 1995

TYPICAL CHARACTERISTICS

calculating power dissipation

With ICC(!) taken from Figure 6, the maximum power dissipation (PT) based on all data outputs changing states
on each read can be calculated by:
PT = VCC(!) x [iCC(!) + (N x 61cc x dc)] + l:(CL x VCc2 x fo)
A more accurate power calculation based on device use and average number of data outputs switching can be
found by:
PT = VCC x [ICC(I) + (N x 61cc x dc)] + l:(Cpd x VCc 2 x fi) + l:(CL x VCc2 x fo)
where:
ICC(I) idle ICC maximum (see Figure 7)
N number of inputs driven by a TTL device
6 Icc increase in supply current
dc duty cycle of inputs at a TTL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
fi data input frequency
fo data output frequency

9r-------r-------.-------r_------r_------r_----~r_----~

8 -e- Vee = 4.5 V

___ Vee=5V
7 ...... Vee=5.5V
TA = 25·
c( 6
E
I
g 5
-
.9!
:E 4
I

rr
_0
3

f - Frequency - MHz

Figure 7. SN74ACT7803 Idle Icc With RDCLK or WRTCLK Switching

~TEXAS
INSTRUMENTS
7-42 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7803
512 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS191 A - MARCH 1991 - REVISED JULY 1995

APPLICATION INFORMATION

SN74ACT7803
CLOCK A WRTCLK ROCLK CLOCKB
wiAA WRTENl on WiRB
CIA WFiftN2 RDEN CSB
0E2 --1

18/
00-017 QO-Q17 BO-B17

SN74ACT7803
- I>
ROCLK WRTCLK
' - - - OEl WRTENl
RDEN WR'f!N2
L OE2

18I
AO-A17 QO-Q17 DO-017

Figure 8. Bidirectional Configuration

SN74ACT7803
WRTCLK WRTCLK RDCLK RDCLK
WRTENl WRTENl RDEN

WFfI'EIii2
IR
m
OR
Ib
0E2
38/

-
DO-D35 00-017 QO-Q17

- -
I OR

IR
J I--
' - - >WRTCLK
' - - WRTENl
SN74ACT7803
ROCLK
RDEN
V
WRTEN2 on
IR OR r- -
0E2 I-
38/
DO-D17 QO-Q17 QO-Q36

Figure 9. Word-Width expansion: 512 x 38 Bits

:illExAs
INSTRUMENTS
POST OFFICE BOX _ . DAllAS. TEXAS 75266 7-43
SN74ACT7803
512 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCASI91A-MARCH 1991-REVISEDJULY 1995

From Output
Under Test
=nT
RL=500n
PARAMETER MEASUREMENT INFORMATION

Input~
tpd -iIII!..--.!.!,
,
\-:;:~---
"
III
oJ
PI
,

, tpd
3V

GND

Output
________J
I' "---~~T-- 1.5 V
3V
OV

LOAD CIRCUIT TOTEM-POLE OUTPUTS

Figure 10. Standard CMOS Outputs (IR, OR, HF, AF/AE)

~---3V

Input 1.5 V 1.5V

I\...._--Ia. ____ OV
tpZL -.J j.- I
I tpLZ -+j I+-
~3.5V
-~ II
Output I I __ *-
- - . - VOL
From Output
Under Test ----<..........>--......-
Test Point tpHZ +l I+- L 0.3 V
~,..---rl .1_ -
-J1
R2 VOH

outp ut _ _ 1.5V ~V~OV

LOAD CIRCUIT VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES

PARAMETER R1,R2 cLt S1

tpZH Open
ten 500n 50pF
tPZL Closed
tpHZ Open
!dis 500n 50pF
tpLZ Closed
tpd 500n 50pF Open
t Includes probe and test-fixture capacitance

Figure 11. 3-State Outputs (Any Q)

~1ExAs
INSTRUMENTS
7-44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
JULY

• Member of the Texas Instruments '. Microprocessor Interface Control logic

Wldebus ™ Family • Programmable Almost-FuIl/Almost-Empty
• Free-Running ClKA and ClKB Can Be Flags
Asynchronous or Coincident • Fast Access Times of 9 ns With a 50-pF
• Read and Write Operations Synchronized load and Simultaneous Switching Data
to Independent System Clocks Outputs
• Two Separate 512 x is Clocked FIFOs • Data Rates up to SO MHz
Buffering Data In Opposite Directions • Advanced BICMOS Technology
• IRA and ORA Synchronized to ClKA • Available In 8O-Pin Quad Flat (PH) and
• IRB and ORB Synchronized to ClKB Space-Saving SO-Pin Thin Quad Flat (PN)
Packages
PH PACKAGE
(TOP VIEW)

~~o~~~~oooo~~~oIIOO
p~~~5~o$>$>~~5~~~~

RSTA FmTB
PENA PENB
AF/AEA AF/AEB
HFA HFB
IRA IRB
GND GND
AO BO
A1 B1
Vee Vee
A2. B2
A3 B3
GND GND
A4 B4
A5 B5
GND GND
A6 B6
A7 B7
GND GND
A8 B8
A9 B9
Vee Vee
A10 B10
A11 B11
GND GND

Widebus is a trademark of Texas Instruments Incorporated.

Copyright © 1995, Texas Instruments Incorporated

-!111ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 7-45
SN74ABT7819
512x18x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125D-JULY 1992- REVISED SEPTEMBER 1995

PNPACKAGE
(TOP VIEW)

1~lgl~ I~ ~
~~o ~
I g~ ~ 8 8f@ ~ ~ I ~ 1~1[g1~1~
o~o~~o~o ~ o~~

• 80 79 78 77 76 75 74 73 72 71 70 69 68 6766 6564 63 62 61
AF/AEA 1 60 AF/AEB
HFA 2 59 HFB
IRA 3 58 IRB
GND 4 57 GND
AO 5 56 BO
A1 6 55 B1
Vee 7 54 Vee
A2 8 53 B2
A3 9 52 B3
GND 10 51 GND
A4 11 50 B4
A5 12 49 B5
GND 13 48 GND
A6 14 47 B6
A7 15 46 B7
GND 16 45 GND
A8 17 44 B8
A9 18 43 B9
Vee 19 42 Vee
A10 20 41 B10
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
~ClC\l(,) OvlOClCDl'-l'-CDCllOv O(,)C\lCl~
""'Z""'T"'" U""'''''Z''''''''''''''''''''Z'-''''' OT""T"'"Zm
<~«>«~«mm~mm>mm~

description
A FI FO memory is a storage device that allows data to be read from its array in the same order it is written. The
SN74ABT7819 is a high-speed, low-power BieMOS bidirectional clocked FIFO memory. Two independent
512 x 18 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to
indicate empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag.
The SN74ABT7819 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The state of the AO-A 17 outputs is controlled by eSA and WiRA. When both eSA and WiRA are low, the outputs
are active. The AO-A17 outputs are in the high-impedance state when either eSA or WiRA is high. Data is
written to FIFOA-B from port A on the low-to-high transition of eLKA when eSA is low, W/RA is high, WENA
is high, and the IRA flag is high. Data is read from FIFOB-A to the AO-A 17 outputs on the low-to-high transition
of eLKA when eSA is low, WiRA is low, RENA is high, and the ORA flag is high.

~1ExAs
INSTRUMENTS
7-46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT7819
512 x 18x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST·OUT MEMORY
SCBS125D- JULY 1992 - REVISED SEPTEMBER 1995

description (continued)
The state of the BO-B17 outputs is controlled by CSB and W/RB. When both CSB and W/RB are low, the outputs
are active. The 80-B17 outputs are in the high-impedance state when either CSB or W/R8 is high. Data is
written to FIFOB-A from port B on the low-to-high transition of ClKB when CSB is low, W/RB is high, WENB
is high, and the IRB flag is high. Data is read from FIFOA-B to the BO-B17 outputs on the low-to-high transition
of ClKB when CSB is low, WiRB is low, RENB is high, and the ORB flag is high.
The setup- and hold-time constraints for the chip selects (CSA, CSB) and write/read selects (W/RA, W/RB)
enable write and read operations on memory and are not related to the high-impedance control of the data
outputs. If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock
cycle, the chip select and write/read select can switch at any time during the cycle to change the state of the
data outputs.
The input-ready and output-ready flags of a FIFO are two-stage synchronized to the port clocks for use as
reliable control signals. ClKA synchronizes the status of the input-ready flag of FIFOA-B (IRA) and the
output-ready flag of FIFOB-A (ORA). ClKB synchronizes the status of the input-ready flag of FIFOB-A (lRB)
and the output-ready flag of FIFOA-B (ORB). When the input-ready flag of a port is low, the FIFO receiving input
from the port is full and writes are disabled to its array. When the output-ready flag of a port is low, the FI FO that
outputs data to the port is empty and reads from its memory are disabled. The first word loaded to an empty
memory is sent to the FIFO output register at the same time its output-ready flag is asserted (high). When the
memory is read empty and the output-ready flag is forced low, the last valid data remains on the FIFO outputs
until the output-ready flag is asserted (high) again. In this way, a high on the output-ready flag indicates new
data is present on the FIFO outputs.
The SN74ABT7819 is characterized for operation from O°C to 70°C.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-47
SN74ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125D-JULY 1992-REVISEDSEPTEMBER 1995

logic symbolt
76 <I> 69
CLKA CLOCK A FIF0512x18x2 CLOCKB eLKB

CSA
80 "-
f--& SN74ABT7819
r--a /I 65
CSB
79 OE1 OE2 66
WiRA b WiRB

::;= '=:;::
.......,t::, & WRITE WRITE & d......,
ENABLE ENABLE
77 FIFOA-B FIFOB-A 68
WENA

----t::,
::::;:. -
~ d-
WENB

& READ READ &

75 " ENABLE
FIFOB-A
ENABLE
FIFOA-B
/I
70
RENA
1 - - 64
RENB

2 " RESET FIFO A-B RESET FIFO B-A /l

63
" FIFOA-B
PROGRAM ENABLE PROGRAM ENABLE /I
FIFO B-A
5 60
IRA INPUT·READY INPUT·READY IRB
PORTA PORTB
74 71
ORA OUTPUT·READY OUTPUT·READY ORB
4 PORTA PORTB 61
HFA HALF·FULL HALF·FULL HFB
FIFOA-B FIFOB-A
3 62
AF/AEA ALMOST·FULUEMPTY ALMOST·FULUEMPTY AF/AEB
~FOA-B FIFOB~

7 58
AO 0 0 BO
8 57
Ai B1
10 55
A2 B2
11 54
A3 B3
13 52
A4 B4
14 51
A5 B5
16 49
A6 B6
17 48
A7 B7
19 1\7 2\7 46
A8 B8

~ ~
20 45
A9 B9
22 43
A10 B10
23 42
A11 B11
25 40
A12 B12
26 39
A13 B13
28 37
A14 B14
29 36
A15 B15
31 34
A16 B16
32 33
A17 17 17 B17

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
Pin numbers shown are for the PH package.

~TEXAS
INSTRUMENTS
7-48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125D - JULY 1992 - REVISED SEPTEMBER 1995

functional block diagram

PENA
RENA
WENA Port-A
CSA Control
+
WiRA
ClKA
RSTA
logIc
Read
PoInter
I
J
), : RegIster:
18
512 x 18
Dual-Port SRAM
FIFOB-A
+-i RegIster

18
t 18
~ WrIte
PoInter I
I
Flag IRB
ORA logIc AF/AEB
FIFOB-A

-
HFB

-
8
AO-A17
BO-B17
8

IRA Flag
AF/AEA logIc
HFA ORB

r
FIFOA-B

I WrIte
I PoInter

t
512 x 18
18
RegIster t-- Dual-Port SRAM
FIFOA-B
I RegIster
I
L
1,.0 .....

t
I Read I
PoInter I RSTB
ClKB
Port-B CSB
Control WiRB
logIc WENB
RENB
PENB

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-49
SN74ABT7819
512x18x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125D- JULY 1992 - REVISED SEPTEMBER 1995

enable logic diagram (positive logic)

CSA ----+---<r---...
WiRA } - - - - - - - - WENFIFOA-B
WENA ---~+_-~_J

1-.....- - - - - - AO-A17 (output enable)

'------<CL~

1 - - - - - REN FIFOB-A
RENA -----------~

~-'J-+------ CSB
WEN FIFOB-A --------f WiRB
WENB

BO-B17 (output enable) -----~~~_ 0-----'

RENFIFOA-B
RENB

FUNCTION TABLES
SELECT INPUTS
AO-A17 PORT·A OPERATION
ClKA CSA W/RA WENA RENA
X H X X X HighZ None
l' l H H X HighZ Write AO-A17 to FIFOA-B
l' l L X H Active Read FIFOB-A to AO-A17

SELECT INPUTS
BO-B17 PORT·B OPERATION
ClKB CSB W/RB WENB RENB
X H X X X HighZ None
l' L H H X HighZ Write 80-B17 to FIFOB-A
l' L L X H . Active Read FIFOA-B to BO-B17

~1ExAs
INSTRUMENTS
7-50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125D - JULY 1992 - REVISED SEPTEMBER 1995

Terminal Functions
PIN NAME 1/0 DESCRIPTION
AO-A17 1/0 Port-A data. The 18-bit bidirectional data port for side A.
FIFOA-B aimost-fuil/almost-empty flag. Depth offsets can be programmed for AF/AEA or the default value of 128 can
AF/AEA 0 be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is high when X or less words or
(512 - Y) or more words are stored in FIFOA-B. AF/AEA is forced high when FIFOA-B is reset.
FIFOB-A aimost-fuil/almost-empty flag. Depth offsets can be programmed for AF/AEB or the default value of 128 can
AF/AEB 0 be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is high when X or less words or
(512 - Y) or more words are stored in FIFOB -A. AF/AEB is forced high when FIFOB -A is reset.
BO-B17 1/0 Port-B data. The 18-bit bidirectional data port for side B.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A to its low-te-high transition
ClKA I
and can be asynchronous or coincident to ClKB.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B to its low-to-high transition
ClKB I
and can be asynchronous or coincident to ClKA.
Port-A chip select. CSA must be low to enable a low-te-high transition of ClKA to either write data from AO-A17 to
CSA I FIFOA-B or read data from FIFOB-A to AO-A17. The AO-A17 outputs are in the high-impedance state when CSA is
high.
Port-B chip select. CSB must be low to enable a low-te-high transition of ClKB to either write data from BO-BI7 to
CSB I FIFOB-A or read data from FIFOA-B to BO-BI7. The BO-BI7 outputs are in the high-impedance state when CSB is
high.
FIFOA- B half-full flag. HFA is high when FIFOA-B contains 256 or more words and is low when FIFOA-B contains 255
HFA 0
or less words. HFA is set low after FIFOA-B is reset.
FIFOB -A half-full flag. HFB is high when FIFOB-Acontains 256 or more words and is low when FIFOB-A contains 255
HFB 0
or less words. HFB is set low after FIFOB-A is reset.
Port-A input-ready flag. IRA is synchronized to the low-to-high transition of ClKA. When IRA is low, FIFOA-B is full and
IRA 0 writes to its array are disabled. IRA is set low during a FIFOA-.B reset and is set high on the second low-to-hightransition
of ClKA after reset.
Port-B input-ready flag. IRB is synchronized to the low-to-high transition of ClKB. When IRB is low, FIFOB-A is full and
IRB 0 writes to its array are disabled.IRB is set low during a FIFOB -A reset and is set high on the second low-te-high transition
of ClKB after reset.
Port-A output-ready flag. ORA is synchronized to the low-to-high transition of ClKA. When ORA is low, FIFOB-A is empty
and reads from its array are disabled. The last valid word remains on the FIFOB-A outputs when ORA is low. Ready data
ORA 0
is present for the AO-A 17 outputs when ORA is high. ORA is set low during a FIFOB-A reset and goes high on the third
low-te-high transition of ClKA after the first word is loaded to an empty FIFOB-A.
Port-B output-ready flag. ORB is synchronized tothe low-to-high transition of ClKB. When ORB is low, FIFOA-B is empty
and reads from its array are disabled. The last valid word remains on the FIFOA-B outputs when ORB is low. Ready data
ORB 0
is present for the BO- B17 outputs when ORB is high. ORB is set low during a FIFOA- B reset and goes high on the third
low-te-high transition of ClKB after the first word is loaded to an empty FIFOA-B.
AF/AEA program enable. After FIFOA-B is reset and before a word is written to its array, the binary value on AO-A7 is
PENA I
latched as an AF/AEA offset when PENA is low and ClKA is high.
AF/AEB program enable. After FIFOB -A is reset and before a word is written to its array, the binary value on BO-B7 is
PENB I
latched as an AF/AEB offset when PENB is low and ClKB is high.
Port-A read enable. A high level on RENA enables data to be read from FIFOB-A on the low-te-high transition of ClKA
RENA I
when CSA is low, WiRA is low, and ORA is high.
Port-B read enable. A high level on RENB enables data to be read from FIFOA-B on the low-te-high transition of ClKB
RENB I
when CSB is 10Vi, WiRB is low, and ORB is high.
FIFOA-B reset. To reset FIFOA-B, four low-te-high transitions of ClKA and four low-te-high transitions of ClKB must
RSTA I
occur while RSTA is low. This sets HFA 10w,IRA low, ORB low, and AF/AEA high.
FIFOB -A reset. To reset FIFOB -A, four low-to-high transitions of ClKA and four low-to-high transitions of ClKB must
RSTB I
occur while RSTB is low. This sets HFB low, IRB low, ORA low, and AF/AEB high.
Port-A write enable. A high level on WENA enables data on AO-A17 to be written into FIFOA-B on the low-te-high
WENA I
transition of ClKA when W IRA is high, CSA is low, and IRA is high.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-51
SN74ABT7819
512x18x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125D - JULY 1992 - REVISED SEPTEMBER 1995

Terminal Functions (Continued)

PIN NAME 1/0 DESCRIPTION
Port-B write enable. A high level on WENB enables data on BO-B17 to be written into FIFOB -A on the low-ta-high
WENB I
transition of ClKB when W IRB is high, CSB is low, and IRB is high.
Port-A write/read select. A high on W/RA enables AO-A17 data to be written to FIFOA-B on a low-ta-high transttion of
ClKA when WENA is high, CSA is low, and IRA is high. A Iowan W/RA enables data to be read from FIFOB-A on a
W/RA I
low-ta-high transition of ClKA when RENA is high, CSA is low, and ORA is high. The AO-A17 outputs are in the
high-impedance state when W/RA is high.
Port-B writelread select. A high on W/RB enables BO-B17 data to be written to FIFOB-A on a low-ta-high transition of
ClKB when WENB is high, CSB is low, and IRB is high. A Iowan W/RB enables data to be read from FIFOA-B on a
W/RB I
low-to-high transition of ClKB when RENB is high, CSB is low, and ORB is high. The BO-B17 outputs are in the
high-impedance state when W/RB is high.

ClKA

ClKB
I
I
RSTA\ : /
I
IRA~ :
I

ORB

HFA~

AF/AEA ??/iW
Figure 1. Reset Cycle for FIFOA-Bt
t FIFOB -A is reset in the same manner.

~TEXAS
INSTRUMENTS
7-52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT7819
512x18x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125D - JULY 1992 - REVISED SEPTEMBER 1995

ClKA

IRA
i i
I I o
I I
\. 1
\.'----+1-----+-'1.
I I
1/
\"'------+-_---+'r
WiRA~ 1
I
I~
I
I I
WENA 88888888888W ~ ~ ~
I I I
~
I
~~~~~ ~_.:..,I I I I
AO-A17 ~word1t ~ Word2t ~ Word3t ~word4t ~
t Written to FIFOA-B
Figure 2. Write Timing - Port A

ClKB

IRB I
I o
I
CSB \"'---_+--__--+-'1I /
WiRB~ !~
I I
!~
I
WENB 88888888888W ~ ~ ~ I I I
~
I
,....-_1 I· I I
BO-B17 ~ word1t~ word2t~ worci3t~ word4t~
tWritten to FIFOB-A

Figure 3. Write Timing - Port B

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-53
SN74ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCBSI25D-JULY 1992- REVISED SEPTEMBER 1995

ClKA

CSA __............~~................................................................................................_O
j
I
WiRA j
j 0

WENA ~ ~'\)o
~"-- ..... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

-tI ~ tsu
AO-A17

elKB
j j
j j
ORB I ,f I }'-______
F tpd ~ r- tpd -.!

CSB ~~................................................_+I............~j........................................-
j I
wffiB ~~................................................_+I............~I........................................-
I j

RENB ~

BO-B17
____ I
~r~--------
~
14-- tpd --.!
j

W1FromFIFOA-B

Figure 4. ORB-Flag Timing and First-Data-Word Fallthrough When FIFOA-B Is Emptyt

t Operation of FIFOB-A is identical to that of FIFOA-B.

~1ExAs
INSTRUMENTS
7-54 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT7819
512x18x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCBS125D- JULY 1992 - REVISED SEPTEMBER 1995

ClKB
I
I 1
CSB I o
I
I 1
WiRB I o
I
RENB I???I I
~~~ ......__________________
I
BO-B17 __________-J)(~________________F_ro_m_F_IF_O_A_-B_________________________
ClKA
I
I

----------------~i--~1 t~----------------
IRA

---.!~I ---*l~I- tpd

1
tpd ....,1+
4 i+14
I 1
------------------------------~I-----------------------------O
I
WENA
W////////////// ~
I
I
WiRA
o

AO-A17 ~TOFIFOA-B_
Figure 5. Write-Cycle and IRA-Flag Timing When FIFOA-B Is Fullt
t Operation of FIFOB-A is identical to that of FIFOA-B.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-55
SN74ABT7819
512 x 18x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125D-~ULY 1992- REVISED SEPTEMBER 1995

ClKA

ORA
o

RENA~ ~ '®88W '®88W ~

ten I. -' ~ -tI .-=i;:td18 tpd

AO-A17 ~ )I( X X )J-!- - - -

Word it Word 2t Word 3t Word 4t

t Read from FIFOB-A

Figure 6. Read Timing - Port A

ClKB

ORB --------+---------------------1 0

~1 t 1
WiRB~~~~1 1 ~
1 1 1

RENB~
ten JIll -'
!
I+- -tI '®88W '®88W ~18
N8888W tpd _"G
!,..----....,.
_I
!
BO-B17 " Word it X Word 2t X Word at X Word 4t ).----

t Read from FIFOA-B

Figure 7. Read Timing - Port B

~1ExAs
INSTRUMENTS
7-56 POST OFFICE BOX 666303 • DALLAS, TEXAS 75285
 CLKA Lf\~Jl-f1JLf\~~~ruL
WENAJ 1I 11 1I 11 . I________________________________

~
1 1 l i n
1 i i i I )~,--------------------------
IRA I I I I' SS

AO-A17~~ @-'07@-!!JT~'~."._~~
1 1 1
~
nJl-ftLJLJtL~~~~fLfL
(')
o
6
~~..t
CLKB (')
1 1 1 I 1 1 I
I ~
i~g
RENB 1 1 1 I 1 I 1 c
1 i 1 _ I 1 1 1
I i l l 1 I m
c

;~~
SS I I I i i I 1
ORB 1 1 1 I 1 1 I ::D
--~SS m

j eo - B17 • S Wi
1

I ss
i i i

I
1

'S
I
I,~ I
~i ~I$1
WZ WY+1 WY+Z W2fiT
1

W258
1
>SE
1

W51Z-X W513-X
~
oZ
~
S SS SS I S- . ~r­
i l l I OJ."

r----
01_
N::D
AF/AEA ~___~I ! 1-1
'-
c- .
~(/)

!:(,iZ
i-n
HFA -1. . ._____ ",-
I::D
::D(/)
~-;-I
gjO (/)
NOTES: eSA, eSB = 0, WiRA = 1, W/RB = 0
CCcn Z
01 ..............
X is the almost-empty offset and Y is the almost-lull offset lor AF/AEA. ~3:~t
HFB and AF/AEB lunction in the same manner lor FIFO B-A. ~mx m
~3:m::J
Figure 8. FIFOA - B (HFA, AF/AEA) Asynchronous Flag Timing _Ox C»

~
"'::D .....
:ll<~co
SN74ABT7819
512x18x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCBS125D - JULY 1992 - REVISED SEPTEMBER 1995

offset values for AF/AE

The aimost-fuil/aimost-empty flag of each FIFO has two programmable limits: the almost-empty offset value (X)
and the almost-full offset value (Y). They can be programmed from the input of the FIFO after it is reset and
before a word is written to its memory. An AF/AE flag is high when its FIFO contains X or less words or (512 - Y)
or more words.
To program the offset values for AF/AEA, PENA is brought low after FIFOA-8 is reset and only when ClKA is
low. On the following low-to-high transition of ClKA, the binary value on AD-A? is stored as the almost-empty
offset value (X) and the almost-full offset value (Y). Holding PENA low for another low-to-high transition of ClKA
reprograms Y to the binary value on AD-A? at the time of the second ClKA low-to-high transition.
During the first two ClKAcycles used for offset programming, PENA can be brought high only when ClKA is
low. PENA can be brought high at any time after the second ClKA pulse used for offset programming returns
low. A maximum value of 255 can be programmed for either X or Y (see Figure 9). To use the default values
of X = Y = 128, PENA must be tied high. No data is stored in FIFOA-8 while the AF/AEA offsets are
programmed. The AF/AE8 flag is programmed in the same manner with PEN8 enabling ClK8 to program the
offset values taken from 80-8?

___--II
CLKA

IRA ______--JI

W/RA~

WENA

AO-A7 ~ XandY X. . __Y_.J~

Figure 9. Programming X and Y Separately for AF/AEA

~TEXAS
INSTRUMENTS
7-58 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125D - JULY 1992 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Voltage range applied to any output in the high state or power-off state, Vo ............. -0.5 V to 5.5 V
Current into any output in the low state, 10 ....•..............•.••........•...•............. 48 mA
Input clamp current, 11K (VI < 0) .......................................................... -18 mA
Output clamp current, 10K (VO < 0) ....................................................... -50 mA
Operating free-air temperature range, TA .............................................. DoC to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

recommended operating conditions

MIN NOM MAX UNIT
vee Supply voitage 4.5 5 5.5 v
VIH High-level input voltage 2 V
Vil low-level input voltage 0.8 V
VI Input voltage 0 Vee V
10H High-level output current -12 mA
10l low-level output current 24 rnA
t.t I t.v Input transition rise or fall rate 5 ns/V
TA Operating free-air temperature 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
VIK Vee = 4.5 V, 11=-18mA -1.2 V
Vee = 4.5 V, IOH=-3mA 2.5
VOH Vee=5 V, IOH=-3mA 3 V
Vee =4.5V, 10H =-12 mA 2
VOL Vee = 4.5 V, IOl=24 mA 0.5 V
II Vee=5.5V, VI = Vee or GND ±1 IJA
10ZH§ Vee =5.5 V, Va = 2.7 V 50 IJA
10Zl§ Vee = 5.5 V, Vo = 0.5 V -50 IJA
loll Vee = 5.5 V, VO=2.5V -40 -100 -180 mA
Outputs high 15
lee Vee = 5.5 V, 10=0, VI = Vee or GND Outputs low 95 mA
Outputs disabled 15
ei eontrol inputs VI = 2.5 V or 0.5 V 6 pF
eo Flags Vo = 2.5 V or 0.5 V 4 pF
eio A or B ports Vo = 2.5 V or 0.5 V 8 pF
* All tYPical values are at Vee = 5 V, TA = 25°e.
§ The parameters IOZH and IOZl include the input leakage current.
II Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-59
SN74ABT7819
512x18x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCBS125D -JULY 1992 - REVISED SEPTEMBER 1995

timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 8)
'ABT7819-12 'ABT7819-15 'ABT7819-20 'ABT7819-30
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 80 67 50 33.3 MHz
tw Pulse duration CLKA, CLKB high or low 4.5 6 8 11 ns
AO-A17 before CLKAi and
3 4 5 5
BO-B17 before CLKBi
GSA before CLKAi and CSB 6 6 7 7
before CLKBi
W/RA before CLKAi and
6 6 7 7
WiRB before CLKBi
WENA before CLKAi and
tsu Setup time 4 4 5 5 ns
WENB before CLKBi
RENA before CLKA i and
5 5 5 6
RENB before CLKBi
PENA before CLKA i and
3 4 5 5
PENB before CLKBi
RSTA or RSTB low before first
3 4 5 5
CLKAi and CLKBi t
AO-A 17 after CLKAi and
0 0 0 0
BO-B17 after CLKBi
CSA after CLKAi and CSB
0 0 0 0
afterCLKBi
W/RA after CLKAi and W/RB
0 0 0 0
afterCLKBi
WENA after CLKAi and
th Hold time 0 0 0 0 ns
WENB after CLKBi
RENA after CLKAi and RENB
0 0 0 0
afterCLKBi
PEN A after CLKA low and
2 2 2 2
PENB after CLKB low
RSTA or RSTB low after fourth
3 3 4 4
CLKA i and CLKBi t
t To permit the clock pulse to be utilized for reset purposes

~1ExAs
INSTRUMENTS
7-60 POST OFFICE eox 655303 • DALLAS, TEXAS 75265
 SN74ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125D - JULY 1992 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 50 pF (unless otherwise noted) (see Figures 10 and 12)
FROM TO 'ABT7819-12 'ABT7819-15 'ABT7819-20 'ABT7819-30
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYPt MAX MIN MAX MIN MAX MIN MAX
'max CLKAorCLKB 80 67 50 33.3 MHz
CLKAi AO-A17 4 7 9 4 10 4 12 4 14
tpd ns
CLKBi BO-B17 4 7 9 4 10 4 12 4 14
CLKAi AO-A17 6
tpd+ ns
CLKBi BO-B17 6
CLKAi IRA 4 9 4 10 4 12 4 14
tpd ns
CLKBi IRB 4 9 4 10 4 12 4 14
CLKAi ORA 3.5 9 3.5 10 3.5 12 3.5 14
tpd ns
CLKBi ORB 3.5 9 3.5 10 3.5 12 3.5 14
CLKAi 8 17 8 17 8 18 8 20
tpd AF/AEA ns
CLKBi 8 17 8 17 8 18 8 20
tpLH RSTA AF/AEA 4 12 4 14 4 15 4 16 ns
CLKAi 8 17 8 17 8 18 8 20
tpd AF/AEB ns
CLKBi 8 17 8 17 8 18 8 20
RSTB AF/AEB 4 12 4 14 4 15 4 16
tpLH ns
CLKAi HFA 8 17 8 17 8 18 8 20
CLKBi 8 17 8 17 8 18 8 20
tpHL HFA ns
RSTA 4 12 4 14 4 15 4 16
tpHL CLKAi HFB 8 17 8 17 8 18 8 20 ns
tpLH CLKBi 8 17 8 17 8 18 8 20
HFB ns
tpHL RSTB 4 12 4 14 4 15 4 16
CSA 2.5 8 2.5 9 2.5 10 2.5 11
ten AO-A17 ns
W/RA 2.5 8 2.5 9 2.5 10 2.5 11
CSB 2.5 8 2.5 9 2.5 10 2.5 11
ten BO-B17 ns
W/RB 2.5 8 2.5 9 2.5 10 2.5 11
CSA 2.5 8 2.5 9 2.5 10 2.5 11
tdis AO-A17 ns
W/RA 2.5 8 2.5 9 2.5 10 2.5 11
CSB 2.5 8 2.5 9 2.5 10 2.5 11
'dis BO-B17 ns
W/RB 2.5 8 2.5 9 2.5 10 2.5 11
t All typical values are at VCC = 5 V, TA =25°C.
:j: This parameter is measured with a 30-pF load (see Figure 10).

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-61
SN74ABT7819
512x 18x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCBSI25D - JULY 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE

VCC~6V
typ+6 I- TA=25°C

cen
RL=5000
/
I
GI
typ+4
/
! ./
/
l'
;!I
c
~/
0 typ+2
,/
I
0.
I
typ
1/
J /
V
typ-2
o 50 100 150 200 250 300
CL - Load CapacItance - pF

Figure 10

SUPPLY CURRENT
vs
CLOCK FREQUENCY
160
TA =75"C I I 1.1 V
CL=OpF VCC=5.5V /
140
,/ V
1I 120
1/ V
VCC=5V - ,/ ",

i 100
k> ~ V V~
:::I ",
/' ,/V , /~
(,)

~
0. 60
v.~
~V", /
:::I
en
I VCC = 4.5 V
e: 60 ./
g
~~
,/
40

20
10 15 20 25 30 35 40 45 50 55 60 65 70

fclock - Clock Frequency - MHz

Figure 11

-!!11ExAs
INSTRUMENTS
7-62 POST OFFICE BOX 655303 • DALLAS. TEXAS 75285
 SN74ABT7819
512x18x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125D - JULY 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

calculating power dissipation

With ICC(f) taken from Figure 11 , the maximum power dissipation (Pr) based on all outputs changing states on
each read can be calculated by:
PT = VCC x ICC(f) + l:(CL x VOH 2 x fo)
where:
maximum ICC per clock frequency
output capacitive load
data output frequency
high-level output voltage

PARAMETER MEASUREMENT INFORMATION

3V

~1.5V
\~5~--------
Input
7V
1 1 ov
S1 I> Rl =R1 =R2 1 1
tpZl -+1 I+- -+1 I+- tpZl
1 1
R1 Output 1 ~3.5V

r-=c-=cG~~
1
From Output _...-_+-_...- Test 1
1 \1.5V 1
Under Test Point I
1 VOL
1
R2 1 tPHZ -+! I+- t

1.. , t------
1
tpZH -+\ I+- 1 ______ +_
VOH
0.3 v--.t
Output ~OV

lOAD CIRCUIT VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PARAMETER R1,R2 Clt S1

Open
ten ...!Elli.. 5000 50 pF
tpZl Closed

!dis ~ 5000 50pF

Open
tpLZ Closed
tpd 5000 50 pF Open
t Includes probe and test-fixture capacitance
Figure 12. Load Circuit and Voltage Waveforms

~1EXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS, TexAS 75265 7-63
7-64
 SN74ACT7811
1024 x 18
FIRST"OUT MEMORY

• Member of the Texas Instruments • Input-Ready, Output-Ready, and Half-Full

Wldebus n. Family Flags
• Independent Asynchronous Inputs and • Cascadable In Word Width and/or Word
Outputs Depth
• 1024 Words x 18 Bits • Fast Access Times of 15 ns With a 5O-pF
• Read and Write Operations Can Be Load
Synchronized to Independent System • High-Output Drive for Direct Bus Interface
Clocks • Available in 68-Pin PLCC (FN) and
• Programmable Almost-FuIl/Almost-Empty Space-Saving 8o-Pin Thin Quad Flat (PN)
Flag Packages
• Pln-to-Pln Compatible With SN74ACT7881,
SN74ACT7882, and SN74ACT7884

FNPACKAGE
(TOP VIEW)

:.::: ,.. C\I

Cl ..J Z Z II-
W OCl Cl
~ ~ ~ Z g ~ ~ w ffl OZ 0:: o~ ~ Z ~
ClClCl~O::O::O::OO::>~O~OO~O
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 60 Vee
11 59 014
12 58 013
13 57 GND
14 56 012
15 55 011
16 54 Vee
17 53 010
18 52 09
19 51 GND
20 50 08
21 49 07
22 48 Vee
23 47 06
24 46 05
25 45 GND
26 44 04
27 282930 31 32333435363738394041 4243

ow Cl 0:: LL 08'" Cl C\I <') 0

I«
LL Cl :.::: ,..
z..Jzz
Cl~OWW~~~
C\I
o<cz-::c 0 Ozoo
~ ~
0
~
Ii:Ii:Ii: «
3:3:3:

Widebus is a trademark of Texas Instruments Incorporated.

Copyright © 1996, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 7-65
SN74ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151 c - JANUARY 1991 - REVISED FEBRUARY 1996

PNPACKAGE
(TOP VIEW)

NC
• 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60 VCC
GNO 2 59 VCC
GNO 3 58 NC
016 4 57 03
017 5 56 02
VCC 6 55 GNO
OR 7 54 01
GNO 8 53 00
VCC 9 52 VCC
RESET 10 51 HF
OE 11 50 IR
ROEN2 12 49 GNO
ROEN1 13 48 GNO
ROCLK 14 47 AF/AE
GNO 15 46 VCC
017 16 45 WRTEN2
016 17 44 WRTEN1
015 18 43 WRTCLK
NC 19 42 GNO
NC 20 41 NC
~~~M~~V~~~~~~M~~~M~~

00> ()CIOOr-.<01t) ..r (') C\I .,.. 0

()..r(') C\I.,..
Z""""""""""O ()OZOOO 0 0 0 0 0
/U-
C§z()
00000 ::> <!l

NC - No internal connection

description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7811 is a 1024 x 18-bit FIFO for high speed and fast access times. It processes data
at rates up to 40 MHz and access times of 15 ns in a bit-parallel format. Data outputs are noninverting with
respect to the data inputs. Expansion is easily accomplished in both word width and word depth.
The SN74ACT7811 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry
adds the ability to synchronize independent read and write (interrupts or requests) to their respective system
clock.
The SN74ACT7811 is characterized for operation from O°C to 70°C.

~1EXAS
INSTRUMENTS
7-66 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C-JANUARY 1991- REVISED FEBRUARY 1996

logic symbolt

(!>
FIFO 1024 x 18
SN74ACT7811

1 _f'..
RESET RESET
29
WRTCLK WRTCLK 35
~
30 IR
WRTENl IN ROY 36
31 WRTEN HALF FULL HF
WRTEN2 33
5 ROCLK ALMOST FULUEMPTY AF/AE
ROCLK 66
4 I-- OUT ROY OR
ROENl &
2
OE ENl ROEN
3
ROEN2
I--
OAF
27

26
"-
, OEF ALMOST FULL
I'"
36
DO 0 0 QO
25 39
01 Ql
24 41
02 Q2
23 42
03 Q3
22 44
04 Q4
21 46
05 Q5
20 47
06 Q6
19 49
07 Q7

~ ~lV
17 50
08 Q8
15 52
09 Q9
14 53
010 Ql0
13 55
011 Qll
12 56
012 Q12
11 58
013 Q13
10 59
014 Q14
9 61
015 Q15
8 63
016 Q16
7 64
017 17 17 Q17

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
Pin numbers shown are for the FN package.

~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-fJ7
SN74ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C-JANUA.RY 1991 - REVISED FEBRUARY 1996

functional block diagram

OE

~J
00-017

ROCLK
L Synchronous
Location 1

ROEN1
ROEN2
Read
Control I Read
Pointer
I
I
Location 2

I 1024 x 18 RAM

WRTCLK
WRTEN1
WRTEN2
Synchronous
Write
Control r- ~
I Write
Pointer I
I Location 1023
Location 1024
I
~J
~ I
Reset Register QO-Q17
Logic
RESET
Status-
Flag OR
Logic IR
HF
AF/AE

~ThXAS
INSTRUMENTS
7-68 POST OFFICE BOX 655303 • DALLAS. TEXAS 752il5
 SN74ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C-JANUARY 1991 - REVISED FEBRUARY 1996

Terminal Functions
TERMINALt
1/0 DESCRIPTION
NAME NO.
Aimost-fuil/almost-emptyflag. The AF/AE boundary is defined by the aimost-fuil/almost-empty offset
value (X). This value can be programmed during reset orthe default value of256 can be used. AF/AE
is high when the FIFO contains (X + 1) or less words or (1 025 - X) or more words. AF/AE is low when
the FIFO contains between (X +2) and (1024 - X) words.
Programming procedure for AF/AE - The aimost-fuil/almost-empty flag is programmed during each
reset cycle. The aimost-fuil/almost-empty offset value (X) is either a user-defined value or the default
of X = 256. Instructions to program AF/AE using both methods are as follows:

AF/AE 33 0 User-defined X
Step 1: Take OAF from high to low.
Step 2: If RESET is not already low, take RESET low.
Step 3: With OAF held low, take RESET high. This defines the AF/AE using X.
Step 4: To retain the current offset for the next reset, keep OAF low.
~
To redefine AF/AE using the default value of X = 256, hold OAF high during Ihe reset cycle.
Define almost full. The high-to-Iow transition of OAF stores the binary value of data inputs as the
OAF 27 I aimost-fuilialmost-empty offset value (X). With OAF held low, a low pulse on RESET defines the
AF/AE flag using X.
Data inputs for 18-bit-wide data to be stored in the memory. Data lines 00-D8 also carry the
00-017 26-19,17,15-7 I
aimost-fuilialmost-empty offset value (X) on a high-to-Iow transition of the DAF.
Half-full flag. HF is high when the FIFO contains 513 or more words and is low when it contains 512
HF 36 0
or less words.
Input-readyflag.IR is high when the FIFO is not full and low when the device is full. During reset, IR
is driven Iowan the rising edge olthe second WRTCLK pulse. IR is then driven high on the rising edge
IR 35 0
of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low,
IR is driven high on the second WRTCLK pulse after the first valid read.
Output enable. The data-out (00 -017) outputs are in the high-impedance state when OE is low. OE
OE 2 I
must be high before the rising edge of RDCLK to read a word from memory.
Output-ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset,
OR is set Iowan the rising edge of the third RDCLK pulse. OR is set high on the rising edge of the
OR 66 0
third RDCLK pulse to occur after the first word is written into the FIFO. OR is set Iowan the rising
edge of the first RDCLK pulse after the last word is read.
38-39,41-42,44, Data outputs. The first data word to be loaded into the FIFO is moved to 00-017 on the rising edge
46-47,49-50, of the third RDCLK pulse to occur after the first valid write. The ROEN1 and RDEN2 inputs do not
00-017 0
52-53, 55-56, affect this operation. Following data is unloaded on the rising edge of RDCLK when ROEN 1, ROEN2,
58-59,61, 63-64 OE, and the OR are high.
Read clock. Data is read out of memory on a low-ta-high transition RDCLK if OR, OE, and RDEN1
and ROEN2 conlrol inputs are high. ROCLK is a free-running clock and functions as the
ROCLK 5 I
synchronizing clock lor all data transfers out of the FIFO. OR is also driven synchronously with
respect to RDCLK.
RDEN1, 4 Read enable. RDEN1 and ROEN2 must be high before a rising edge on RDCLK to read a word out
I
ROEN2 3 of memory. RDEN1 and ROEN2 are not used to read the first word stored in memory.
A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and
WRTCLK cycles. This ensures that the internal read and write pointers are reset and OR, HF, and
IR are low and AF/AE is high. The FIFO must be reset upon power up. With DAF at a low level, a low
RESET 1 I
pulse on RESET defines the AF/AE status flag using the aimost-fuil/almost-empty offset value (X),
where X is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines
the AF/AE flag using the default value of X = 256.
t Terminals listed are for the FN package.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-69
SN74ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C-JANUARY 1991 - REVISED FEBRUARY 1996

Terminal Functions (Continued)

TERMINALt
1/0 DESCRIPTION
NAME NO.
Write clock. Data is written into memory on a low-te-high transition of WRTCLK if IR, WRTEN1, and
WRTCLK 29 I WRTEN2 are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all
data transfers into the FIFO. IR is also driven synchronously with respect to WRTCLK.
Write enables. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word
WRTEN1, 30
I to be written into memory. WRTEN1 and WRTEN2 do not affect the storage of the
WRTEN2 31
almost-fuIValmost-empty offset value (X).
t Terminals listed are for the FN package.

WRTCLK

WRTEN1

WRTEN2

00-017

RDCLK

RDEN1

RDEN2

OE ----------~------~--~----~----~--------~-----------1
o
QO-Q17 Invalid
i i i

AF/AE Q15lfri~i¥wisa i I
I
HF B:D:Oi~ci*21 i I
I
I
IR ~',9iri~i¥W~~ I
I
Stofe the Value of 00-08 as X
I Define the AF/AE Flag Using the
Value of X
t X is the binary value of DO-DB only.

Figure 1. Reset Cycle: Define AF/AE Using the Value of X

~TEXAS
INSTRUMENTS
7-70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS151C-JANUARY 1991 - REVISED FEBRUARY 1996

RESET

OAF ~if.~~'!ff!l!!I~
I
WRTCLK I

WRTEN1

WRTEN2

00-017

ROCLK

ROEN1

ROEN2

OE --------~------~--~--------~------~---------- 1
o
QO-Q17 Invalid
i i i

Define the AF/AE Flag

=
Using the Value of X 256

Figure 2. Reset Cycle: Define AF/AE Using the Default Value

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-71
SN74ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C-JANUARY 1991-REVISEDFEBRUARY 1996

1
o

WRTCLK
~~~r-f1-
1 1 1 1
1 1 I I 1
WRTEN1 1 1 1 1 o
1 1 1 1
I I 1 1
WRTEN2

00-017

ROCLK

1
ROEN1
o
1 1 1 I I
1 1 1 1 1
ROEN2 1 1 1 I I
1 1 1 1 1
I
I. 1
1
1
1
1
1 1
OE
I 1 1 1 1 o
1 1 1 I: I:
QO-Q17 _______I_nV_al_ld______ ~><~------~------W~:-1------~------~~-
OR I
AF/AE

HF

IR
L
Figure 3. Write Cycle

~1ExAs
INSTRUMENTS
7-72 POST OFFICE lOX 655303 • DAllAS. TEXAS 75265
 SN74ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCASI51C-JANUARY 1991 - REVISED FEBRUARY 1996

1 1
WRTEN11l :
1 1

WRTEN2 il :
1 1

00-017 ~ Wl:025
1 1

ROCLK 1 ,-+-1--'I~~~r--fl-fl-
1

ROEN1 J 1
1
1
1

ROEN2 ~:I--_""
1
OEjl I
iHI
QO-Q17
+25

OR I
1
1
1
AF/AE 1

1
1
HF 1
1
1

IR 1 ..._____.......
Figure 4. Read Cycle

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-73
SN74ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C-JANUARY 1991- REVISED FEBRUARY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee ...................................•...................... -0.5 V to 7 V
Input voltage, VI ...............................................................•............. 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . • . . . . . .. • . .. 5.5 V
Operating free-air temperature range, TA ............................................... O°C to 70°C
Storage temperature range, Tstg .................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" Is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
Vil low-level input vottage 0.8 V
IOH High-level output current -8 mA
IOl low-level output current 18 mA
TA Operating free-air temperature 0 70 ·C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TVP* MAX UNIT
VOH Vcc= 4.5V. IOH=-8mA 2.4 V
Val VCC=4.5V. IOl-16mA 0.5 V
II Vcc= 5.5V. VI=VCc orOV ±5 J.LA
IOZ VCC=5.5V. VO-Vcc orOV ±5 J.LA
VI aVCC-0.2VorOV 400 J.LA
ICC§
One input at 3.4 V. Other inputs at VCC or GND 1 mA
Ci VI = 0 V. f - 1 MHz 4 pF
Co Vo = 0 V. f - 1 MHz 8 pF
:j: All tYPical values are at VCC = 5 V. TA = 25·C.
§ ICC tested with outputs open

~1ExAs
INSTRUMENTS
7-14 POST OFFICE BOX ,656303 • DALlAS. TEXAS 75266
 SN74ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS151C-JANUARY 1991- REVISED FEBRUARY 1996

timing requirements (see Figures 1 through 8)

'ACT7811-15 'ACT7811-18 'ACT7811-20 'ACT7811-25
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 40 35 28.5 16.7 MHz
DO-D17 high or low 10 12 14 20
WRTCLKhigh 7 8.5 10 17
WRTCLKlow 10 11 14 23
RDCLKhigh 7 8.5 10 17
RDCLKlow 10 11 14 23
tw Pulse duration ns
DAF high 10 10 10 10
WRTEN1, WRTEN2
10 10 10 10
high or low
OE, RDEN1, RDEN2
10 10 10 10
high or low
DO-D17 before WRTCLKi 5 5 5 5
WRTEN1, WRTEN2 high
5 5 5 5
before WRTCLKi
OE, RDEN1, RDEN2 high
5 5 5 5
before RDCLKi
Reset: RESET low before first
7 7 7 7
tsu Setup time WRTCLK and RDCLKi ns
Define AF/AE: DO-D8 before
5 5 5 5
DAF!
Define AF/AE: DAF! before
7 7 7 7
RESETi
Define AF/AE (defautt):
5 5 5 5
DAF high before RESETi
DO-D17 afterWRTCLKi 1 1 1 1
WRTEN1, WRTEN2 high after
1 1 1 1
WRTCLKi
OE, RDEN 1, RDEN2 high after
1 1 1 1
RDCLKi
Reset: RESET low after fourth
0 0 0 0
th Hold time WRTCLK and RDCLKi ns
Define AF/AE: DO-D8 after
1 1 1 1
DAF!
Define AF/AE: DAF low after
0 0 0 0
RESETi
Define AF/AE (default):
1 1 1 1
DAF high after RESETi
.. for reset purposes
t To permit the clock pulse to be utilized

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-75
SN74ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS151C-JANUARY 1991 -REVISED FEBRUARY 1996

switching characteristics over recommended operating free-air temperature range (see Figures 9
and 10)
Vcc = 4.5 V to 5.5 V,
CL=50pF,
FROM TO RL = 5000,
PARAMETER TA = O·C to 70·C UNIT
(INPUT) (OUTPUT)
'ACT7811-15 'ACT7811-18 'ACT7811-20 'ACT7811-25
MIN TYP MAX MIN MAX MIN MAX MIN MAX
WRTCLKor
fmax 40 35 28.5 16.7 MHz
RDCLK
tpd 4 12 15 4 18 4 20 4 25
RDCLKi AnyQ ns
tpd t 10.5
tpd WRTCLKi IR 2 10 2 12 2 14 2 16 ns
tpd RDCLKi OR 2 10 2 12 2 14 2 16 ns
WRTCLKi 6 20 6 22 6 24 6 26
tpd AF/AE ns
RDCLKi 6 20 6 22 6 24 6 26
tPLH WRTCLKi 6 19 6 21 6 23 6 25
HF ns
tpHL RDCLKi 6 19 6 21 6 23 6 25
tPLH AF/AE 3 19 3 21 3 23 3 25
RESETt ns
tpHL HF 4 21 4 23 4 25 4 27
ten 2 11 2 11 2 11 2 11
OE AnyQ ns
tdis 2 14 2 14 2 14 2 14
t This parameter IS measured with CL = 30 pF (see Figure 5).

operating characteristics, Vee =5 V, TA =25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance per 1K bits CL =50 pF, f = 5 MHz

~TEXAS
INSTRUMENTS
7-76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151 C - JANUARY 1991 - REVISED FEBRUARY 1996

TYPICAL CHARACTERISTICS

TYPICAL PROPAGATION DELAY TIME

vs
LOAD CAPACITANCE
18
VCC~5V
_ TA=25°C
17
1/1 RL=500n
c ,/'
I 16
011
E ,/'
1= ./
:.. 15
III
V"
~ ./
c 14
i:i' 13
/ '"
e-
li.
I 12
1/
'a
_a.
11 /
10
I
o 50 100 150 200 250 300

C L - Load Capacitance - pF

Figure 5

-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-77
SN74ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C- JANUARY 1991 - REVISED FEBRUARY 1996

TYPICAL CHARACTERISTICS

TYPICAL POWER DISSIPATION CAPACITANCE

vs
SUPPLY VOLTAGE
68
I I
u. f, = 5 MHz
Co
I
Q)
67
TA = 25°C ./
u CL= 50pF
c
~
u
,/
'"
Co 66 /
t'3
c
,/
0
:; 65 /
Co

:~
,/
Q
64 V
I
a.
I ,/
V
63
'&. ,/

62
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5

Vcc - Supply Voltage - V

Figure 6

calculating power dissipation

The maximum power dissipation (PT) of the SN74ACT7811 can be calculated by:
PT = Vee x [Icc + (N x ~Iee x dc)] + ~ (Cpd x Vee2 x fj) + ~ (CL x Vce2 x fo)
where:
Icc power-down ICC maximum
N number of inputs driven by a TTL device
~ Icc increase in supply current
dc duty cycle of inputs at a TTL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
fj data input frequency
fo data output frequency

~TEXAS
INSTRUMENTS
7-78 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C-JANUARY 1991- REVISED FEBRUARY 1996

APPLICATION INFORMATION
expanding the SN74ACT7811
The SN74ACT7811 is expandable in width and depth. Expanding in word depth offers special timing
considerations:
After the first data word is loaded into the FI Fa, the word is unloaded and the output-ready flag (OR) output
goes high after (N x 3) read-clock (RDCLK) cycles, where N is the number of devices used in depth
expansion.
After the FIFO is filled, the input-ready flag (lR) output goes low, the first word is unloaded, and the IR flag
output is driven high after (N x 2) write-clock cycles, where N is the number of devices used in depth
expansion.

CLOCK

WRTCLK
WRTEN1
SN74ACT7811
WRTCLK
WRTEN1
ROCLK
OR
1 SN74ACT7811
WRTCLK
WRTEN1
ROCLK
ROEN1
ROCLK
ROEN1
L
WRTEN2
IR
WRTEN2
IR
ROEN1
ROEN2 n WRTEN2
IR
ROEN2
OR
ROEN2
OR
OE t--5V OE OE

00-017 00-017 QO-Q17 00-017 QO-Q17 QO-Q17

Figure 7. Word-Depth Expansion: 2048 Words x 18 Bits, N = 2

SN74ACT7811
WRTCLK WRTCLK ROCLK ROCLK
WRTEN WRTEN1 ROEN1 ROEN
WRTEN2 ROEN2
IR OR
OE
~ OE

018 - 035 00-017 QO-Q17 Q18-Q35

.....--
IR
-0 '---
SN74ACT7811
WRTCLK ROCLK
-
I OR

WRTEN1 ROEN1 r- -
WRTEN2 ROEN2
IR OR
OE r-
00-017 00-017 QO-Q17 QO-Q17

Figure 8. Word·Width Expansion: 1024 Words x 36 Bits

~ThxAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-79
SN74ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS151 C - JANUARY 1991 - REVISED FEBRUARY 1996

PARAMETER MEASUREMENT INFORMATION

From Output Input~

UnderTe~ ~
RL=5000 1. T CL=50pF
Output
I
14- tpd-+l

_ _ _ _- . J
, 1

-- --
LOAD CIRCUIT TOTEM·POLE OUTPUTS

Figure 9. Standard CMOS Outputs

7V "~~I'V \ ~,~---::
l RL= R1 = R2
tpZL -.I, ~ -! 1__
S1
, PLZ ~I ~
R1
From Output _ ......_
Under T~
...._---,.__ Test
Point Output
- - - - : '...... ,
: "1.5V
.
'
: p
,

. - - I - VOL
.. 3.5 V

R2 , tPHZ -.I 1+ L 0.3 V

tpZH ~ j4- , ~
~
--VOH

Output 1.5 V {" ;3~

=OV
LOAD CIRCUIT
VOLTAGE WAVEFORMS

PARAMETER R1,R2 cLt S1

I tpZH Open
ten 5000 50pF
tpZL Closed
tpHZ Open
!dis ~ 5000 50pF
tpLZ Closed
tpd 5000 50pF Open
t Includes probe and test fixture capacitance
Figure 10. 3-State Outputs (Any Q)

~1ExAs
INSTRUMENTS
7-80 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7881
1024 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY

• Member of the Texas Instruments • Input-Ready, Output-Ready, and Half-Full

Wldebus™ Family Flags
• Independent Asynchronous Inputs and • Expandable In Word Width and/or Word
Outputs Depth
• Read and Write Operations Can Be • Fast Access Times of 11 ns With a 50-pF
Synchronized to Independent System Load
Clocks • High Output Drive for Direct Bus Interface
• Programmable Almost-Full/Almost-Empty • Package Options Include 68-Pin PLCC (FN)
Flag or Space-Saving 80-Pln Shrink Quad Flat
• Pin-to-Pin Compatible With SN74ACT7882, (PN) Packages
SN74ACT7884, and SN74ACT7811

FNPACKAGE
(TOP VIEW)

~ ~ N
....JZZ If-W
g ~ ~ w fB o~ a:: oc:: ~ ~ ~
~ ~ c:: ~
ooo~a::a::a::oa::?~o~oo~o
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
014 10 60 Vee
013 11 59 014
012 12 58 013
011 13 57 GNO
010 14 56 012
09 15 55 011
Vee 16 54 Vee
08 17 53 010
GNO 18 52 09
07 19 51 GNO
06 20 50 08
05 21 49 07
04 22 48 Vee
03 23 47 06
02 24 46 05
01 25 45 GNO
00 26 44 04
27 282930 31 32 33 34 3536 3738394041 4243

Iu.. 0 ~ ~ NOW 0 a:: u.. 0 0 ~ 0 N '" 0

<Z....JZZO<Z-~oOOzOOo
o~()WW> iJ::~ > ~ >
ti: ti: ti: < .
~~~

Widebus is a trademark of Texas Instruments Incorporated.

Copyright © 1996, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-81
SN74ACT7881
1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996

PNPACKAGE
(TOP VIEW}

ooNnnro~~nnnro~~~oo~~~~~

NC 1 • 60 Vee
GNO 2 59 Vee
GNO 3 58 NC
016 57 03
017 56 02
55 GNO
54 01
53 00
Vee 9 52 Vee
RESET 10 51 HF
OE 11 50 IR
ROEN2 12 49 GNO
ROEN1 13 48 GNO
ROCLK 14 47 AF/AE
GNO 15 46 Vee
017 16 45 WRTEN2
016 17 44 WRTEN1
015 18 43 WRTCLK
NC 19 42 GNO
NC 20 41 NC
~~~~~~V~~M~~~~~~~~~~

Ne - No internal connection

description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7881 is organized as 1024 x 18 bits. The SN74ACT7881 processes data at rates up
to 67 MHz and access times of 11 ns in a bit-parallel format. Data outputs are noninverting with respect to the
data inputs. Expansion is easily accomplished in both word width and word depth.
The SN74ACT7881 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry
adds the ability to synchronize independent reads and writes to their respective system clocks.
The SN74ACT7881 is characterized for operation from O°C to 70°C.

~TEXAS
INSTRUMENTS
7-82 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7881
1024 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996

logic symbolt

<I>
FIFO
SN74ACT7881 -1024 x 18

1 "- RESET
RESET
29
WRTCLK WRTCLK
30 35

~WRTEN
WRTEN1 IN ROY IR
31 36
WRTEN2 HALF FULL HF
5 33
ROCLK
ROEN1
4
2
- ROCLK
&
ALMOST FULUEMPTY
OUT ROY
66
AF/AE
OR

OE ENl ROEN
3
ROEN2
27 -
OAF "-
, OEF ALMOST FULL
r
26 38
DO 0 0 QO
25 39
01 Q1
24 41
02 Q2
23 42
03 Q3
22 44
04 Q4
21 46
05 Q5
20 47
06 Q6
19 49
07 Q7
17 50
08 Q8
15 ®®1V 52
09 Q9
14 53
010 Ql0
13 55
011 Q11
12 56
012 Q12
11 58
013 Q13
10 59
014 Q14
9 61
015 Q15
8 63
016 Q1B
7 64
017 17 17 Q17

tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the FN package.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-83
SN74ACT7881
1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996

functional block diagram

OE

00-017

~,
ROCLK
L Synchronous
R d
Location 1
Location 2
I
Read I I
ROEN1
Control Po:ter :
ROEN2

I RAM
1024 x 18

WRTCLK Synchronous
WRTEN1
WRTEN2
Write
Control - -
I Write
I Pointer
I
l .
•
I
~
~ Reset Logic I Register QO-Q17

OR
Status-
Flag IR
Logic HF
AF/AE

~1ExAs
INSTRUMENTS
7-84 POST OFFICE BOX 855303. DALLAS. TEXAS 75266
 SN74ACT7881
1024 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996

Terminal Functions
TERMINALt
I/O DESCRIPTION
NAME NO.
Aimost-fuli/almost-emptyflag. The AF/AE boundary is defined by the almost-fuIValmost-empty offset
value (X). This value can be programmed during reset, orthe default value of256 can be used. AF/AE
is high when the FIFO contains (X + 1) or less words or (1025-X) or more words. AF/AE is low when
the FIFO contains between (X +2) and (1024 - X) words.
Programming procedure for AF/AE - The aimost-fuli/almost-empty flag is programmed during each
reset cycle. The aimost-fuli/almost-empty offset value (X) is either a user-defined value or the default
of X .. 256. Instructions to program AF/AE using both methods are as follows:

AF/AE 33 0 User-defined X
Step 1: Take DAF from high to low.
Step 2: If RESET is not already low, take RESET low.
Step 3: With DAF held low, take RESET high. This defines the AF/AE using X.
Step 4: To retain the current offset for the next reset, keep DAF low.
~
To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle.
Define-almost-full. The high-to-Iow transition of DAF stores the binary value of data inputs as the
DAF 27 I almost-fuIValmost-empty offset value (X). With DAF held low, a low pulse on RESET defines the
almost-fuIValmost-empty (AF/AE) flag using X.
Data inputs for 18-bit-wide data to be stored in the memory. A high-to-Iow transition of DAF captures
DO-D17 26-19,17,15-7 I
data for the almost-empty/almost-full offset (X) from D8- DO.
Half-full flag. HF is high when the FIFO contains 512 or more words and is low when the number of
HF 36 0
words in memory is less than half the depth of the FIFO.
Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR
is driven Iowan the rising edge olthe second WRTCLK pulse.IR is then driven high on the rising edge
IR 35 0
of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low,
IR is driven high on the second WRTCLK pulse after the first valid read.
Output enable. The 00-017 outputs are in the high-impedance state when OE is low. OE must be
OE 2 I
high before the rising edge of RDCLK to read a word from memory.
Output-ready flag. OR is high when the FIFO is not empty and low when the FIFO is empty. During
reset, OR is set Iowan the rising edge of the third RDCLK pulse. OR is set high on the rising edge
OR 66 0
of the third RDCLK pulse to occur after the first word is written into the FIFO. OR is set Iowan the
rising edge of the first RDCLK pulse after the last word is read.
38-39,41-42,44, Data outputs. The first data word to be loaded into the FIFO is moved to 00-017 on the rising edge
46-47,49-50, of the third RDCLK pulse to occur after the first valid write. RDEN1 and RDEN2 do not affect this
00-017 0
52-53,55-56, operation. Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2. OE. and
58-59.61,63-64 OR are high.
Read clock. Data is read out of memory on the low-to-high transition of RDCLK if OR, OE. RDEN1.
RDCLK 5 I and RDEN2 are high. RDCLK is a free-running clock and functions as the synchronizing clock for
all data transfers out of the FIFO. OR is also driven synchronously with respect to the RDCLK signal.
RDEN1, 4 Read enable. RDEN1 and RDEN2 must be high before a rising edge on RDCLK to read a word out
I
RDEN2 3 of memory. RDEN1 and RDEN2 are not used to read the first word stored in memory.
Reset. A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and
WRTCLK cycles. This ensures that the internal read and write pointers are reset and that OR, HF,
and IR are low, and AF/AE is high. The FIFO must be reset upon power up. With DAF at a low level,
RESET 1 I
a low pulse on RESET defines AF/AE using the aimost-fuli/almost-empty offset value (X), where X
is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines the
AF/AE flag using the default value of X = 256.
t Terminals hsted are for the FN package.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7~5
SN74ACT7881
1024 x 18 CLOCKED FIRST-IN,FIRST-OUT MEMORY
SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996

Terminal Functions (Continued)

TERMINALt
1/0 DESCRIPTION
NAME NO.
Write clock. Data is written into memory on a low-to-high transition of WRTCLK if IR, WRTEN1, and
WRTCLK 29 I WRTEN2 are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all
data transfers into the FIFO. IR is also driven synchronously with respect to WRTCLK.
Write enable. WRTEN 1 and WRTEN2 must be high before a rising edge on WRTCLK for a word to
WRTEN1, 30
I be written into memory. WRTEN1 and WRTEN2 do not affect the storage of the almost-fuIValmost-
WRTEN2 31
empty offset value (X).
t Terminals listed are for the FN package.

WRTCLK

WRTEN1

WRTEN2

DO-D17

RDCLK

RDEN1

RDEN2

OE

QO-Q17 Invalid
I I I

AF/AE

Store the Value of Data as X Define the AF/AE Flag Using the
Programmed Value of X
t X is the binary value on 08- DO.
Figure 1. Reset Cycle: Define AF/AE Flag Using a Programmed Value of X

~ThxAs
INSTRUMENTS
7-86 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7881
1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS227C-FEBRUARY 1993- REVISED FEBRUARY 1996

DAF Don't Care

----------~------------------~
WRTCLK

WRTEN1

00-017

ROCLK

ROEN1

ROEN2

AF/AE

HF

IR

Figure 2. Reset Cycle: Define AF/AE Flag Using the Default Value fo X =256

~TEXAS
INSTRUMENTS
POST OFFICE BOX 855303 • DALlAS, TEXAS 75265 7~7
SN74ACT7881
1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996

WRTCLK

WRTEN1 I i i I
I I I I
I I I I
WRTEN2 --.J

RDCLK

RDEN1

i i i i i
RDEN2
------' i
I
I
I
I
I
I
I
I
I
OE
I I I I I
I I I I I

QO-Q171§§§§§§§(®*[(~....._ _--..,....:_ _..,..:W_1_---,-:_ _..,..:_

~~
OR _____________________

AF/AE

HF I
----------------------~ I
IR
L
DATA WORD NUMBERS
FOR FLAG TRANSITIONS
TRANSITION WORD
A B C
W513 W(1025-X) Wl025

Figure 3. Write Cycle

~TEXAS
INSTRUMENTS
7-88 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7881
1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS227C- FEBRUARY 1993- REVISED FEBRUARY 1996

WRTCLK

WRTEN1 ~~
I ____________~___________________________________________

WRTEN2 --t1~ ____________ ___________________________________________

~

00-017 .i:oI3I.....i-r-"l~W':O'O:~QoQ,QQ~'P-'W':O'O:~QoQ,QQ~~W':O'O:~QoQ,QQ~~W':O'O:~QoQ,QQ~~:..Q"j~Qo,Q.
RDCLK I ~I~~
RDEN1 ..J I I
I
I
I
I
I
I
RDEN2 - -.. i -----' I I I
OE
--hiHi--~--------------~I------~~------~I~------------~I----
I I I I
QO-Q17 ~J'''''';';;.....J'''-''''';';';''''-\~;';':;';;'-.:r W~+2) ~~~ r
OR I
I
I
I
L--
AF/AE I I~------------------
I
HF I
I
IR 1 ...______-'
DATA WORD NUMBERS FOR FLAG TRANSITIONS
TRANSITION WORD
A B C 0 E F
W513 W514 W(1024-X) W(1025-X) W1024 W1025

Figure 4. Read Cycle

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 7-89
SN74ACT7881
1024 x 18 CLOCKED FIRST-IN,FIRST-OUT MEMORY
SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996

absolute maximum ratings over operating free-air temperature ranget

Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, VI ............................................................................. 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range, TA ............................................... O°C to 70°C
Storage temperature range, Tstg .................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indica!ed under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN MAX UNIT
VCC Supply vo~age 4.5 5.5 V
vlH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High~level output current -8 mA
IOL Low-level oulput current 16 mA
TA Operating free-air temperature 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN Tyn MAX UNIT
VOH VCC=4.5 V. IOH=-8mA 2.4 V
VOL VCC=4.5V. IOL= 16mA 0.5 V
II VCC=5.5V. VI =VCC orO i5 !!A
IOZ VCC =5.5 V. Vo=VccorO i5 ~
VI =VCC - 0.2 V or 0 400 ~
ICC§
One input at 3.4 V. Other inputs at VCC or GND 1.2 mA
Ci VI =0. f= 1 MHz 4 pF
Co VO-O. f = 1 MHz 8 pF
:(: All tYPical values are at VCC =5 V. TA =25°C.
§ ICC tested with outputs open.

~1ExAs
INSTRUMENTS
7-90 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7881
1024 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 4)
'ACT7881-15 'ACT7881-20 'ACT7881-30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 67 50 33.4 MHz
WRTCLKhigh 5 7 8.5
WRTCLKlow 7 7 11
tw Pulse duration ROCLKhigh 5 7 8.5 ns
ROCLKlow 7 7 11
Whlgh 7 7 10
00-017 before WRTCLKt 5 5 5
WRTEN1, WRTEN2 high before WRTCLKt 4 5 5
DE, ROEN1, ROEN2 high before ROCLKt 4 5 5
Reset: RESET low before first WRTCLKt end
tsu Setup time 5 6 7 ns
ROCLKtt
Define AF/AE: DO-DB before OAF.!. 3 5 5
Define AF/AE: OAF.!. before RESrn 3 6 7
Define AF/AE (default): OAF high before ~ 4 5 5
00- 017 after WRTCLKt 0 0 0
WRTEN1, WRTEN2 high after WRTCLKt 0 0 0
DE, ROEN1, ROEN2 high after ROCLKt 0 0 0
Reset: RESET low after fourth WRTCLKt and
th Hold time 0 0 0 ns
ROCLKtt
Define AF/AE: 00-08 after i5iiJ'.!. 0 0 0
Define AF/AE: OAF low after RESrn 0 0 0
Define AF/AE (default): OAF high after ~ 0 0 0
t To permit the clock pulse to be utilized for reset purposes

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figures 7 and 8)
FROM TO 'ACT7881-15 'ACT7881-20 'ACT7881-30
PARAMETER UNIT
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX
fmax WRTCLK or RDCLK 67 50 33.4 MHz
tpd 3 12 3 13 3 18
ROCLKt AnyQ ns
tpcj+
ted WRTCLKt IR 2 8 2 9.5 2 12
ns
tpd ROCLKt OR 2 8 2 9.5 2 12
WRTCLKt 6 17 6 19 6 22
tpd AF/AE ns
ROCLKt 6 17 6 19 6 22
tpLH WRTCLKt 6 14 6 17 6 21
HF ns
tpHL ROCLKt 6 14 6 17 6 21
tpLH AF/AE 3 12 3 17 3 21
RESET.!. ns
tpHL HF 3 14 3 19 3 23
ten 2 9 2 11 2 11
OE AnyQ ns
Idis 2 10 2 14 2 14
:I: ThiS parameter Is measured with CL Z 30 pF (see Figure 5).

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266 7-91
SN74ACT7881
1024x18 CLOCKEDFIRST·IN, FIRST·OUT MEMORY
SCAS227C.""' FEBRUARY 1993 - REVISED FEBRUARY 1996

operating characteristics, Vee =5 V, TA = 25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance per 1K bits

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
18
VCC~5V
17 _ RL=5000
II) TA = 25°C
I:
I 16
V
CD
E /
..
i=
>-
a;
15
V
./
0
I:
0
14 V
/
:; /
01
13
II
2
Q.
I 12
II
"
...0.
11
/
10
I
o 50 100 150 200 250 300

CL - Load Capacitance - pF

Figure 5

~TEXAS
INSTRUMENTS
7-92 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7881
1024 x 18 CLOCKED FIRST-IN. FIRST-OUT MEMORY
SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996

TYPICAL CHARACTERISTICS
POWER DISSIPATION CAPACITANCE
va
SUPPLY VOLTAGE
88
fl=15M~Z
TA=25°C ./
CL=50pF

./
V
l/
V
./
./
/
./
/'
82
4.5 4.8 4.7 4.8 4.8 5 5.1 5.2 5.3 5.4 5.5
Vee - Supply Voltage - V

Figure 6

calculating power dissipation

The maximum power dissipation (PT) of the SN74ACT7881 can be calculated by:
P-r. Vee x [Icc + (N x Alec x de») + I.(Cpd x Vcr? x fi) + I.(CL x Vcr? x foJ
where:
Icc power-down lee maximum
N = number of inputs driven by a TTL device
Alee'" Increase in supply current
dc = duty cycle of inputs at a TTL high level of 3.4 V
Cpd = power dissipation capacitance
CL output capacitive load
fi • data input frequency
fo ... data output frequency

~1EXAS
INSTRUMENTS
POST OFFICE BOX 856303 • DALLAS. TEXAS 75286 7-93
SN74ACT7881
1024>< 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS227C,.. FEBRUARY 1993 - REVISED FEBRUARY 1996

PARAMETER MEASUREMENT INFORMATION

From Output
underTest~

RL=6oo0 1 .I CL=60pF

- -
LOAD CIRCUIT TOTEM·POLE OUTPUTS

Figure 7. Standard CMOS Outputs

7V ,,~~ .. v \ :~---::
~
-+l it
RL= R1 = R2
S1 tpZL PLZ " : i+-
R1
II III~ ... a.5V
From Output _
Under Teet
...._ ...._ ...._ Teet
Point Output I \. 1.5V :
I.
I---t.
. - I - VOL
R2 I tpHZ -.I 1+ L 0.3 V
tpZH -+I ~ I j
I --
Output ,1.5
.
V \- ~ ;3-;
'-.:.:..:
VOH

... 0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS

PARAMETER R1,R2 cLt S1

len ~ 5000 50pF

Open
tpZL Closed

!dis ~ 6000 60pF

Open
tpLZ Closed
ted 5000 ·60pF Open
t Includes probe and test fixture capacitance
Figure 8. 3-St$te Outputs (Any Q)

~TEXAS
INSTRUMENTS
7-94 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7881
1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996

APPLICATION INFORMATION

expanding the SN74ACT7881

The SN74ACT7881 is expandable in both word width and word depth. Word-depth expansion is accomplished
by connecting the devices in series such that data flows through each device in the chain. Figure 9 shows two
SN74ACT7881 devices configured for word-depth expansion. The common clock between the devices can be
tied to either the write clock (WRTCLK) of the first device or the read clock (RDCLK) of the last device. The
output-ready flag (OR) of the previous device and the input-ready flag (IR) of the next device maintain data flow
to the last device in the chain whenever space is available.
Figure 10 shows two SN74ACT7881 devices in word-width expansion. Word-width expansion is accomplished
by simply connecting all common control signals between the devices and creating composite input-ready (IR)
and output-ready (OR) signals. The aimost-fuil/aimost-empty flag (AF/AE) and half-full flag (HF) can be sampled
from anyone device. Word-depth expansion and word-width expansion can be used together.

CLK

WRTCLK
WRTEN1
SN74ACT7881

WRTCLK
WRTEN1
ROCLK
OR
1 SN74ACT7881

WRTCLK
WRTEN1
RDCLK
RDEN1
ROCLK
ROEN1
WRTEN2 WRTEN2 ROEN1 L WRTEN2 RDEN2 ROEN2
IR IR ROEN2 '1 IR OR OR
OE ' - - 5V OE OE
00-017 00-017 QO-Q17 00-017 QO-Q17 QO-Q17

Figure 9. Word-Depth Expansion: 2048/4096/8192 Words x 18 Bits, N = 2

SN74ACT7881
WRTCLK WRTCLK ROCLK ROCLK
WRTEN WRTEN1 ROEN1 RDEN
WRTEN2 ROEN2
- IR OR
l:J
018-035
I 00-017 QO-Q17
OE
I
OE
Q18-Q35

IR I SN74ACT7881 I OR

- WRTCLK ROCLK
' - - - WRTEN1 ROEN1 - r--
WRTEN2 ROEN2
IR OR
OE -
00-017 00-017 QO-Q17 QO-Q17

Figure 10. Word-Width Expansion: 1024 Words x 36 Bits

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-95
 SN74ACT7882
2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

• Member of the Texas Instruments • Input-Ready, Output-Ready, and Half-Full

Wldebus ™ Family Flags
• Independent Asynchronous Inputs and • Cascadable In Word Width and/or Word
Outputs Depth
• Read and Write Operations Can Be • Fast Access Times of 11 ns With a 5O-pF
Synchronized to Independent System Load
Clocks • High Output Drive for Direct Bus Interface
• Programmable Almost-FuIl/Almost-Empty • Available In 68-Pln PLCC (FN) or
Flag Space-Saving 80-Pln Shrink Quad Flat (PN)
• Pln-to-Pln Compatible With SN74ACT7881, Packages
SN74ACT7884, and SN74ACT7811

FNPACKAGE
(TOP VIEW)

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

~
014 10 60 Vee
013 11 59 014
012
011
12
13
58
57
013
GND
:;
010 14 56 012 w
09 15 55 011 a:
Vee 16 54 Vee a..
GNO
08

07
17
18
19
53
52
51
010
09
GND
ti::J
06 20 50 08 C
05
04
21
22
49
48
07
Vee
oa:
03
02
23
24
47
46
06
05
a..
01 25 45 GND
00 26 44 04
n~~M~~~M~~~~~~~Ga

ILL 0 ::.:: ~ C\J 0 W 0 II: LL 0 0 ~ 0 C\J CO) 0

<z~zzo<z-~ocrcrzcrcro
00 wW>i:i::o > 0 >
5:5:5: <
~~~

Widebus is a trademark of Texas Instruments Incorporated.

PRODUCT PREVIEW Inlonnalion con...,. prodUctIln lf1elonnatlve or Copyright <C> 1994, Texas Instruments Incorporated

~1EXAS
....Ign phase 01 Cl8Y8IOpment. Ch_1Ic da" and other
speclllcations e......Ign goals. T.... lnatrum.n18 r........ If1. right to
change or dtsconUnue til... products without notice.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-97
 SN74AeT7882
2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445 -,.JUNE 1994

PNPACKAGE
(TOP VIEW)

oo~~nroronnnnro~M~M~~~~~

NC • 60 Vee
GND 59 Vee
GND 3 58 NC
016 57 03
017 56 02
Vee 55 GND
OR 7 54 01
53 00
Vee 9 52 Vee
RESET 51 HF
OE 11 50 IR
RDEN2 49 GND
RDEN1 48 GND
"tJ RDCLK 47 AF/AE
::D
o GND
D17
46
45
Vee
WRTEN2
C D16 44 WRTEN1
c D15 43 WRTCLK
o NC 42 GND
-I NC 20 41 NC
~~~M~UV~~~~~~~~~~~S~
"tJ
::D
m
<
- Ne - No internal connection
m
:e description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7882 is organized as 2048 x 18 bits. The SN74ACT7882 processes data at rates up
to 67 MHz and access times of 11 ns in a bit-parallel format. Data outputs are noninverting with respect to the
data inputs. Expansion is easily accomplished in both word width and word depth.
The SN74ACT7882 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry
adds the ability to synchronize independent reads and writes to their respective system clocks.
The SN74ACT7882 is characterized for operation from O°C to 70 o e.

~TEXAS
INSTRUMENTS
7-98 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7882
2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445 - JUNE 1994

logic symbolt

<I>
FIFO
SN74ACT7882 - 2048 x 18

1 i'..
RESET RESET
29
WRTCLK WRTCLK
30 35
WRTEN1
WRTEN2
31 ~WRTEN IN ROY
HALF FULL
36
IR
HF
5 33
ROCLK ROCLK ALMOST FULUEMPTY AF/AE
4 66
ROEN1 ~ OUT ROY OR
2
OE EN1 ROEN
3
ROEN2
OAF
27

26
i'..
.,~ ALMOST FULL
r
38
DO 0 0 QO
01
02
25
24
23
39
41
42
Q1
Q2 ->==
W

W
03 Q3
04
22 44
Q4 a:
05
21 46
Q5
D.
06
20 47
Q6 t-
07
19 49
Q7
O
17 50 ::J
08
15 ~~1'7 52
Q8
C
09
14 53
Q9
0
010
13 55
Q10 a:
011
12 56
Q11 D.
012 Q12
11 58
013 Q13
10 59
014 Q14
9 61
015 Q15
8 63
016 Q16
7 64
017 17 17 Q17

t This symbol is in accordance with ANSIIIEEE Std 91-1984 and lEG Publication 617-12.
Pin numbers shown are for the FN package.

-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-99
 SN74ACT7882
2048 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS446-JUNE 1994

functional block diagram

OE

00-017

L ~7
location 1

I
RDCLK Synchronous
Read Location 2
RDEN1
Control
Read
Pointer
II
RDEN2

I RAM
2048 x 18

WRTCLK
WRTEN1
WRTEN2
Synchronous
Write
Control I-- I--
I Write I
I
Pointer I •
•
I
~
"o
:xJ.
C
g Reaet Logic I Register QO-Q17

OR
c:> Statue-
Flag IR

~ Logic HF
AF/AE

"m<
:xJ

-
~

~1ExAs
INSTRUMENTS
7-100 POST OFFICE BOX 666303. DALLAS. TEXAS 75265
 SN74ACT7882
2048 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS445 - JUNE 1994

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME NO.
Aimost-fuil/almost-emptyflag. The AF/AE boundary is defined by the aimost-fuil/almost-empty offset
value (Xl. This value can be programmed during reset orthe default value of 256 can be used. AF/AE
is high when the number of words in memory is less than or equal to X. AF/AE is also high when the
number of words in memory is greater than or equal to (2048 - Xl.
Programming procedure for AF/AE is programmed during each reset cycle. The almost-fuIValmost-
empty offset value (Xl is either a user-defined value orthe default of X ~ 256. Instructions to program
AF/AE using both methods are as follows:
User-defined X
AF/AE 33 0 Step 1: Take DAF from high to low. The low-to-high transition of DAF input stores the binary
value on the data inputs as X. The following b~s are used, listed from most significant
bit to least significant bit D9 - DO.
Step 2: If RESET is not already low, take RESET low.
Step 3: With DAF held low, take RESET high. This defines AF/AE using X.
Step 4: To retain the current offset for the next reset, keep DAF low.
DmauIt.X
To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle.
Define-almost-full. The high-to-Iow transition of DAF stores the binary value of data inputs as the 3:
w
DAF 27 I almost-fuIValmost-empty offset value (Xl. With DAF held low, a low pulse on RESET defines the
almost-fuIValmost-empty (AF/AEl flag using X. :;
DO-D17 26-19,17,15-7 I
Data inputs for 18-bit-wide data to be stored in the memory. A high-to-Iow transition on DAF captures w
data for the almost-empty/almost-full offset (Xl from D9-DO.
Half-full flag. HF is high when the FIFO contains 1024 or more words and is low when the number
a:
HF 36 0 Q.
of words in memory is less than half the depth of the FIFO.

IR 35 0
Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR
is driven low on the riSing edge ofthesecond WRTCLK pulse.IR is then driven high on the rising edge
of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low,
ti:::J
IR is driven high on the second WRTCLK pulse after the first valid read. C
OE 2 I
Output enable. The 00-017 outputs are in the high-impedance state when OE is low. OE must be
high before the rising edge of RDCLK to read a word from memory.
oa:
Output-ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset,
OR is set low on the rising edge of the third RDCLK pulse. OR is set high on the rising edge of the
Q.
OR 66 0 third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising
edge of the first RDCLK pulse after the last word is read.
38-39,41-42,44, Data out. The first data word to be loaded into the FIFO is moved to 00-017 on the rising edge of
46-47,49-50, the third RDCLK pulse to occur after the first valid write. RDENl and RDEN2 do not affect this
00-017
52-53,55-56,
0
operation. Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2, OE, and
58-59,61,63-64 OR are high.
Read clock. Data is read out of memory on the low-to-high trans~ion at RDCLK if OR, OE, and
RDCLK 5 I RDENl and RDEN2 are high. RDCLK is a free-running clock and functions as the synchronizing
clock for all data transfers out of the FIFO. OR is also driven synchronously with respect to RDCLK.
RDEN1, 4 Read enable. RDENl and RDEN2 must be high before a rising edge on RDCLK to read a word out
I
RDEN2 3 of memory. RDENl and RDEN2 are not used to read the first word stored in memory.
Reset. A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and
WRTCLK cycles. This ensures that the internal read and write pointers are reset and that OR, HF,
and IR are low, and AF/AE is high. The FIFO must be reset upon power up. With DAF at a low level,
RESET 1 I
a low pulse on RESET defines AF/AE using the aimost~fuil/aimost-empty offset value (Xl, where X
is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines the
AF/AE flag using the default value of X =256.

-!!1 TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS. TEXAS 75265 7-101
 SN74ACT7882
2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445 - JUNE 1994

Terminal Functions (continued)

TERMINAL
I/O DESCRIPTION
NAME NO.
Write clock. Data is written into memory on a low-to-high transition of WRTCLK if IR. WRTEN1. and
WRTCLK 29 I WRTEN2 are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all
data transfers into the FIFO. IR is also driven synchronously with respect to WRTCLK.
Write enable. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word to
WRTEN1, 30
I be written into memory. WRTEN1 and WRTEN2 do not affect the storage of the aimost-fuillaimost-
WRTEN2 31
empty offset value (X).

WRTCLK

WRTEN1

"tJ
WRTEN2
:tJ
oC 00-017

C
o RDCLK
-I
RDEN1
"tJ
:tJ
m RDEN2

S
m OE

:E QO-Q17 Invalid
I I i

Store the Value of Data as X Define the AF/AE Flag Using the
Value of X
t X is the binary value on 09-00.
Figure 1. Reset Cycle: Define AF/AE Using a Programmed Value of X

~TEXAS
INSTRUMENTS
7-102 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7882
2048 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS445 - JUNE 1994

RESET

OAF Don't Care

WRTCLK

WRTEN1

WRTEN2

00-017

RDCLK

RDEN1

~
RDEN2 W
:;
OE w
a:
D..
QO-Q17
I I I I t-
I O
I ::J
j
C
I
I oa:
I
I D..
I
I
I
I
I
I Define the AF/AE Flag Using
=
the Default Value of X 256

Figure 2. Reset Cycle: Define AF/AE Using the Default Value

-!!J TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-103
 SN74ACT7882
2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445 - JUNE 1994

~~~r-fL
WRTCLK

WRTEN1 i i i i
i i i i
i i i i
WRTEN2 --1 i
i
i
i
i
i
i
i

00-017 I WI I I I I I I
W2 W3 W4

~~~~*
RDCLK

i
~~~$L
i I I I
RDEN1 I I I I I
I I I I I
"0 i I I I I
RDEN2 I i I I I
::D I I I I I
0 OE i I I I I
C I I I I I
c:
0
-I
QD-Q17 Invalid
~ : :W1
:I :i
"0
::D
OR I i
i
I
I
i I
m AF/AE I I
S I
m i
:e HF I
I
IR
L
DATA WORD NUMBERS FOR FLAG TRANSITIONS
TRANSITION WORD
A B C
W1025 W(2049-X) W2049

Figure 3. Write

~lExAs
INSTRUMENTS
7-104 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7882
2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445 - JUNE 1994

WRTCLK

RDCLK

RDEN1 .J 1

RDEN2 - I ---'
.. i i
OE ~-~---~--~---~---~i------~i---
QO-Q17 '--"'_~' ....,;.;.;.~r.:;;.;.;.:r-...;.;.w~~+~~~~~---"'Tr--
__
3:
w
OR I i L-- :>
i I
w
I I~-------------
AFIAE
I a:
HF I
Q.
I
IR 1 ...______ ..1 b
:J
DATA WORD NUMBERS FOR FLAG TRANSITIONS C
A B
TRANSITION WORD
C D E F
oa:
W1025 W1030 W(2048-X) W(2049-X) W2048 W2049 Q.
Figure 4. Read

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-105
 SN74ACT7882
2048:>< 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS44Q-JUNE 1994

absolute maximum ratings over operating free-air temperature ranget

Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, V, ....................................•.....................•.................. 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range, TA ............................................... O°C to 70°C
Storage temperature range ........................................................ -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN MAX UNIT
VCC Supply voHage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voHage 0.8 V
10H High-level output current -8 mA
10L LOW-level output current 16 mA
'"0 Operating free-air temperature 70 ·C
lJ
TA
°
oC electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
c: PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT

~ VOH
VOL
VCC- 4.5V,
VCC =4.5 V,
IOH=-8mA
IOL-16mA
2.4
0.5
V
V
'"0 II VCC =5.5 V, VI_ VCC orO ±5 IJA
lJ 10Z VCC-5.5V, VO-Vcc orO ±5 IJA
m VI =Vee-0.2VorO

-=e
400 IJA
< ICC§
One input at 3.4 V, Other Inputs at Vee or GND 1 mA
m Ci VI_O, f =1 MHz 4 pF
Co VO-O, f.l MHz 8 pF
:/:AII typIcal values are at Vce - 5 V, TA =25°e.
§ ICC tested with outputs open.

~1ExAs
INSTRUMENTS
7-106 POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
 SN74ACT7882
2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445 - JUNE 1994

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 4)
'ACT7882·15 'ACT7882·20 ' ACT7882·30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 67 50 33.4 MHz
WRTCLKhigh 6 7 8.5
WRTCLKlow 6 7 11
tw Pulse duration RDCLKhigh 6 7 8.5 ns
RDCLKlow 6 7 11
DAF high 6 7 10
Data in (DO-D17) before WRTCLKi 4 5 5
WRTEN1, WRTEN2 high before WRTCLKi 4 5 5
OE, RDEN1, RDEN2 high before RDCLKi 4 5 5
Reset: RESET low before first WRTCLKi and
tsu Setup time 5 6 7 ns
RDCLKit
Define AF/AE: DO-D8 before DAFt 4 5 5
Define AF/AE: DAFt before RESETi 5 6 7

~
Define AF/AE (default): DAF high before RESETi 4 5 5
Data in (DO- D17) after WRTCLKi 0 0 0
W
WRTEN1, WRTEN2 high afterWRTCLKi
OE, RDEN1, RDEN2 high after RDCLKi
0
0
0
0
1
1 >
w
th Hold time
Reset: RESET low after fourth WRTCLKi and
RDCLKit
0 0 0 ns a:
Define AF/AE: DO-D8 after DAFt 0 0 1
c..

t
Define AF/AE: DAF low after RESETi
Define AF/AE (default): DAF high after RESETi
To permit the clock pulse to be utilized for reset purposes
0
0
0
0
0
1 b
::J
C
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figures 7 and 8)
oa:
PARAMETER
FROM TO 'ACT7882·15 'ACT7882·20 'ACT7882·30
UNIT
c..
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX
fmax WRTCLK or RDCLK 67 50 33.4 MHz
tpel 4 11 4 13 4 18
RDCLKi AnyQ ns
tpel:t:
tpel_ WRTCLKi IR 2 9 2 9.5 2 12
ns
tpd RDCLKi OR 2 9 2 9.5 2 12
WRTCLKi 6 17 6 19 6 22
tpel AF/AE ns
RDCLKi 6 17 6 19 6 22
tpLH WRTCLKi 6 15 6 17 6 21
HF ns
tpHL RDCLKi 6 15 6 17 6 21
tpLH AF/AE 3 16 3 17 3 21
RESETt ns
tpHL HF 4 18 4 19 4 23
ten 2 11 2 11 2 11
OE AnyQ ns
tdis 2 14 2 14 2 14
:t: ThiS parameter IS measured With CL = 30 pF (see Figure 5).

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-107
 SN74ACT7882
2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS.445 - JUNE 1994

operating characteristics, Vee = 5 V, TA =25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance per 1K bits CL - 50 pF, f = 5 MHz

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME

vs
LOAD CAPACITANCE
18
VCC~5V
_ RL=500(.l
17
TA = 25°C
'"cI 18
.,/
Q)
E
i= ./
V
15
ic /
,;'

o"
c 14
:tJ ~
i /
C
C
J
Q.
13

12
I
o-I I

J. 11 I
I
"m
:tJ 10
o 50 100 150 200 250 300

-<m CL - Load Capacitance - pF

Figure 5
~

~1EXAS
INSTRUMENTS
7-108 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7882
2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445-JUNE 1994

TYPICAL CHARACTERISTICS
POWER DISSIPATION CAPACITANCE
va
SUPPLY VOLTAGE
68
LL fl =15M~z
Q.
I TA = 25°C /
8c 67 CL=50pF
,/
~Q. 66 /
~
c V
t 65 lL
~ ,/
V
64

JI
'a 63
/'
,/

8" ./
62
~
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5

VCC - Supply Voltage - V

s:w
Figure 6 a:
D.
calculating power dissipation
The maximum power dissipation (PT) of the SN74ACT7882 can be calculated using:
b
:)
PT = Vee x [Icc + (N x ~Iee x dc)) + L(Cpd x Vee2 x fi) + L(CL x Vee2 x foJ c
where: o
Icc power-down ICC maximum
a:
D.
N number of inputs driven by a TIL device
~Iee increase in supply current
dc duty cycle of inputs at a TIL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
fi data input frequency
fo data output frequency

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-109
 SN74ACT7882
20;1\8 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445 -JUNE 1994

PARAMETER MEASUREMENT INFORMATION

From Output
Input -..I, \ 1 . ; - V - - - - - 3V

Under Test ~ , , ov
Rl=500'1 1 T Cl=50pF
Output _ _ _ _J
14- tpd -+I

/
... tpd ___
' r----""~+-- 1.5V
3V
OV
- -
lOAD CIRCUIT TOTEM·POlE OUTPUTS

Figure 7. Standard CMOS Outputs

7V .~ ~ ..Y \ ;.~---::
~ Rl= R1 = R2
S1 tPZl ~ i+tPLZ -.: I+-
"o
l'J
C
From Output
Under Test
R1
Test
Point Output
, i'
---;-..,
,
'-----I.,
\ 1.5V f--'*-
,, ,'1/1 -3.6V
-
~--=- VOL
c:
(') tpZH ~
, tPHZ
j4-=-
-+I 1+ f.
, ~
0.3 V

~ Output /1.5 V- \- ~;~ VOH

"m<
l'J lOAD CIRCUIT
.
VOLTAGE WAVEFORMS
'2:: "OV

-
~
PARAMETER R1,R2 Clt S1
Open
!en ~ 500'1 50pF
tpZL Closed
Open
!elis ..!f.t!L 500'1 50pF
tPLZ Closed
ted 500'1 50pF Open
t Includes probe and test fixture capaCitance
Figure 8. 3-State Outputs (Any Q)

~1ExAs
INSTRUMENTS
7-110 POST OFFICE BOX 655303 • DALLAS. TEXAS 75285
 SN74ACT1882
2048 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS445-JUNE 1994

APPLICATION INFORMATION

expanding the SN74ACT7882

The SN74ACT7882 is expandable in both word width and word depth. Word-depth expansion is accomplished
by connecting the devices in series such that data flows through each device in the chain. Figure 9 shows two
SN74ACT7882 devices configured for depth expansion. The common clock between the devices can be tied
to either the write clock (WRTCLK) of the first device or the read clock (RDCLK) of the last device. The
output-ready flag (OR) of the previous device and the input-ready flag (IR) of the next device maintain data flow
to the last device in the chain whenever space is available.
Figure 10 is an example of two SN74ACT7882 devices in word-width expansion. Width expansion is
accomplished by simply connecting all common control signals between the devices and creating composite
input-ready (IR) and output-ready (OR) signals. The aimost-fuil/aimost-empty flag (AF/AE) and half-full flag
(HF) can be sampled from anyone device. Depth expansion and width expansion can be used together.

CLOCK

WRTCLK
WRTEN1
SN74ACT7882

WRTCLK
WRTEN1
ROCLK
OR
1 WRTCLK
WRTEN1
SN74ACT7882

ROCLK
ROEN1
ROCLK
ROEN1 3:
WRTEN2 WRTEN2 ROEN1 L WRTEN2 ROEN2 ROEN2 W
IR IR ROEN2 1 IR OR OR :;
OE - 5 V OE OE W
00-017 00-017 QO-Q17 00-017 QO-Q17 QO-Q17 a:
Q.
Figure 9. Word-Depth Expansion: 2048/409618192 Words x 18 Bits, N = 2 t-
O
:J
SN74ACT7882 C
WRTCLK WRTCLK ROCLK 0
WRTEN WRTEN1 ROEN1
ROCLK
ROEN a:
WRTEN2 ROEN2 Q.
- IR OR
~
018-035
I 00-017 QO-Q17
OE
T I
OE
Q18-Q35

IR I SN74ACT7882 I OR
'--- WRTCLK ROCLK
'--- WRTEN1 ROEN1 r- -
WRTEN2 ROEN2
IR OR
OE ~

00-017 00-017 QO-Q17 QO-Q17

Figure 10. Word-Depth Expansion: 2048 Words x 36 Bits

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS. TeXAS 75265 7-111
7-112
 SN74ACT7884
4096 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS444 - JUNE 1994

• Members of the Texas Instruments • Input-Ready, Output-Ready, and Half-Full

Wldebus™ Family Flags
• Independent Asynchronous Inputs and • Cascadable In Word Width and/or Word
Outputs Depth
• Read and Write Operations Can Be • Fast Access Times of 11 ns With a 50-pF
Synchronized to Independent System Load
Clocks • High Output Drive for Direct Bus Interface
• Programmable Almost-Full/Almost-Empty • Available In S8-Pin PLCC (FN) or
Flag Space-Saving 80-Pln Shrink Quad Flat (PN)
• Pin-to-Pin Compatible With SN74ACT7881, Packages
SN74ACT7882, and SN74ACT7811

FNPACKAGE
(TOP VIEW)

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
014
013
10
11
60
59
Vee
014
3:
w
012
011
12
13
58
57
013
GNO
:;
010 14 56 012 w
09 15 55 011 a:
Vee 16 54 Vee Q.

GNO
08

07
17
18
19
53
52
51
010
09
GNO
t>
~
06 20 50 08 c
05
04
21
22
49
48
07
Vee
oa:
03 23 47 06 Q.
02 24 46 05
01 25 45 GNO
00 26 44 04
V~~~~~~M~~~~~~~G~

ILl<Z5ZZ0<Z-~oOOzOOo
. 0 ::.:: - 0 W 0 a: LI. 0
C\I 0 0 0 - C\I C')

O(!)I-~~>U:(!) > (!) >

a:a:a: <
~~~

Widebus is a trademark of Texas Instruments Incorporated.

PRODUCT PREVIEW Information concerns products In tile formative or Copyright © 1994. Texas Instruments Incorporated

~TEXAS
design phase of deveiopmOnL CharactoriotiC data Ind oilier
speclflcattons are design goals. Texaalnstrumenta reserves the right to
change or dlscondnue these products without notice.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-113
 SN74ACT7884
4096 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS444-JUNE 1994

PNPACKAGE
{TOP VIEW)

~OVMCC~~OO C 0 Cc
~O~~zz_~o~mzro~o~~zz3
O>OO~~OO>OO~OO>OO~~

MNnnn~nnnnro~~~~~~ro~~

NC 1 • 60 Vee
GND 2 59 Vee
GND 3 58 NC
Q16 57 Q3
Q17 56 Q2
Vee 6 55 GND
OR 7 54 Q1
GND 8 53 QO
Vee 9 52 Vee
RESET 10 51 HF
OE 11 50 IR
RDEN2 12 49 GND
RDEN1 13 48 GND
'lJ RDCLK 14 47 AF/AE
l:J GND 15 46 Vee
0 017 16 45 WRTEN2
C D16 17 44 WRTEN1
C 015 18 43 WRTCLK
0 NC 19 42 GND
-I NC 20 41 NC
~~n~~~n~~~~~~~~~~~~~
'lJ
l:J OVM~~omoroc~~~VM~~O~O
z~~~~~COCZCCCCCCCC Z
m CCCCc > ~ C

!=5 Ne - No internal connection

m
:e description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7884 is organized as 4096 x 18 bits. The SN74ACT7884 processes data at rates up
to 67 MHz and access times of 11 ns in a bit-parallel format.- Data outputs are noninverting with respect to the
data inputs. Expansion is easily accomplished in both word width and word depth.
The SN74ACT7884 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry
adds the ability to synchronize independent reads and writes to their respective system clocks.
The SN74ACT7884 is characterized for operation from O°C to 70°C.

~1ExAs
INSTRUMENTS
7-114 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7884
4096 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS444-JUNE 1994

logic symbolt

ell
FIFO
SN74ACT7884 - 4098 x 18

1
REfiT
29 " RESET
WRTCLK WRTCLK
30 35
~WRTEN
WRTEN1 IN ROY IR
31 38
WRTEN2 HALF FULL HF
5 33
ROCLK ROCLK ALMOST FULUEMPTY AF/AE
88
ROEN1
4
2
---a- OUT ROY OR

OE EN1 ROEN
3
ROEN2
OAF
27
.,
" ~ ALMOST FULL r
DO
28
0 0
38
QO ~
01
02
03
28
24
23
39
41
42
Q1
Q2
Q3
-
W
>
W
04
22 44
Q4 a:
21 48
as D..
05
08
20
19
47
49
Q8 ....
0
07 Q7
17 50 ::l
08
15 ~~1V 52
Q8
C
09 Q9
0
010
14
13
53
55
Q10 a:
011
12 58
Q11 D..
012 Q12
11 58
013 Q13
10 59
014 Q14
9 81
015 Q15
8 83
018 Q18
7 84
017 17 17 Q17

t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the FN package.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-115
 SN74ACT7884
4096 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS444 - JUNE 1994

functional block diagram

OE

~J
00-017

ROCLK
L Synchronous
Location 1
Location 2
ROEN1
ROEN2
Read
Control I R d
po:ter :
I

RAM
I 4096 x 18

WRTCLK Synchronous
WRTEN1
WRTEN2
Write
Control - I--
I Write
I Pointer
I
I ..
I
." ~J
:D
0 RESET
~ Reset Logic I Register QO-Q17

C OR
c: Status-
Flag IR
0 OAF
Logic HF
-f AF/AE
."
:D
m
S
m
:E

~TEXAS
INSTRUMENTS
7-116 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7884
4096 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS444 - JUNE 1994

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME NO.
Almost-fuIValmost-emptyfiag. The AF/AE boundary is defined by the aimost-fuil/almost-empty offset
value (X). This value can be programmed during reset orthe default value of 256 can be used. AF/AE
is high when the number of words in memory is less than or equal to X. AF/AE is also high when the
number of words in memory is greater than or equal to (4096 - X).
Programming procedure for AF/AE is programmed during each reset cycle. The aimost-fuil/almost-
empty offset value (X) is either a user-defined value or the default of X = 256. Instructions to program
AF/AE using both methods are as follows:
User-defined X
AF/AE 33 0 Step 1: Take DAF from high to low. The low-te-high transition of DAF stores the binary value
on the data inputs as X. The following bits are used, listed from most significant bit
to least significant bit DlO-DO.
Step 2: If RESET is not already low, take RESET low.
Step 3: With DAF held low, take RESET high. This defines AF/AE using X.
Step 4: To retain the current offset for the next reset, keep DAF low.
.omauJ1X
To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle.
Define-almost-full. The high-te-Iow transition of DAF stores the binary value of data inputs as the 3:
w
DAF 27 I almost-fuIValmost-empty offset value (X). With DAF held low, a low pulse on RESET defines the
almost-fuIValmost-empty (AF/AE) flag using X. :;
DO-D17 26-19,17,15-7 I
Data inputs for 18-bit-wide data to be stored in the memory. A high-te-Iow transition on DAF captures w
data for the almost-empty/almost-full offset (X) from D1 0- DO.
a:::
HF 36 0
Half-full flag. HF is high when the FIFO contains 2048 or more words and is low when the number
of words in memory is less than half the depth of the FIFO.
a.
IR 35 0
Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR
is driven low on the rising edge olthe second WRTCLK pulse. IR is then driven high on the rising edge
of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low,
ti
::J
IR is driven high on the second WRTCLK pulse after the first valid read. C
OE 2 I
Output enable. The 00-017 outputs are in the high-impedance state when OE is low. OE must be
high before the rising edge of RDCLK to read a word from memory.
oa:::
OR 66 0
Output-ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset,
OR is set low on the rising edge of the third RDCLK pulse. OR is set high on the rising edge of the
a.
third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising
edge of the first RDCLK pulse after the last word is read.
38-39,41-42,44, Data out. The first data word to be loaded into the FIFO is moved to 00-017 on the rising edge of
46-47,49-50, the third RDCLK pulse to occur after the first valid write. RDENl and RDEN2 do not affect this
00-017 0
52-53,55-56, operation. Following data is unloaded on the rising edge of RDCLK when RDEN 1, RDEN2, OE, and
58-59,61,63-64 OR are high.
Read clock. Data is read out of memory on the low-te-high transition at RDCLK if OR, OE, RDEN1,
RDCLK 5 I and RDEN2 are high. RDCLK is a free-running clock and functions as the synchronizing clock for
all data transfers out of the FIFO. OR is also driven synchronously with respect to RDCLK.
RDEN1, 4 Read enable. RDENl and RDEN2 must be high before a rising edge on RDCLK to read a word out
I
RDEN2 3 of memory. RDENl and RDEN2 are not used to read the first word stored in memory.
Reset. A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and
WRTCLK cycles. This ensures that the internal read and write pointers are reset and that OR, HF,
RESET and IR are low, and AF/AE is high. The FIFO must be reset upon power up. With DAF at a low level,
1 I
a low pulse on RESET defines AF/AE using the aimost-fuil/almost-empty offset value (X), where X
is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines AF/AE
using the default value of X = 256.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 7-117
 SN74ACT7884
4096 x18 CLOCKED FIRST-IN, FIRST·OUT MEMORY
SCAS444 - JUNE 1994

Terminal Functions (continued)

" .
TERMINAL
110 DESCRIPTION
NAME; NO.
Write clock. Data is written into memory on a low-to-high transition of WRTCLK if IR, WRTEN1, and
'vJRTCLK 29 I WRTEN2 are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all
. data transfers into the FIFO. IR is also driven synchronously with respect to WRTCLK.
Write enable. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word to
iNRTEN1, 30
I be written into memory. WRTEN1 and WRTEN2 do not affect the storage of the aimost-fuil/almost-
WRTEN2 31
empty offset value (Xl.

RESET

OAF ~]1,h]~A~
WRTCLK I 1 2 3 I

WRTEN1

i:J
:IJ WRTEN2

0 00-017
C
C
0 RDCLK
-I
RDEN1

"m
:IJ
RDEN2

<
-m OE

:E QO-Q17 Invalid
I I I
OR ~r:aIi4~ )(Vh'
I
AF/AE ~I~vgl~~ I
I
HF %.Tn{all4~
:){)(L' I
I
IR &S&SZ~~l'n~
Store the Value of Data as X Define the AF/AE Flag Using the
Value of X
t X is the binary value on 010-00.
Figure 1. Reset Cycle: Define AF/AE Using a Programmed Value of X

~1ExAs
INSTRUMENTS
7-118 POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
 SN74ACT7884
4096 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS444 - JUNE 1994

OAF Don't Care

--------~~------------------~
WRTCLK

WRTENl

WRTEN2

RDCLK

RDENl

RDEN2
s:w
:;
OE w
a:
QO-Q17 Invalid
a..
i i i
t5
::J
C
I
I oa:
I
I
i
a..
I
I
I
I
I Define the AF/AE Flag Using
=
the Default Value of X 256

Figure 2. Reset Cycle: Define AF/AE Using the Default Value

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS. TeXAS 75265 7-119
 SN74ACT7884
4096 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS444 - JUNE 1994

~r-0~r-fL
WRTCLK

WRTEN1 I I I I
I I I I
I I I I
WRTEN2 .-J I
I
I
I
I
I
I
I
00-017 I WI I I I I I I
W2 W3 W4
~~otc~$
RDCLK

I
~~~r1!L
I I I I
RDEN1 I I I I I
I I I I I
I I I I I

"0
::D
RDEN2

OE
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
C I I I I I

~
C Invalid
QO-Q17
0 : :W1
: :
-I I I
I I

"m
OR I
I I
::D I I
I I
-m
AF/AE
< I
I
HF I
~ I
IR
L
DATA WORD NUMBERS FOR FLAG TRANSITIONS
TRANSITION WORD
A B C
W2049 W(4097-X) W4097

Figure 3. Write

~1ExAs
INSTRUMENTS
7-120 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7884
4096 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS444 - JUNE 1994

WRTCLK

RDCLK

RDEN1 .J 1

RDEN2 _ 1_--,
... I I
OE ~~~---~------~----~I~------+I------------~I----

QO-Q17 _-i-______ ~::::~:~:::~:~~f__W-(X-+2)-!--A_+:X---B--~~--C-i-~ __D ~~:::::~:F--- 3:

_____
E__ w
OR I
I
I
I
I
I
L- 5>
I I I...- - - - - - - - w
AF/AE
a:
HF
I
I
c...
I
IR IL._____---' b
:J
DATA WORD NUMBERS FOR FLAG TRANSITIONS C
A B
TRANSITION WORD
C D E F
oa:
W2049 W2050 W{4096-X) W(4097-X) W4096 W4097 c...
Figure 4. Read

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7-121
 SN74ACT7884
4096 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS444-JUNE 1994

absolute maximum ratings over operating free-air temperature ranget

Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, VI ............................................................................. 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range, TA ............................................... O°C to 70°C
Storage temperature range ........................................................ -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings·' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other cond~ions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
10H High-level output current -8 mA
10L Low-level output current 16 mA

"tJ TA Operating free-air temperature 0 70 ·e

::c
o
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
C PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
o VOH Vee = 4.5 V, 10H =-8mA 2.4 V
-t VOL Vee=4.5 V. IOL=16mA 0.5 V
"tJ II Vee = 5.5 V, VI- Vee orO ±5 JJA
::c 10Z Vee=5.5V, VO=Vee orO ±5 JJA
m VI = Vee - 0.2 V or 0 400 JJA
S lee§
One input at 3.4 V, Other inputs at Vee or GND 1 mA
m ei VI = 0, f= 1 MHz 4 pF

:e eo Vo=O,
:j: All tYPical values are at Vee = 5 V, TA = 25·e.
f = 1 MHz 8 pF

§ lee tested with outputs open.

-!111ExAs
INSTRUMENTS
7-122 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7884
4096 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS444 - JUNE 1994

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 4)
'ACT7884-15 'ACT7884-20 'ACT7884-30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 67 50 33.4 MHz
WRTCLKhigh 6 7 8.5
WRTCLKlow 6 7 11
tw Pulse duration ROCLKhigh 6 7 8.5 ns
ROCLKlow 6 7 11
OAF high 6 7 10
Data in (00- 017) before WRTCLKi 4 5 5
WRTEN1. WRTEN2 high before WRTCLKi 4 5 5
OE. ROEN1. ROEN2 high before ROCLKi 4 5 5
Reset: RESET low before first WRTCLKi and
tsu Setup time 5 6 7 ns
ROCLKit
Define AF/AE: 00-08 before OAF.!, 4 5 5
Define AF/AE: OAF.!, before RESETI 5 6 7
Define AF/AE (default): OAF high before RESETi
Data in (00-017) after WRTClKi
4
0
5
0
5
0
~
W
WRTEN1. WRTEN2 high after WRTCLKi 0 0 1
:;
OE. ROEN1. ROEN2 high after ROCLKi 0 0 1
w
th Hold time
Reset: RESET low after fourth WRTCLKi and
ROCLKit
0 0 0 ns a:
Define AF/AE: 00-08 after OAF.!, 0 0 1
D..
Define AF/AE: OAF low after RESETi 0 0 0 I-
Define AF/AE (default): OAF high after RESETi 0 0 1 o
t To permit the clock pulse to be utilized for reset purposes ::J
C
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figures 7 and 8)
oa:
FROM TO 'ACT7884-15 'ACT7884-20 'ACT7884-30 D..
PARAMETER UNIT
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX
f max WRTCLK or ROCLK 67 50 33.4 MHz
tpd 4 11 4 13 4 18
ROCLKi AnyQ ns
Igd+
tpd WRTCLKi IR 2 9 2 9.5 2 12
ns
Ipd ROCLKi OR 2 9 2 9.5 2 12
WRTCLKi 6 17 6 19 6 22
tpd AF/AE ns
ROCLKi 6 17 6 19 6 22
tPLH WRTCLKi 6 15 6 17 6 21
HF ns
tPHL ROCLKi 6 15 6 17 6 21
tpLH AF/AE 3 16 3 17 3 21
RESET.!, ns
tpHL HF 4 18 4 19 4 23
ten 2 11 2 11 2 11
OE AnyQ ns
tdis 2 14 2 14 2 14
+ This parameter IS measured with CL = 30 pF (see Figure 5).

-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-123
 SN74ACT7884
4096 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS444-JUNE 1994

operating characteristics, Vee = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance per 1K bits

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
18
VCC~5V
17 r- RL=5000
III TA=25°C
c
I
GI
16 V
~ /'
/
15

"'D f
c 14
./
.;'

:II
0
'&i /~
o & 13
C
c:
e
II.
I 12
/
o-I .J 11 I
"'D 10
I
:II o 50 100 150 200 250 300
m
-
CL - Load Capacitance - pF
< FigureS

~1ExAs .
INSTRUMENTS
7-124 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7884
4096 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS444-JUNE 1994

TYPICAL CHARACTERISTICS
POWER DISSIPATION CAPACITANCE
VB
SUPPLY VOLTAGE
68
u.
Do
fl =15M~Z
TA = 25°C
I
67 ./
8c CL=SOpF

:!
:.lDo ./
V
66
8c /
.S! /
1 65
/
-=
is
64 V
I I
83
V
V
J. V
82
3:
w
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5

Vee - Supply Voltage - V 5>

w
Figure 6 a:
Q.
calculating power dissipation
The maximum power dissipation (PT) of the SN74ACT7884 can be calculated using:
t;
::J
PT = Vcc x [Icc + (N x ~lcC x dc)] + l:(Cpd x Vcc2 x fi) + l:(CL x Vcc 2 x foJ C
where: oa:
Icc power-down ICC maximum Q.
N number of inputs driven by a TIL device
~Icc increase in supply current
dc duty cycle of inputs at a TIL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
fi data input frequency
fo data output frequency

~1EXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265 7-125
 SN74ACT7884
4096 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS444 - JUNE 1994

PARAMETER MEASUREMENT INFORMATION

3V
\1.~V-----
From Output Input-A

~
OV
U"",Tom I
Rl =500 Q T Cl =50 pF
I
14- tpd-+l l4-tpd -tI

~
3V

-::- -::-
Output )t OV

lOAD CIRCUIT TOTEM· POLE OUTPUTS

Figure 7. Standard CMOS Outputs

,- ~"Y \ :~---::
."
S1
R1
tPZl -+i i'PlZ -.: ,.....

:IJ _---!I~ I I I '" 3.5 V

oC From Output
Under Test
Test
Point Output : ' \ 1.5V :~ VOL

C I tPHZ -.I 1+ t. 0.3 V

o -+I I+- I j
1
tpZH
-I Output 1.5 V \. ~;.~ VOH
." "'OV
:IJ lOAD CIRCUIT
m VOLTAGE WAVEFORMS
<
-
m PARAMETER R1,R2 clt S1
:e ten
I tpZH
tpZL
5000 50 pF
Open
Closed
I tpHZ Open
tdis 5000 50 pF
tpLZ Closed
tpd 5000 50 pF Open
t Includes probe and test fixture capacitance
Figure 8. 3-State Outputs (Any Q)

-!!1TEXAS
INSTRUMENTS
7-126 POST OFFICE BOX 655303 • PALLAS, TEXAS 75265
 SN74ACT7884
4096 x 18 CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS444 - JUNE 1994

APPLICATION INFORMATION

expanding the SN74ACT7884

The SN74ACT7884 is expandable in both word width and word depth. Word-depth expansion is accomplished
by connecting the devices in series such that data flows through each device in the chain. Figure 9 shows two
SN74ACT7884 devices configured for depth expansion. The common clock between the devices can be tied
to either the write clock (WRTCLK) of the first device or the read clock (RDCLK) of the last device. The
output-ready flag (OR) of the previous device and the input-ready flag (I R) of the next device maintain data flow
to the last device in the chain whenever space is available.
Figure 10 is an example of two SN74ACT7884 devices in word-width expansion. Width expansion is
accomplished by simply connecting all common control signals between the devices and creating composite
input-ready (IR) and output-ready (OR) signals. The aimost-full/aimost-empty flag (AF/AE) and half-full flag
(HF) can be sampled from anyone device. Depth expansion and width expansion can be used together.

CLOCK

WRTCLK
WRTEN1
SN74ACT7884

WRTCLK
WRTEN1
ROCLK
OR
1 WRTCLK
WRTEN1
SN74ACT7884

ROCLK
ROEN1
ROCLK
ROEN1
"'
~
WRTEN2 WRTEN2 ROEN1 L WRTEN2 ROEN2 ROEN2 W
IR IR ROEN2 ~ IR OR OR :;
OE - 5 V OE OE W
00-017 00-017 QO-Q17 00-017 QO-Q17 QO-Q17 a:
D..
Figure 9. Word·Depth Expansion: 2048/409618192 Words x 18 Bits, N = 2 I-
0
::J
SN74ACT7884 C
WRTCLK WRTCLK ROCLK 0
WRTEN WRTEN1 ROEN1
ROCLK
ROEN a:
WRTEN2 ROEN2 D..
r-- IR OR

018-035
I 00-017 QO-Q17
OE --:l
T I
OE
Q18-Q35

IR I SN74ACT7884 I OR
'-- WRTCLK ROCLK
- WRTEN1 ROEN1 - -
WRTEN2 ROEN2
IR OR
OE -
00-017 00-017 QO-Q17 QO-Q17

Figure 10. Word-Depth Expansion: 4096 Words x 36 Bits

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 7-127
7-128
8-1
 18-BIT STROBED FIFOS
Features Benefits

• Members of Texas Instruments Widebus™ • Combine wider data-path capability with

family reduced package area
• Advanced BiCMOS process • F~st access time for improved system
cycle time and performance
• 0.8-J.lm CMOS process • Fast access times combined with low
power
• Support clock rates up to 67 MHZ • Supports high-performance systems
• Fast access times • Access times as low as 12 ns for
improved performance
• High drive capabilities • Drive capability as high as -12 mA to
24 mA for high fanout and bus
applications
• Depth from 16 to 2K words • Allows greater system optimization
• Load/unload clock rising-edge triggered • Reduces timing and pulse-shaping
requirements
• Asynchronous load/unload clock • Independent read and write capabilities
• Grey-code flag architecture • Eliminates race conditions

-
• Output edge control (OECTM) circuitry • Improved reliability
en • Distributed Vee and GND • Improved noise immunity and mutual
o"'" coupling effects
C"
CD • Fine-pitch package options • Significantly reduce critical board space
Co
• Available in EIAJ 80-pin TQFP packages • Board-space savings of up to 70% over
:I! 68-pin PLCC option
"T1
oUJ

8-2
 SN74ACT7814
64 x 18
STROBED FIRST·IN, FIRST·OUT MEMORY
-APRIL 1992 - REVISED SEPTEMBER 1995

• Member of the Texas Instruments DLPACKAGE

(TOP VIEW)
Wldebus ™ Family
• Load Clock and Unload Clock Can Be
Asynchronous or Coincident OE
017
• 64 Words by 18 Bits 016
• Low-Power Advanced CMOS Technology 015 015
• Full, Empty, and Half-Full Flags 014 GNO
• Programmable Almost-FuIl/Almost-Empty 013 014
Flag 012 Vee
011 013
• Fast Access Times of 15 ns With a 50-pF
012
Load and All Data Outputs Switching
Simultaneously 011
010
• Data Rates From 0 to 50 MHz 08 09
• 3-State Outputs GNO GNO
• Pin Compatible With SN74ACT7804 and 07 08
SN74ACT7806 06 07
• Packaged In Shrink Smail-Outline 30e-mil 05 06
(DL) Package Using 25-mll Center-ta-Center 04 05
Spacing 03 Vee
02 04
description 01 03
DO 02
A FIFO memory is a storage device that allows HF GNO
data to be written into and read from its array at PEN 01
independent data rates. The SN74ACT7814 is a AF/AE 00
64-word by 18-bit FIFO for high speed and fast LOCK UNCK
access times. It processes data at rates up to NC
NC
50 MHz and access times of 15 ns in a bit-parallel
NC NC
format.
FULL
Data is written into memory on a low-to-high
transition at the load clock (LOCK) input and is
read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of
words clocked in exceeds the number of words clocked out by 64. When the memory is full, LOCK signals have
no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and
aimost-fuil/aimost-empty (AFtAE) flags. The FULL output is low when the memory is full and high when the
memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF
output is high when the FIFO contains 32 or more words and is low when it contains 31 or less words. The AFtAE
status flag is a programmable flag. The first one or two low-to-high transitions of LOCK after reset are used to
program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN) is low.
The AFtAE flag is high when the FIFO contains X or less words or (64 - Y) or more words. The AFtAE flag is
low when the FIFO contains between (X + 1) and (63 - y) words.

Widebus is a trademark of Texas Instruments Incorporated.

Copyright © 1995, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS. TeXAS 75265 8-3
SN74ACT7814
64x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209A - APRIL 1992 - REVISED SEPTEMBER 1995

description (continued)
A low level on the reset (RESEn input resets the internal stack pointers and sets FULL high, HF low, and
EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up.
The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs.
It is important to note that the first word does not have to be unloaded. The data outputs are non inverting with
respect to the data inputs and are in the high-impedance state when the output-enable (OE) input is high.
The SN74ACT7814 is characterized for operation from aoc to 7aoC.

logic symbolt

cp
FIFO 64x 18
SN74ACT7814
1
RESET
"- RESET
25 28
LOCK LOCK FULL FULL
22
32 HALF-FULL HF
UNCK UNCK 24
56 ALMOST FULUEMPTY AF/AE
OE "'- ENl 29
23 EMPTY EMPTY
"'- PROGRAM ENABLE
PEN
.., r
21 33
DO 0 0 QO
20 34
01 Ql
19 36
02 Q2
18 37
03 Q3
17 38
04 Q4
16 40
05 Q5
15 41
06 Q6
14 42
07 Q7
12 43
08 Q8

~ ~lV
11 45
09 Q9
9 46
010 Ql0
8 47
011 Qll
7 48
012 Q12
6 49
013 Q13
5 61
014 Q14
4 53
015 Q15
3 54
016 Q16
2 55
017 17 17 Q17

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.

~1ExAs
INSTRUMENTS
8-4 POST OFFICE eox 665303 • DALLAS. TEXAS 75265
 SN74ACT7814
64 x 18
STROBED FIRST·IN, FIRST·OUT MEMORY
SCAS209A - APRIL 1992 - REVISED SEPTEMBER 1995

functional block diagram

OE

00-017

1
Location 1
Read Location 2
UNCK Pointer
f--+-
64x 18SRAM
T
Write I
LOCK
Pointer
~ r- Location 63
Location 64

I .1'
1 QO-Q17

EMPTY
Reset
Logic t- Status-
Flag
FULL

Logic HF
AF/AE

Terminal Functions
TERMINAL
110 DESCRIPTION
NAME NO.
Aimost-fuil/almost-emptyflag. Depth-offset values can be programmed for AF/AE, orthe default value
AF/AE 24 0 of 8 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when
memory contains X or less words or (64 - Y) or more words. AF/AE is high after reset.
2-9,11-12,
00-017 I 18-bit data input port
14-21
Empty flag. EMPTY is high when the FIFO memory is not empty; EMPTY is low when the FIFO memory
EMPTY 29 0
is empty or upon assertion of RESET.
Full flag. FULLis high when the FIFO memory is not full or upon assertion of RESET; FULLis low when
FULL 28 0
the FIFO memory is full.
HF 22 0 Half-full flag. HF is high when the FIFO memory contains 32 or more words. HF is low after reset.
LOCK 25 I Load clock. Data is written to the FIFO on the rising edge of LOCK when FULL is high.
OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state.
Program enable. After reset and before the first word is written to the FIFO, the binary value on 00-04
PEN 23 I
is latched as an AF/AE offset value when PEN is low and WRTCLK is high.
33-34,36-38,
00-017 40-43,45-49, 0 18-bit data output port
51,53-55
RESET 1 I Reset. A low level on RESET resets the FIFO and drives FULL high and HF and EMPTY low.
UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 8-5
SN74ACT7814
64x 18
STROBED FIRST·IN, FIRST·OUT MEMORY
SCAS209A - APRIL 1992 - REVISED SEPTEMBER 1995

offset values for AF/AE

The aimost-fuil/aimost-empty flag has two programmable limits: the almost-empty offset value (X) and the
almost~full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written
to memory. The AF/AE flag is high when the FIFO contains X or less words or (64 - Y) or more words.
To program the offset values, program enable (PEN) can be brought low after reset only when LOCK is low. On
the following low-to-high transition of LOCK, the binary value on 00-04 is stored as the almost-empty offset
value (X) and the almost-full offset value (Y). Holding PEN low for another low-to-high transition of LOCK
reprograms Y to the binary value on 00-04 at the time of the second LOCK low-to-hlgh transition. Writes to
the FIFO memory are disabled while the offsets are programmed. A maximum value of 31 can be programmed
for either X or Y (see Figure 1). To use the default values of X = Y = 8, PEN must be held high.

RESET \ " ' -_ _ _ _ 1

LOCK

00-04 ~:*€~*e~ XandY X__ Y_ _ X______

/
Figure 1. Programming X and Y Separately

~1ExAs
INSTRUMENTS
8-6 POST OFFICE BOX 655303 • DALLAS, TEXAS 76265
 SN74ACT7814
64x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209A - APRIL 1992 - REVISED SEPTEMBER 1995

.,..0 .,..0

eco
-
C)
·c
0
a
G)
()
c

-e
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G)
a:
C)
c
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C)
III
u::
"C
C
III
,;
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G)
a:
-GS
';::
3:
I:'i
G)
~
:::I
C)

i i!

g'>
'iii -g
:::I ..
CI)(
.!!!-
ILO
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il:"
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G>=
.c ::l
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I~ I~
Ii
~

I~
~ IL
"" ""
I~
W G> G>
C)
Q C)
z (; < J: ,50
a
...I
0
a
I :::I
8
I ::IE
W
il:
< as

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8-7
SN74ACT7814
64 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209A - APRIL 1992 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)f
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, VI ...•.•..•..••.................•.•.....•.•...................•.........••... 7 V
Voltage applied to a disabled 3-state output .................................................. 5.5 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

'ACT7814-20 'ACT7814-25 'ACT7814-40
UNIT
MIN MAX MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input Voltage 2 2 2 V
VIL LOW-level input Voltage 0.8 0.8 0.8 V
IOH High-level output current Q outputs, Flags -8 -8 -8 rnA
Q outputs 16 16 16
IOL LOW-level output current rnA
Flags 8 8 8
fClock Clock frequency 50 40 25 MHz
LOCK high or low 7 8 12
UNCK high or low 7 8 12
tw Pulse duration ns
PEN low 7 8 12
RESET low 10 10 12
00-017 before LOCKi 5 5 5
tsu Setup time PEN before LOCKi 5 5 5 ns
LOCK inactive before RESET high 5 6 6
00-017 after LOCKi 0 0 0
LOCK inactive after RESET high 5 6 6
th Hoidtime ns
PEN low after LOCKi 3 3 3
PEN high after LOCK! 0 0 0
TA Operating free-air temperature 0 70 0 70 0 70 ·C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
VOH VCC=4.5V. IOH=-8mA 2.4 V
I Flags VCC=4.5V, IOL=8 rnA 0.5
VOL V
I Q outputs Vce =4.5V. IOL= 16 rnA 0.5
II VCC= 5.5 V, VI =VccorO ±5 JJA
IOZ VCC= 5.5V. Vo=VccorO ±5 JJA
ICC VI = VCC - 0.2 V or 0 400 JJA
L\lee§ Vce= 5.5V. One input at 3.4 V. Other inputs at VCC or GNO 1 rnA
Ci VI=O. f = 1 MHz 4 pF
Co VO=O, f = 1 MHz 8 pF
:f: All tYPical values are at VCC = 5 V, TA = 25·e.
§ This is the supply current for each input that is at one of the specified TIL voltage levels rather 0 V or VCC.

~TEXAS
INSTRUMENTS
8-8 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7814
64x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209A - APRIL 1992 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figures 5 and 6)
FROM TO 'ACT7814-20 'ACT7814-25 'ACT7814-40
PARAMETER UNIT
PNPUT) (OUTPUT) MIN TYpt MAX MIN MAX MIN MAX

'max LDCKorUNCK 50 40 25 MHz

LDCKf 9 20 9 22 9 24
tpd
UNcKf AnyQ 6 11.5 15 6 18 6 20 ns
tpdt UNCKf 10.5
tPLH LDCKf 6 15 6 17 6 19
UNCKf EMPTY 6 15 6 17 6 19 ns
tpHL
RESET low 4 16 4 18 4 20
tpHL LDCKf 6 15 6 17 6 19
UNCKf FULL 6 15 6 17 6 19 ns
tPLH
RESET low 4 18 4 20 4 22
LDCKf 7 18 7 20 7 22
tpd
UNCKf AF/AE 7 18 7 20 7 22 ns
tpLH RESET low 2 10 2 12 2 14
tpLH LDCKf 5 18 5 20 5 22
UNCKf HF 7 18 7 20 7 22 ns
tpHL
RESET low 3 12 3 14 3 16
ten 2 9 2 10 2 11
OE AnyQ ns
'dis 2 10 2 11 2 12
t All typical values are at VCC = 5 V, TA = 25°C.
:j: This parameter is measured at CL = 30 pF (see Figure 3).

operating characteristics, Vee = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance per FI FO channel Outputs enabled

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8-9
SN74ACT7814
64x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209A - APRIL 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME

vs
LOAD CAPACITANCE

~5V
typ+8
Vee ~
I-TA = 25°C
V
..T typ+ 8
RL=5000

/
/
Q)
E
j::
i;' typ+4
/
V
;!i /
c
/
ie typ + 2
/
Q.
I
typ
V
"
...0.
I
I
typ-2
o 50 100 150 200 250 300

eL - Load capacitance - pF

Figure 3

SUPPLY CURRENT
vs
CLOCK FREQUENCY
200 I
TA = 75°C
180 eL=OpF Vec=5.5V /
180
0(
E 140
Vee = 5 V "" / 1/
ii
I

120
/ Y ./
t:
::I
0 100 / / '/
b
0.
0.
::I 80
/ /~ Vee = 4.5 V

~ 'l'
II)
I
60
£
E
0
40 ~~
20
0
,~p
o 10 20 30 40 50 80 70
fclock - Clock Frequency- MHz

Figure 4

~TEXAS
INSTRUMENTS
8-10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7814·
64x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209A - APRIL 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

calculating power dissipation

With ICC(f) taken from Figure 4, the maximum power dissipation (PT) based on all data outputs changing states
on each read can be calculated by:
PT = VCC x [ICC(f) + (N x Aicc x dc)] + l:(CL x VCc2 x fal
A more accurate power calculation based on device use and average number of data outputs switching can be
found by:
.p,- =Vcc x [ICC + (N x AICC x dc)] + l:(Cpd x vcc2 x fj) + l:(CL x Vcc 2 x fo)
where:
Icc power-down Icc maximum
N number of inputs driven by a TTL device
A Icc increase in supply current
dc duty cycle of inputs at a TTL high level of 3.4 V
Cpd '" power dissipation capacitance
CL = output capacitive load
fj '" data input frequency
fo = data output frequency

~.1ExAs "
INS1RUMENTS
POST OFFICE BOX _ • DALlAS. TEXAS 76266 8-11
SN74ACT7814
64x 18
STROBED FIRST·IN, FIRST·OUT MEMORY
SCAS209A - APRIL 1992 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION

SN74ACT7814
LOCK LOCK UNCK UNCK

EMPTY -
---G=]
FULL
I
OE
-
018 - 035 ./ 00-017 QO-Q17 Qi8-Q35

SN74ACT7814
- po LOCK UNCK

FULL EMPTY - I--

OE -
00-017 ."\ 00-017 QO-Q17 QO-Qi7

Figure 5. Word-Width Expansion: 64 Words by 36 Bits

~1ExAs
INSTRUMENTS
8--12 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7814
64x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS209A-APRIL 1992- REVISED SEPTEMBER 1995

=nI
PARAMETER MEASUREMENT INFORMATION

Input L \ ~5-;--- 3V
From Output
Under Test
--'1 I· GND
tpd ~~-~~ I I
Rl=5000 I ~ ~ ~d
Output
_ _ _ _oJ
I I ~----\:::T -- ov
1.5 V
3V

lOAD CIRCUIT TOTEM-POLE OUTPUTS

Figure 6. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE)

- - - - 3V
Input 1.5V
'--_--J.~ - - - - 0V
7V ~ 1
-+i ,....
~
tPlZ
=3.5V
S1 I 1
Output I' __ L
'--_..J..J._ - T -

r
VOL
From Output Test Point tpHZ -+-I I+- L 0.3 V
Under Test ---<_--41____.....-
tpZH -+I l.J. __ VOH
R2

Output _ _ --oJ! 1.5 V ~ V = 0 V 1.5 V

lOAD CIRCUIT VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PARAMETER R1,R2 clt S1

tPZH Open
ten 5000 50 pF
tPZL Closed
tpHZ Open
ldis 5000 50 pF
tpLZ Closed
tpel 5000 50 pF Open
t Includes probe and test-fixture capacitance
Figure 7. 3-State Outputs (Any Q)

-!II TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 8-13
8-14
 SN74ACT7806
256 x 18
FIRST·OUT MEMORY

• Member of the Texas Instruments DLPACKAGE

Wldebus ™ Family (TOP VIEW)

• Load Clock and Unload Clock Can Be

RESET OE
Asynchronous or Coincident
017 017
• 256 Words by 18 Bits 016 016
• Low·Power Advanced CMOS Technology 015 015
• Full, Empty, and Half·Full Flags 014 GNO
• Programmable Almost·FuIl/Almost·Empty 014
Flag Vee
013
• Fast Access Times of 15 ns With a 50·pF
012
Load and All Data Outputs Switching
Simultaneously 011
010
• Data Rates From 0 to 50 MHz 08 09
• 3·State Outputs GNO GNO
• Pin Compatible With SN74ACT7804 and 07 08
SN74ACT7814 06 07
• Packaged in Shrink Small·Outline 300·mil 05 06
(DL) Package Using 25·mil Center·to·Center 04 05
Spacing 03 Vee
02 04
description 01 03
00 02
A FIFO memory is a storage device that allows HF GNO
data to be written into and read from its array at PEN 01
independent data rates. The SN74ACT7806 is a AF/AE 00
256-word by 18-bit FIFO for high speed and fast LOCK UNCK
access times. It processes data at rates up to NC NC
50 MHz and access times of 15 ns in a bit-parallel NC NC
format. FULL
Oata is written into memory on a low-to-high
transition at the load clock (LOCK) input and is
read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of
words clocked in exceeds the number of words clocked out by 256. When the memory is full, LOCK signals have
no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and
aimost-fuil/aimost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the
memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF
output is high when the FIFO contains 128 or more words and is low when it contains 127 or less words. The
AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LOCK after reset are
used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN)
is low. The AF/AE flag is high when the FIFO contains X or less words or (256 - Y) or more words. The AF/AE
flag is low when the FIFO contains between (X + 1) and (255 - Y) words.

Widebus is a trademark of Texas Instruments Incorporated.

Copyright © 1995. Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8-15
SN74ACT7806
256 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS438A - APRIL 1992 - REVISED SEPTEMBER 1995

description (continued)
A low level on the reset (RESET) input resets the internal stack pOinters and sets FULL high, HF low, and
EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up.The
first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs. It is
important to note that the first word does not have to be unloaded. The data outputs are noninverting with respect
to the data inputs and are in the high-impedance state when the output-enable (OE) input is high.
The SN74ACT7806 is characterized for operation from O°C to 70°C.

logic symbolt

<l>
FIFO 256 x 18
SN74ACT7806
1 ,..,
RESET RESET
25 28
LOCK LOCK FULL FULL
22
32 HALF·FULL HF
UNCK UNCK 24
56 ALMOST FULUEMPTY AF/AE
OE
23 ",.., EN1
EMPTY
29
EMPTY
PEN
,
PROGRAM ENABLE
r
21 33
DO 0 0 QO
20 34
01 Q1
19 36
02 Q2
18 37
03 Q3
17 38
04 Q4
16 40
05 Q5
15 41
06 Q6
14 42
07 Q7
12 43
08 Q8

~ ~1V
11 45
09 Q9
9 46
010 Q10
8 47
011 Q11
7 48
012 Q12
6 49
013 Q13
5 51
014 Q14
4 53
015 Q15
3 54
016 Q16
2 55
017 17 17 Q17

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617·12.

~TEXAS
INSTRUMENTS
8-16 POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
 SN74ACT7806
256 x 18
STROBED FIRST·IN, FIRST·OUT MEMORY
SCAS438A - APRIL 1992 - REVISED SEPTEMBER 1995

functional block diagram

OE

J
00-017

Location 1
Read Location 2
UNCK Pointer
f-+---
256 x 18SRAM
T
Write I
LOCK
Pointer
~ r-- Location 255
Location 256

I .f'
1 QO-Q17

EMPTY
Reset
Logic t- Status-
Flag
FULL

Logic HF

AF/AE

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
Aimost-fuil/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value
AF/AE 24 0 of 32 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when
memory contains X or less words or (256 - Y) or more words. AF/AE is high after reset.
2-9,11-12,
DO-D17 I 18-bit data input port
12-14
Empty flag. EMPTY is high when the FIFO memory is not empty; EMPTY is low when the FI FO memory
EMPTY 29 0
is empty or upon assertion of RESET.
Full flag. FULL is high when the FIFO memory is not full or upon assertion of RESET; FULL is low when
FULL 28 0
the FIFO memory is full.
HF 22 0 Half-full flag. HF is high when the FIFO memory contains 128 or more words. HF is low after reset.
LDCK 25 I Load clock. Data is written to the FIFO on the rising edge of LOCK when FULL is high.
OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state.
Program enable. After reset and before the first word is written to the FIFO, the binary value on 00-06
PEN 23 I
is latched as an AF/AE offset value when PEN is low and WRTCLK is high.
33-34,36-38,
00-017 40-43,45-49, 0 18-bit data output port
51,53-55
RESET 1 I Reset. A low level on this input resets the FIFO and drives FULL high and HF and EMPTY low.
UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 8-17
SN74ACT7806
256 x 18
STROBED FIRST·IN, FIRST·OUT MEMORY
SCAS438A - APRIL 1992 - REVISED SEPTEMBER 1995

offset values for AF/AE

The aimost-fuil/aimost-empty flag has two programmable limits, the almost-empty offset value (X) and the
almost-full offset value (Y). They can be programmed after the FI FO is reset and before the first word is written
to memory. The AF/AE flag is high when the FIFO contains X or less words or (256 - Y) or more words.
To program the offset values, program enable (PEN) can be brought low after reset only when LOCK is low. On
the following low-to-high transition of LOCK, the binary value on 00-06 is stored as the almost-empty offset
value (X) and the almost-full offset value (Y). Holding PEN low for another low-to-high transition of LOCK
reprograms Y to the binary value on 00-06 at the time of the second LOCK low-to-high transition. Writes to
the FIFO memory are disabled while the offsets are programmed. A maximum value of 127 can be programmed
for either X or Y (see Figure 1). To use the default values of X = Y = 32, PEN must be held high.

RESET ~'-_ _ _- - ' /

LOCK

00-06 ~ XandY X~ Y~X __ _________

/
Figure 1. Programming X and Y Separately

~1ExAs
INSTRUMENTS
8-18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7806
256 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS438A - APRIL 1992 - REVISED SEPTEMBER 1995

_0 _0

:il
~ ;
..
?- -I
t'3 CI)
I.)
·c C
0
a ...
CI)

.!
CI)
II:

~- -N
Cl
c
'E
F
Cl
III
u::

~- -~
'tJ
C
III
.~ 'tf
III
CI)
j! II:
§
';:
3:
N
...
CI)
::::J
Cl
u:::

~>
,- 'C
II) C
~<U
mx
.!1!_
IL 0
w.,
C(.=!
it<U
c(>
.,=
,c'"
:.:: ... :.:: ... w ., .,
-s
Ii I~ I~
I~
IL
I.)
a c I.)
z 0 c(
it
J: ,sa
..J
0
I ~ I
15 c(
~~
a 8

'!11 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8-19
SN74ACT7806
256 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS438A - APRIL 1992 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, VI ........................................................................... 7 V
Voltage applied to a disabled 3-state output ................................... ,.............. 5.5 V
Operating free-air temperature range, TA ......................................... . . . .. O·C to 70·C
Storage temperature range, Tstg .................................................. -65·C to 150°C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings' only, and
functional operation of the device at these or any other condHions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated condHions for extended periods may affect device reliability.

recommended operating conditions

'ACT7806-20 'ACT7806-25 'ACT7806-40
UNIT
MIN MAX MIN MAX MIN MAX
VCC Supply voHage 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 V
IOH High-level output current Q outputs, Flags -8 -8 -8 mA
Q outputs 16 16 16
IOL Low-level output current mA
Flags 8 8 8
fclock Clock frequency 50 40 25 MHz
LOCK high or low 7 8 12
UNCK high or low 7 8 12
tw Pulse duration ns
PEN low 7 8 12
RESET low 10 10 12
00-017 before LOCKi 5 5 5
tsu Setup time PEN before LocKi 5 5 5 ns
LOCK inactive before RESET high 5 6 6
00-017 aiter LocKi 0 0 0
LOCK inactive aiter RESET high 5 6 6
th Hold time ns
PEN low aiter LocKi 3 3 3
PEN high aiter LOCK.!. 0 0 0
TA Operating free-air temperature 0 70 0 70 0 70 ·C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
VOH VCCm4.5V, IOHm-8mA 2.4 V
I Flags VCC=4.5V, IOL-8mA 0.5
VOL V
I Q outputs Vee=4.5V, IOL-16mA 0.5
II Vec=5.5V, VlaVceorO ±5 J1A
IOZ Vec- 5.5V, VO=VCe orO ±5 J1A
ICC Vee- 5.5V, VI = VCe-0.2VorO 400 J1A
alec§ Vec m5.5 V, One input at 3.4 V, Other inputs at Vce or GNO 1 mA
Ci VI=O, f-1 MHz 4 pF
Co VO=O, f= 1 MHz 8 pF
:j: All tYPical values are at Vce = 5 V, TA _ 25·e.
§ This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

~I 1ExAs
NSTRUMENTS
8-2.0 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ACT7806
256 x 18
STROBED FIRST·IN, FIRST·OUT MEMORY
SCAS438A - APRIL 1992 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figures 5 and 6)
FROM TO ' ACT7806-20 'ACT7806-25 ' ACT7806-40
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYpt MAX MIN MAX MIN MAX
fmax LDCKorUNCK 50 40 25 MHz
LDCKi 9 20 9 22 9 24
tpd
UNcKi AnyQ 6 11.5 15 6 18 6 20 ns
tpd:!: UNCK1' 10.5
tpLH LDCKi 6 15 6 17 6 19
UNCK1' EMPTY 6 15 6 17 6 19 ns
tPHL
RESET low 4 16 4 18 4 20
tpHL LDCKi 6 15 6 17 6 19
UNCK1' FULL 6 15 6 17 6 19 ns
tpLH
RESET low 4 18 4 20 4 22
LDCKi 7 18 7 20 7 22
lpd AF/AE 7 20 7 22 ns
UNCK1' 7 18
tpLH RESET low 2 10 2 12 2 14
tpLH LDCKi 5 18 5 20 5 22
UNCK1' HF 7 18 7 20 7 22 ns
tpHL
RESET low 3 12 3 14 3 16
ten 2 9 2 10 2 11
OE AnyQ ns
leIis 2 10 2 11 2 12
t All typical values are at VCC _ 5 V, TA - 25°C.
:!: This parameter is measured at CL • 30 pF (see Figure 3).

operating characteristics, Vee = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS
Power dissipation capacitance per FIFO channel Outputs enabled

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 8-21
SN74ACT7806
256 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS438A - APRIL 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME

vs
LOAD CAPACITANCE

VCC~SV
typ+ 8
~
r- TA=2SoC
RL = soon V
1/1
typ + 6 /
c
I
II>
/
E
i=
>- typ + 4
/
V
~c ./

i typ + 2 V
[ /
£I /
'1:1 typ
_D.
/
typ-2
I
o so 100 1S0 200 2S0 300
CL - Load Capacitance - pF

Figure 3

SUPPLY CURRENT
vs
CLOCK FREQUENCY
200 I
TA =7S0C
180 CL= OpF VCC= S.SV
/
V
160
~
E
I 140
VCC= V-.....". V- I/
~ 120 L ~ --""-
/ / /
:::I
(J
100
~
D.
:::I 80
/ / ~ VCC=4.SV
~ '/'"
Ul
I
s: 60
g 40 ~ '?/
20
0
,~p
o 10 20 30 40 SO 60 70
fclock - Clock Frequency - MHz

Figure 4

~1ExAs
INSTRUMENTS
8-22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7806
256 x 18
STROBED FIRST·IN, FIRST·OUT MEMORY
SCAS438A - APRIL 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

calculating power dissipation

With ICC(!) taken from Figure 4, the maximum power dissipation (PT) based on all data outputs changing states
on each read can be calculated by:
PT = Vcc x [lCC(!) + (N x ~Icc x dc)] + l:(CL x Vcc 2 x fo)
A more accurate power calculation based on device use and average number of data outputs switching can be
found by:
PT = Vcc x [ICC + (N x ~Icc x dc)] + l:(Cpd x Vcc 2 x fi) + l:(CL x Vcc 2 x fo)
where:
Icc power-down Icc maximum
N number of inputs driven by a TTL device
~ Icc increase in supply current
dc duty cycle of inputs at a TTL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
fi data input frequency
fo data output frequency

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 8-23
SN74ACT7806
256 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS438A-APRIL 1992- REVISED SEPTEMBER 1995

APPLICATION INFORMATION

SN74ACT7806
LOCK LOCK UNCK UNCK

FULL EMPTY --
~
I
OE
018-035 00-017 QO-Q17 Q18-Q35

SN74ACT7806
'--- P. LOCK UNCK

FULL EMPTY - f--

OE -
00-017 00-017 QO-Q17 QO-Q17

Figure 5. Word·Wldth Expansion: 256 Words by 36 Bits

~1ExAs
INSTRUMENTS
8-24 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7806
256 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS438A - APRIL 1992 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

L \ ~~---
=-r-l
Input 3V

Fr~~d~~~~! ~ I. GND

1T
RL=5000 CL=50pF
tpd -I'III"'_~~
I

I ,.----~_r_ - -
I
II1II
I
~ tpd

-- -- output_ _ _ _ ..,1 ~ ov
3V

LOAD CIRCUIT TOTEM-POLE OUTPUTS

Figure 6. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE)

, - - - - 3V

Input 1.5 V
I ~ ____ OV
7V tPZL--.I ~ I
I I ~ I+-
~
tPLZ
~3.5V
S1 RL = R1 = R2 ---hI II
Output I I _ _ :L
R1
- - . - - VOL
From Output
Under Test ----<.......................-
Test Point tPHZ +I I+- L 0.3 V

R2
~ l...:t __ VOH

outp ut _ _-J!1.5V ~V~OV

LOAD CIRCUIT VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES

PARAMETER R1, R2 CLf S1

tpZH Open
ten 5000 50pF
tpZL Closed
tpHZ Open
tdis 5000 50pF
tpLZ Closed
tpd 5000 50pF Open
t Includes probe and test-fixture capacitance
Figure 7. 3-State Outputs (Any Q)

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 8-25
8-26
 SN74ACT7804
512 x 18
STROBED FIRST FIRST·OUT MEMORY
1992 - REVISED SEPTEMBER 1995

• Member of the Texas Instruments DLPACKAGE

Wldebus ™ Family (TOP VIEW)

• load Clock and Unload Clock Can Be

Asynchronous or Coincident
RESET 1 OE
017 55 017
• 512 Words by 18 Bits 016 016
• low·Power Advanced CMOS Technology 015 015
• Full, Empty, and Half·Full Flags GNO
• Programmable Almost.FuIl/Almost·Empty 51 014
Flag 012 Vee
011 013
• Fast Access Times of 15 ns With a 50·pF 010 012
load and All Data Outputs Switching
Vee 47 011
Simultaneously
09 11 46 010
• Data Rates From 0 to 50 MHz 08 45 09
• 3-State Outputs GNO GNO
• Pin Compatible With SN74ACT7806 and 07 08
SN74ACT7814 06 07
• Packaged in Shrink Small·Outline 30Q-mll 05 06
(Dl) Package Using 25·mil Center·to·Center 04 05
Spacing 03 Vee
02 04
description 01 03
DO 02
A FIFO memory is a storage device that allows HF GNO
data to be written into and read from its array at PEN 01
independent data rates. The SN74ACT7804 is a AF/AE 00
512-word by 18-bit FIFO for high speed and fast LOCK UNCK
access times. It processes data at rates up to NC NC
50 MHz and access times of 15 ns in a bit-parallel NC NC
format. FULL EMPTY
Data is written into memory on a low-to-high
transition at the load-clock (LOCK) input and is Ne - No internal connection
read out on a low-to-high transition at the
unload-clock (UNCK) input. The memory is full
when the number of words clocked in exceeds the
number of words clocked out by 512. When the memory is full, LOCK signals have no effect on the data residing
in memory. When the memory is empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and
aimost-fuil/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the
memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF
output is high when the FIFO contains 256 or more words and is low when it contains 255 or less words. The
AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LOCK after reset are
used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN)
is low. The AF/AE flag. is high when the FIFO contains X or less words or (512 - Y) or more words. The AF/AE
flag is low when the FIFO contains between (X + 1) and (511 - Y) words.

Widebus is a trademark of Texas Instruments Incorporated.

Copyright ~ 1995, Texas Instruments Incorporated
~~C18~~~1:.\\'!.or,r~:.Is~~:,eu:~:':~m=
standard W8I'I1Inty. Production processing does not nectB88r11y Include
tesUng of all paramet.... ~TEXAS
INSTRUMENTS
POST OFFiCe BOX 655303 • DALLAS. TeXAS 75265 8-27
SN74ACT7804
512 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204A - APRIL 1992 - REVISED SEPTEMBER 1995

description (continued)
A low level on the reset (RESET) input resets the internal stack pointers and sets FULL high, AF/AE high, HF
low, and EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon
power up.
The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs.
It is important to note that the first word does not have to be unloaded. The data outputs are non inverting with
respect to the data inputs and are in the high-impedance state when the output-enable (OE) input is high.
The SN74ACT7804 is characterized for operation from O°C to 70°C.

logic symbolt

<I>
FIFO 512 x 18
SN74ACT7804
1 r--. RESET
RESET
25 28
LOCK LOCK FULL FULL
22
32 HALF·FULL HF
UNCK UNCK 24
56 ALMOST FULUEMPTY AF/AE
OE "- EN1 29
23 EMPTY EMPTY
PEN "- PROGRAM ENABLE

, r
21 33
DO 0 0 QO
20 34
01 Q1
19 36
02 Q2
18 37
03 Q3
17 38
04 Q4
16 40
05 Q5
15 41
06 Q6
14 42
07 Q7
12 43
08 Q8

~ ~1V
11 45
09 Q9
9 46
010 Q10
8 47
011 Q11
7 48
012 Q12
6 49
013 Q13
5 51
014 Q14
4 53
015 Q15
3 54
016 Q16
2 55
017 17 17 Q17

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617·12.

~TEXAS
INSTRUMENTS
8-28 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7804
512 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204A - APRIL 1992 - REVISED SEPTEMBER 1995

functional block diagram

OE

00-017

1
Location 1
Read Location 2
UNCK Pointer
f-+-
512 x 18 SRAM
r
Write I
LOCK
Pointer
~ r-- Location 511
Location 512

I ~f'
~ QO-Q17

EMPTY
Reset
Logic t- Status-
Flag
FULL

Logic HF
AF/AE

Terminal Functions
TERMINAL
110 DESCRIPTION
NAME NO.
Aimost-fuil/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value
AF/AE 24 0 of 64 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AFIAE is high when
memory contains X or less words or (512 - Y) or more words. AF/AE is high after reset.
2-9,11-12,
00-017 I 18-bit data input port
14-21
EMPTY 29 0 Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.
FULL 28 0 Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF 22 0 Half-full flag. HF is high when the FIFO memory contains 256 or more words. HF is low after reset.
LOCK 25 I Load clock. Data is written to the FIFO on the rising edge of LOCK when FULL is high.
OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state.
Program enable. After reset and before the first word is written to the FIFO, the binary value on 00-07
PEN 23 I
is latched as an AF/AE offset value when PEN is low and LOCK is high.
33-34,36-38,
00-017 40-43,45-49, 0 18-bit data output port
51.53-55
Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and EMPTY
RESET 1 I
low.
UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS. TeXAS 75265 8-29
SN74ACT7804
512 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204A - APRIL 1992 - REVISED SEPTEMBER 1995

offset values for AF/AE

The aimost-fuil/almost-empty flag has two programmable limits: the almost-empty offset value (X) and the
almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written
to memory. The AF/AE flag is high when the FIFO contains X or less words or (512 - Y) or more words.
To program the offset values, PEN can be brought low after reset only when LOCK is low. On the following
low-to-high transition of LOCK, the binary value on 00 -07 is stored as the almost-empty offset value (X) and
the almost-full offset value (Y). Holding PEN low for another low-to-high transition of LOCK reprograms Y to the
binary value on 00-07 at the time of the second LOCK low-to-high transition. Writes to the FIFO memory are
disabled while the offsets are programmed. A maximum value of 255 can be programmed for either X or Y
(see Figure 1). To use the default values of X =Y = 64, PEN must be held high.

RESET \ ' - -_ _ --1/

LOCK

00-07 ~ XandY X___ Y~X _________

/
Figure 1. Programming X and Y Separately

~TEXAS
INSTRUMENTS
8-30 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 RESET
LJ
PEN
o
LOCK

00-017

UNCK

1
---+4-------~--~--+_--4-4-----~---4----_4--------_T-------O
~
o
OE

~~~ QO-Q17

~~~d
at: EMPTY

~3: AF/AE

!~
~~
HF
~
::0
om
j FULL cn m
oC
~"11
"'-
~::o
OefinetheAF/AE Flag Using »0
the Default Value of X and Y ::'-;-1
"Il_
~Z
r_
Figure 2. Write, Read, and Flag Timing Reference <0"11
"'-
"'::0
~0
~-;-I
000 0
gJc: Z
f(l-l ~
:!l3: (J'I »
mm ..... o
~3:~-I
~OX ~
~ "'::0 ..... 0
~-<Q)ooIlo
SN74ACT7804
512 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204A - APRIL 1992 - REVISED SEPTEMBER 1995

absolute maximum ratings ov~r operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, VI ........................................................................... 7 V
Voltage applied to a disabled 3-state output ................................................... 5.5 V
Operating free-air temperature range, TA .............................................. ooe to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

'ACT7804-20 'ACT7804-25 'ACT7804-40
UNIT
MIN MAX MIN MAX MIN MAX
Vee Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 V
10H High-level output current o outputs, Flags -8 -8 -8 rnA

Low-level output current

o outputs 16 16 16
rnA
10L
Flags 8 8 8
fclock Clock frequency 50 40 25 MHz
LOCK high or low 7 8 12
UNCK high or low 7 8 12
tw Pulse duration ns
PEN low 7 8 12
RESET low 10 10 12
00-017 before LOCKi 5 5 5
tsu Setup time PEN before LOCKi 5 5 5 ns
LOCK inactive before RESET high 5 6 6
00-017 after LOCKi 0 0 0
LOCK inactive after RESET high 5 6 6
th Hold time ns
PEN low after LOCKi 3 3 3
PEN high after LOCK.!. 0 0 0
TA Operating free-air temperature 0 70 0 70 0 70 ·C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
VOH VCC=4.5V, 10H =-8mA 2.4 V
I Flags VCC=4.5 V, 10L = 8 rnA 0.5
V
VOL
JOoutputs VCC = 4.5 V, IOL=16mA 0.5
II VCC=5.5 V, VI = VCC orO ±5 JJA
10Z VCC =5.5 V, Vo=VCCorO ±5 JJA
ICC VCC=5.5 V, VI = VCC - 0.2 V or 0 400 JJA
t.ICC§ VCC=5.5V, One input at 3.4 V, Other inputs at VCC or GNO 1 rnA
Ci VI=O, f= 1 MHz 4 pF
Co VO=O, f = 1 MHz 8 pF
:j: All tYPical values are at VCC = 5 V, TA = 25°C.
§ This is the supply current for each input that is at one of the specified TIL voltage levels rather 0 V or VCC.

~1EXAS
INSTRUMENTS
8-32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7804
512 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204A - APRIL 1992 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figures 5 and 6)
FROM TO 'ACT7804-20 'ACT7804-25 ' ACT7804-40
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYPt MAX MIN MAX MIN MAX
fmax LOCKorUNCK 50 40 25 MHz
tpd LOCKi 9 20 9 22 9 24
tod UNCKi AnyQ 6 11.5 15 6 18 6 20 ns
tod:j: UNCKi 10.5
tpLH LOCKi 6 15 6 17 6 19
tpHL UNCKi EMPTY 6 15 6 17 6 19 ns
tpHL RESET low 4 16 4 18 4 20
tpHL LOCKi 6 15 6 17 6 19
tPLH UNCKi FULL 6 15 6 17 6 19 ns
tpLH RESET low 4 18 4 20 4 22
tod LOCKi 7 18 7 20 7 22

~d UNCKi AF/AE 7 18 7 20 7 22 ns
tpLH RESET low 2 10 2 12 2 14
tpLH LOCKi 5 18 5 20 5 22
tPHL UNCKi HF 7 18 7 20 7 22 ns
tpHL RESET low 3 12 3 14 3 16
ten 2 9 2 10 2 11
OE AnyQ ns
idis 2 10 2 11 2 12
t All typical values are at VCC = 5 V. TA = 25°C.
:j: This parameter is measured at CL = 30 pF (see Figure 3).

operating characteristics, Vee =5 V, TA =25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance per FI FO channel Outputs enabled CL = 50 pF. f = 5 MHz

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265 8-33
SN74ACTI804
512 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204A - APRIL 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME

vs
LOAD CAPACITANCE
typ+8
VCC~SV
- TA=2S"C
~
"
RL = 5000 ./
til typ+ 8
c
I
II V
! /
~ typ+4
I'
~ /
!V
II
'a
. .Q.
typ + 2

typ
/
V
/

/
typ-2
o so 100 150 200 250 300

CL - Load Capacitance - pF

Figure 3

SUPPLY CURRENT
vs
CLOCK FREQUENCY
200 I
TA=7SoC
180 CL=OpF VCc=s.SV
J j
I'
180
c(
E
I 140
VCc=SV~
V l/
I 120 / Y ./
0
~

100 / / /
~
Q. V/ :,/ VCC=4.SV
ri 80
I
80 h V
~ 40 ~~
20 ,. ~
0
o 10 20 30 40 SO 80 70
fclock - Clock Frequency - MHz

Figure 4

~1ExAs
INSTRUMENTS
8-34 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7804
512 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204A - APRIL 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

calculating power dissipation

With ICC(I) taken from Figure 4, the maximum power dissipation (PT) based on all data outputs changing states
on each read can be calculated by:
Pr = Vcc x [ICC(I) + (N x ~Icc x dc)] + :E(CL x VCc2 x fo)
A more accurate power calculation based on device use and average number of data outputs switching can be
found by:
PT = VCC x [Icc + (N x ~Icc x dc)] + :E(Cpd x Vcc2 x fi) + :E(CL x Vcc2 x fo)
where:
Icc power-down Icc maximum
N number of inputs driven by a TIL device
~ Icc increase in supply current
dc duty cycle of inputs at a TIL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
fl data input frequency
fo data output frequency

~1ExAs
INSTRUMENTS
POST OFFICE BOX _ . DALLAS, TEXAS 75265 1h'35
SN74ACT7804
512 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204A - APRIL 1992 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION

SN74ACT7804
LOCK LOCK UNCK UNCK

EMPTY
-.
FULL
~
OE
-
I

018-035 ." 00-017 QO-Q17 Q18-Q35

SN74ACT7804
'-- > LOCK UNCK

FULL EMPTY r- -

OE r-
00-017 / 00-017 QO-Q17 QO-Q17

Figure 5. Word·Wldth Expansion: 512 Words by 36 Bits

-!11 TEXAS
INSTRUMENTS
8-36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7804
512 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204A- APRIL 1992 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

Input L \ -;,~--- 3V
From Output
---11 I· GND
underTeet=Jl
RL=500n T CL=50pF
tpd -t~4--~~
I 14
I
~tpd
I

-=- ":" output_ _ _ _ JII,._---""\t---

~ OV
SV

LOAD CIRCUIT TOTEM·POLE OUTPUTS

Figure 6. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE)

, - - - - 3V
Input 1.5 V 1.5 V
I (l ____ OV
tpZL --.I j.- I
I I tPLZ -+t I+-
~
II -S.5V

Output I I __ :L 1.5V
R1
I --.- VOL
From Output - -.....-...4.-......- Test Point I tpHZ +l I+- L O.S V
Under Test
tPZH -+1.1+- ,..J
I __ I
R2
Output !. 1.5 V \- t::.
'-=- ;S V
~OV
VOH

LOAD CIRCUIT VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PARAMETER R1,R2 CLt S1

tpZH Open
ten 500n 50pF
tpZL Closed
tpHZ Open
!dis 500n 50pF
tpLZ Closed
Ipd 500n 50pF Open
t Includes probe and test-fixture capacitance
Figure 7. 3-State Outputs (Any Q)

~1ExAs
INSTRUMENTS
POST OFFICE BOX 665303 • DAllAS. TEXAS 75265 8-37
8-38
 SN74ABT7820
512x18x2
FIRST-OUT MEMORY
I 1995

• Member of the Texas Instruments • Programmable Almost-FuIl/Almost-Empty

Wldebus ™ Family Flags
• Independent Asynchronous Inputs and • Empty, Full, and Half-Full Flags
Outputs • Fast Access Times of 12 ns With a 50-pF
• Produced In Advanced BICMOS Load and Simultaneous Switching Data
Technology Outputs
• Two Separate 512 x 1S FIFOs Buffering • Supports Clock Rates up to 67 MHz
Data In Opposite Directions • Available in SO-Pin Quad Flat (PH) and
Space-Saving SO-Pin Thin Quad Flat (PN)
Packages
PH PACKAGE
(TOP VIEW)

RSTA RSTB
PENA PENB
AF/AEA AF/AEB
HFA HFB
FULLA FULLB
GND GND
AO BO
A1 B1
Vee Vee
A2 B2
A3 B3
GND GND
A4 B4
A5 B5
GND GND
A6 B6
A7 B7
GND GND
A8 B8
A9 B9
Vee Vee
A10 B10
A11 B11
GND GND

Widebus is a trademark of Texas Instruments Incorporated.

Copyright © 1995, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 8-39
SN74ABT7820
512x 18x2
STROBED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS206B - AUGUST 1991 - REVISED SEPTEMBER 1995

PNPACKAGE
(TOP VIEW)

AF/AEA 60 AF/AEB
HFA 2 59 HFB
FULLA 3 58 FULLB
GND 4 57 GND
AO 5 56 BO
A1 6 55 B1
Vee 7 54 Vee
A2 8 53 B2
A3 9 52 B3
GND 10 51 GND
A4 11 50 B4
A5 12 49 B5
GND 13 48 GND
A6 14 47 B6
A7 15 46 B7
GND 16 45 GND
A8 17 44 B8
A9 18 43 B9
Vee 19 42 Vee
A10 20 41 B10
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ABT782a is arranged as two 512 by 18-bit FIFOs for high speed and fast access times.
It processes data at rates from a to 67 MHz with access times of 12 ns in a bit-parallel format.
The SN74ABT7820 consists of bus-transceiver circuits, two 512 x 18 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs
(GAB and GBA) control the transceiver functions. The SAB and SBA control inputs select whether real-time or
stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight
fundamental bus-management functions that can be performed with the SN74ABT7820.
The SN74ABT7820 is characterized for operation from aoc to 7aoe.

~TEXAS
INSTRUMENTS
8-40 POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
 SN74ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206B- AUGUST 1991 - REVISED SEPTEMBER 1995

BusA .1II.iiii. BusB BusA BusB

SAB SBA GAB GBA SAB SBA GAB GBA

L X H L X X L L

BusA BusB BusA BusB

SAB SBA GAB GBA SAB SBA GAB GBA

X L L H H L H H

BusA BusB BusA BusB

SAB SBA GAB GBA SAB SBA GAB GBA

H X H L L H H H

BusA BusB
BusA
BusB

SAB SBA GAB GBA SAB SBA GAB GBA

X H L H H H H H

Figure 1. Bus-Management Functions

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 8-41
SN74ABT7820
512x18x2
STROBED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS206B- AUGUST 1991 - REVISED SEPTEMBER 1995

SELECT·MODE CONTROL TABLE

CONTROL OPERATION
SBA SAB A BUS BBUS
L L Real-time B to A bus Real-time A to B bus
H L FIFO B to A bus Real-time A to B bus
L H Real-time B to A bus FIFO A to B bus
H H FIFO B to A bus FIFO A to B bus

OUTPUT·ENABLE CONTROL TABLE

CONTROL OPERATION
GBA GAB A BUS BBUS
L L Isolationlinput to A bus Isolationlinput to B bus
H L A bus enabled Isolation/input to B bus
L H Isolation/input to A bus B bus enabled
H H A bus enabled B bus enabled

Figure 1. Bus-Management Functions (Continued)

~1ExAs
INSTRUMENTS
8-42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206B- AUGUST 1991 - REVISED SEPTEMBER 1995

logic symbolt

<l>
FIFO
66 512x18x2
SAB SN74ABT7820
79 :}MOOE
SBA
65
GAB EN1
80
GBA EN2
1 64
RSTA i'.
RESET A RESET B /I
RSTB
2 63
PENA
77
'" PROG ENA PROG ENB /I
68
PENB
LOCKA LOCKA LOCKB LOCKB
69 76
UNCKA UNCKA UNCKB UNCKB
5 60
FULLA FULLA FULLB FULLB
70 75
EMPTYA EMPTYA EMPTYB EMPTYB
3 ALMOST FULU ALMOST FULU 62
AF/AEA ALMOST EMPTY A ALMOST EMPTY B AF/AEB
4 61
HFA
,
HALF-FULL A HALF-FULL B
r
HFB

7 58
AO 0 0 BO
8 57
A1 B1
10 55
A2 B2
11 54
A3 B3
13 52
A4 B4
14 51
A5 B5
16 49
A6 B6
17 48
A7 B7
19 46
A8 B8
~ ~
20 45
A9 B9
22 43
A10 B10
23 42
A11 B11
25 40
A12 B12
26 39
A13 B13
28 37
A14 B14
29 36
A15 B15
31 34
A16 B16
32 33
A17 17 17 B17

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the PH package.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 8-43
SN74ABT7820
512 x 18 x 2
STROBEl) BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206B - AUGUST 1991 - REVISED SEPTEMBER 1995

logic diagram (positive logic)

SAB

SBA
1 I'...
Ln --/'

HFB
I in
- CIl
FIFOB RSTB
512 x 18
AF/AEB PENB

EMPTYB FULLB
UNCKB LDCKB
~

~l
~

GBA
Q [1) D BO
I
[2)
I
r I [3]
Ir-+ [4]
I
IL 1_of_18_Channels
!
_ _ _ _ _ _ _ ..1I ••
[15]
[16)
To Other Channels
[17]
[16)

GAB

CIl
I
RSTA FIFO A HFA
512 x 18 AF/AEA
PENA
FULLA EMPTYA
LDCKA
., UNCKA

AO D [1)
[2]
[3]
r
Q

ifgp4
i
i
I

L=__
[4]
•• I I I
[15] 1.~!.~~~J
[16)
To Other Channels
[17]
[18]

-!!11ExAs
INSTRUMENTS
8-44 POST OFFICE BO~ 655303- DAllAS. TEXAs 75265
 SN74ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206B - AUGUST 1991 - REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL 1/0 DESCRIPTION
AO-A17 1/0 Port-A data. The 18-bit bidirectional data port for side A.
FIFO A almost-fuIValmost-empty flag. Depth-offset values can be programmed for AF/AEA orthe default value of 128 can
AF/AEA 0 be used for both the almost-empty offset (Xl and the almost-full offset (Y). AF/AEA is high when FIFO A contains X or
less words or (512 - Y) or more words. AF/AEA is set high after FIFO A is reset.
FIFO B aimost-fuil/almost-emptyflag. Depth-offset values can be programmed for AF/AEB or the default value of 128 can
AF/AEB 0 be used for both the almost-empty offset (Xl and the almost-full offset (Yl. AF/AEB is high when FIFO B contains
X or less words or (512 - Y) or more words. AF/AEB is set high after FIFO B is reset.
BO-B17 I/O Port-B data. The 18-b~ bidirectional data port for side B.
FIFO A empty flag. EMPTYA is low when FIFO A is empty and high when FIFO A is not empty. EMPTYA is set low after
EMPTYA 0
FIFO A is reset.
FIFO B empty flag. EMPTYB is low when FIFO B is empty and high when FIFO B is not empty. EMPTYB is set low after
EMPTYB 0
FIFO B is reset.
FULLA 0 FIFO A full flag. FULLA is low when FIFO A is full and high when FIFO A is notfull. FULLA is set high after FIFO A is reset.
FULLB 0 FIFO B full flag. FULLB is low when FIFO B is full and high when FIFO B is notfull. FULLB is set high after FIFO B is reset.
GAB I Port-B output enable. BO-B17 outputs are active when GAB is high and in the high-impedance state when GAB is low.
GBA I Port-A output enable. AO-A 17 outputs are active when GBA is high and in the high-impedance state when GBA is low.
FIFO A half-full flag. HFA is high when FIFO A contains 256 or more words and is low when FIFO A contains 255 or less
HFA 0
words. HFA is set low after FIFO A is reset.
FIFO B half-full flag. HFB is high when FIFO B contains 256 or more words and is low when FIFO B contains 255 or less
HFB 0
words. HFB is set low after FIFO B is reset.
FIFO A load clock. Data is written into FIFO A on a low-to-high transition of LDCKA when FULLA is high. The first word
LOCKA I
written into an empty FIFO A is sent directly to the FIFO A data outputs.
FIFO B load clock. Data is written into FIFO B on a low-ta-high transition of LDCKB when FULLB is high. The first word
LDCKB I
written into an empty FIFO B is sent directly to the FIFO B data outputs.
FIFO A program enable. After reset and before a word is written into FIFO A, the binary value on AO-A7 is latched as
PENA I
an AF/AEA offset value when PENA is low and LOCKA is high.
FIFO B program enable. After reset and before a word is written into FIFO B, the binary value on BO-B7 is latched as
PENB I
an AF/AEB offset value when PENB is low and LDCKB is high.
RSTA I FIFO A reset. A low level on RSTA resets FIFO A forcing EMPTYA low, HFA low, FULLA high, and AF/AEA high.
RSTB I FIFO B reset. A low level on RSTB resets FIFO B forcing EMPTYB low, HFB low, FULLB high, and AF/AEB high.
Port-B read select. SAB selects the source of BO-B17 read data. A low level selects real-time data from AO-A17. A high
SAB I
level selects the FIFO A output.
Port-Aread select. SBA selects the source of AO-A17 read data. A low level selects real-time data from BO - B17. A high
SBA I
level selects the FI FO B output.
UNCKA I FIFO A unload clock. Data is read from FIFO A on a low-ta-high transition of UNCKA when EMPTYA is high.
UNCKB I FIFO B unload clock. Data is read from FIFO B on a low-ta-high transition of UNCKB when EMPTYB is high.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 8-45
 1!l en (TI en
I
0')
timing diagram for FIFO At >-t ..... Z
fg:xJN .....
:$OX -1:>0
~m_l>
RSTA ~ >mCDm
I ~OX ::::I
VimNCD
PENA I -i-
-0
N
0
o I ~ij

~J1J1~~i.----­
LOCKA 'm
ill 0
s-t
00-
mO
$+!Sl"'18~:~t~H ~¥.{c:~~
gz
AO-A17 ':ll>
irir-
I I I I I I s:"
00_
m:xJ
UNCKA 1IIIIInnnnn :!'en
@
o
I I I I I I Yc,...-..j L- 1 YH yH YT---1 ~-;-I
I I I I I I I I I I I Ji!!
1~4r QO-Q17 .oJool, ,
I WO:d1 I :
•
~~ -'R~ W«d~~(j
~ 129 130 257 258 ~~ ~
_ 1~:;:';a:dQ,
•
::!!
:xJ

l!i~~d
en
I -;t
eC
.7
JJ
I I I
I I
I I I
I I I I
I oc:
~~
EMPTYA I I I I I -t
I I I I 1--- 3:
m
~(jJ II WI
. .I II II II 3:
o
FULLA I I I I
~ ~
HFA
I
I
I
I
I
I
I
I
I
I
I
II I
I
I
I

AF/AEA
I
I
I
I
I
I
I .
I
II I
I
I
I
I I I
I I I
I I I
Set X = Y= 128 Empty + X Half-Full Full - Y Full Full - Y Half-Full Empty + X Empty

t SAB = GAB = H, GBA = L

Operation of FIFO B is identical to that of FIFO A.
 SN74ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS206B - AUGUST 1991 - REVISED SEPTEMBER 1995

offset values for AF/AE

The aimost-fuil/aimost-empty flag of each FIFO has two programmable limits: the almost-empty offset value (X)
and the almost-full offset value (Y). The offsets of a flag can be programmed from the input of its FIFO after it
is reset and before any data is written to its memory. An AF/AE flag is high when its FIFO contains X or less words
or (512 - Y) or more words.
To program the offset values for AF/AEA, program enable (PENA) can be brought low after FIFO A is reset and
only when LOCKA is low. On the following low-to-high transition of LOCKA, the binary value on AO-A7 is stored
as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PENA low for another
low-to-high transition of LOCKA reprograms Y to the binary value on AO-A7 at the time of the second LOCKA
low-to-high transition.
PENA can be brought back high only when LOCKA is low during the first two LOCKA cycles. PENA can be
brought high at any time after the second LOCKA pulse returns low. A maximum value of 255 can be
programmed for either X or Y (see Figure 2). To use the default values of X = Y = 128 for AF/AEA, PENA must
be tied high. No data is stored in the FIFO when its AF/AE offsets are programmed. The AF/AEB flag is
programmed in the same manner. PENB enables LOCKB to program the AF/AEB offset values taken from
BO-B7.

LOCKA

AO-A17 ~ XandY )(~____Y__-J)(~______w_or_d_1______

EMPTYA ~ /
Figure 2. Programming X and Y Separately for AF/AEA

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS. TeXAS 75265 8-47
SN74ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206B- AUGUST 1991 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Voltage range applied to any output in the high state or power-off state, Vo ............. -0.5 V to 5.5 V
Current into any output in the low state, 10 .....•.•.•...........•..•......••...........••... 48 rnA
Input clamp current, 11K (VI < 0) .......................................................... -18 rnA
Output clamp current, 10K (Vo < 0) ....................................................... -50 rnA
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 4.5 5.5 V
VIH High-level input voltage 2 V
Vil low-level input voltage 0.8 V
VI Input voltage 0 VCC V
10H High-level output current -12 mA
10l lOW-level output current 24 mA
At/tN Input transition rise or fall rate 5 ns/V
TA Operating free-air temperature 0 70 ·C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
VIK VCC=4.5V, 11=-18mA -1.2 V
VCC=4.5V, IOH=-3mA 2.5
VOH VCC=5V, 10H --3 mA 3 V
VCC=4.5V, IOH=-12mA 2
VOL VCC=4.5V, 10l= 24 mA 0.55 V
II VCC=5.5V, VI = VCC or GND ±5 IIA
10lH§ VCC= 5.5 V, Vo = 2.7 V 50 IIA
10ll§ VCC-5.5V, VO= 0.5V -50 IIA
1011 VCC =5.5 V, Vo = 2.5 V -40 -100 -180 mA
Outputs high 15
ICC VCC = 5.5 V, 10=0, VI = VCC or GND Outputs low 95 mA
Outputs disabled 15
Ci Control inputs VI = 2.5 V or 0.5 V 6 pF
Co Flags Vo = 2.5 V or 0.5 V 4 pF
Cio A or B ports Vo = 2.5 V or 0.5 V 8 pF
:j: All tYPical values are at VCC = 5 V, TA = 25·C.
§ The parameters 10lH and lOll include the input leakage current.
11 Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

~1ExAs
INSTRUMENTS
8-48 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206B - AUGUST 1991 - REVISED SEPTEMBER 1995

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
'ABT7820-15 'ABT7820-20 'ABT7820-25 'ABT7820-30
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 67 50 40 33 MHz
LOCKA, LOCKB high 4 6 9 11
LOCKA, LOCKB low 4 6 9 11
Pulse
tw UNCKA, UNCKB high 4 6 9 11 ns
duration
UNCKA, UNCKB low 4 6 9 11
RSTA, RSTB low 6 8 10 12
AO-A17 before LOCKAt and
3 4 4 4
BO-B17 before LOCKBt
PENA before LOCKA t and
5 5 5 5
tsu Setup time PENB before LOCKBt ns
LOCKA inactive before RSTA high
and LOCKB inactive before RSTB 3 3 4 4
high
AO-A17 after LOCKAt and
0 0 0 0
BO-B17 after LOCKBt
PENA after LOCKA low and
th Hold time 2 2 2 2 ns
PENB after LOCKB low
LOCKA inactive after RSTA high and
3 3 4 4
LOCKB inactive after RSTB high

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8-49
SN74ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS206B-AUGUST 1991- REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 5)
FROM TO 'ACT782()"15 'ACT782()"20 'ACT782()"25 'ACT7820-30
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYPt MAX MIN MAX MIN MAX MIN MAX
f max LOCK, UNCK 67 50 40 33.3 MHz
LOCKAi,
4 14 4 15 4 18 4 20
LOCKBi
tpd BfA ns
UNCKAi,
4 9 12 4 13.5 4 15 4 17
UNCKBi
UNCKAi,
tpd:j: BfA 8 ns
UNCKBi
LOCKAi,
tpLH 4 14 4 15 4 17 4 19
LOCKBi EMPTYA,
ns
UNCKAi, EMPTYB
tpHL 4 13 4 14 4 16 4 18
UNCKBi
RSTA low, EMPTYA,
tpHL 6 16 6 16 6 18 6 20 ns
RSTB low EMPTYB
LOCKAi, FULLA,
tpHL 6 13 6 14 6 16 6 18 ns
LOCKBi FULLB
UNCKAi,
6 15 6 15 6 17 6 19
UNCKBi FULLA,
tPLH ns
RSTAlow, FULLB
8 20 8 20 8 22 8 22
RSTBlow
LOCKAi,
8 16 8 17 8 18 8 20
LOCKBi AFfAEA,
tpd ns
UNCKAi, AFfAEB
8 16 8 17 8 18 8 20
UNCKBi
RSTAlow, AFfAEA,
tpLH 2 12 2 14 2 16 2 18 ns
RSTB low AFfAEB
LOCKAi,
tpLH HFA, HFB 8 15 8 15 8 17 8 19 ns
LOCKBi
UNCKA, UNCKB 8 15 8 15 8 17 8 19
tpHL RSTA low, HFA, HFB ns
2 12 2 14 2 16 2 18
RSTBlow
SABfSBA§ 2 10 2 11 2 12 2 14
tpd BfA ns
NB 2 9 2 10 2 11 2 13
ten GBNGAB NB 2 6.5 2 8 2 10 2 12 ns
tdis GBNGAB NB 2 11 2 12 2 13 2 14 ns
t All tYPical values are at 5 V. TA = 25'C.
:j: This parameter is measured with a 30-pF load (see Figure 3).
§ These parameters are measured with the internal output state of the storage register opposite to that of the bus input.

~TEXAS
INSTRUMENTS
8-50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT7820
512x 18x2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS208B - AUGUST 1991 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS
PROPAGATION DELAY nME
VB
LOAD CAPACITANCE

VCC~5V
typ+8 ,... TA = 25°C

.
c:
RL=500C
/
I
I
typ+4
/
1=
l'
~
c:
0 typ+2
./
,/
/
"
~/
Ie
Go /
I
typ

..1. V
/
typ-2
o 50 100 150 200 250 300
CL - Load Capacitance - pF

Figure 3

SUPPLY CURRENT
VB
CLOCK FREQUENCY
180
TA=75°C I . I J_ V
CL=OpF YCc=5.5V /
140

/
V ./V
1 120

~
a
I

100
VCC=5Y

v
,/V ,/V , /
> V ./V" , /V
~
b
8:
8J
80 ,
./ ~
I V , / VYCC =4.5Y
s: 80
8
40
~~ ,/
20
10 15 20 25 30 35 40 45 50 65 80 85 70

'clock - Clock Frequency - MHz

Figure 4

:lllExAs
INSTRUMENTS
POST OFFICE BOX 8155303 • DAU.t.S. TEXAS 76265 8-51
SN74ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS206B - AUGUST 1991 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

calculating power dissipation

With ICC(!) taken from Figure 4, the maximum power dissipation (PT) based on all outputs changing states on
each read can be calculated by:
PT = Vec x IcC(!) + L(CL x Vcc2 x fa)
where:
ICC(!) maximum Icc per clock frequency
CL output capacitive load
fa data output frequency

PARAMETER MEASUREMENT INFORMATION

3V
\~5~--------

7V
Input ~1.5V
OV

~
1 1
I
S1 Rl =R1 =R2 tPZl-'1
1
1..-
1
-.1
1
i..- tPlZ

t
Output 1 ~3.5V
1 1
1 1 . - O.3V
From Output Test Point 1 \1.5V
Under Test I -- VOL
1
I. tPHZ
1
-+i
--f---
1"-

r,v
1
tPZH -+i 1.....- 1 J_
_____

~------
.J O.3V
VOH

Output ~OV
-=
VOLTAGE WAVEFORMS
lOAD CIRCUIT ENABLE AND DISABLE TIMES

PARAMETER R1, R2 clt S1

ten ~ 5000 50pF

Open
tpZL Closed

tdis ~ 5000 50 pF
Open
tpLZ Closed
tpd 5000 50 pF Open
t Includes probe and test-lixture capacitance
Figure 5. Load Circuit and Voltage Waveforms

'INSTRUMENTS
!!1 TEXAS
8-52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7802
1024 x 18
FIRST-OUT MEMORY
- REVISED SEPTEMBER 1995

• Load and Unload Clocks Can Be • Fast Access Times of 30 ns With a So-pF
Asynchronous or Coincident Load
• Low-Power Advanced CMOS Technology • Fall-Through Time Is 20 ns Typical
• 1024 Words x 1S Bits • Data Rates From 0 to 40 MHz
• Programmable Almost-FuIl/Almost-Empty • High-Output Drive for Direct Bus Interface
Flag • 3-State Outputs
• Empty, Full, and Half-Full Flags • Available in S8-Pin PLCC (FN) and SO-Pin
Thin Quad Flat (PN) Packages
FNPACKAGE
(TOP VIEW)

o 0 ~en 00 D. Or-.
~ ~ ~ Z zoo w w OZ:::i: __ltu
CD 0 10
z_ I~
ccc~~ZZO~>~w~oo~o
9 8 7 6 5 4 3 2 1 68 67 66 65 64 6362 61
014 10 60 Vee
013 11 59 Q14
012 12 58 Q13
011 13 57 GNO
010 14 56 Q12
09 15 55 Q11
Vee 16 54 Vee
08 17 53 Q10
GNO 18 52 Q9
07 19 51 GNO
06 20 50 Q8
05 21 49 Q7
04 22 48 Vee
03 23 47 Q6
02 24 46 Q5
01 25 45 GNO
00 26 44 Q4
~~~~~~~M~~~~$~M~a

I~ ~ 5 ~ ~ ~~~~
o~o ..J
o~ ~I::I ~ ~
« LL
08 & ~
~
a8~ 0

Ne - No Internal connection

Copyright C 1995. Texas Instruments InCOlpOraled

:illEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN74ACT7802
1024 x 18
STROBED FIRST·IN, FIRST·OUT MEMORY
SCAS187B - AUGUST 1990 - REVISED SEPTEMBER 1995

PNPACKAGE
(TOP VIEW)
Lt)()'<tC'?OOC\l~()O 0 () 00
~ () ~ ~ Z Z ~ ~ ()~ 0) Z CO I'- ()!Q Lt) Z Z "!t
a>aa~~aa>aa~aa>oa~~o

oo~~n~ro~~nnrooo~~~~Mro~~

NC 1 • 60 Vee
GNO 2 59 Vee
GNO 3 58 NC
016 4 57 03
017 5 56 02
Vec 6 55 GNO
EMPTY 7 54 01
GNO 8 53 00
Vce 9 52 Vee
RESET 10 51 HF
OE 11 50 FULL
NC 12 49 GNO
NC 13 48 GNO
UNCK 14 47 AF/AE
GNO 15 46 Vee
017 16 45 NC
016 17 44 NC
015 18 43 LOCK
NC 19 42 GNO
NC 20 41 NC
21 222324 25 26 2728 29 30 31 32 33 3435 36 37 38 39 40
() '<t C'? C\I ~ 0
z~~~""~O()OzOOOooooo<z
0) () co 0 r-- (!) Lt) '<t C'? C\I .... 01Ll. ()
00000 > ~ 0

NC - No internal connection

description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7802 is a 1024-word by 18-bit FIFO for high-speed applications. It processes data
in a bit-parallel format at rates up to 40 MHz and access times of 30 ns.
Oata is written into the FIFO memory on a low-to-high transition on the load-clock (LOCK) input and is read out
on a low-to-high transition on the unload-clock (UNCK) input. The memory is full when the number of words
clocked in exceeds by 1024 the number of words clocked out. When the memory is full, LOCK has no effect on
the data in the memory; when the memory is empty, UNCK has no effect.
A low level on the reset (RESED input resets the FIFO internal clock stack pointers and sets FULL high, AF/AE
high, HF low, and EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset
upon power up. The Q outputs are noninverting and are in the high-impedance state when the output-enable
(OE) input is low.
When writing to the FIFO after a reset pulse or when the FIFO is empty, the first active transition on LOCK drives
EMPTY high and causes the first word written to the FIFO to appear on the Q outputs. An active transition on
UNCK is not required to read the first word written to the FIFO. Each subsequent read from the FIFO requires
an active transition on UNCK.
The SN74ACT7802 can be cascaded in the word-width direction but not in the word-depth direction.
The SN74ACT7802 is characterized for operation from O°C to 70°C.

~TEXAS
INSTRUMENTS
8-54 POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
 SN74ACT7802
1024 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187B - AUGUST 1990 - REVISED SEPTEMBER 1995

logic symbolt

<I>
FIFO 1024 x 18
SN74ACT7802
1 r-.. RESET
RESET
29 35
LOCK LOCK FULL FULL
5 36
UNCK UNCK HALF FULL HF
33
2 ALMOST FULUEMPTY AF/AE
OE EN1 66
27 r-.. EMPTY EMPTY
OAF
, OEF ALMOST FULL
r
26 38
DO 0 0 QO
25 39
01 Q1
24 41
02 Q2
23 42
03 Q3
22 44
04 Q4
21 46
05 Q5
20 47
06 Q6
19 49
07 Q7
17 50
08 Q8
09
15
~ ~1V 52
Q9
14 53
010 Q10
13 55
011 Q11
12 56
012 Q12
11 58
013 Q13
10 59
014 Q14
9 61
015 Q15
8 63
016 Q16
7 64
017 17 17 Q17

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the FN package.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 8-55
SN74ACT7802
1024 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187B - AUGUST 1990 - REVISED SEPTEMBER 1995

functional block diagram

OE

DO-D17

{;
LDCK Write
Control
~ ... ~
I Read I
Pointer I
I
/
location 1
Location 2

I Write : 1024 x 18 RAM

UNCK Reed I Pointer I
Control - I--
Location 1023
Location 1024

.1"'-
Reset
t-
I 1 QO-Q17

Logic Stetua-
I
Flag EMPTY
Logic PULL
HF
AF/AE

Terminal Functions
TERMINAL
110 DESCRIPTION
NAME NO.t
Almost-fuIValmost-empty flag. Oepth-<lffset values can be programmed for AF/AE, or the default value
AF/AE 33 0 of 256 can be used for the a1most-empty almost-full offset (Xl. AF1AE Is high when memory contains X
or less words or (1024 - Xl or more words. AF/AE is high after reset.
Oefine almost full flag. The high-to-Iow transition of W stores the binary value of data Inputs as
OAF 27 I the almost-fuIValmost-empty offset value (Xl. With OAF held low, a low pulse on RESET defines AF1AE
usingX. I

7-15,17,
00-017 I lS-bit date input port
19-26
EMPTY 66 0 Empty flag. EMffi is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.
FULL 35 0 Full flag. FULL is low when the FIFO is fUll. A FIFO reset causes FULL to 90 high.
HF 36 0 Half-full flag. HF is high when the FIFO memory contains 512 or more words. HF is low after reset.
LOCK 29 I Load clock. Data is written to the FIFO on the rising edge of LOCK when FULL is high.
OE 2 I Output enable. When OE is low, the data outputs are in the high-impedance stele.
38-39,41-42,
44,46-47,
00-017 49-50,52-53, 0 18-bit data output port
55-56, 58-59,
61,63-64
RESET Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and EMPTY
1 I
low.
UNCK 5 I Unload clock. Oata is read from the FIFO on the rising edge of UNCK when EMffi is high.
,
t Pin numbers shown are for the FN package.

~1EXAS
INSTRUMENTS
8-66 POST OFFICE SOX 665303 • DALlAS. TEXAS 75265
 SN74ACT7802
1024 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCASI87B - AUGUST 1990 - REVISED SEPTEMBER 1995

offset value values for AF/AE

The FIFO memory status is monitored ~the full (FULL), empty (EMPTY), half-full (HF), and
aimost-fuli/aimost-empty (AF/AE) flags. The FULL output is low when the memory is full; the EMPTY output is
low when the memory is empty. The HF output is high when the memory contains 512 or more words and low
when it contains less than 512 words. The level of the AF/AE flag is determined by both the number of words
in the FIFO and a user-definable offset X. AF/AE is high when the FIFO is almost full or almost empty, i.e., when
it contains X or less words or (1024 - X) or more words. The aimost-fuli/aimost-empty offset value is either
user-defined or the default value of 256; it is programmed during each reset cycle as follows:
user-defined X:
Take OAF from high to low.
If RESET is not already low, take RESET low.
With OAF held low, take RESET high. This defines the AF/AE flag using X.
default X:
To redefine the AF/AE flag using the default value of X =256, hold OAF high during the reset cycle.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 8-57
 en ....... en
~
C/l
~-I°Z
0> ~:DI\) .....
~Ool:oool:oo
I RESET --u I
u-
I
"'m X
::.m . . . . O»
~ c (Ie):::I
OAF
l: ~o0!1'tcare~1 ~
C
~-
~:D
lSen
-n (Ie)
0
I\)
LOCK
---L-+-fl-t4rfl;rfl;~~ : ';"-;-1
::D-
mZ
~lx$~1RSaW2~+2.~pon't,9!r?,~
<-
00-017 ffl:!!
0:D
men
UNCK II I I I I~_ n _ n_ n.- nn! ~-;-I
I I \----f '""-\r--t &.....\~ L.....4r---' "'-1 L-.J-
I I I ! !2o
I I , " I! me:
"
~
• OE
I I
I:
I
r-T
I I
--r i 1--- I - i i ::D-I
ih:
---+-\1~ ~$$$SED......;--
"'m
~- oo-Q17

E~~ I : W1:
I : 3:
o
~ EMPTY ~II I I I I 1--+_
..... ~

,~~
~-::L..+I-'. I I I I

I
AF/AE 2a I : 1 I I -----I- I-
I I--____~~I------~
~~
!J> I HF 3a I
I
I :

~
[\i
I FULL ZllI U
en
I
Define the AFIAE Offset Value (X) Define the AF/AE Offset value (Xl
Using the Data on DO - 08 Using the Default Value of 256

Figure 2. Write, Read, and Flag Timing Reference

 SN74ACT7802
1024 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187B - AUGUST 1990 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, VI ............................................................................. 7 V
Voltage applied to a disabled 3-state output .................................................. , 5.5 V
Operating free-air temperature range, TA ............................................... ooe to 70°C
Storage temperature range, Tstg .................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

'ACT7802-25 'ACT7802-40 'ACT7802-60
UNIT
MIN MAX MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 V
IOH High-level output current -8 -8 -8 mA
IOL Low-level output current 16 16 16 mA
fclock Clock frequency 40 25 16.7 MHz
LOCK high or low 10 14 20
UNCK high or low 10 14 20
tw Pulse duration ns
OAF high 10 10 10
RESET low 20 25 25
00-07 before LDCKi 4 5 5
RESET inactive (high) before LDCKi 5 5 5
tsu Setup time Define AF/AE: 00-08 before OAF.!, 5 5 5 ns
Define AF/AE: OAF.!, before RESETi 7 7 7
Define AF/AE (default): OAF high before RESETi 5 5 5
00-07 after LDCKi 1 2 2
Define AF/AE: 00-08 after OAF.!, 0 0 0
th Hold time ns
Define AF/AE: OAF low after RESETi 0 0 0
Define AF/AE (default): OAF high after RESETi 0 0 0
TA Operating free-air temperature 0 70 0 70 0 70 ·C

~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 8-59
SN74ACT7802
1024 x 18
STROBED FIRST·IN, FIRST·OUT MEMORY
SCAS187B - AUGUST 1990 - REVISED SEPTEMBER 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VOH VCC = 4.5 V, IOH=~8mA 2.4 V
VOL VCC=4.5V, IOL=16mA 0.5 V
II VCC-5.5V, VI-VccorO ±5 IlA
10Z VCC = 5.5 V, Vo=VccorO ±5 IlA
ICCt VI = VCC - 0.2 V or 0 400 IlA
dICC:!: Vcc = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1 mA
Ci VI =0, 1-1 MHz 4 pF
Co VO=O, 1= 1 MHz 8 pF
t All typical values are at VCC = 5 V, TA = 25°C.
t ICC tested with outputs open

switching characteristics over recommended ranges of supply voltage and operating free·air
temperature, CL = 50 pF (see Figures 4 and 5)
FROM TO 'ACT7802·25 'ACT7802·40 'ACT7802·60
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYpt MAX MIN MAX MIN MAX
Imax LDCKorUNCK 40 25 16.7 MHz
tpd LDCKi AnyQ 8 20 30 8 35 8 45 ns
too UNCKi AnyQ 12 30 12 35 12 45 ns
tpd§ UNCKi AnyQ 21 ns
tpLH LDCKi 4 18 4 20 4 22
EMPTY ns
tPHL UNCKi 2 18 2 20 2 22
tpHL RESET.!. EMPTY 2 18 2 20 2 22 ns
tpHL LDCKi FULL 4· 18 4 20 4 22 ns
UNCKi 4 17 4 19 4 21
tpLH FULL ns
RESET.!. 2 17 2 19 2 21
LDCKi 2 20 2 22 2 24
tpd AF/AE ns
UNCKi 2 20 2 22 2 24
tpLH RESET.!. AF/AE 2 17 2 19 2 21 ns
tpLH LDCKi HF 2 18 2 20 2 22 ns
UNCKi 2 18 2 20 2 22
tpHL HF ns
RESET.!. 2 17 2 19 2 21
ten OE AnyQ 2 12 2 14 2 16 ns
tdis OE AnyQ 2 14 2 16 2 18 ns
t All tYPical values are at VCC = 5 V, TA _ 25°C.
§ This parameter is measured with CL = 30 pF (see Figure 1).

operating characteristics, Vee =5 V, TA =25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitancer per channel CL = 50 pF, I = 5 MHz

~1ExAs
INSTRUMENTS
8-60 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT7802
1024 x 18
STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187B - AUGUST 1990 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
typ+8
VCC=5V ....
..
c typ+6
RL=500n
TA=25°C /
I
GI
V
E ./
i=
/
f
c
typ+4
/
i typ+2
V
[
2
Do.
/
I
V
J typ
/
typ-2
I
o 50 100 150 200 250 300

CL - Load capacitance - pF

Figure 1

POWER DISSIPATION CAPACITANCE

vs
SUPPLY VOLTAGE
typ + 3
II.
a. f=15M~Z
I TA = 25°C /
8c typ+2 I-CL=50pF
:g
/
V
! typ+1
B
c
0
/
V
= typ
i
c
typ-1
/
/
JI
typ-2
V
/'
"
8" V
typ-3
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5

VCC - Supply Voltage - V

Figure 2

-!!11EXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265 !Hl1
SN74ACT7802
1024 x 18
STROBED FIRST-IN, FIRST·OUT MEMORY
SCAS187B - AUGUST 1990 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

calculating power dissipation

The maximum power dissipation (PT) of the SN74ACT7802 can be calculated by:
Pr = Vee x [lee + (N x ~Iee x dc)] + :E(Cpd x Vee2 x fi) + :E(CL x Vee2 x fo)
where:
lee power-down lee maximum
N number of inputs driven by a TIL device
~ lee increase in supply current
dc duty cycle of inputs at a TIL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
fj data input frequency
fo data output frequency

~TEXAS
INSTRUMENTS
8-62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT7802
1024 x 18
STROBED FIRST·IN, FIRST·OUT MEMORY
SCAS187B - AUGUST 1990 - REVISED SEPTEMBER 1995

APPLICATION INFORMATION

SN74ACT7802
LOCK LOCK UNCK UNCK

---
J----,
FULL EMPTY

OE
--
I
OE

018-035 00-017 QO-Q17 Q18-Q35

SN74ACT7802
- LOCK UNCK

EMPTY - I--
FULL
OE -
00-017 '-J 00-017 QO-Q17 QO-Q17

Figure 3. Word-Width Expansion: 1024 Word by 36 Bit

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265 !HI3
SN74ACT7802
1024 x 18
STROBED FIRST-IN, FIRST·OUT MEMORY
SCAS187B - AUGUST 1990 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

Input.L \ ~~--- 3V
From o u t p u t = n ~ I. GND
Under Test

RL=500n T tpd -oIII14f--~~

I
I
lOIII
I
~ tpd
I
I

Output I I ,.------.~T - -
1.5 V
3V

-----' OV

LOAD CIRCUIT TOTEM·POLE OUTPUTS

Figure 4. Standard CMOS Outputs (FULL, AF/AE, EMPTY)

7V -------- 3V

6 Input ~1.5V \1.5V

RL = Rl = R2 SI
ov
1 1
tpzL ....1 I.- .... 1 *-tPLZ
1
I 1 I ~3.5V

K~~~~
Rl 1
1
From Output Test Output \1.5V 1
1
Under Test Point 1 VOL
1
tPHZ -+I I+- t
t----'-
1
CL tpZH -+I I+- I
R2

Output 11.5V
----3 VOH
O.3V
~ov

-= VOLTAGE WAVEFORMS
LOAD CIRCUIT ENABLE AND DISABLE TIMES

PARAMETER Rl, R2 cLt SI

tPZH Open
ten 500n 50pF
tpZL Closed
tPHZ Open
!dis 500n 50 pF
tpLZ Closed
tod 500n 50 pF Open
t Includes probe and test·fixture capacitance
Figure 5. 3·State Outputs (Any Q)

~ThxAS
INSTRUMENTS
8-64 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
I Multi-Q™18-Bit FIFO

9-1
 MULTI-QTM 18·BIT FIFO
Features Benefits

• Three programmable FIFOs on one • Permits user to define each FIFO queue
device. Depths range from 256 to 4K depth for quality of service (OOS)
words.
• Synchronous multiplexer for queue output • Allows user to easily select desired output
selections
• Cell-ready flag for each queue • Indicates minimum of one complete cell
synchronized to read clock available for reads
• Three programmable-cell flags • Allows user to choose each cell-status
indicator
• Programmable-cell size for each queue • Allows user to define from 10 to 32 l8-bit
words for cell
• Clocked interface • Read and write enables synchronized to
continuous clock signal
• Separate programming/diagnostic bus • Allows separate bus for programming
required parameters as well as allowing a
direct path into each cell for diagnostics
• Input and output start of cell indicator • Ensures cell alignment for writes and
III
s:: • O.8-J.1m CMOS process •
reads
Fast access times combined with low
c power
;::;:
I' • EIAJ standard 100-pin thin quad flat • Fine-pitch package option for reduced
~ package (TOFP) board space
-'"
cp
D:J
=t:
-o
."
."

9-2
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE-QUEUE (MULTI-QTM) FIRST-IN, FIRST-OUT MEMORY
WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS
SCAS443A - JUNE 1994 - REVISED JULY 1995

• 4096 x 18 Total Memory Size • Programmable Flag With Hysteresis for

• Three Programmable-Depth FIFOs on One Each Queue Synchronized to Write Clock
Device • Last Word of Cell Flag Synchronized to
• Memory Allocation of 256 x 18 Blocks Read Clock
• Two Separate Read and Write Clocks • Input or Output Bus Size of 9 Bits or
That Can Operate Synchronously or 18 Bits, Byte StufflDestuff Capability
Asynch ronously • Data Access Times of 11 ns
• Clocked Interface; Read and Write Enables • Synchronous Multiplexer for Queue Output
Synchronize Data Transfers to Continuous Selection
Clocks • 8-bit Bidirectional Programming Port
• Programmable Cell Size From 10 to 32 • Clock Frequencies up to 50 MHz
18-Bit Words
• Produced in 0.8-~m Advanced CMOS
• Cell-Abort Feature to Discard a Previous Technology
Cell Write
• Available in 100-Pin Thin Quad Flat (PZ)
• Cell-Ready Flag for Each Queue Package
Synchronized to Read Clock

description
The Multi-Q FIFO is a first-in, first-out (FIFO) memory with three programmable-length queues and a total
~
W
memory size of 4096 words of 18 bits each to provide two or three quality of service (QOS) bins for ATM traffic
in a single device. The core memory is divided into sixteen 256 x 18 blocks that can be allocated to each queue
:;
according to the user's need. w
a:
Flags for the queues are designed to indicate the presence or absence of entire cells rather than individual
words. The number of 18-bit words that constitutes one cell is programmable by the user and has a default value
a.
of 27. A cell-ready (CR) flag for a queue is high when at least one complete cell is present in the queue. Each I-
CR flag is synchronized to the read clock (RDCLK). The full flag (FF) for each queue is synchronized to the write o
clock (WRTCLK) and indicates when no more cells can be written to the queue. A programmable flag (PF) is ::l
provided for each queue, which is synchronized to the WRTCLK. Each PF has two programmable values. PF C
is low when the number of cells in the queue are greater than or equal to the first limit, and it is set high when
the number of cells in the queue are reduced to the second limit. This allows the user to define a hysteresis
oa:
threshold for the flag if it is needed. a.
WRTCLK and RDCLK are designed to be free-running clock inputs to maintain the proper synchronization of
the flags. The clocks are synchronized or asynchronous in phase, frequency, or both. Writes to one of the three
queues is done by a rising edge of WRTCLK when the queue's write enable (WRTEN) is high. Any write can
be done to two or three olthe queues simply by asserting two or three olthe WRTEN inputs for a WRTCLK rising
edge. Data is read from a queue by the rising edge of RDCLK when the queue is selected by the multiplexer
(MUXO, MUX1) inputs and the read enable (RDEN) is high. Configuration registers can be programmed to set
the input or output port sizes to 9 bits or 18 bits. Big- or little-end ian data format can be selected for the buses.
When matching 9-bit buses to 18-bit or 36-bit buses with the Multi-Q, byte stuffing can be selected for the data
input and byte destuffing can be done on the data output.

Multi-Q is a trademark of Texas Instruments Incorporated.

PRODUCT PREVIEW Information concerns products In the formative or Copyright © 1995, Texas Instruments Incorporated

~TEXAS
design phase of development Charactetlstlc data and other
specltlcatlons are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9-3
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE-QUEUE (MULTI-QTM) FIRST-IN, FIRST.;OUT MEMORY
WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS
SCAS443A-JUNE 1994-REVISEDJULY 1995

PZPACKAGE
(TOP VIEW)

~~ Z ~>-
UJ I-
UJ I- 0 0a: I- 0 10UJI
UJ I- 0 0 0 0 0 0
~ ~ ~ ~ 0 Ia: <!l ~IoWZZZO
I- UJ
a:a:a:a:~WZa: ~~~Z~MN
<!l <!l <!llo.. !i
al <!l o..!i ~O
0.. 0.. 0.. 0.. 0.. 0.. 0..

ABRT 1 75 GNO
GNO 2 74 ROCLK
ISOC 3 73 MUXI
ALER 4 72 MUXO
FFI 5 71 ROEN
PFI 6 70 OE
FF2 7 69 OSOC
GNO 8 68 GNO
PF2 9 67 CRI
FF3 10 66 CR2
PF3 11 65 CR3
Vee 12 64 Vee
DO 13 63 00
01 14 62 01
"tJ 02 15 61 GNO
:D 03 16 60 02
0 04 17 59 03
GNO 18 58 GNO
C 05 19 57 04
C 06 20 56 05
0 07
08
21 55 Vee
-I Vee
22
23
54 06
53 07
"tJ 09 24 52 Vee
:D Dl0 25 51 08
m re~rereg~~~~~~~~~~~~~~~~~~~g

S o~NM~oo~~~o~~o~~ooMNo~oom

m o~~~~zz~~~o~~o~~zz~~o~~zO
~ooo0<!l<!l0oo~OO~00<!l<!l0O~00<!l

:e

-!!1 TEXAS
INSTRUMENTS
9-4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE-QUEUE (MULTI-QTM) FIRST-IN, FIRST-OUT MEMORY
WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS
SCAS443A - JUNE 1994 - REVISED JULY 1995

functional block diagram

POE
os - - - . . .
RfW -----..
BREQ -....,.....--+1 Auxiliary-Bus
Control 8
PO-P7 -4--r--!.......
OWRDY -4---1
Reset
Logic
1 - - - - - - - - - RST
WRTCLK - - . - - - - ' . - - - - -....- - RDCLK

WRTEN1 Configuration MUXO

WRTEN2 Registers MUX1
WRTEN3 RDEN

ABRT
ISOC r---:~----l-----------+----;~--~---
Flags OSOC

ALER
PF1
~=t=====t---:'::~-1
- Queue1
CR1

FF1 -+--+----------; ,-------1-----+---+--- CR2

PF2 -+--+----------; ...-----+-----+----+--- CR3

FF2 Queue2 _
-+--+----------;_____ 3:
w
PF3 .....--+----------; Queue3
FF3 -4--t-----~__~~--~ :;
w
Write-Address Generation a::
2 4096 x 18 15 16 OE
a..
I-
Dual-Port
SRAM QO-Q17
o
00-017 In 16 ~
256 x 18 c
Divisions

Read-Address Generation
oa::
a..

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9-5
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A - JUNE 1994 - REVISED JULY 1995

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME
ABRT I Abort. When ABRT is held low, all data stored since the queue's last cell-abort marker are discarded.
Align error. ALER maintains cell synchronization at the input. If ISOC and internal start-of-cell status disagree, ALER
ALER 0
is low and writes are disabled.
Bus request. When BREO is low, DWRDY is set low and writes are performed to the configuration registers. When
BREO I
BREO is high, DWRDY is set high and writes are performed to the 18-bit input port.
Cell-ready flag. CR for each queue is high when at least one complete cell is present in the queue. CR is set low upon
CR 0
the read of the last word or byte in a cell, if no other complete cells are stored in the FIFO.
DO-D17 I 18-bit data input port
Data strobe. A high-to-Iow transition of DS latches the data on the 8-bit programming bus to the configuration registers.
DS I
A low-to,high transition of DS sends the data from configuration registers to the programming bus.
Data-write ready. DWRDY gives control of data writing to the input bus or the 8-bit programming bus. Data writes to the
DWRDY 0 programming bus are allowed when DWRDY is low and data writes to the synchronous bus are allowed when DWRDY
is high.
Full flag. Full flag for each queue is synchronized to the WRTCLK. When FF is low, no more cells can be written to the
FF 0
FIFO. FF is set high by the second low-ta-high transition ofWRTCLK after the last byte or word read of a cell in the queue.
ISOC I Input start of cell. ISOC must be high for the first word or byte write of a cell and low for all other word or byte writes.
"tJ
::D MUX1,
I Multiplexer inputs. MUX1 and MUXO select one of the three queues output registers.
o MUXO
OE I Output enable. 00-017 are in the high-impedance state when OE is low.
C Output start of cell. OSOC is high when the first word or byte of cell is present in the output register of the queue. When
C OSOC 0
o PO-P7 I/O
any other word or byte of a cell or invalid data is present in the output register of the queue, OSOC is low.
8-bit bidirectional programming bus
-I
Programmable flag. PF is low when the number of cells in the queue are greater than or equal to write threshold stored
"tJ PF 0 in the queue's PFX_W register. PF is set high when the number of cells in the queue are reduced to the read threshold
::D stored in the queue's PFX_R register.
m POE I Program output enable. The programming bus (PO- P7) outputs are active when POE is low and RIW is high.

S 00-017 0 18-bit data output port

m FIFO reset. To reset FIFO, four low-to-high transitions of WRTCLKand four low-to-high transition of RDCLK must occur

:e RST

RDCLK
I

I
while RST is low.
Read clock. RDCLK is a continuous clock and is asynchronous or coincident to WRTCLK. A low-to-high transition of
RDCLK reads data from a queue when the queue is selected by MUXO, MUX1 and RDEN is high.
R/W I Read/write select. R/W high selects a read operation and low selects a write operation on the 8-bit programming bus.
Read enable. RDEN high enables a low-ta-high transition of the read clock to read data from the queue selected by
RDEN I
MUX1 and MUXO.
Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A low-to-high transition
WRTCLK I
of WRTCLK writes data to one of the 3 queues when WRTEN and FF are high.
WRTEN I Write enable. A queue's WRTEN must be high to enable a low-ta-high transition of WRTCLK to write data to the queue.

~TEXAS
INSTRUMENTS
9-6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A - JUNE 1994 - REVISED JULY 1995

detailed description
reset
The Multi-Q FIFO is reset by setting the reset (RST) input low for four WRTCLK and four RDCLK low-to-high
transitions. When the device is reset, the cell ready (CR1 , CR2, and CR3) flags for each queue are set low, the
programmable flags (PF1 , PF2, and PF3) are set high, the full flags (FF1 , FF2, and FF3) are set high, the align
error (ALER) is set high, and the output start of cell (OSOC) is set low. During a device reset, the default values
shown in Table 1 are loaded into the configuration registers.

Table 1. Configuration Registers

REGISTER NO. OF DEFAULT PROGRAMMABLE
REGISTER NAME FUNCTION
SYMBOL BITS VALUE RANGE
Chooses the data input and output bus size
PORT Port Control 5 0 Bit-slice control
and format. Controls output byte destuffing.
Defines number of 256 x 18 memory blocks
Qll Queuel length 5 8 0-16
allocated to Queuel
Defines number of 256 x 18 memory blocks
QL2 Queue2 length 4 6 0-15
allocated to Queue2

~
Defines number of 256 x 18 memory blocks
Ql3 Queue3 length 4 2 0-15
allocated to Queue3
ClSZ Cell Size 6 27 10-32 Defines the number of 18-bit words in one cell

PF1_W
Programmable Flag I,
1-409
Defines the number of cells stored In.Queuel :;
Write Threshold
9 71
to set PFI low w
PF1_R
Programmable Flag I,
9 70 0-408
Defines the number of cells stored in Queuel a:
Read Threshold to reset PFI high a..
Programmable Flag 2, Defines the number of cells stored In ,Queue2
PF2_W

PF2_R
Write Threshold
Programmable Flag 2,
9

9
51

50
1-383

0-382
to set PF2 low
Defines the number of cells stored ir;! Queue2
b
::J
Read Threshold to reset PF2 high
C
PF3_W
Programmable Flag 3,
Write Threshold
8 13 1-383
Defines the number of cells stored in QueueS
to set PF3 low oa:
Programmable Flag 3, Defines the number of cells stored in Queue3
PF3_R
Read Threshold
8 12 0-382
to reset PF3 high a..
default values for the configuration registers
Port Control:
A 4-bit register that controls the sizing and word-align functions of the input and output data ports. Figure 1
shows the bit configuration of the port-control register. Table 2 lists the register bits, names, and functions.
4 3 2 o
OUTSTF OUTSIZ INSTF IN BE INSIZ

Figure 1. Port-Control Register

~1ExAs
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS, TEXAS 75265 9-7
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A - JUNE 1994 - REVISED JULY 1995

default values for the configuration registers (continued)

Table 2. Port·Control Register Bits

BIT NAME VALUE FUNCTION
0 INSIZ o(default value) Enables an lS-bit input data bus
1 Enables a 9-bit input data bus
1 IN BE o(default value) Enables the placement of DO-OS data in memory with a little-endian format if INSIZ bit is a 1
1 Enables the placement of DO-OS data in memory with a big-endian format (INSIZ bit is a 1)
2 INSTF o(default) Sets the end of a cell write to be the last byte write of the last word as defined by the cell size (CLSZ)
register if INSIZ bit is a 1
1 Sets the end of a cell write to be the first byte write of the last word and the byte write is copied to both
bytes of the word (INSIZ bit is a 1)
3 OUTSTF o (default) Enables lS-bit data output
1 Enables 9-bit data output
4 OUTSTF o (default) Allows byte reads to precede normally on all words of a cell (OUTSIZ bit is a 1)
After the first byte of the last word of a cell is read, the last byte of the last word of that cell is ignored
1
and the first byte of the first word of the subsequent cell is read (OUTSIZ bit is a 1).

"tI Queue Length:

:IJ The three queue-length registers (QL 1, QL2, and QL3) have default values of 8, 6, and 2, respectively. This
oC defines the 18-bit wide Queue1 memory depth as 2048 (8 x 256); Queue2 memory depth as 1536 (6 x 256);
and Queue3 memory depth as 512 (2 x 256). The QL 1 register has five bits and can be programmed to utilize
C the entire memory of the device for Queue1.
o Cell Size:
-4
The cell-size register (CLSZ) has a default value of 27. This defines 27 18-bit words as one cell for the cell-ready
"tI flags and programmable flags.
:IJ
m Programmable-Flag Write Threshold:
<
- The default values for the PF1_W, PF2_W, and PF3_W registers are chosen to set the respective
m programmable flags low when the number of 27-word cells stored in its queue is five cells from filling its buffer.
:e Programmable-Flag Read Threshold:
The default values for the PF1_R, PF2_R, and PF3_R registers are chosen to reset the respective
programmable flags high when the number of 27-word cells stored in its queue is reduced by (PF1_W)-1,
(PF2_W)-1, (PF3_W)-1.
data writes
Data writes are synchronized to the write clock (WRTCLK) and can occur asynchronous to the read clock
(RDCLK) while any of the three queues are being read. The data-write-ready (DWRDY) output must be high
to allow a data write from the data inputs (DO-D17) into one or more of the queue memories. When DWRDY
is high, the low-to-high transition 01 WRTCLK stores data (DO-D17) in Queue1 when the WRTEN1 input is high
and the FF1 output is high, Queue2 when the WRTEN2 input is high and the FF2 output is high, and Queue3
when the WRTEN3 input is high and the FF3 output is high. Data can be stored in two or three queues
simultaneously by asserting two or three WRTEN signals.
The input start-ol-cel.1 (ISOC) input and the align-error (ALER) output are used to maintain cell synchronization
at the input 01 the device. The ISOC should be high lor the lirst word or byte write 01 a cell and should be low
lor all other word or byte writes 01 the cell. The SN74ACT53861 maintains its own start-ai-ceil status and
compares this to the ISOC on each word or byte write. If a word or byte write is attempted when the (SOC and
the internal start-ol-cell status disagree, the write is prevented and ALER is set low.

~TEXAS
INSTRUMENTS
9-S POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A-JUNE 1994 - REVISED JULY 1995

data writes (continued)

When all words of a cell are successfully written to one of the queues, the queue flags are updated. In addition
to updating the queue flags, a completed cell write moves the cell-abort markerto the next memory write location
in the queue. After a reset, the cell-abort marker for each queue is positioned at the first memory write location.
If a 9-bit data input is selected by the port-control register, data is input to the FIFO through bits ~O-DB. If the
INBE bit of the PORT register is set to 1, data is stacked into memory big-endian style with the first byte write
of a word stored in the 09-017 byte and the second byte write of a word stored in the ~O-DB byte. If INBE
is set to 0, little-end ian stacking is enabled with the first byte write of a word stored in the ~O-DB byte and the
second byte write of a word stored in the 09-017 byte.
All data writes since a queue's last cell-abort marker are discarded when the abort (ABRT) input is held low and
the queue's write enable (WRTEN 1, WRTEN2, or WRTEN3) is held high for a low-to-high transition of WRTCLK.
The internal write pointer for the queue memory is set to the cell-abort marker for the queue, discarding all data
written since the last cell completion. No data write is performed during the abort cycle.
data reads
Data reads are synchronized to the read clock (ROCLK) and can occur asynchronous to the write clock
(WRTCLK) while any of the three queues are being written. A data read is done on a queue by the low-to-high
transition of ROCLK when the queue is selected by the multiplexer (MUXO, MUX1) inputs (see Table 3), the read
enable (ROEN) input is high, and the cell-ready-flag (CR1, CR2, or CR3) output for the queue is high. ~
W
Table 3. Output·Queue Selection by Multiplexer Inputs :;
MUX1 MUXO QUEUE OUTPUT w
0 0 Queue1 a:
0 1 Queue1 a..
1
1
0
1
Queue2
Queue3 t;
:::J
The status of the OUTSIZ bit in the PORT register determines if the output data bus size is 1B-bit word or 9-bit C
byte. If OUTSIZ is 0, each read outputs a new queue word on 00-017. If OUTSIZ is 1, the first read outputs
a new queue word on 00-017 and the next read swaps the byte order of OO-OB and 09-017. This pattern oa:
is repeated for each subsequent word read.
If the OUTSTF bit in the PORT register is a 1 and the OUTSIZ bit is a 1, the first byte read of the last word of
a..
a cell completes the cell read and the next byte read outputs a new word on the data bus, discarding the last
byte of each cell. No change in data output flow occurs if OUTSTF is a O.
The cell-ready flag and programmable flag for each queue are updated upon the read of the last word of a cell.
The number of words in a cell is defined by the contents of the cell-size (CLSZ) configuration register. When
the output-data-bus size is byte and the OUTSTF bit is a 0, the last byte read of the last word of a cell updates
the flags. If OUTSTF bit is a 1, the first byte read of the last word of a cell updates the flags.
The output-start-of-cell (OSOC) output is high when the first word or byte of a cell is present in the output register
of the queue selected by the MUX1 and MUXO inputs. When any other word or byte of a cell is present in the
output register of the queue selected by the MUX1 and MUXO outputs or if the contents of the selected register
is invalid, the OSOC is low. OSOC is synchronous to the low-to-high transition of ROCLK.
Switching queues for data output is done synchronous to the low-to-high transition of ROCLK. If ROEN and the
cell-ready flag are high at the time the queue output switch occurs, a read is done on the new queue. If ROEN
is low at the time the queue output switch occurs, the previously read data value held in the new queue's output
register is output on 00-017. Oueue switching should only be performed on cell boundaries.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 9-9
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE-QUEUE (MULTI-QTM) FIRST-IN, FIRST-OUT MEMORY
WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS
SCAS443A- JUNE 1994 - REVISED JULY 1995

data reads (continued)

OE controls the state of the data outputs (QO-Q17). When OE is high, QO-Q17 are active. When OE is low,
QO-Q17 are in the high-impedance state.
cell-ready flags
Each queue has a cell-ready flag (CR1, CR2, or CR3) that is high when at least one complete cell is stored in
the queue. The cell-ready flags are synchronized to the low-to-high transition of the RDCLK. After reset, the
cell-ready flags are set low. The low-to-high transition of a queue's cell-ready flag is initiated when a cell write
to an empty queue is complete. The queue's cell-ready flag is set high by the second RDCLK rising edge after
this event. The cell-ready flag is set low upon the read of the last word or byte in a cell if no other complete cells
are loaded in the queue. Reads from a queue are inhibited while its cell-ready flag is low.
full flags
Each queue has a full flag (FF1, FF2, or FF3) that is set high when at least one complete cell space is available
in the queue. Upon programming the queue length and the cell size, the SN74ACT53861 calculates the
maximum number of complete cells which can be written to a queue. When the number of cells stored in a queue
is equal to this maximum value, the queue's full flag is set low. full flags are synchronous to the low-to-high
transition of the WRTCLK. When a queue's full flag is low, the full flag is set high by the second WRTCLK
low-to-high transition after the last byte or word read of a cell in the queue.
"tI
:::D programmable flags
oC Each queue has one programmable flag (PF1, PF2, or PF3) that is synchronized to the low-to-high transition
of the WRTCLK. Two registers per queue define the boundaries of the programmable flags; the write threshold
C register (PF1_W, PF2_W, or PF3_W) and the read threshold register (PF1_R, PF2_R, or PF3_R). When the
o-I word write that stores the number of complete cells equals the queue's PFx_W register, its programmable flag
is set low. The low-to-high transition of the programmable flag is initiated by the read of the last word or byte
in a cell. This reduces the number of stored cells equal to the queue's PFx_R value. The programmable flag
"tI is set high by the second WRTCLK low-to-high transition after this event.
:::D
m programming the configuration registers
:S The configuration registers for the Multi-Q FIFO can be programmed after a device reset and before data is
m written to one of the queues. The programming port (PO-P7) is used to sequentially write or read the
:e configuration registers.
In order to write to the configuration registers, control of the bus must first be acquired by asserting the
bus-request (BREQ) input low, which in turn sets the data write ready (DWRDY) output low after two rising edges
of WRTCLK. DWRDY gives data-writing control to the synchronous input bus (WRTCLK, WRTEN1-3,
DO-D17) orthe 8-bit programming bus. Data writes to the programming bus are allowed when DWRDYis low
and data writes to the synchronous input bus are allowed when DWRDY is high. Data on PO-P7 is written to
the configuration registers on the high-to-Iow transition of data strobe (DS) when DWRDY is low and the
read/write (RIW) input is low. The configuration registers are written in the sequence shown in
Table 4. Ten writes are needed to program the configuration registers. After all ten registers are programmed,
further data-write attempts to the configuration registers are ignored until the device is reset again. When
programming is complete, BREQ is set high to set DWRDY high and returns input control to the 18-bit
synchronous input port. A list of rules for configuration register programming follows.
Rules for queue length (QL 1, QL2, QL3) register values:
Zero is the minimum value.
Sixteen is the maximum value for QL 1. Fifteen is the maximum value for QL2 and QL3.
Only QL 1 and QL2 can be programmed by the user. QL3 is calculated by the device to use the remaining
memory (if any exists).

~1ExA.s
INSTRUMENTS
9-10 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE-QUEUE (MULTI-QTM) FIRST-IN, FIRST-OUT MEMORY
WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS
SCAS443A-JUNE 1994- REVISED JULY 1995

programming the configuration registers (continued)

Rules for cell-size (CS) register values:
Ten is the minimum value.
Thirty-two is the maximum value.
Rules for programmable-flag write-threshold (PF1_W, PF2_W, and PF2_W) register values:
One is the minimum value.
Value must not exceed number of complete cells that can be stored in the buffer defined by its queue length
register and the cell-size register.
The PF1_W, PF2_W, and PF3_W registers are nine bits each. The most significant eight bits are
programmable by the user and the least significant bit is always a 1; therefore, PFx_W values are odd.
Rules for programmable-flag read-threshold (PF1_R, PF2_R, and PF3_R) register values:
Zero is the minimum value.
Value must be less than the corresponding programmable-flag write-threshold register value.
The PF1_R, PF2_R, and PF3_R registers are nine bits each. The most significant eight bits are
programmable by the user and the least significant bit is always 0; therefore, all PFx_R values are even. 3:
Table 4. Accessing Configuration Registers From the Programming Bus for Data Writes >
W

PROGRAMMING W
WRITE
ORDER
REGISTER BUS PORTS a:
MSB lSB D..
1 PORT P4 PO
I-
2 Qll P4 PO o
3 QL2 P3 PO ::J
4 ClSZ P5 PO C
5
6
PF1_W
PF1_R
P7
P7
PO
PO
oa:
7 PF2_W P7 PO D..
8 PF2_R P7 PO
9 PF3_W P7 PO
10 PF3 R P7 PO

The programming bus (PO-P7) is a bidirectional port whose outputs are active when the
program-output-enable (POE) input is low and the read/write (RIW) input is high. When the PO-P7 outputs are
active, data from the configuration registers are output. The next configuration register in sequence shown in
Table 5 is sent to the programming-bus outputs on a low-to-high transition of DS when RIW is high. After all ten
registers have been read in sequence, a subsequent programming-bus read accesses the PORT register again.
Unused bit values for a register appear as logical 0 on the programming bus.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 9-11
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A - JUNE 1994 - REVISED JULY 1995

programming the configuration registers (continued)

Table 5. Accessing Configuration Registers From the Programming Bus for Data Reads
PROGRAMMING
WRITE BUS PORTS
REGISTER
ORDER
MSB LSB
1 PORT P3 PO
2 Ql1 P4 PO
3 QL2 P3 PO
4 ClSZ P5 PO
5 PF1_W P7 PO
6 PF1_R P7 PO
7 PF2_W P7 PO
8 PF2_R P7 PO
9 PF3_W P7 PO
10 PF3 R P7 PO

"tJ WRTCLK
:c
o RDCLK
c
c --.I It--
I
tsu(RS)

o RST - - - - . {
~'I~~I
I____+--+______________- J

-I tpd(W·AE) ~ I.i-
"tJ
:c
ALER 71ZZZZZ2211 I I I
I
t~(W-FF) k--tli tpd(W·FF) H
m }~------
<
-m %?Z,'l/J/ZlJ,2Zl7lZJ1
:e PF(1,2,3)
I tpd(R·CR) i---.I

Figure 2. Device Reset

~1ExAS
INSTRUMENTS
9-12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A - JUNE 1994 - REVISED JULY 1995

WRTCLK I \~-------{ \ {
I I
I I
I I
tsu(EN) ---I~~.-.! th(EN)
14-1. I

ISOC vzzz;vzzzzzz;rA I ~~~

I I
I I
I I
tsu(EN) I. ~. .! th(EN) tsu(EN) ~ ~.~ th(EN)
WRTEN1 7/??Z2lZZZZlZZlZ I t>\~ No Operation t";"2;':;2~2""2"'2"'2"'2"';
I
1+ tsu(O) -¥---tI th(O)
00-017~word1ofcell~
NOTES: A. DWRDY = H
B. Data is loaded to Queue2 or Queue3 in the same manner when the corresponding WRTEN is active.
C. INSIZ bit of PORT register = 0

Figure 3. Writing Word-Length Data to Queue1

WRTCLK I \~-------{ \~------{ ~

I
w
5>
w
a:
ISOC a?I2ZIlfl/l//ZlZ4 a..
I-
I
I
o
::l
tSU(EN~ ~~ C
-'lZZZ2ZZZ?2?ZZ
WRTEN1
I
~.
o
X8888888 a:
tsu(O) I. .! th(O)
00-08 ~ Byte1 of Cell ~ Byte20fCeli
a..
Stored In Stored In
09-017 Byte 00-08 Byte
NOTES: A. DWRDY = H
B. Data is loaded to Queue2 or Queue3 in the same manner when the corresponding WRTEN is active.
C. INSIZ bit of PORT register = 1; INBE bit of PORT register = 1.

Figure 4. Writing Byte Data to Queue1 in Big-Endian Configuration

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9-13
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A-JUNE 1994 - REVISED JULY 1995

WRTCLK I ,'-----{ ,'-----{

I

ISOC V7/ZT//////ZZIIZI

WRTENl zrlZ/// / / ? Z Z I
I
Z?/T0\\\\\'>
tsu(D) I.. 'I" " th(D)
DO-DS ~ BytelofCeU ~ Byte2ofCeUXXX><X>O<X
Stored In Stored In
DO-OS Byte D9-D17 Byte
NOTES: A. DWRDY = H
B. Data is loaded to Queue2 or Queue3 in the same manner when the corresponding WRTEN is active.
C. INSIZ bit of PORT register = 1; INBE bit of PORT register = o.
'tJ Figure 5. Writing Byte Data to Queue1 in Little-Endian Configuration
:D
oC WRTCLK I ,'-_ _ _ _{ ,'-_ _ _.....J/
I
C I
o-I tsu(EN) .. ---.,~~
114- ..
I
f---tI" th(EN)
ISOC ~~ct I R2";Z"'Z';'Z"'Z""Z""Z""Z"'/."'Z"'Z"?'Z"?'Z"?'Z"?'7,.-----.:\:~$~s:~s:~$~$~s:-.:-<"S
'tJ I
:D I
m
-m<
==
NOTES: A. CLSZ = 27 for the example
B. DWRDY= H
C. A cell is confirmed to Queue2 or Queue3 in the same manner when the corresponding WRTEN is active.
D. INSIZ bit of PORT register = 0

Figure 6. CeU·Write Completion With 18-Bit Input

~TEXAS
INSTRUMENTS
9-14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A-JUNE 1994- REVISED JULY 1995

WRTCLK I ,---_.....{ I
,'---_.....{ I

I
tSU(EN)t ~. ~ ~. ~th(EN)
WRTEN1 WZlZlflllZllZZZ ~ ~ ;(\\\\~
tsu(D) I. ~. ~ th(D) tsu(D) ~ ~I. ~I th(D)
00-08 ~ Byte 54 of Cell ~ Byte1 ofcell>cxxxxxxx>,..,~~~r-
NOTES: A. CLSZ = 27 for the example
B. DWRDY=H
C. A cell is confirmed to Queue2 or Queue3 in the same manner when the corresponding WRTEN is active.
D. INSIZ bit of PORT register = 1; INSTF bit of PORT register = o.
Figure 7. Cell-Wrlte-Completlon Example With 9-Bit Input and No Byte Stuffing
3:
WRTCLK I ,---_.....{ 1
,-----{
1
->w
1 W
1
0::
tSU(ENt ~I. ~.th(EN) tSU(E:~ .I. ~ th(EN) a..
1 p //?IT/1Z?ZZZZ27 l~~
1 1
1
6
::l
1

~. ~ ~. ~th(EN) C
WRTEN1 2l7!ZlZZZ?fl22/Z%
tSU(EN)t
~ ~ 0-~~ o
tsu(D) I. ~. ~ th(D) tsu(D) 14 .1. ~I th(D)
0::
00-08 ~Byte530fcell~ Byte10fcell~ a..
Copied to Upper and
Lower Bytes of the Word
NOTES: A. CLSZ = 27 for the example
B. DWRDY=H
C. A cell is confirmed to Queue2 or Queue3 in the same manner when the corresponding WRTEN is active.
D. INSIZ bit of PORT register = 1; INSTF bit of PORT register = 1.

Figure 8. Cell·Wrlte-Completlon Example With 9·Blt Input and Byte Stuffing

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 9-15
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE-QUEUE (MULTI-QTM) FIRST-IN, FIRST-OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A-JUNE 1994 - REVISED JULY 1995

WRTCLK I ,~ ________{ \ I
I

ISOC~--""';-
F tpd(W-AE) -tI

I \~----------------
WRTEN ?/27ZZ2?IZ?/ZZZZ2 tSU(EN~ ~- ~h(EN)
(1,2, or 3) "-"-"""............"""-'''''''-'~......'-''-''
ISOC Disagrees With the SN74ACT53861
Internal Start-of-Celllndication

Figure 9. Setting ALER When ISOC Is Misaligned

WRTCLK I 'I...___. . .{ 'I...____{

tsu(EN) I- -I- .I th(EN) I
ABRT -----r~~$~$-.::$-.::$-.:$-.:$~$~$:-O~:-O~~~~, I l"/...,/.'"'::/....;/.~~?,..?,..?,..?,.?,.?,.?.".?.".?.".2""/"'---;-1- - - - -
"'CJ I I
~- t&~
J]
oc ISOC VVAZZVfllllV?2Vl?),mvPWAYLJjj
t+- tpd(W-AE) -.!
c
o
-t
"'CJ
WRTEN1 ?Z2ZZIZZZ/?/ZIlA
J]
m 0 0 - 0 1 7 . ~
<
- Data Written to Queue1 Memory Location
m
~ NOTES: A. DWRDY = H
Pointed to by Cell-Abort Marker

< B. Data written since the last confirmation in Queue2 or Queue3 are aborted In the same manner when the corresponding WRTEN
is active.

Figure 10. Aborting Data In Queue1 Written Since the Last Cell Completion

-!111ExAs
INSTRUMENTS
9-16 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A - JUNE 1994 - REVISED JULY 1995

RDCLK I ,------'l( '-----1 ,\..._ _---J 1

1 1
CR1

MUXO ?lZZZ//ZZZZZ 1 \S8&$&S&$&9'

IsuIEN) t.-14--t"0101~""''' IhlEN) 1

MUX1~ i~ i~ IZlZllZZZZ
.. ~

RDEN zv;vzzzro Isu(EN) 14 tj Ih(EN)

i w<><><><><><><x
14-- la --to!
1

iV>~~~~~~'\'\
14-- la --to!
IZZll2ll2/
No Operation
QO-Q17 ~~~~~~~~~~~~~t1w~o~rdE1~O~fC~eilllllF~rO~m~Q~u~eU~e~1)t::::~W~O~rd~2~Of~C~e!II~Fr~O~m~Q~u~eU~e~1::
NOTES: A. OE = H
B. Data is read from Queue2 in the same manner when CR2 is high with MUX1 = Hand MUXO = L. Data is read from Queue3 in the
same manner when CR3 is high with MUX1 = Hand MUXO = H.
C. OUTSIZ bit of PORT register = 0

Figure 11. Reading Word-Size Data From Queue1 ==

W
:;
w
RDCLK I ,\...---.Ji( ''----1 ' ...._ _---J 1 a:
D..
1 1
CR1
r )IPdIR'OS) 14 ~PdIR'OS)
b
:::J
C
IsuIEN) t.-14- *I~...., IhlEN)
.....
1 '--------------------
oa:
~
1
7/7ATazzzJ \XXXXX8XX>f
MUXO

tsu(EN) 14 +., thlEN)

1
1
\S\\\\\\\)
D..
MUX1
~~I~ I ~ tlIIlIITl?
RDEN
Ir '>s~,\,\,\\
ta --to!
'"'"~ mzzzzzz;
No Operation
QO-Q8 ~~~~~~~~~~~~~(JB~eL1o~f~C~el[IF~r~Om~Q~Ue~u~e1[jc::::iB~I~e2~o~f£C~eIUIF~ro~maQ9u~e~u~e1L::
~ta~ ~ta--to!
Q9-Q17 ~~~~~~~~~~~~~(]B~e2[o~f~C~el[IF~r~Om~Q~ue~u~e1[jc::::!B~t!e1Go~f£C~eIDIF1ro~m~Q§u~e~u~e1c::
NOTES: A. OE = H
B. Data is read from Queue2 in the same manner when CR2 is high with MUX1 = Hand MUXO = L. Data is read from Queue3 in the
same manner when CR3 is high with MUX1 = Hand MUXO = H.
C. OUTSIZ bit of PORT register = 1

Figure 12. Reading Byte-Size Data From Queue1

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9-17
 SN74ACT53861
4096 x18 CLOCKED MULTIPLE-QUEUE (MULTI-QTM) FIRST-IN, FIRST-OUT MEMORY
WITH THREE PROGRAMMABLE-DEPTH bUFFERS AND CELL-BASED FLAGS
SCAS443A - JUNE 1994 - REVISED JULY 1995

RDCLK " ' { , ' - -_ _{ ''-___..,,1

I I I

1/lZl2

Last Word of Cell First Word of a Cell

""C NOTES: A. CLSZ. 27 for the example
::D
o
C
B. OE=H
C. Data is read from Queue2 in the same manner when CR2ls high with MUXI
same manner when CR3 is high with MUXI - Hand MUXO • H.
=H and MUXO - L. Data is read from Queue3 in the

D. OUTSIZ bit of PORT register = 1; OUTSTF bH of PORT register. 1.

e
~
""C RDCLK _ _---'''
Figure 13. Reading Byte-Size Data With Byte Destufflng

' { ,'---_....{ ,
I
::D
m CRI I I I

osoc _____~i-------t-~-(R-.O-S-)rl~·:~----~j---------~====~
rI t,tPd(R.OS)
-
< I I. ________ ~

~ CR2
I
I
I
I
I
I
I
I
MUXOZZ/ iI R/lllAZVZ7!Z/2
MUX1'\\\ i \\\\\\&\\~
I
RDENLd !
Read Queue1 . Read Queue2I ! \\\\~
Read Queue2
QO-Q17-------*
I+- Ie --tj

Last Word of Cell

~ Ie --tj
*
Flret Word of a Cell
It- ta --tI
*--------
From Queue1 From Queue2
NOTES: A. OE - H
B. If a read from Queue2 is disabled by CR210w or RDEN low during the cycte the output switch occurs, the previous data held in the
Queue2 output register is output.
C. OUTSIZ bit of PORT register = 0
Figure 14. Example of Switching Queues on the Output

~1ExAs
INSTRUMENTS
9-18 POST. OFFICE sox 655303. DALlAS. TEXAS 75265
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE-QUEUE (MULTI-QTM) FIRST-IN, FIRST-OUT MEMORY
WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS
SCAS443A-JUNE 1994- REVISED JULY 1995

WRTCLK
ISOC ___________________________________________________________

ALER

WRTEN1
122?7 ~~$~$~$~$~~L_ _____________________________________
00-017
Last Word Write of Only Cell In Queue1
ROCLK

tpd(R-CR)
CR1 ________________________ -J! ~---{ 1
1 ! p=tPd(R-CR)
1
1 1 1
tpd(R-OS) 14-14--tt~ 14 ~ tpd(R,OS)
oSoC _____________________________~I---Ji 1 \. 1
1 1 ~~I~---------
1 1
ORA VZZZZ71l/ZZ2ZZ??V2ZZZ!/ll I~
1
I ~ I \\\\\\\\\)
1 1 ~
W
~
1 1
MUX1,
MUXO --------------------------~~~----~i--------~I-----------
: (0,1)
:;
j+-- ta -'I j+- ta ~ 14- t8 -t! w
QO-Q17_ W1 * W2-Wn-1 *....-~w~n-- a::
Q.
NOTES: A. Outputs enabled (OE = H); word bus size
B. When byte size output bus is used:
- If OUTSTF bit of PORT register = 1, CR1 set low by first byte read of Wn.
- If OUTSTF bit of PORT register = 0, CR1 set low by last byte read of Wn.
6::J
Figure 15. CR1 Timing Example C
o
a::
Q.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9-19
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A-JUNE 1994- REVISED JULY 1995

WRTCLK

I I
WRTEN1 I~ I
I I
ISOC _ _ _ _ _
r--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-;
_ _ _ _ _ __
I
ALER I
I I
00-017
Last Write of Cell to Fill Queue1 I
J.----! Ipd(W-FF) ~ tpd(W-FF)
FF1 - - - - - - \ J
ROCLK

ROEN _ _ _ _ _ _ _ _ _ _ _ _ _ _~&v.~/.~4f I"~~~~~ ______________

MUX1, ;;V : (0,1)
"tJ MUXO~~---------------_r.~~---------------
:IJ
OSOC _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I _ _ _ _ _ _ _ _ _ _ _ _ _ __
oC ~I

I
I4-ta~
C QO-Q17~..-----~w~n------
o Last Read of Cell
-I
"tJ NOTES: A. Outputs enabled (OE = H); word bus size
:IJ B. When byte size output bus is used:
m -
If OUTSTF bit of PORT register = 1, FFI set low by first byte read of Wn.
- If OUTSTF bit of PORT register = 0, FFI set low by last byte read of Wn.
S Figure 16. FF1 Timing Exampll!
m
:e

~ThxAs
INSTRUMENTS
9-20 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE-QUEUE (MULTI-QTM) FIRST-IN, FIRST-OUT MEMORY
WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS
SCAS443A - JUNE 1994 - REVISED JULY 1995

WRTCLK
I I
WRTEN1 1////1 I~ I
I I
ISOC _ _ _ _ _ _Ir-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-il_ _ _ _ _ __
I
ALER
I
I I
00-017
Last Write of Cell to Fill Queue1 to PFCW Cells I
~ tpd(W.PF) I+----tI tpd(W.PF)
PF1 - - - - - - \ 1
ROCLK

ROEN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~t~2~21 i~~~-~-~-------------------

MUX1, ~ : !O,1)
MUXO~----------------------~.~~--------------
I
3:
w
OSOC _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _I~------------------
I
jf-ta--ti
5>
w
QO-Q17~-------:w":"!'n------ a::
Last Read of Cell to Reduce a..
Queue1 to PF1_R Cells
t-
NOTES: A. Outputs enabled (OE =H); word bus size O
B. When byte size output bus is used:
- II OUTSTF bit of PORT register =I, PF1 set low by first byte read of Wn. :l
- If OUTSTF bit of PORT register =0, PF1 set low by last byte read of Wn. C
Figure 17. PF1 Timing Example oa::
a..

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 9-21
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE-QUEUE (MULTI-QTM) FIRST-IN, FIRST-OUT MEMORY
WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS
SCAS443A-JUNE 1994- REVISED JULY 1995

WRTCLK

1
\~____~I______________~~(~j_ _ _ _ _ _ _ _ -JIr---~I~---------
1
tpd(D.WR)~ 14-
DWRDY ;,..,.---..;.....;----.....{
tpd(D.WR)~ r-
,,.---------
I~·------------~)\~r-----------------~'
R/W ~S~S~S~S~:s:~S~S~:s:~S~S~\:~S~~ (( /,.---------
~ JI
tSU(DR.DS)/lI4---~~~....--_ _ _ _ __

-r' ~ th(P) tSU(P) 14

PO-P7 ----------(~~---1~Q!~D Wrlte10

PORT

Figure 18. Writing to the Programming Registers

IfjJ

"tJ
JJ DWRDY
oC f(

~
J1
R/W--4
C
o-I 1
1
1
1

~
1
DS
"tJ --+-1.-.1\
JJ ten(p) i-I H tpd(DS-P) idls(p)jt-t!
m PO-P7 ~ Read1 X Read2 X Read3 Xr---::R~ea~d4:--x=---Ir-x Read10 '1--
<
- PORT QL1 QL2 QL3 PF3_R
m
:e Figure 19. Reading From the Programming Registers

~ThxAs
INSTRUMENTS
9-22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A-JUNE 1994 - REVISED JULY 1995

absolute maximum ratings over operating free·air temperature range (unless otherwise noted)t
Supply voltage range, Vee .. ~ ....................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI> Vee) ............................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ........................................... ±50 mA
Continuous output current, 10 (Vo = 0 to Vee) ............................................. ±50 mA
Continuous current through Vee or GND ................................................. ±400 mA
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
3:
w
Vil
IOH
low-level input vo~age
High-level output current
0.8
-8
V
mA -
>
IOl low-level output current 16 mA
w
TA Operating free-air temperature a 70 °e a:
D.
electrical characteristics over recommended operating free-air temperature range (unless I-
otherwise noted) 0
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT :::J
VOH Vee = 4.5 V, IOH =-4mA 2.4 V o
VOL
II
Vee=4.5V,
Vee = 5.5 V,
IOl=8mA
VI = Vee orO
0.5
±5
V
!lA
oa:
IOZ Vee = 5.5 V, Vo=Vee orO ±5 !lA D.
ICC Vee = 5.5 V, VI = Vee - 0.2 V or 0 400 !lA
Alee§ Vee = 5.5 V, One input at 3.4 V, Other inputs at Vee or GND 1 mA
ei VI =0, f= 1 MHz 4 pF
Co VO=O, f= 1 MHz 8 pF
:j: All tYPical values are at Vee = 5 V, TA = 25°C.
§ This is the supply current when each input Is at one of the specified TTL voltage levels rather than 0 V or Vee.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9-23
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE·QUEUE (MULTI·QTM) FIRST·IN, FIRST·OUT MEMORY
WITH THREE PROGRAMMABLE·DEPTH BUFFERS AND CELL·BASED FLAGS
SCAS443A-JUNE 1994- REVISED JULY 1995

timing requirements over recommended ranges of supply voltage and operating free·air
temperature (see Figures 2 through 19)
MIN MAX UNIT
fclock Clock frequency, WRTCLK or RDCLK 50 MHz

tc Clock cycle time, WRTCLK or RDCLK 20 ns

tw(CLKH} Pulse duration, WRTCLK and RDCLK high 7 ns

tw(CLKL} Pulse duration, WRTCLK and RDCLK low 7 ns

tw(DS} Pulse duration, DS high or low 15 ns

tsu(D} Setup time, DO- D17 before WRTCLKi 5 ns

Setup time, ISOC, ASRT, WRTEN1, WRTEN2, and WRTEN3 before WRTCLKi; RDEN, MUXO,
tsu(EN} 5 ns
and MUX1 before RDCLKi

tsu(RS} Setup time, RST low before WRTCLKi or RDCLKit 7 ns

tsu (RS2} Setup time, RST high before first data write 20 ns

tsu(R-DS} Setup time, RIW before DSJ, 8 ns

tsu(DR-DS} Setup time, DWRDY before DSJ, 8 ns

tsu(P} Setup time, PO-P7 before DSJ, 8 ns

"'0 Hold time, 00-017 after WRTCLKi 0 ns
th(D}
JJ
o th(EN}
Hold time, ISOC, ASRT, WRTEN1, WRTEN2, and WRTEN3 after WRTCLKi; RDEN, MUXO, and
MUX1 after RDCLKi
0 ns
C
C th(RS} Hold time, RST low after WRTCLKi or RDCLKit 7 ns

o th(R-DS} Hold time, RIW after DSJ, 1 ns

-I th(P} Hold time, PO-P7 after DSJ, 1 ns
"'0 t ReqUirement to count the clock edge as one of at least four needed to reset a FIFO
JJ
m switching characteristics over recommended ranges of supply voltage and operating free-air
< temperature, CL = 30 pF (see Figures 20 and 21)
-
m PARAMETER MIN MAX UNIT

:E ta

tpd(R-CR}
Access time, RDCLKi to 00 -017
Propagation delay time, RDCLKi to CR1, CR2, or CR3
11
10
ns
ns

tpd(R-OS} Propagation delay time, RDCLKi to OSOC 10 ns

tpd(W-AE} Propagation delay time, WRTCLKi to ALER 10 ns

tpd(W-PF} Propagation delay time, WRTCLKi to PF1, PF2, or PF3 10 ns

tpd(W-FF} Propagation delay time, WRTCLKi to FF1 , FF2, or FF3 10 ns

tpd(W-WR} Propagation delay time, WRTCLKi to DWRDY 10 ns

tpd(DS-P} Propagation delay time, Dsi to PO-P7 20 ns

ten(O} Enable time, OE to 00-017 active 1 ns

tdis(O} Disable time, OE to 00-017 at high impedance 9 ns

ten(p} Enable time, POE and RIW to PO-P7 active 1 ns

tdis(P} Disable time, POE and RIW to PO-P7 at high impedance 9 ns

~TEXAS
INSTRUMENTS
9-24 POST OFFICE BOX 655303. DALLAS, TEXAS 75265
 SN74ACT53861
4096 x 18 CLOCKED MULTIPLE-QUEUE (MULTI-QTM) FIRST-IN, FIRST-OUT MEMORY
WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS
SCAS443A-JUNE 1994- REVISED JULY 1995

PARAMETER MEASUREMENT INFORMATION

From Output
Under Test ~
Input ---1' ~--------~ 3V
r · ; - V - - - - - OV

RL = 500 0 1 T CL = 50 pF
Output
14- tpd ~

)t
l4- tpd ~

'\2 ::
-- --
LOAD CIRCUIT TOTEM· POLE OUTPUTS

Figure 20. Standard CMOS Outputs

7V
Input 1 1.5v \ 1.5~--- 3V
l RL= R1 = R2
~I 1\ OV

51 tpZL -.: :+t PLZ -..: I+-

R1
----;1""\.1 1I '" 3.5 V ==
W
From Output Test
~ :;
Under Test Point Output : ' \ 1.5V: VOL
w
1 tpHZ -.I 1+ f 0.3 V a:
IPZH -.J J+-
1
1 I
.J __ VOH
D..
Output of -0.;V I-
o
LOAD CIRCUIT
::l
VOLTAGE WAVEFORMS C
oa:
PARAMETER R1, R2 CLt 51
Open
D..
I tpZH
ten 5000 50pF
tpZL Closed
I tpHZ Open
letis 5000 50 pF
tpLZ Closed
tod 5000 50 pF Open
t Includes probe and test·fixture capacitance
Figure 21. 3-State Outputs

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 9-25
9-26
10-1
 3.3-V LOW-POWERED 18-BIT FIFOS
Features Benefits

• Designed for 3.3-V operations • Ensures maximum clock speed, access

times and low power operations
• Drop-in replaceable for the following: • Allows easy scalability from 5 V to 3.3 V
Clocked 5 V: SN74ACT7803 Clocked 3.3 V: SN74ALVC7803
SN74ACT7805 SN74ALVC7805
SN74ACT7813 SN74ALVC7813
Strobed 5 V: SN74ACT7804 Strobed 3.3 V: SN74ALVC7804
SN74ACT7806 SN74ALVC7806
SN74ACT7814 SN74ALVC7814
• Members of Texas Instruments Widebus™ • Combined wider data-path capability with
family reduced board space area
• 0.8-J,1m CMOS process • Fast access times combined with low
power
• TI's advanced clocked interface • Supports free-running clocks with enables
• Clock frequencies as high as 50 MHz • Supports high-performance systems
• Fast access time • Access times as low as 13 ns for
improved performance
• High drive capabilities • -8 mA/16 mA drive capability for high
fanout and bus applications
• Depth from 64 to 2K words • Multiple depths to optimize system
applications
• Latched input and output registers • Allows for fast access times as well as
setup and hold times as reduced setup
and hold times
• Grey-code flag architecture • Eliminates race conditions
• First-word fall-through • Eases system interface requirements
• Programmable AF/AE flag • Increases design flexibility
• Multistage flag synchronization • Increases reliability by increasing mean
time between failures (MTBF)
• Output edge control (OECTM) circuitry • Improved reliability
• Distributed Vee and GND • Improved noise immunity and mutual
coupling effects
• JEDEC standard 56-pin SSOP package • 18-bit product in equal or less space than
9-bit FIFO options

10-2
 SN74ALVC7803, SN74ALVC7805, SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW-POWERED CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS436B- JUNE 1994- REVISED JULY 1995

• Operates at 3-V to 3.6-V Vee DLPACKAGE

(TOP VIEW)
• Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
RESET 1 OE1
• Read and Write Operations Synchronized 017 017
to Independent System Clocks 016 016
• Low-Power Advanced CMOS Technology 015 015
• Half-Full Flag and Programmable 014 GNO
Almost-FuIl/Almost-Empty Flag 014
• Bidirectional Configuration and Width 012 Vee
Expansion Without Additional Logic 011 013
012
• Input-Ready Flag Synchronized to Write
Clock Vee 011
09 010
• Output-Ready Flag Synchronized to Read 08 09
Clock
GNO GNO
• Fast Access Times of 13 ns With a SO-pF 07 08
Load and All Data Outputs Switching 06 07
Simultaneously 05 06
• Data Rates From 0 to SO MHz 04 05
• Pin Compatible With SN74ACT7803, 03 Vee
SN74ACT780S, and SN74ACT7813 02 04
• Available in Shrink Small-Outline 30o-mil 01 03
(OL) Package Using 2S-mil Center-to-Center 00 02
Lead Spacing HF GNO
PEN 01
description AF/AE 00
WRTCLK ROCLK
The SN74ALVC7803, SN74ALVC7805, and WRTEN2
SN74ALVC7813 are FIFOs suited for buffering WRTEN1
asynchronous data paths at 50-MHz clock rates IR OR
and 13-ns access times. These devices are
designed for 3-V to 3.6-V VCC operation. The
56-pin shrink small-outline (DL) package offers
greatly reduced board space over DIP, PLCC, and
conventional SOIC packages. Two devices can
be configured for bidirectional data buffering
without additional logic.
The write clock (WRTCLK) and read clock (RDCLK) should be free running and can be asynchronous or
coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low,
and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low
and OR is high. The first word written to memory is clocked through to the output buffer regardless of the RDEN,
OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four
WRTCLK and four RDCLK riSing edges occur to clear the synchronizing registers. Resetting the FIFO initializes
the IR, OR, and HF flags iow and the AF/AE flag high. The FIFO must be reset upon power up.
The SN74ALVC7803, SN74ALVC7805, and SN7 4ALVC7813 are characterized for operation from O°C to 70°C.

Copyright © 1995, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 10-3
SN74ALVC7803, SN74ALVC7805, SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW-POWERED CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS436B- JUNE 1994- REVISED JULY 1995

logic symbolt
<I>
1 FIFO 512 x 18 or
"- RESET 256 x 180r
RESET
25 64x 18
WRTCLK WRTCLK
27
WRTEN1 28
26 JWRTEN In Ready IR
WRTEN2
32
" Half-Full
22
HF
ROCLK ROCLK 24
56 Almost-Full I Empty AF/AE
"- 29
OE1
OE2
30 "- =::::J EN1 Out Ready OR

~&
"- ROEN
31 I"-
23 -
I"-
,
Program Enable
r
21 33
DO 0 0 QO
20 34
01 Q1
19 36
02 Q2
18 37
03 Q3
17 38
04 Q4
16 40
05 Q5
15 41
06 Q6
14 42
07 Q7
12 43
08 Q8

~ ~1'7
11 45
09 Q9
9 46
010 Q10
8 47
011 Q11
7 48
012 Q12
6 49
013 Q13
5 51
014 Q14
4 53
015 Q15
3 54
016 Q16
2 55
017 17 17 Q17

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.

~TEXAS
INSTRUMENTS
10-4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ALVC7803, SN74ALVC7805, SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW-POWERED CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS436B-JUNE 1994- REVISED JULY 1995

functional block diagram

---4 ~ Output
- H Control

~J
00-017

- RAM
ROCLK -4 I--
'--
Synchronous
Read
f---+-
I Read
Pointer
I
I
- r--- Control

I 512 x 18 (7803),
256 x 18 (7805),
64 x 18 f7813)
WRTCLK - H I---'
WRTEN1 -i--
WRTEN2 -f--
--
Synchronous
Write
Control -
I Write I
Pointer I
I

I
lJ
Register QO-Q17

'-I t- Status-
'---I Reset Flag OR
----I Logic Logic IR
HF
AFJAE

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 10-5
SN74ALVC7803, SN74ALVC7805, SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW-POWERED CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS436B-JUNE 1994- REVISED JULY 1995

Terminal Functions
TERMINAL
110 DESCRIPTION
NAME NO.
Aimost-fuilialmost-emptyflag. Depth-offset values can be programmed for this flag. orthe default
value of 64 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE
AF/AE 24 0 is high when memory contains X or less words or (512 minus Y) or more words. AF/AE is high
after reset.
2-9,11-12,
DO-D17 I 18-bit data input port
14-21
HF 22 0 Half-full flag. HF Is high when the FIFO memory contains 256 or more words. HF is low after reset.
Input-ready flag.IR is synchronized to the low-te-high transition of WRTCLK. When IR is low, the
IR 28 0 FIFO is full and writes are disabled. IR is low during reset and goes high on the second low-te-high
transition of WRTCLK after reset.
Output enables. When OE1, 00, and RDEN are low and OR is high, data is read from the FIFO
OE1, OE2 56,30 I on a low-te-high transition of RDCLK. When either OE1 or OE2 is high, reads are disabled and
the data outputs are in the high-Impedance state.
Output-ready flag. OR is synchronized to the low-te-high transition of RDCLK. When OR is low,
the FIFO is empty and reads are disabled. Ready data is present on 00-017 when OR is high.
OR 29 0
OR is low during reset and goes high on the third low-to-high transition of RDCLK after the first
word is loaded to empty memory.
Program enable. After reset and before the first word is written to the FIFO, the binary value on
PEN 23 I
DO-D7 is latched as an AF/AE offset value when PEN is low and WRTCLK is high.
33-34,36-38, 18-bit data output port. After the first valid write to empty memory, the first word is output on
00-017 40-43,45-49, 0 00-017 on the third rising edge of RDCLK. OR is also asserted high at this timeto indicate ready
51,53-55 data. When OR is low, the last word read from the FIFO is present on 00-017.
Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK.
RDCLK 32 I A low-te-high transition of RDCLK reads data from memory when OE1, OE2, and RDEN are low
and OR is high. OR is synchronous to the low-to-high transition or RDCLK.
Read enable. When RDEN, OE1, and OE2 are low and OR is high, data is read from the FIFO
RDEN 31 I
on the low-te-high transition of RDCLK.
Reset. To reset the FIFO, four low-te-high transitions of RDCLK and four low-to-high transitions
RESET 1 I
of WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high.
Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK.
WRTCLK 25 I A low-to-high transition of WRTCLK writes data to memory when WRTEN2 is low, WRTEN1 is
high, and IR is high. IR is synchronous to the low-to-high transition of WRTCLK.
WRTEN1, Write enables. When WRTEN1 is high, WRTEN2 is low, and IR is high, data is written to the FIFO
27,26 I
WRTEN2 on a low-te-high transition of WRTCLK.

~1ExAs
INSTRUMENTS
10-6 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALVC7803, SN74ALVC7805, SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW·POWERED CLOCKED FIRST·IN, FIRST·OUT MEMORIES
SCAS436B-JUNE 1994- REVISED JULY 1995

WRTCLK

I I

DO-D17 I
'DOJtfar!"
'A'/:,AL/

I I I I
RDCLK I 1 2 3 4 I
I
_ ~I
OE1 ~Don'tCar~~
/)-,/;/,

I I
I
I LLLL'

RDEN ~b~n\C:,t~ 'LA' <LA"

QO-Q17 Invalid

Define the AF/AE Flag UsIng the Default value of X =Y =64

Figure 1. Reset Cycle

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 10-7
SN74ALVC7803, SN74ALVC7805, SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW-POWERED CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS4368 -JUNE 1994 - REVISED JULY 1995

1
o

WRTCLK

WRTEN1 I I I
o
I I I
WRTEN2 ---, : I I
I
DO-D17 mJ VA f0J r?1 ~
WI W2 W3 W4 W+) ~ A ~ v)~ ~ V:
I I I
RDCLK

I I I
~~~A
OE1 I I I 1
----------------+
------~I------~------~I------~-- o
I I I
I I I 1
I I I o
I I I
OE2 __________________+I________~I:------~~------~1 ______ ~I--- o

QO-Q17 _______I_nv_al_ld______ ~><~------~--------~-1------~------_r~---

I I
OR _ _ _ _ _ _.... I : !
I I
AF/AE
: I
I I
I I
HF __________________________________ ~

II :I
I
IR I L
DATA WORD NUMBER FOR FLAG TRANSITIONS
TRANSITION WORD
DEVICE
A B C
SN74ALVC7803 W257 W(513-Y) W513
SN74ALVC7805 W129 W(257-Y) W257
SN74ALVC7813 W33 W(65-Y) W65

Figure 2. FIFO Write

~TEXAS
INSTRUMENTS
10-8 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALVC7803,SN74ALVC7805,SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW-POWERED CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS436B - JUNE 1994 - REVISED JULY 1995

PEN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0
1

WRTCLK

I I
WRTEN1-n I
I I
I I 1
WRTEN2 ! !
o
I I
00-017 ) Wr13 V//////////~/////ff//dM'/u////////////W/////m
I I
RDCLK I I---'I~~~~
......
I
I I
I 1
OE1 I o
I I
I I
RDEN III I
I I I
I I I
I I I I
OE2
I I I I
I I
I
QO-Q17 W1
>G:X : W3

I
OR
I I I L--
I I I
AF/AE
I
I : I~-----------
I I
HF
I
I
I
I
I
IR , ' - -_ _ _ _- - '

DATA WORD NUMBERS FOR FLAG TRANSITIONS

TRANSITION WORD
DEVICE
A B C 0 E F
SN74ALVC7803 W257 W258 W(512-X) W(513-X) W512 W513
SN74ALVC7805 W129 W130 W(256-X) W(257-X) W256 W257
SN74ALVC7813 W33 W34 W(64-X) W(65-X) 64 65

Figure 3. FIFO Read

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10-9
SN74ALVC7803, SN74ALVC7805, SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW·POWERED CLOCKED FIRST·IN, FIRST·OUT MEMORIES
SCAS436B -JUNE 1994 - REVISED JULY 1995

offset values for AF/AE

The aimost-fuil/aimost-empty (AF/AE) flag has two programmable limits: the almost-empty offset value (X) and
the almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is
written to memory. If the offsets are not programmed, the default values of X =Y = 64 are used. The AF/AE
flag is high when the FIFO contains X or less words or (512 minus Y) or more words.
Program enable (PEN) should be held high throughout the reset cycle. PEN can be brought low only when IR
is high. On the following low-to-high transition of WRTCLK, the binary value on 00-07 is stored as the almost
empty offset value (X) and the almost full offset value (Y). Holding PEN low for another low-to-high transition
of WRTCLK reprograms Y to the binary value on 00-07 at the time of the second WRTCLK low-to-high
transition. When the offsets are being programmed, writes to the FIFO memory are disabled regardless of the
state of the write enables (WRTEN1, WRTEN2). A maximum value of 255 can be programmed for either X or
Y (see Figure 4). To use the default values of X = Y = 64, PEN must be held high.

WRTCLK

00-07

IR

WRTENl

WRTEN2~
Figure 4. Programming X and Y Separately

absolute maximum ratings over operating free·air temperature range (unless otherwise noted)t
Supply voltage range, Vee ........................................................ -0.5 V to 4.6 V
Input voltage range, VI (see Note 1) ................................................ -0.5 V to 4.6 V
Output voltage range, Vo (see Notes 1 and 2) ................................. -0.5 V to Vee + 0.5 V
Input clamp current, 11K ( VI < 0) ......................................................... - 50 mA
Output clamp current, 10K ( Vo < 0 or Vo > Vee) .......................................... ± 50 mA
Continuous output current, 10 (VO = 0 to Vee) ........................................... ±50 mA
Continuous current through Vee or GNO ................................................. ± 100 mA
Voltage applied to a disabled 3-state output .................................................. 3.6 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings can be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.

~1ExAs
INSTRUMENTS
10-10 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ALVC7803,SN74ALVC7805,SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW-POWERED CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS436B-JUNE 1994 - REVISED JULY 1995

recommended operating conditions

SN74ALVC7803-20 SN74ALVC7803-25 SN74ALVC7803-40
SN74ALVC7805-20 SN74ALVC7805-25 SN74ALVC7805-40
SN74ALVC7813-20 SN74ALVC7813-25 SN74ALVC7813-40 UNIT
VCC =3.3 V ± 0.3 V VCC =3.3 V ± 0.3 V VCC =3.3 V ± 0.3 V
MIN MAX MIN MAX MIN MAX
VIH High-level input voltage 2 2 2 V
VII Low-level input voltage 0.8 0.8 0.8 V
High-level output current,
IOH VCC=3V -8 -8 -8
Q outputs, Flags
mA
Low-level output current,
IOL VCC= 3V 16 16 16
Q outputs, Flags
fclock Clock frequency 50 40 25 MHz
DO-D17 high or
9 10 14
low
WRTCLK high or
7 8 12
low
RDCLK high or low 7 8 12
tw Pulse duration ns
PEN low 9 9 12
WRTEN1 high,
8 8 12
WRTEN210w
OE1,OE210w 9 9 12
RDEN low 8 8 12
DO-D17 before
5 5 5
WRTCLK1'
WRTEN1, WRTEN2
5 5 5
before WRTCLK1'
OE1, OE2 before
5 6 6
RDCLK1'

Setup time RDEN before

tsu 5 5 7 ns
RDCLK1'
Reset: RESET low
before first
6 6 6
WRTCLK1' and
RDCLKit
PEN before
6 6 6
WRTCLK1'
DO-D17 after
0 0 0
WRTCLK1'
WRTEN1, WRTEN2
0 0 0
after WRTCLK1'
OE1, OE2, RDEN
0 0 0
afterRDCLK1'
th Hold time ns
Reset: RESET low
after fourth
2 2 2
WRTCLK1' and
RDCLKit
PEN low after
2 2 2
WRTCLK1'
TA Operating free-air temperature 0 70 0 70 0 70 'C
.. for reset purposes
t To permit the clock pulse to be utilized

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265 10-11
SN74ALVC7803, SN74ALVC7805, SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW-POWERED CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS436B-JUNE 1994 - REVISED JULY 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP* MAX UNIT
VIK .VCC=3V, IIK=-18mA -1.2 V
VCC = MIN to MAX, IOH =-100 IlA VCC-0.2
VOH Flags, Q outputs V
VCC=3 V, IOH=-8 mA 2.4
Flags, Q outputs VCC = MIN to MAX, IOL = 100 IlA 0.2
VOL Flags VCC=3V, IOL=8mA 0.4 V
Q outputs VCC=3 V, IOL=16mA 0.55
II VCC = 3.6 V, VI =VCC or GND ±5 IlA
IOZ VCC =3.6V, Vo =VCC or GND ±10 IlA
ICC VI = VCC orO 40 IlA
VCC=3.6V, Other inputs at VCC or GND,
LlICC§
One input at VCC - 0.6 V
500 IlA
Ci VCC = 3.3 V, VI = VCC or GND 2.5 pF
Co VCC = 3.3 V, Vo = VCC or GND 5.5 pF
.. shown as MIN or MAX, use the appropriate value specified
t For conditions ., .
.. under recommended operating conditions
1: All typical values are at VCC = 3.3 V, TA = 25°C.
§ This is the supply current for each input that is at one of the specified TIL voltage levels rather than 0 V or VCC.

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 50 pF (unless otherwise noted) (see Figure 7)
SN74ALVC7803-20 SN74ALVC7803-25 SN74ALVC7803-40
SN74ALVC7805-20 SN74ALVC7805-25 SN74ALVC7805-40
FROM TO SN74ALVC7813-20 SN74ALVC7813-25 SN74ALVC7813-40
PARAMETER UNIT
(OUTPUT) PNPUT}
Vcc = 3.3 V ± 0.3 V VCC=3.3V ± 0.3 V VCC=3.3V ± 0.3 V
MIN MAX MIN MAX MIN MAX
WRTCLKor
f max 50 40 25 MHz
RDCLK
tpd RDCLKI AnyQ 4 13 4 15 4 20 ns

tpd WRTCLKI IR 3 11 3 13 3 15 ns
tod RDCLKI OR 3 11 3 13 3 15 ns
tpd WRTCLKI AF/AE 7 19 7 21 7 23 ns
tod RDCLKI AF/AE 7 19 7 21 7 23 ns
tpLH WRTCLKI 7 17 7 19 7 21
HF ns
tpHL RDCLKI 7 18 7 20 7 22
tpLH AF/AE 2 11 2 13 2 15
RESET low ns
tpHL HF 2 12 2 14 2 16
ten 2 11 2 11 2 14
OE1, OE2 AnyQ ns
tdis 2 11 2 14 2 14

operating characteristics, Vee =3.3 V, TA =25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance Outputs enabled CL= 50 pF, f = 5 MHz

~1ExAs
INSTRUMENTS
10-12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ALVC7803, SN74ALVC7805, SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW·POWERED CLOCKED FIRST·IN, FIRST·OUT MEMORIES
SCAS436B- JUNE 1994- REVISED JULY 1995

APPLICATION INFORMATION

SN74ALVC78xx
CLOCK A WRTCLK ROCLK CLOCKB

W/RA WRTEN1 OE1 W/RB

CSA WRTEN2 ROEN CSB

OE2 U
18/
00-017 QO-Q17 BO-817

SN74ALVC78xx
'-- ~ ROCLK WRTCLK
- OE1 WRTEN1
ROEN WRTEN2
L OE2

18
AO-A17 QO-Q17 00-017

Figure 5. Bidirectional Configuration

SN74ALVC78xx
WRTCLK WRTCLK ROCLK ROCLK

WRTEN1 WRTEN1 ROEN -

WRTEN2 WRTEN2 OEI
IR OR

OE2
36
00-017 QO-Q17

-
00-035

IR
-L
r--
SN74ALVC78xx
' - - >WRTCLK ROCLK
-
I OR

'--- WRTEN1 ROEN

WRTEN2 OE1
IR OR r-- r-

OE2 '-

36/
00-017 QO-Q17 QO-Q35

Figure 6. Word·Width Expansion: 512 x 36 Bit, 256 x 36 Bit, and 64 x 36 Bit

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10--13
SN74ALVC7803, SN74ALVC7805, SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW-POWERED CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS436B-JUNE 1.994- REVISED JULY 1995

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
va
CLOCK FREQUENCY

=
fdata 112 fclock
120 =
TA 75°C -t--t--I---I---t--,~--:.01
CL=OpF

OE-~~-~~-~~-~~~

o 10 20 30 40 50 60 70 60 90

fclock - Clock Frequency - MHz

Figure 7

calculating power dissipation

With ICC(f) taken from Figure 7, the dynamic power (Pd), based on all data outputs changing states on each read,
can be calculated by:
Pd = VCC x [ICC(f) + (N x ~ICC x dc)] + r(CL x VCc2 x fo)
A more accurate total power (PT) can be calculated if quiescent power (Pq) is also taken into consideration.
Quiescent power (Pq) can be calculated by:
Pq = VCC x [ICC(I) + (N x ~ICC x dc)]
Total power would be:
PT'= Pd + Pq
The above equations provide worst-case power calculations.
Where:
N = number of inputs driven by TIL levels
~Icc = increase in power supply current for each input at a TIL high level
de = duty cycle of inputs at a TIL high level of 3.4 V
CL = output capacitance load
fo = switching frequency of an output
ICC(I) = idle current, supply current when FIFO is idle .. pF x fclock = 0.2 x fclock
(current is due to free-running clocks)
pF = power factor (the slope of idle current versus clock frequency)
ICC(f) = active current, supply current when FIFO is transferring data

~1ExAs .
INSTRUMENTS
10-14 POST OFFICE BOX 655303 • DAllAS. TEXAS 75285
 SN74ALVC7803, SN74ALVC7805, SN74ALVC7813
512 x 18, 256 x 18, 64 x 18
LOW-POWERED CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS436B - JUNE 1994 - REVISED JULY 1995

PARAMETER MEASUREMENT INFORMATION

o 6V
SI
500 a o Open
From Output ----4I>---_-JV\I\r----'
Under Test
CL =50pF
(see Note A) T 500 a

LOAD CIRCUIT FOR OUTPUTS

14--- tw --+I
1 1 __- - - -

3V Input 3 }(\.1._5_V_ _
3V

OV
OV VOLTAGE WAVEFORMS
PULSE DURATION
Itsu th 1

Data ---'~1.5V ~ 3V
3V
Output
Input _ _- - ' " ~ OV Control 1.5 V
(low-level
VOLTAGE WAVEFORMS 1 ~ ____ OV
enabling)
SETUP AND HOLD TIMES
tpZL --.J 14- 1
1 1 tpLZ~ 14-
Output ----.11 '-.\+ - V- - L~I 3V
(SeeN~:~; .Ll.5V \~-;--- 3V Waveform 1 1
1
1.5 1 I
IV£.L~O~V
----11 1 . OV SI at 6 V VOL
-ioII!.f------..~ 1 1
(see Note C) 1 tpHZ --.I 14-
tPLH I" 1 14.t tpHL
Output
tPZH ~ 14- I
1 1 I ---
Output !1.5V
1 ~-----~n VOH --
1.5V
Waveform 2
SI at GND
___ ..J!~I.~ _~V
VOH

OV
(see Note C)
-------~. VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ,. 10 MHz, Zo = 50 a, tr ,. 2.5 ns, tf ,. 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

3-STATE OUTPUTS (ANY Q)

PARAMETER Rl, R2 cLt SI
tpZH GND
ten 500a 50 pF
tpZL 6V
tpHZ GND
tdis 500 a 50 pF
tpLZ 6V
tpd tPLH/tPHL 500a 50 pF Open
t Includes probe and test-fixture capacitance

Figure 8. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE)

-!!1TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS. TEXAS 75265 10-15
10-16
 SN74ALVC7804, SN74ALVC7806, SN74ALVC7814
512 x 18, 256 x 18, 64 x 18
LOW-POWERED FIRST-IN FIRST-OUT MEMORIES
SCAS437C-

• Operate at 3-Y to 3.6-Y Yee DLPACKAGE

(TOP VIEW)
• Load Clock and Unload Clock Can Be
Asynchronous or Coincident
RESET 1 OE
• Low·Power Advanced CMOS Technology 017 2 017
• Full, Empty, and Half·Full Flags 016 3 016
• Programmable Almost·Fuli/Almost·Empty 015 4 015
Flag 014 5 GNO
• Fast Access Times of 18 ns With a 50·pF 014
Load and All Data Outputs Switching 012 Vee
Simultaneously 011 013
012
• Data Rates From 0 to 40 MHz
011
• 3-State Outputs 010
• Pin Compatible With SN74ACT7804, 08 09
SN74ACT7806, and SN74ACT7814 GNO GNO
• Available in Shrink Small·Outllne 30Q-mil 07 08
Package (DL) Using 25-mil Center·to·Center 06 07
Spacing 05 06
04 05
description 03 Vee
02 04
A FIFO memory is a storage device that allows
01 03
data to be written into and read from its array at
DO 36 02
independent data rates. The SN74ALYC7804,
SN74ALVC7806, and SN74ALVC7814 are 18-bit HF 35 GNO
PEN 34 01
FIFOs with high speed and fast access times.
Data is processed at rates up to 40 MHz with AF/AE 33 00
access times of 18 ns in a bit-parallel format. LOCK UNCK
These memories are designed for 3-V to 3.6-V NC NC
VCC operation. NC NC
Data is written into memory on a low-to-high
transition of the load clock (LOCK) and is read out
on a low-to-high transition of the unload clock
(UNCK). The memory is full when the number of words clocked in exceeds the number of words clocked out
by 512. When the memory is full, LOCK has no effect on the data residing in memory. When the memory is
empty, UNCK has no effect.
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and almost-
full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the memory
is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF output
is high whenever the FIFO contains 256 or more words and low when it contains 255 or less words. The AF/AE
status flag is a programmable flag. The first one or two low-to-high transitions of LOCK after reset are used to
program the almost-empty offset value (X) and the almost·full offset value (V) if program enable (PEN) is low.
The AF/AE flag is high when the FIFO contains X or fewer words or 512 - Y or more words. The AF/AE flag
is low when the FIFO contains between X + 1 and 511 - Y words.

Copyright © 1996, Texas Instruments Incorporated

~~~~~~o~:1: S~~::81;:~t!r::: fe'!-=~m:i
slandord warranty. Production pro<;OSSlng doaa not n _ l y Include
testing 01 all parameters. ~lEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10-17
SN74ALVC7804, SN74ALVC7806, SN74ALVC7814
512 x 18, 256 x 18, 64 x 18
LOW·POWERED FIRST·IN, FIRST·OUT MEMORIES
SCAS437C- JUNE 1994 - REVISED FEBRUARY 1996

description (continued)
A low level on the reset (RESET) resets the internal stack pointers and sets FULL high, AF/AE high, HF low,
and EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset on power up.
The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs.
The data outputs are in the high-impedance state when the output-enable (OE) is high.
The SN74ALVC7804, SN74ALVC7806, and SN74ALVC7814 are characterized for operation from O°C to 70°C.

logic symbolt

ctl
FIFO 512 x 18 or
256 x 18 or
1 64x 18
..1'. RESET
RESET
25 28
LOCK LOCK Full FULL
22
32 Half-Full HF
UNCK UNCK 24
56 Almost Full/Empty AF/AE
OE "- EN1 29

PEN
23

21
.,
"- Program Enable
Empty

r
33
EMPTY

DO 0 0 QO
20 34
01 Q1
19 36
02 Q2.
18 37
03 Q3
17 38
04 Q4
16 40
05 Q5
15 41
06 Q6
14 42
07 Q7
12 43
08 Q8

~ ~1V
11 45
09 Q9
9 46
010 Q10
8 47
011 Q11
7 48
012 Q12
6 49
013 Q13
5 51
014 Q14
4 53
015 Q15
3 54
016 Q16
2 55
017 17 17 Q17

t This symbol is in accordance with ANSI/IEEE Sid 91-1984 and lEe Publication 617-12.

~TEXAS
INSTRUMENTS
10-18 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ALVC7804, SN74ALVC7806, SN74ALVC7814
512 x 18, 256 x 18, 64 x 18
LOW-POWERED FIRST-IN, FIRST-OUT MEMORIES
SCAS437C-JUNE 1994 - REVISED FEBRUARY 1996

functional block diagram

OE

00-017

J
RAM
Read
UNCK Pointer
f--+-
512 x 18 ('7804)
256 x 18 ('7806)
I 64 x 18 (,7814)
Write I
LOCK
Pointer -

I .1"-
~ QO-Q17

Reset
Logic r-
I
Status-
Flag
EMPTY
FULL

HF
Logic
AF/AE

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
Almost full/almost empty flag. Depth-offset values can be programmed for this flag or the default
value of 64 can be used for both the almost empty offset (X) and the almost full offset (Y). AF/AE
AF/AE 24 0
is high when memory contains X or fewer words or 512 - Y or more words. AF/AE is high after
reset.
2-9,11-12,
00-017 I 18-bit data input port
14-21
EMPTY 29 0 Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.
FULL 28 0 Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF 22 0 Half-full flag. HF is high when the FIFO memory contains 256 or more words. HF is low aiter reset.
LOCK 25 I Load clock. Data is written to the FIFO on the rising edge of LOCK when FULL is high.
OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state.
Program enable. After reset and before the first word is written to the FIFO, the binary value on
PEN 23 I
00-07 is latched as an AF/AE offset value when PEN is low and WRTCLK is high.
33-34,36-38,
00-017 40-43,45-49, 0 18-bit data output port
51,53-55
Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and
RESET 1 I
EMPTY low.
UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.

-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10-19
SN74ALVC7804, SN74ALVC7806, SN74ALVC7814
512 x 18, 256 x 18, 64 x 18
LOW-POWERED FIRST-IN, FIRST-OUT MEMORIES
SCAS437C-JUNE 1994- REVISED FEBRUARY 1996

_ 0

CD
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CD
a:

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'0 :s
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~TEXAS
INSTRUMENTS
10-20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ALVC7804, SN74ALVC7806, SN74ALVC7814
512 x 18, 256 x 18, 64 x 18
LOW-POWERED FIRST-IN, FIRST-OUT MEMORIES
SCAS437C - JUNE 1994 - REVISED FEBRUARY 1996

DATA WORD NUMBERS FOR FLAG TRANSITIONS

TRANSITION WORD
DEVICE
A B C 0 E F G H I
SN74ALVC7814 W32 W(64-Y) W64 W33 W34 W(64-X) W(65-X) W64 W64
SN74ALVC7806 W128 W(256-Y) W256 W129 W130 W(256-X) W(257-X) W255 W256
SN74ALVC7804 W256 W(512-Y) W512 W257 W258 W(512-X) W(513-X) W511 W512

Figure 1. Write, Read, and Flag Timing Reference (Continued)

offset values for AF/AE

The aimost-fuil/almost-empty (AF/AE) flag has two programmable limits: the almost-empty offset value (X) and
the almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is
written to memory. The AF/AE flag is high when the FIFO contains X or fewer words or 512 - Y or more words.
To program the offset values, PEN can be brought low after reset. On the following low-to-high transition of
LOCK, the binary value on 00-07 is stored as the almost-empty offset value (X) and the almost-full offset value
(Y). Holding PEN low for another low-to-high transition of LOCK reprograms Y to the binary value on 00-07
at the time of the second LOCK low-to-high transition. Writes to the FIFO memory are disabled while the offsets
are programmed. A maximum value of 255 can be programmed for either X or Y (see Figure 2). To use the
default values of X = Y = 64, PEN must be held high.

LOCK

X'--_y------Jx"-____
/
Figure 2. Programming Xand Y Separately

-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10-21
SN74ALVC7804, SN74ALVC7806, SN74ALVC7814
512 x 18, 256 x 18, 64 x 18
LOW-POWERED FIRST-IN, FIRST-OUT MEMORIES
SCAS437C - JUNE 1994 - REVISED FEBRUARY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee ........................................................ -0.5 V to 4.6 V
Input voltage range, VI (see Note 1) ................................................ -0.5 V to 4.6 V
Output voltage range, Va (see Notes 1 and 2) ................................. -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0) .......................................................... -50 mA
Output clamp current, 10K (Va < 0 or Va > Ved ........................................... ± 50 mA
Continuous output current, 10 (Va =0 to Vee) ............................................ ±50 mA
Continuous current through Vee or GND ................................................. ± 100 mA
Voltage applied to a disabled 3-state output .................................................. 3.6 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other cond~ions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings can be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.

recommended operating conditions

SN74ALVC7804-25 SN74ALVC7804-40
SN74ALVC78!&25 SN74ALVC7806-40
SN74ALVC7814-25 SN74ALVC7814-40 UNIT
VCC = 3.3 V ::I: 0.3 V VCC=3.3V::I: 0.3 V
MIN MAX MIN MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VI InputvoHage 0 VCC 0 VCC V
Vo Output voltage 0 VCC 0 VCC V
High-level output current,
IOH VCC=3V -8 -8 mA
Q outputs, flags
Low-level output current,
IOL VCC-3V 16 16 mA
Q outputs, flags
fclock Clock frequency 40 25 MHz
DO-017 high or low 8 12
LOCK high or low 8 12
tw Pulse duration UNCK high or low 8 12 ns
PEN low 8 12
RESET low 10 12
00-017 before LOCK1' 5 5
tsu Setup time LOCK inactive before RESET high 6 6 ns
PEN before LOCKi 8 8
DO-017 after LOCK1' 0 0
PEN high after LOCK low 0 0
th Hold time ns
PEN low after LOCK1' 3 3
LOCK inactive after RESET high 6 6
TA Operating free-air temperature 0 70 0 70 ·C

~1ExAs
INSTRUMENTS
10-22 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74AlVC7804, SN74AlVC7806, SN74AlVC7814
512 x 18, 256 x 18, 64 x 18
lOW-POWERED FIRST-IN, FIRST-OUT MEMORIES
SCAS437C - JUNE 1994 - REVISED FEBRUARY 1996

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT
VCC = MIN to MAX, 10H = -100!lA VCC- 0.2
VOH Flags, Q outputs V
VCC=3V, 10H =-8 mA 2.4
Flags, Q outputs VCC = MIN to MAX, 10L = 100!lA 0.2
VOL Flags VCC = 3 V, 10L= 8 mA 0.4 V
Qoutputs VCC=3V, 10L= 16 mA 0.55
II VCC = 3.6 V, VI =VCC or GND ±5 !lA
10Z VCC = 3.6 V, Vo =VCC or GND ±10 !lA
ICC VCC =3.6 V, VI = VCC or GND and 10 = 0 40 !lA
VCC = 3.6 V, One input at VCC-0.6 V,
AICC§ 500 !lA
Other inputs at VCC or GND
Ci VCC =3.3 V, VI = VCC or GND 3 pF
Co VCC = 3.3 V, Vo = VCC or GND 6 pF
.. shown as MIN or MAX, use the appropriate value specliled
t For condItIons .. .
.. under recommended operatmg condItIons
:j: All typical values are at V CC = 3.3 V, TA = 25°C.
§ This is the supply current lor each input that is at one 01 the specified TTL voltage levels rather than 0 V or Vcc.

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 50 pF (unless otherwise noted) (see Figure 4)
SN74ALVC7804-25 SN74ALVC7804-40
SN74ALVC7806-25 SN74ALVC7806-40
FROM TO SN74ALVC7814-25 SN74ALVC7814-40
PARAMETER UNIT
(INPUT) (OUTPUT)
VCC=3.3V ± 0.3 V VCC = 3.3 V ± 0.3 V
MIN MAX MIN MAX

'max LDCKor UNCK 40 25 MHz

tpd LDCK1' 9 22 9 24
AnyQ ns
tod UNCK1' 6 18 6 20
tPLH LDCK1' 6 17 6 19
tpHL UNCK1' EMPTY 6 17 6 19 ns
tpHL RESET low 4 18 4 20
tpHL LDCK1' 6 17 6 19
tpLH UNCK1' FULL 6 17 6 19 ns
tpLH RESET low 4 20 4 22
tpd LDCK1' 7 20 7 22
tod UNCK1' AF/AE 7 20 7 22 ns
tpLH RESET low 2 12 2 14
tpLH LDCK1' 5 20 5 22
tpHL UNCK1' HF 7 20 7 22 ns
tpHL RESET low 3 14 3 16
ten 2 10 2 11
OE AnyQ ns
tdis 2 11 2 12

operating characteristics, Vee =3.3 V, TA =25°C

PARAMETER TEST CONDITIONS
Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, 1= 5 MHz

-!II TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 10-23
SN74ALVC7804, SN74ALVC7806, SN74ALVC7814'
512 x 18, 256 x 18, 64 x 18
LOW-POWERED FIRST-IN, FIRST-OUT MEMORIES
SCAS437C-JUNE 1994-REVISED FEBRUARY 1996

APPLICATION INFORMATION

SN74ALVC78xx
LOCK LOCK UNCK UNCK

-
-4
~
FULL EMPTY

OE
-
I

018-035 00-017 QO-Q17 Q18-Q35

SN74ALVC78xx
'--- > LOCK UNCK

FULL EMPTY f- -

OE f-

00-017 00-017 QO-Q17 QO-Q17

Figure 3. Word·Width Expansion: 512 x 36 Bit, 256 x 36 Bit, and 64 x 36 Bit

~1ExAs
INSTRUMENTS
10-24 POST OFFICE BOX 655303- DALlAS, TEXAS 75265
 SN74ALVC7804,SN74ALVC7806,SN74ALVC7814
512 x 18, 256 x 18, 64 x 18
LOW·POWERED FIRST·IN, FIRST·OUT MEMORIES
SCAS437C - JUNE 1994 - REVISED FEBRUARY 1996

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY

=
fdata 1/2 fclock
120 =
TA 75°C --+---+--t--I---t-~+-,
~ CL=OpF
I

O~~-~~-~~-~-~~~

o 10 20 30 40 50 60 70 80 90
fclock - Clock Frequency - MHz

Figure 4

calculating power dissipation

With ICC(f) taken from Figure 4, the dynamic power (Pd) based on all data outputs changing states on each read
can be calculated by:
Pd = VCC x [ICC(f) + (N x ~Icc x dc)] + :E(CL x VCc2 x fa)

A more accurate total power (PT) can be calculated if quiescent power (Pq) is also taken into consideration.
Quiescent power (P q) can be calculated by:
Pq = VCC x [ICC(I) + (N x ~Icc x dc)]

Total power is:

PT= Pd + Pq

The above equations provide worst-case power calculations.

Where:
N number of inputs driven by TIL levels
~Icc increase in power supply current for each input at a TIL high level
dc duty cycle of inputs at a TIL high level of 3.4 V
CL output capacitance load
fa switching frequency of an output
ICC(I) idle current, supply current when FIFO is idle ~ pF x fclock = 0.2 x fclock
(current is due to free-running clocks)
pF power factor
ICC(f) active current, supply current when FIFO is transferring data

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 10-25
SN74ALVC7804, SN74ALVC7806, SN74ALVC7814
512 x 18, 256 x 18, 64 x 18
LOW-POWERED FIRST-IN, FIRST-OUT MEMORIES
SCAS437C - JUNE 1994 - REVISED FEBRUARY 1996

PARAMETER MEASUREMENT INFORMATION

o 6V

soon
Sl o Open
From Output_-e_~t---'INIr-_-J
Under Test
CL=SOpF
(see Note A) T soon

LOAD CIRCUIT FOR OUTPUTS

14-- tw ----+I
1 I~____

Timing
Input ___ ~_-J~~1._S_V__~___
3V

OV
Input 3 X\,,1._S_V_ _ : :

VOLTAGE WAVEFORMS
~ tsu .~ th ·1 PULSE DURATION
1 1
Data
Input J .. 1.S_V
____ ~ :: Output
Control
(low-level
1.SV 1.SV
3V

VOLTAGE WAVEFORMS I ~ ____ ov

enabling)
SETUP AND HOLD TIMES
tPZL....J ~ I
tpLZ~ 14-
_-+I, ___ Lrv:=I-
I I

(SeeN~:~~ --.A 1.SV \~-;--- 3V

1 OV
Output
wa;~~~~~
I I
I
1.SV· I
IV£L~O~V
3V

VOL
I
-""~I--~~ I
(see Note C) I tpHZ -.I !.-
I ~1

Output
tPLH I'"

________J.
1
Ir----~~--VOH
!1.SV
14
I
tpHL

1.SV
VOL
Output tpZH
Waveform 2
S1 at G N D 1 . S V
-+I

(see Note C) _ _ _....._'-- -

I 14-

-
I
~- --
VOH -0.3 V
-
VOH

0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR s 10 MHz, Zo a 50 tr s 2.5 ns, tf S 2.5 ns. n.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

3-STATE OUTPUTS (ANY Q)

PARAMETER R1,R2 cLt S1
tpZH GND
ten 500n 50pF
tpZL 6V
tPHZ GND
tdis 500n 50pF
tpLZ 6V
tpd tpLH/tPHL 500n 50pF Open
t Includes probe and tesl-flxture capacitance

Figure 5. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE)

~TEXAS .
INSTRUMENTS
10-26 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
11-1
 DSP 32· AND 36·BIT CLOCKED FIFOS
Features Benefits

• 36-bit FIFO interface • Single-chip implementation for high levels

of intergration
• Bidirectional 32-bit and 36-bit options • Two dual-port SRAMs allow true
bidirectional capability.
• Depths from 256 to 2K words • Multiple depths to optimize system
storage applications
• Mailbox-register bypass • Quick access to priority information
• Microprocessor-control circuitry • Interface matches most processors and
DSP bus-cycle timing and
communications
• Synchronous retransmit option • Permits user-defined retransmission point
• Multiple default values for separate AF • Easy alternatives for flag settings
and AE flags
Q • Parallel and serial flag programming • Choice of status-flag programming modes
o
n option~
• 67% less board space than equivalent
; • EIAJ standard 120-pin thin quad flat 132-pin PQFPs; over 66% less board
c. package (TQFP) space than four 9-bit 32-pin PLCC
!! equivalents
"'T1
oen • TI has established alternate source
options
• Standardization that comes from a
common second source

III

11-2
 SN74ACT3631
512 x 36
FIRST·OUT MEMORY
- REVISED SEPTEMBER 1995

• Free-Running ClKA and ClKB Can Be • Output-Ready and Almost-Empty Flags

Asynchronous or Coincident Synchronized by ClKB
• Clocked FIFO Buffering Data From Port A • low-Power O.8-Mlcron Advanced CMOS
to Port B Technology
• Synchronous Read-Retransmit Capability • Supports Clock Frequencies up to 67 MHz
• Mailbox Register in Each Direction • Fast Access Times of 11 ns
• Programmable Almost-Full and • Pin-to-Pin Compatible With the
Almost-Empty Flags SN74ACT3641 and SN74ACT3651
• Microprocessor Interface Control logic • Available in Space-Saving 12o-Pin Thin
• Input-Ready and Almost-Full Flags Quad Flat (PCB) and 132-Pin Plastic Quad
Synchronized by ClKA Flat (PQ) Packages

description
The SN74ACT3631 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies
up to 67 MHz and has read access times as fast as 11 ns. The 512 x 36 dual-port SRAM FIFO buffers data from
port A to port B. The FI FO memory has retransmit capability, which allows previously read data to be accessed
again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and
almost empty) to indicatewhen a selected number of words is stored in memory. Communication between each
port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail
has been stored. Two or more devices can be used in parallel to create wider data paths. Expansion is also
possible in word depth.
The SN74ACT3631 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to ClKA. The
output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to ClKS. Offset
values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input.
The SN74ACT3631 is characterized for operation from O°C to 70°C.
For more information on this device family, see the application reports FIFO Patented Synchronous Retransmit:
Programmable DSP-Interface Application for FIR Filtering and FIFO Mailbox-Bypass Registers: Using Bypass
Registers to Initialize DMA Control in the 1996 High-Performance FIFO Memories DeSigner's Handbook,
literature number SCAA012A.

Copyright © 1995, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-3
SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCA.S246F~ AUGUST 1993 - REVISED SEPTEMBER 1995

~~~~~~~~~E~~~~~~~~~~§g~~~~~~~m
A35 1 90 835
A34 2 89 834
A33 3 M 833
A32 4 ~ 832
Vee 5 M GND
A31 6 M 831
A30 7 ~ 830
GND 8 ~ 829
A29 9 ~ 828
A28 10 827
A27 11 826
A26 12 Vee
A25 13 825
A24 14 824
A23 15 GND
GND 16 823
A22 17 822
Vee 18 821
A21 19 820
A20 20 819
A19 21 818
A18 22 GND
GND 23 817
A17 24 816
A16 25 Vee
A15 26 815
A14 27 814
A13 28 813
Vee 29 812
A12 GND

Ne - No internal connection

~TEXAS
INSTRUMENTS
11-4 POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
 SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

NC NC
835 NC
834 A35
833 A34
832 A33
GND A32
831 Vee
830 A31
829 A30
828 GND
827 A29
826 A28
Vee A27
825 A26
824 A25
GND A24
823 A23
822 GND
821 A22
820 Vee
819 A21
818 A20
GND A19
817 A18
816 GND
Vee A17
815 A16
814 A15
813 A14
812 A13
GND Vec
NC A12
NC NC

NC - No internal connection
t Uses Yamaichi socket IC51-1324-828

~1ExAs
INSTRUMENTS
POST OFFICE BOX 666303 • DAUAS. TEXAS 75285 11-5
SN74ACT3631
512 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS2l46F - AUGUST 1993 - REVISED SEPTEMBER 1995

functional block diagram

I
•
Mall1
Register
I
MBF1

~~
ClKA - I
CSA -

........ -I
Port-A
WiRA - Control
ENA - logic r- r--
MBA - I--
5!'
II: ... 512 x 36
~
*
l
SRAM ::I
'S
Reset c. %
0 r+-
logic
- .5

T :!:: ....
RTM
36 .c E (,)
(,) f1)._
c c ... f-+
>- t! 0

.. I
I Write
Pointer
II Read
Pointer
~
(/)1j..J

II:
, RFM

AO-A35
t t BO-B35

IR Status-Flag I OR
I I
AF logic I AE

+
FSO/SD Flag-Offset

~
FS1/SEN Register r-- ClKB
Port-B CSB
10 '-- r-- Control

~
W/RB
logic
Mall2 I ENB
"<~ Register I f+- MBB

-!!1 TEXAS
INSTRUMENTS
11-6 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMijE\!-11195

Terml.nal Functions
TERMINAL
1/0 DESCRIPTION
NAME
AO-A35 1/0 Port-A data. The 36-bit bidirectional data port for side A.
Almost-empty flag. Programmable flag synchronized to ClKB. AE is low when the number of words in the FIFO is less
AE 0
than or equal to the value in the almost-empty offset register (X).
Almost-full flag. Programmable flag synchronized to ClKA. AF is low when the number of empty locations in the FIFO
AF 0
is less than or equal to the value in the almost-full offset register (Y).
BO-B35 1/0 Port-B data. The 36-bit bidirectional data port for Side B.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
ClKA I
or coincident to ClKB. IR and AF are synchronous to the low-ta-high transHion of ClKA.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
ClKB I
or coincident to ClKA. OR and AE are synchronous to the Iow-ta-high transition of ClKB.
Port-A chip select. CSA must be low to enable a low-ta-high transition of ClKA to read or write data on port A. The
GSA I
AO-A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-ta-high transition of ClKB to read or write data on port B. The
CSB I
.BO-B35 outputs are in the high-impedance state when CSB is high.
ENA I Port-A master enable. ENA must be high to enable a low-ta-high transition of ClKA to read or write data on port A.
ENB I Port-B master enable. ENB must be high to enable a low-ta-hlgh transition of ClKB to read or write data on port B.
Flag offset select 1/serial enable, flag offset select OIserial data. FSlISEN and FSO/SD are dual-purpose Inputs used
for flag offset register programming. During a device reset, FS1/SEN and FSO/SD select the lIag offset programming
method. Three offset register programming methods are available: automatically load one of two preset values, parallel
FS1/SEN, load from port A, and serial load.
I
FSO/SD When serial load is selected for flag offset register programming, FS 1/SEN is used es an enable synchronous to the
low-ta-high transition of ClKA. When FS1/SEN is low, a rising edge on ClKA loads the bit present on FSO/SD Into the
X and V offset registers. The number of bit writes required to program the offset register is 18. The first bit write stores
the V-register MSB and the last bit write stores the X-register lSB.
Input-ready flag. IR is synchronized to the low-ta-high transition of ClKA. When IR is low, the FIFO is full and writes to
IR 0 its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point
of the retransmit data and prevents further writes. IR Is set low during reset and is set high aiter reset.
MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
MBB I BO-B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
FIFO data for output.
Mail1 register flag. MBF1 is set low by the low-ta-high transition of ClKA that writes data to the mail1 register. MBF1
MBF1 0 is set high by a low-ta-high transition of ClKB when a port-B read is selected and MBB is high. MBF1 is set high by a
reset.
Mail2 register flag. MBF2 Is set low by the low-ta-high transition of ClKB that writes data to the mail2 register. MBF2
MBF2 0 is set high by a low-ta-high transition of ClKA when a port-A read Is selected and MBA is high. MBF2 is set high bya.
reset.
Output-ready flag. OR is synchronized to the low-ta-high transition of ClKB. When OR is low, the FIFO is empty and
OR 0 reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during
the reset and goes high on the third low-ta-high transition of ClKB aiter a word is loaded to empty memory.
Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-ta-high transition of ClKB to reset
RFM I
the read pOinter to the beginning retransmit location and output the first selected retransmit data.
Reset. To reset the device, four low-ta-high transitions of CLKA and four Iow-to-high transitions of ClKB must occur
RST I
while RST is low. The low-ta-hlgh transition of RST latches the status of FSO and FS1 for AF and AE offset selection.
Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR Is high), a low-ta-high
transition of ClKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected
RTM I
word remains the initial retransmH point until a low-ta-high transition of ClKB occurs while RTM is low, taking the FIFO
out of retransmit mode.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75285 .11-,·7
SN74ACT3631
512 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

Terminal Functions (Continued)

TERMINAL
I/O DESCRIPTION
NAME
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a
WiRA I
low-ta-high transition of ClKA. The AO-A35 outputs are in the high-impedance state when WiRA is high.
Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a
W/RB I
low-ta-high transition of ClKB. The BO-B35 outputs are in the high-impedance state when W/RB is low.

detailed description
reset
The SN74ACT3631 is reset by taking the reset (RST) input low for at least four port-A clock (ClKA) and four
port-B clock (ClKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset
initializes the memory read and write pointers and forces the input-ready (IR) flag low, the output-ready (OR)
flag high, the almost-empty (AE) flag low, and the almost-full (AF) flag high. Resetting the device also forces
the mailbox flags (MBF1, MBF2) high. After a FIFO is reset, its input-ready flag is set high after at least two clock
cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory.
almost-empty flag and almost-full flag offset programming
Two registers in the SN74ACT3631 are used to hold the offset values for the almost-empty and almost-full flags.
The almost-empty (AE) flag offset register is labeled X, and the almost-full (AF) flag offset register is labeled Y.
The offset registers can be loaded with a value in three ways: one of two preset values are loaded into the offset
registers, parallel load from port A, or serial load. The offset register programming mode is chosen by the flag
select (FS 1, FSO) inputs during a low-to-high transition on the RST input (see Table 1).

Table 1. Flag Programming

FS1 FSO RST X AND Y REGISTERSt
H H i Serial load
H l i 64
l H i 8
l l i Parallel load from port A
t X register holds the offset for AE; Y register holds the
offset for AF.

preset values
If a preset value of 8 or 64 is chosen by FS1 and FSO at the time of a RST low-to-high transition according to
Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is
necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on ClKA.
parallel load from port A
To program the X and Y registers from port A, the device is reset with FSO and FS1 low during the low-to-high
transition of RST. After this reset is complete, the IR flag is set high after two low-to-high transitions on ClKA.
The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X.
Each offset register of the SN74ACT3631 uses port-A inputs (AB-AO). The highest number input is used as
the most significant bit of the binary number in each/case. Each register value can be programmed from 1 to
508. After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM.

~ThXAS
INSTRUMENTS
11-8 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3631
512 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

seria//oad
To serially program the X and Y registers, the device is reset with FSO/SD and FS1/SEN high during the
low-to-high transition of RST. After this reset is complete, the X and Y register values are loaded bitwise through
FSO/SD on each low-to-high transition of CLKA that FS 1/SEN is low. Writes of 18 bits are needed to complete
the programming. The first-bit write stores the most significant bit of the Y register, and the last-bit write stores
the least significant bit of the X register. Each register value can be programmed from 1 to 508.
When the option to program the offset registers serially is chosen, the input-ready (IR) flag remains low until
all register bits are written. The IR flag is set high by the low-to-high transition of CLKA after the last bit is loaded
to allow normal FIFO operation.
FIFO write/read operation
The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (WiRA). The AO-A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The AO-A35 outputs are active when both CSA and W/RA are low.
Data is loaded into the FIFO from the AO-A35 inputs on a low-to-high transition of CLKA when CSA and the
port-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the input-ready (IR) flag are high
(see Table 2). Writes to the FIFO are independent of any concurrent FIFO reads.

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA AO-A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-Impedance state None
L H H L i In high-impedance state FIFO write
L H H H i In high-impedance state Mail1 write
L L L L X Active, mail2 register None
L L H L i Active, mail2 register None
L L L H X Active, mail2 register None
L L H H i Active, mail2 register Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A with the exception that the port-B write/read select
(W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (BO-B35) outputs is
controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The BO-B35 outputs are
in the high-impedance state when either CSB is high orW/RB is low. The BO-B35 outputs are active when CSB
is low and W/RB is high.
Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB and the port-B
mailbox select (MBB) are low, W/RB, the port-B enable (ENB), and the output-ready (OR) flag are high
(see Table 3). Reads from the FIFO are independent of any concurrent FIFO writes.

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS, TeXAs 75265 11-9
SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SC'AS246F '" AUGUST 1993 - REVISED SEPTEMBER 1995

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

CSB W/RB ENB MBB ClKB BO-B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L L L X X In high-impedance state None
L L H l l' In high-impedance state None
L L H H l' In high-impedance state Mail2write
L H L l X Active, FIFO output register None
L H H L l' Active, FIFO output register FIFO read
L H L H X Active, mail1 register None
L H H H l' Active, mail1 register Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select can change states during the
setup- and hold-time window of the cycle.
When the output-ready (OR) flag is low, the next data word is sent to the FIFO output register automatically by
the ClKB low-to-high transition that sets the output-ready flag high. When OR is high, an available data word
is clocked to the FIFO output register only when a FIFO read is selected by the port-B chip select (CSB),
write/read select (W/RB), enable (EN B), and mailbox select (MBB).
synchronized FIFO flags
Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the
flags' reliability by reducing the probability of metastable events on their outputs when ClKA and ClKB operate
asynchronously to one another (see the application report Metastability Performance of Clocked FIFOs in the
1996 High-Performance FIFO Memories Data Book, literature number SCAD003C). OR and AE are
synchronized to ClKS. IR and AF are synchronized to ClKA. Table 4 shows the relationship of each flag to the
number of words stored in memory.

Table 4. FIFO Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS IN TOClKB TOClKA
FIF011
OR AE AF IR
0 L L H H
1 toX H L H H
(X + 1) to [512 - (Y + 1)1 H H H H
(512 - Y) to 511 H H L H
512 H H L L
t X is the almost-empty offset for AE. Y is the almost-full offset for AF.
:j: When a word is present in the FI FO output register, its previous memory
location is free.

~TEXAS
INSTRUMENTS
11-10 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

output-ready flag (OR)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array (ClKS). When
the output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low,
the previous data word is present in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine
that controls an output-ready flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is empty, empty+ 1, or empty+2. From the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of ClKS; therefore, an output-ready flag is low if a word
in memory is the next data to be sent to the FIFO output register and three ClKS cycles have not elapsed since
the time the word was written. The output-ready flag of the FI FO remains low until the third low-to-high transition '
of ClKS occurs, simultaneously forcing the output-ready flag high and shifting the word to the FIFO output
register.
A lowcto-high transition on ClKS begins the first synchronization cycle of a write if the clock transition
occurs at time tsk(1), or greater, after the write. Otherwise, the subsequent ClKS cycle can be the first
synchronization cycle (see Figure 6).
input-ready flag (IR)
The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array (ClKA). When the
input-ready flag is high, a memory location is free in the SRAM to write new data. No memory locations are free
when the input-ready flag is low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an
input-ready flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM
status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready
to be written in a minimum of three cycles of ClKA; therefore, an input-ready flag is low if less than two cycles
of ClKA have elapsed since the next memory write location has been read. The second low-to-high transition
on ClKA after the read sets the input-ready flag high, and data can be written in the following cycle.
A low-to-high transition on ClKA begins the first synchronization cycle of a read if the clock transition
occurs at time tsk(1), or greater, after the read. Otherwise, the subsequent ClKA cycle can be the first
synchronization cycle (see Figure 7).
almost-empty flag (AE)
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array (ClKS). The
state machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that
indicates when the FI FO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty
state is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset,
programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset
programming). The almost-empty flag is low when the FIFO contains X or fewer words and is high when the
FIFO contains (X + 1) or more words. A data word present in the FIFO output register has been read from
memory.
Two low-to-high transitions of ClKS are required after a FIFO write for the almost-empty flag to reflect the new
level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1) or more words remains low iftwo cycles
of ClKS have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set
high by the second low-to-high transition of ClKS after the FIFO write that fills memory to the (X + 1) level.
A low-to-high transition of ClKS begins the first synchronization cycle if it occurs at time tsk(2), or greater, after
the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent ClKS cycle can be the first
synchronization cycle (see Figure 8).

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-11
SN74ACT3631
512 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

almost-full flag (AF)

The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). The state
machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by
the contents of register Y. This register is loaded with a preset value during a FIFO reset, programmed from port
A, or programmed serially (see almost-empty flag and almost-full flag offset programmin{j). The almost-full flag
is low when the number of words in the FIFO is greater than or equal to (512 - V). The almost-full flag is high
when the number of words in the FIFO is less than or equal to [512 - (Y + 1)]. A data word present in the FIFO
output register has been read from memory.
Two low-to-high transitions of CLKA are required after a FIFO read for its almost-full flag to reflect the new level
offill; therefore, the almost-full flag of a FIFO containing [512 - (Y + 1)] or fewer words remains low if two cycles
of CLKA have not elapsed since the read that reduced the number of words in memory to [512 - (Y + 1)]. An
almost-full flag is set high by the second low-to-high transition of CLKA after the FIFO read that reduces the
number of words in memory to [512 - (Y + 1)]. A low-to-high transition of CLKA begins the first synchronization
cycle if it occurs at time tsk(2), or greater, after the read that reduces the number of words in memory to
[512 - (Y + 1)]. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 9).
synchronous retransmit
The synchronous-retransmit feature of the SN74ACT3631 allows FIFO data to be read repeatedly starting at
a user-selected position. The FIFO is first put into retransmit mode to select a beginning word and prevent
on-going FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three
words can retransmit repeatedly starting at the selected word. The FIFO can be taken out of retransmit mode
at any time and allow normal device operation.
The FIFO is put in retransmit mode by a low-to-high transition on CLKS when the retransmit-mode (RTM) input
is high and OR is high. This rising CLKS edge marks the data present in the FIFO output register as the first
retransmit data. The FIFO remains in retransmit mode until a low-to-high transition occurs while RTM is low.
When two or more reads occur after the initial retransmit word, a retransmit is initiated by a low-to-high transition
on CLKS when the read-from-mark (RFM) input is high. This rising CLKS edge shifts the first retransmit word
to the FIFO output register and subsequent reads can begin immediately. Retransmit loops can be done
endlessly while the FIFO is in retransmit mode. RFM must be low during the CLKS rising edge that takes the
FIFO out of retransmit mode.
When the FI FO is put into retransmit mode, it operates with two read pointers. The current read pointer operates
normally, incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE
flags. The shadow read pOinter stores the SRAM location at the time the device is put into retransmit mode and
does not change until the device is taken out of retransmit mode. The shadow read pOinter is used by the IR
and AF flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set low by the write that
stores (512 - Y) words after the first retransmit word. The IR flag is set low by the 512th write after the first
retransmit word.
When the FIFO is in retransmit mode and RFM is high, a rising CLKS edge loads the current read pOinter with
the shadow read-pointer value and the OR flag reflects the new level of fill immediately. If the retransmit changes
the FIFO status out of the almost-empty range, up to two CLKS rising edges after the retransmit cycle are
needed to switch AE high (see Figure 11). The rising ClKS edge that takes the FIFO out of retransmit mode
shifts the read pointer used by the IR and AF flags from the shadow to the current read pOinter. If the change
of read pointer used by IR and AF should cause one or both flags to transition high, at least two CLKA
synchronizing cycles are needed before the flags reflectthe change. A rising CLKA edge after the FIFO is taken
out of retransmit mode is the first synchronizing cycle of IR if it occurs at time tsk(1) or greater after the rising
CLKS edge (see Figure 12). A rising CLKA edge after the FIFO is taken out of retransmit mode is the first
synchronizing cycle of AF if it occurs at time t sk(2), or greater, after the rising CLKS edge (see Figure 14).

~TEXAS
INSTRUMENTS
11-12 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

mailbox registers
Two 36-bit bypass registers pass command and control information between port A and port B. The
mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation.
A low-to-high transition on ClKA writes AO-A35 data to the mail1 register when a port-A write is selected by
CSA, W/RA, and ENA with MBA high. A low-to-high transition on ClKB writes 80-B35 data to the mail2 register
when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mail register sets its
corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while its mail flag is
low.
When the port-B data (BO-B35) outputs are active, the data on the bus comes from the FIFO output register
when the port-B mailbox select (MBB) input is low and from themail1registerwhenMBBishigh.Mail2 data
is always present on the port-A data (AO-A35) outputs when they are active. The mail1 register flag (MBF1)
is set high by a low-to-high transition on ClKB when a port-B read is selected by CSB, W/RB, and ENB with
MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on ClKA when a port-A read
is selected by CSA, W/RA, and ENA with MBA high. The data in a mail register remains intact after it is read
and changes only when new data is written to the register.

ClKA
--tI I.- th(RS)
ClKB

_ _ _ _......1
r-.I tsu(RS) 1
1
1
1
~
1 It

tsu(FS) 1:-r"1 I
h(FS)
.
I
I
I
RST \, 1 II I
1 1 1 I
FS1,FSO

~ tpd(C-IR) It----.J 1 tpd(C-IR) i----l

IR 0&\\\\\\\\\\\~W. : 1'----
tpd(C-OR) 1.----.1
OR&~~~~
tpd(R-F) !----.J
AE \\\\\\\$s\~
tpd(R-F) I.----.i
AFVZZTA;vA
__ tpd(R-F) J+------tI
~B:F~ mzzzzzzzz]
Figure 1_ FIFO Reset Loading X and Y With a Preset Value of Eight

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-13
SN74ACT3631
512 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

CLKA
1 1 I
I .
RS'f
- - 1• 1 .J.
.
tau(FS) I ~ 14- th(FS)
1
I.
1
I
I
I
I
I
I
FS1,FSO ~ w!///Z2ZW(ZVVi
tpd(C-IR) ~ .1 I I
IR Y 1 I
I tau EN ~I It- th(EN)
ENA 0ZZZl/llT///lA/lVlZZZZlA' ! ~ W2QQ? ~)$'
-+' J+: th(D)

AO-A35
AF Offset AE Offset First Word Stored In FIFO
(Y) (X)

NOTE A: GSA - L. WiRA = H. MBA - L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the Almost·Fuli Flag and Almost-Empty Flag Offset Values From Port A

CLKA
I I
RST _ _-"",
II II

1 I Ipd(C-IR) ~~_~.I
IR ______ ~I--------------~~------------~(\T(----~I~------------Jy--
1- ----+J ~ I+-
th(SP) --+I I+-
th(SEN) L Ii th(SEN)
tau(FS) I-i J+-tJ 1
tau(SEN) .. H 1 u(SEN)
FS1/SEN ""Z2L2J~"""';"";-11---~~;.;.c,\ I mm.. ~~ n~2"'2"'2"-:2"-:2""2I:"'z"'z"'2"'2"'2"'2'"
I ::::;j ~ - Fth(SD)

FSOISD ;;;;14::::::i
AF Offset AE Offset
(y) MSS (X) LSS

NOTE A: It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored untillR is set high.

Figure 3. Serially Programming th~ Almost-Full Flag and Almost-Empty Flag Offset Values

-!111ExAs
INSTRUMENTS
11-14 POST OFFICE BOX 665303 • OALLAS. TEXAS 75265
 SN74ACT3631
512 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

14 te ~I
tw(ClKH)
I
14 ~14 ~I tw(CLKL)
ClKA } '\
I

rI
\ I
I
\ (
I
'---
I I I
IR High
~14' th(EN)
I
tsu(EN) I14 I
I I

I~
I
CSA
tsu(EN)
~14 ~14 ~ th(EN)
I
I
1/
I
I
I
WiRA
V/I/Zll1lZl{ IF I I \\\\\\\\\\
tsu(EN) 14 ~14 ~ th(EN) I I
MBA I I I

ENA I
tsu(O) 14 ~I ul th(O)
AO-A35 'No Operation <;888888&
Figure 4. FIFO Write-Cycle Timing

i4-~--- te ---~~
tw(CLKH) ~14- - -...~114-4-'-----.l~1 tw(CLKl)
ClKB I,...-------.{I...-__~y \ ( \ r""--~'---
I 1 I
I I I
OR High
I I I
I I I
----~ I I
CSB} I I I /
I I I
W/RB 7Z"7"%"7"%"7"%"7"/I-:lI.....-------+I--------+---------1II"---.::\-.:"~-.:"S-.:"S-.:"S-.:"S-.:"S-.:"S-.:"S-.:"";
I I I
MBB -----+-1~\ I I

I I ~SU(EJ I:SU(EN~ ~U(EN~:

I I I : - th(EN} I -J j4- th(EN) I -tI !+- th(EN)
ENB
~ I ~ 1 \\\\§\\wi tvzzm;
~ I.......J
r-
tpd(M-OV) I 101 I I I No
"I tdls
BO-B35 - - - -....
ten ~

~
1

W1
J.- ta ~
* W2 *
j+" ta ~
W3
Operation r
j

Figure 5. FIFO Read-Cycle Timing

-!11 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-15
SN74ACT3631
512 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

ClKA
I
CSA ________I______
~lo~w ~ ________________________________________________
I
W/RA High ~ I
tsu(EN) i -+' J..- th(EN)

MBA //Z/T/lU
~tSU(EN)
(;"'2"'7'Z';'2+7;"2'-Z"'V""'Z""Z""Z"'Z"'Z"'Z"'Z"'Z"'7'Z7"Z7"Z"'Z'-2"'V"'z""'z""Z"'Z""'Z'"Z"'Z"'Z"'7'Z7"Z7"Z"'Z"'Z"'z"'V""'z""~"'z"'2""'2"'2"'7'2"'7';
..I!::.. th(EN)
ENA tl/7a I
I
~,,".$...$...:$i>-$
..\ _ - - - - - - - - - - - - - - - - - - - - - -
I .
IR High I I
AO-A35 ~ tsk(1)t I" ~" -Pc
tW(ClKH); ~ tw(ClKl) .
ClKB· 1 2 3
tpd(C-OR) !f-~I-~,...-~==~
OR Old Data In FIFO Output Register
-----~~~ __ ~~~~ ________ ~I~--J ----------
CSB~lO~W~ ________________________________.I
I ________ -r__________________

W/RB High I I

ENB =/2ZZZZZIZ22/ZlA
If-ta-J
BO-B35------------~O~ld~D~m~a~ln~F~IF~o~o~m~p-u~tR~5~1~~e-r--------~*~--------~W~1~--------

t tsk(l) is the minimum time between a rising ClKA edge and a rising ClKS edge ior OR to transition high and to clock the next word to the FIFO
output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tsk(l). then the transition of
OR high and the first word load to the output register can occur one CLKS cycle later than shown.

Figure 6. OR-Flag Timing and Flrst-Data-Word Fallthrough When the FIFO Is Empty

~TEXAS
INSTRUMENTS
11-16 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ACT3631
512 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

I.--- te ----.I
tw(CLKH) I. ~. ~ tw(CLKL)
CLKB
CSB
I
~Lo~w~
\.~_--J{
________ ~1
'~_--,/ ''-_-J/
I ____________________________________________________
,-----
I
W/RB High I
I
MBB -=Lo~w~____~....~1~--------------------------------------------------
tsu(EN) l-f;)~(EN)
ENB t)F~/i I '~~0~$~$~\~__________________________________

OR High I
BO-B~ __~F~IF~O~O~u~t~u~tR~e~ls~te~r--~~N~e~~~w~o~rd~F~ro~m~FI~FO~............______........................__....____

----.I
CLKA ---'\'-_-J/~---'\
jf- tsk(l)t --.114-14- - t e
tw(CLKH) 14
11 "
~ t.
~
tw(CLKL)
2 \ ____~I ',-_-,r-
Ipd(C-IR) I. I. ~I
.1 tpd(C-IR)
IR FIFO Full
----------------------------------~
I i
I ,'------
CSA Low I
-------------------------------------~I--------------
W/RA

MBA

ENA
...
High

\$
\.... s:. . s:...:\:...:\:...s:...s:.s:. ...
.... $.... ...~
0.... S"' ....~,....~,....:\: s:. . s:.s:. ....s:.s:. ...
...~
....$....0.... $... $.... S"' ....~,....$~S.... $....$....
I
tsu(EN) ~ th(EN)
s:. . s:...:\:....\i
I
tSU(EN)~ th(EN)
=.

AO-A~

t tsk(l) is the minimum time between a rising elKS edge and a rising elKA edge for IR to transition high in the next elKA cycle. If the time between
the rising elKS edge and rising elKA edge is less than tsk(I). then IR can transition high one elKA cycle later than shown.

Figure 7_ IR-Flag Timing and First Available Write When the FIFO Is Full

~TEXAS
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS, TEXAS 75266 11-17
SN74ACT3631
512 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS246F -AUGUST 1993 - REVISED SEPTEMBER 1995

ClKA

ENA
~ ~~~S~~~~$~$.$~~~ ______________________________________________
It- tsk(2)t -tI
ClKB

AE X Words In FIFO
"-__- . 2

j
r tpd(C-AE) "'I tpd(C-AE)
Y(X+ 1) Words In FIFO
14 -I
'-
tsu(EN) H ~th(EN)
ENB ______________________________________________~It~z~z~,~~~~~.g~ ~

t tsk(2) is the minimum time between a rising ClKA edge and a rising ClKB edge for AE to transition high in the next CLKBcycle.lfthetime between
the rising CLKA edge and rising C.!:KB edge is less than tsk(2). then AE cs.!!.transition high one CLKB cycle later than shown.
NOTE A: FIFO wrtte (CSA =L. W/RA =H. MBA =L). FIFO read (CSB =L. W/RB =H. MBB =L)

Figure 8. Timing for AE When FIFO Is Almost Empty

I.- tsk(2)t -tI

ClKA I \
tsu(EN)
t
I..-::tI
\
I+- th(EN)
/'--+11"'\ Y~1-"""\ 12
1
''-_-II
ENA I/?//?~I ~~ 1
1
1
tpd(C.AF) 14 tpd(C-AF) 114-.---tit!
AF [512 - (Y + 1)) Words In FIFO
!,-----
ClKB----1 \'---..,/ '--
ENB ____________________&1t~2~z~,2~2~2.g : ~~_~~~~~$~$~~~ ___________________________
t tsk(2) isthe minimum time between a rising CLKA edge and a rising CLKB edge for AFto transttion high in the next CLKAcycle.lfthetime between
the rising ClKB edge and rising C.!:KA edge is less than tsk(2). then AF cs.!!.transltion high one CLKA cycle later than shown.
NOTE A: FIFO write (GSA = l. W/RA =H. MBA =l). FIFO read (CSB =L. W/RB =H. MBB =L)

Figure 9. Timing for AF When the FIFO Is Almost Full

~1EXAS
INSTRUMENTS
11-18 POST OFFICE BOX 665303 • DALLAS. TEXAS ~
 SN74ACT3631
512 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY

ClKB / \
tsu(EN)I~
t
th(EN)
\ I
I
\
'wtEN) $ I
~(EN)
\ ,
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

1
\
1 1
tW'
~
ENB /IT/} I 1
tsu(EN) ~ th(EN)
1 --: tsu(EN) th(EN)
I
RTM
mJ I~ I
1 I1 ~"" 1
I k><xAA.
I 1 tsu(EN) ~ th(EN) 1
I
RFM
I
1
1 Il/J : t\\~ 1
1
1 1 1 1
OR
I 1 1 1
High
I 1 1 1
I+- ta-.l I+--ta---l I+- la ---I I+- ta ---I
BO-B35 WO
Inillate Retransmit Mode
With WO as First Word
* Wi
* W2
Retransmit From
Selected Position
* ,WO
End Retransmit
Mode
* Wi

NOTE A: CSB = l. W/RB = H. MBB = L. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit.
Other enables are shown only to relate retransmit operations to the FIFO output register.

Figure 10. Retransmit Timing Showing Minimum Retransmit Length

ClKB / \ t
I
I
\ Ii \ ~2
I
I
''-_--'I ''---
RTM High 1 1
1 I
-I 1-lh(RM) 1
tsu(RM) --14---+1 I I
RFM 1/?l?7!J t\\\\\\\ I
I
I.
I_---*'"tl- tpd(C-AEI
AE _ _ _ _ _ _X_or_ __
Fewer __
Words __
From .;...;;._ _ _ _ _ _ _ _- ' (X + 1) or More Words From Empty
Empty

NOTE A: X is the value loaded in the almost-empty flag offset register.

Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-19
SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

14- ts k(1)t -+I

ClKA \ I~--I:,",\ / - 1 -......\ 12 '\",._....,,/ ' ..._....,,1
1 tpd(C-IR) ~
IR FIFO Filled to First Retransmllt Word '--o-ne-o-r-=M":"o-re"""!":'w=-=rl~te-=l-o-ca-=t~lo-n-s"='A-va-=lI~ab="="le
I
1
ClKB --I \ 1
1
\ / \ / \ / '--
tsu(EN) 14 ~14 ~I th(EN)
RTM
~~ ~
t tsk(1) is the minimum time between a rising ClKB edge and a rising ClKA edge for IR to transition high in the next ClKA cycle. If the time between
the rising ClKB edge and rising ClKA edge is less than tsk(1). then IR can transition high one ClKA cycle later than shown.

Figure 12. IR Timing From the End of Retransmit M~de When One or More Write Locations Are Available

I+-- tsk(2)t -+I

ClKA ,\",._...."/~--ti~\ /~1-......\ 12 '\-_......J/ ',-_oJ!
I tpd(C.AE) ~
AF ..:.;.=-.....;.:-=~;..;...;=-.;;.;..;..;;.;~=-.;.;.;.==~;.;;.;.;;.... ~---------------------
(512 - V) or More Words Past First Retransmit Word _ _ _ _ _ _ _ (Y + 1) or More Write locations Available

1
ClKB --I \ ~ \ / \'--_..1/ ,\-_--J/ '-
tsu(EN) 14 ~~ ~ th(EN)
RTM
\\%\ ~
t tsk(2) is the minimum time between a rising ClKB edge and a rising ClKA edge for AF to transition high in the next ClKA cycle. If the time between
the rising ClKB edge and rising ClKA edge is less than tsk(2). then AF can transition high one ClKA cycle later than shown.
NOTE A: V is the value loaded in the almost·full flag offset register.

Figure 13. AF Timing From the End of Retransmit Mode When (Y + 1)

or More Write Locations Are Available

-!!11EXAS
INSTRUMENTS
11-20 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3631
512 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

, I '\-__..J/ ,'-_ _--J/

'--
ClKA /
tsu(EN) H r-
-----~~~I--------------------------------
th(EN)

I I
WiRA
7I?Z?A/ZZIZ?I :I W
I
MBA
?l?W?ZZ2?4 :W
ENA

AO-A35

ClKB /

WIRB 2?fll/1: I ~\\\\\>

MBB ______~I------~/I
I II
i__,
tsu(ENI~~ th(EN)
~
I
ENB :
,
I ,I
I.. i,..
wm
~I tpd(M-OV).1 tpd(C-MR)
~1. : 0\ :. :..
. $".......+1_______
!~ .1
ten H tdls ~
BO-B35
FIFO Output Register

Figure 14. Timing for Mail1 Register and MBF1 Flag

-!11 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-21
SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

I \....__...,/ \
\\-__--J/ I
ClKB
r- '-
tsu(EN) H Ih(EN)
------~~~-----------------
I I I
W/RB ~S~$~~~$~$~$~$~$~$~$~S) :£"2~0~7~--------------------~---
I I I
MBB
'lZ/fl??II!4 :D
ENB
0ZVZZZ2lJ{ 1 ~
BO-B35
~ I
ClKA I
-.I \'-----1r -..!
\'----- IF
\\o.._---!I_..J/
tpd(C.MF) tpd(C-MF)
-------+--~\\o.._ _ _ _ _~I----)~-----
I 1
\ I I I
I I I I
WiRA i:
...'''',....$~$~$~\:.... : ~""Z""Z..,.072'72'727272'7"
MBA
I I ISu(EN)~ Ih(EN) I
ENA I
I
I
I
R22Z? t~$.$~$~\__~I_ _ __
- I
len H ).
+.1- - - - idls j----.I

Figure 15. Timing for Mall2 Register and MBF2 Flag

~TEXAS
INSTRUMENTS
11-22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Va (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Vee) ............................................... ±20 mA
Output clamp current, 10K (Va < 0 or Va> Vee> ........................................... ±50 mA
Continuous output current, 10 (Va = 0 to Vee> ............................................. ±50 mA
Continuous current through Vee or GND ................................................. ±400 mA
Operating free-air temperature range, TA ............................ . . . . . . . . . . . . . . . . .. OOG to 70 G 0

Storage temperature range, Tstg .................................................. -65°G to 1500 G

t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings can be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current -4 mA
IOL Low-level output current 8 mA
TA Operating free-air temperature 0 70 'C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP* MAx UNIT
VOH VCC=4.5V, IOH=-4mA 2.4 V
VOL VCC = 4.5 V. IOL=8mA 0.5 V
II VCC m 5.5V. VI =VccorO ±5 IlA
IOZ VCC=5.5V, Vo=VccorO ±5 IlA
ICC VCC=5.5V, VI = VCC-0.2 VorO 400 IlA
CSA=VIH AO-A35 0
CSB=VIH BO-B35 0
VCC = 5.5 V, One input at 3.4 V,
AleC§ CSA=VIL AO-A35 1 mA
Other inputs at VCC or GND
CSB=VIL BO-B35 1
All other inputs 1
ei VI=O, f= 1 MHz 4 pF
Co VO=O, f_1 MHz 8 pF
=I: All typical values are at Vce = 5 V, TA = 25'C.
§ This is the supply current when each input is at one of the specHied TTL voltage levels rather than 0 V or Vce.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-23
SN14ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246F -AUGUST 1993- REVISED SEPTEMBER 1995

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 15)
'ACT3631-15 'ACT3631-20 'ACT3631-30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency, CLKA or CLKB 66.7 50 33.4 MHz
tc Clock cycle time, CLKA or ClKB 15 20 30 ns
tw(CH) Pulse duration, CLKA and ClKB high 6 8 12 ns
tw(CL) Pulse duration, CLKA and ClKB low 6 8 12 ns
tsu(D) Setup time, AO-A35 before CLKAi and BO-B35 before CLKBi 7 7.5 8 ns
tsu(SEN)+ Setup time, FS1/SEN before CLKAi 5 6 7 ns
Setup time, CSA, W/RA, and MBA to CLKAi;
tsu(EN2) 7 7.5 8 ns
CSB, W/RB, and MBB before ClKBi
tsu(RM) Setup time, RTM and RFM to ClKBi 6 6.5 7 ns

tsu(RS) Setup time, RST low before CLKA i or CLKBit 5 6 7 ns

tsu(FS) Setup time, FSO and FS1 before RST high 9 10 11 ns
tsu(SD)+ Setup time, FSO/SD before ClKA i 5 6 7 ns
Isu(EN1) Setup time, ENA to CLKAi; ENB to ClKBi 5 6 7 ns

th(D) Hold time, AO-A35 after ClKAi and BO-B35 after CLKBi a a a ns
th(EN1) Hold time, ENA after CLKA i; ENB after ClKBi a 0 a ns
Hold time, CSA, W/RA, and MBA after CLKAi;
th(EN2) CSB, W/RB, and MBB after CLKBi
a a a ns

th(RM) Hold time, RTM and RFM after ClKBi 0 0 a ns

th(RS) Hold time, RST low after CLKAi or ClKBit 5 6 7 ns

th(FS) Hold time, FSO and FS 1 after RST high a 0 0 ns
th(SP)+ Hold time, FS1/SEN high after RST high a a a ns
th(SD)+ Hold time, FSO/SD after Cl.KAi a a a ns
th(SEN)+ Hold time, FS1/SEN after ClKAi a a a ns
tsk(l)§ Skew time between ClKA i and ClKBi for OR and IR 9 11 13 ns
tsk(2)§ Skew time between ClKA i and CLKBi for AE and AF 12 16 20 ns
t ReqUirement to count the clock edge as one of at least four needed to reset a FI FO
+ Only applies when serial load method used to program flag offset registers
§ Skew time is not a timing constraint for proper device operation and is included to illustrate the timing relationship between CLKA cycle and ClKB
cycle.

-!/} TEXAS
INSTRUMENTS
11-24 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 1 through 15)
'ACT3631-15 'ACT3631-20 'ACT3631-30
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
ta Access time, CLKBt to BO-B35 3 11 3 13 15 ns
tpd(C-IRl Propagation delay time, CLKAt to IR 0 8 0 10 0 12 ns
tpd(C-OR) Propagation delay time, CLKBt to OR 1 8 1 10 1 12 ns
tpd(C-AEl Propagation delay time, CLKBt to AE 1 8 1 10 1 12 ns
tpd(C-AF) Propagation delay time, CLKAt to AF 1 8 1 10 1 12 ns
Propagation delay time, CLKAt to MBF1 low or MBF2 high and
tpd(C-MF) 0 8 0 10 0 12 ns
CLKBt to MBF2 low or MBF1 high
Propagation delay time, CLKAt to BO-B35t and CLKBt to
tpd(C-MR) 3 13.5 3 15 3 17 ns
AD-A35:!:
tpd(M-DV) Propagation delay time, MBB to BO-B35 valid 3 13 3 15 3 17 ns
tpd(R-F) Propagation delay time, RST low to AE low and AF high 1 15 1 20 1 30 ns
Enable time, CSA and W/RA low to AO-A35 active and CSB low
ten 2 12 2 13 2 14 ns
and W/RB high to BO-835 active
Disable time, GSA or W/RA high to AO-A35 at high impedance
tdis 1 10 1 11 1 12 ns
and CSB high or W/RB low to BO- B35 at high impedance
t Writing data to the mail1 register when the BO-B35 outputs are active and MBB is high
:!: Writing data to the mail2 register when the AO-A35 outputs are active and MBA is high

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 11-25
SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250 ,..---r---r---r---r---r---r----,
fdata = 1/2 fclock
=
TA 25°C
CL=OpF
1I 200~--r---r_--r_--r_--r_~~~

~
<3 150 ~--r_--r_--r_--f-7i'~h,IC_r____i
~
8:
alI 100~--r_--r_~~~r_--r_--r____i

8
g

O~--~--~--~--~--~--~~
o 10 20 30 40 50 60 70

fclock - Clock Frequency - MHz

Figure 16

calculating power dissipation

With lee(f) taken from Figure 16, the maximum power dissipation (PT) of the SN74ACT3631 can be calculated
by:
PT = Vee x [Iee(f) + (N x ~Iee x dc)] + L(CL x Vee 2 x fo)
Where:
N = number of inputs driven by TIL levels
~Iee = increase in power supply current for each input at a TIL high level
dc = duty cycle of inputs at a TIL high level of 3.4 V
CL = output capacitive load
fo = switching frequency of an output

~TEXAS
INSTRUMENTS
11-26 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3631
512 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246F - AUGUST 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

5V

11000
From Output
Under Test - - . - - - - .

6800 -::::::- 30pF

---..... (see Note A)

LOAD CIRCUIT

-....If~.~
Timing 1 3V High-Level - 3V
Input ______J~ Jr ~~ __ _ GND
Input ,.V • ~ GND

tsu~th 14-- tw --+i

I I
Data, ~-=-,,-::- 3V
Enable ~1.5V ~ Low-Level ~ 1.5 V J;;;;- 3V
Input GND Input ~ :"'V':'" _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

3V
Output L
Enable ---I: 1.5 V
I GND
~ 14-tPLZ
II ----~
-3V
Low-Level
Output I
--j-II
I
-.I
I
J4-tPZH
VOL
Input
--f
tpd~
1.5V
\~5~--

~tpd
3V

GND

VOH
High-Level I
Output

~
I I
I I
l4-tPHZ
-OV
In-Phase
Output 1 1.5V
~
VOH

VOL

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 17_ Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-27
11-28
 SN74ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST·OUT MEMORY
- JANUARY 1994- REVISED SEPTEMBER 1995

• Free-Running ClKA and ClKB Can Be • Output-Ready (OR) and Almost-Empty (AE)
Asynchronous or Coincident Flags Synchronized by ClKB
• Clocked FIFO Buffering Data From Port A • low-Power O.B-Micron Advanced CMOS
to Port B Technology
• Memory Size: 1024 x 36 • Supports Clock Frequencies up to 67 MHz
• Synchronous Read-Retransmit Capability • Fast Access Times of 11 ns
• Mailbox Register in Each Direction • Pin-to-Pin Compatible With the
• Programmable Almost-Full and SN74ACT3631 and SN74ACT3651
Almost-Empty Flags • Available in Space-Saving 120-Pin Thin
• Microprocessor Interface Control logic Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
• Input-Ready (IR) and Almost-Full (AF) Flags
Synchronized by ClKA

description
The SN74ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies
up to 67 MHz and has read access times as fast as 12 ns. The 1D24 x 36 dual-port SRAM FIFO buffers data
from port A to port B. The FIFO memory has retransmit capability, which ailows previously read data to be
accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words is stored in memory. Communication
between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal
when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths.
Expansion is also possible in word depth.
The SN74ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The
output-ready (OR) flag and almost-empty (A E) flag of the FIFO are two-stage synchronized to ClKS. Offset
values for the almost-fuil and almost-empty flags of the FIFO can be programmed from port A or through a serial
input.
The SN74ACT3641 is characterized for operation from DOC to 70°C.
For more information on this device family, seethe application reports FIFO Patented Synchronous Retransmit:
Programmable DSP-Interface Application for FIR Filtering and FIFO Mailbox-Bypass Registers: Using Bypass
Registers to Initialize DMA Control in the 1996 High-Performance FIFO Memories Designer's Handbook,
literature number SCAAD12A.

Copyright © 1995. Texas Instruments Incorporated

~:'CTlcoO:':~1: ::r::~8~~ ::~::=m:
standard warranty. Production processing does not necessarily Include
testing 01 all paramet8l1. ~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-29
SN74ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

PCB PACKAGE
(TOP VIEW)

~~~~~~~E~E~~~~~~~~~§~~~~~~~~~~
A35 1 00 B35
A34 2 ~ B34
A33 3 ~ B33
A32 4 ~ B32
Vee 5 ~ GND
A31 6 ~ B31
A30 7 M B30
GND 8 ~ B29
A29 9 § B28
A28 10 81 B27
A27 11 80 B26
A26 12 79 Vee
A25 13 78 B25
A24 14 77 B24
A23 15 76 GND
GND 16 75 B23
A22 17 74 B22
Vee 18 73 B21
A21 19 72 B20
A20 W n B19
A19 21 70 B18
A18 22 69 GND
GND 23 68 B17
A17 ~ ~ B16
A16 25 66 Vee
A15 26 65 B15
A14 27 64 B14
A13 28 63 B13
Vee 29 62 B12
A12 30 61 GND
M~~~~~~~~~~~~~~~~~~g~~~~~ffi~ffim~

Ne - No internal connection

~1ExAs
INSTRUMENTS
11-30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

NC NC
B35 NC
B34 A35
B33 A34
B32 A33
GND A32
831 Vee
B30 A31
B29 A30
B28 GND
B27 A29
B26 A28
Vee A27
B25 A26
B24 A25
GND A24
B23 A23
B22 GND
B21 A22
B20 Vee
B19 A21
B18 A20
GND A19
B17 A18
B16 GND
Vee A17
B15 A16
B14 A15
B13 A14
B12 A13
GND Vee
NC A12
NC NC

Ne - No internal connection
t Uses Yarnalchi socket 1051-1324-828

~I 1ExAs
NSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75266 11~1
SN74ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

functional block diagram

.-
Mall1 I
MBF1

Register
-

~~
ClKA I
CSA - Port-A
WiRA - Control .....-
ENA - logic I-- I--
~ j ~
MBA - I-
g>
a:
'5
... 1024x 36
SRAM ~ ~ ::I
Reset D.
.5 t
0 r+-
logic
- T :t::
36 "fi ~.2 RTM
c c 8' f+4
~ 1I Pointer
Write II Read
Pointer
r ~l!~
1111)
a:
RFM

AO-A35
IR
AF ~
•
Status-Flag
logic
t BO-B35

OR
AE

+
FSO/SD Flag-Offset

~ W/RB
FS1/SEN Register f- ClKB
Port-B CSB
10 '--f-

~
Control
logic ENB
Mall2
~~ I f+-
..
Register MBB

~TEXAS
INSTRUMENTS
11-32 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME
AO-A35 1/0 Port-A data. The 36-bit bidirectional data port for side A.
Almost-empty flag. Programmable flag synchronized to ClKB. AE is low when the number of words in the FI FO is less
AE 0
than or equal to the value in the almost-empty offset register (X).
Almost-full flag. Programmable flag synchronized to ClKA. AF is low when the number of empty locations in the FIFO
AF 0
is less than or equal to the value in the almost-full offset register (Y).
BO-B35 1/0 Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
ClKA I
or coincident to ClKB. IR and AF are synchronous to the low-to-high transition of ClKA.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
ClKB I
or coincident to ClKA. OR and AE are synchronous to the low-to-high transition of ClKB.
Port-A chip select. CSA must be low to enable a low-to-high transition of ClKA to read or write data on port A. The
CSA I
AO-A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of ClKB to read or write data on port B. The
CSB I
BO-B35 outputs are in the high-impedance state when CSB is high.
ENA I Port-A master enable. ENA must be high to enable a low-to-high transition of ClKA to read or write data on port A.
ENB I Port-B master enable. ENB must be high to enable a low-to-high transition of ClKB to read or write data on port B.
Flag-offset select llserial enable, flag-offset select Olserial data. FSl/SEN and FSO/SD are dual-purpose inputs used
for flag-offset register programming. During a device reset, FSl/SEN and FSO/SD select the flag-offset programming
method. Three offset-register programming methods are available: automatically load one of two preset values, parallel
FSl/SEN, load from port A, and serial load.
I
FSO/SD When serial load is selected for flag-offset-register programming, FSl/SEN is used as an enable synchronous to the
low-to-high transition of ClKA. When FSI ISEN is low, a rising edge on ClKA loads the bit present on FSO/SD into the
X and Y offset registers. The number of bit writes required to program the offset registers is 20. The first bit write stores
the V-register MSB and the last bit write stores the X-register lSB.
Input-ready flag. IR is synchronized to the low-to-hi~h transition of ClKA. When IR is low, the FIFO is full and writes to
IR 0 its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point
of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset.
MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
MBB I BO-B35 outputs are active, a high level on MBB selects data from the mail 1 register for output and a low level selects
FIFO data for output.
Maill register flag. MBFl is set low by the low-to-high transition of ClKA that writes data to the mail1 register. MBFl
MBF1 0 is set high by a low-to-high transition of ClKB when a port-B read is selected and MBB is high. MBFl is set high by a
reset.
Mail2 register flag. MBF2 is set low by the low-to-high transition of ClKB that writes data to the mail2 register. MBF2
MBF2 0 is set high by a low-to-high transition of ClKA when a port-A read is selected and MBA is high. MBF2 is set high by a
reset.
Output-ready flag. OR is synchronized to the low-to-high transition of ClKS. When OR is low, the FIFO is empty and
OR 0 reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during
the reset and goes high on the third low-to-high transition of ClKB after a word is loaded to empty memory.
Read from mark. When the FI FO is in retransmit mode, a high on RFM enables a low-to-high transition of ClKS to reset
RFM I
the read pointer to the beginning retransmit location and output the first selected retransmit data.
Reset. To reset the device, four low-to-high transitions of ClKA and four low-to-high transitions of ClKS must occur
RST I
while RST is low. The low-to-high transition of RST latches the status of FSO and FS1 for AF and AE offset selection.
Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high
transition of ClKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected
RTM I
word remains the initial retransmit point until a low-to-high transition of ClKS occurs while RTM is low, taking the FIFO
out of retransmit mode.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-33
SN74ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

Terminal Functions (Continued)

TERMINAL
I/O DESCRIPTION
NAME
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a
W/RA I
low-to-high transition of ClKA. The AO-A35 outputs are in the high-impedance state when WlRA is high.
Port-B write/read select. A Iowan W/RB selects a write operation lind a high selects a read operation on port B for a
W/RB I
low-to-high transition of ClKB. The BO-B35 outputs are in the high-impedance state when W/RB is low.

detailed description
reset
The SN74ACT3641 is reset by taking the reset (RST) input low for at least four port-A clock (ClKA) and four
port-S clock (ClKS) low-la-high transitions. RST can switch asynchronously to the clocks. A reset initializes the
memory read and write pointers and forces the input-ready (IR) flag low, the output-ready (OR) flag low, the
almost-empty (AE) flag low, and the almost-full (AF) flag high. Resetting the device also forces the mailbox flags
(MSF1, MBF2) high. After a FIFO is reset, its input-ready flag is set high after at least two clock cycles to begin
normal operation. A FIFO must be reset after power up before data is written to its memory.
almost-empty flag and almost-full flag offset programming
Two registers in the SN74ACT3641 are used to hold the offset values for the almost-empty and almost-full flags.
The almost-empty (AE) flag offset register is labeled X, and the almost-full (AF) flag offset register is labeled Y.
The offset registers can be loaded with a value in three ways: one of two preset values are loaded into the offset
registers, parallel load from port A, or serial load. The offset register programming mode is chosen by the flag
select (FS1, FSO) inputs during a low-to-high transition on RST (see Table 1).

Table 1. Flag Programming

FS1 FSO RST X AND Y REGISTERSt
H H i Serial load
H l i 64
L H i 8
l l i Parallel load from port A
t X register holds the offset for AE; Y register holds the
offset for AF.

preset values
If a preset value of 8 or 64 is chosen by FS1 and FSO at the time of a RST low-la-high transition according to
Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is
necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on ClKA.
parallel load from port A
To program the X and Y registers from port A, the device is reset with FSO and FS1 low during the low-la-high
transition of RST. After this reset is complete, IR is set high after two low-to-high transitions on ClKA. The first
two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X. Each offset
register of the SN74ACT3641 uses port-A inputs (A9-AO). Data input A9 is used as the most significant bit of
the binary number. Each register value can be programmed from 1 to 1020. After both offset registers are
programmed from port A, subsequent FIFO writes store data in the SRAM.

~TEXAS .
INSTRUMENTS
11-34 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

serial load
To program the X and Y registers serially, the device is reset with FSO/SD and FS1/SEN high during the
low-to-high transition of RST. After this reset is complete, the X and Y register values are loaded bitwise through
FSO/SD on each low-to-high transition of elKA that FS1/SEN is low. Twenty-bit writes are needed to complete
the programming. The first-bit write stores the most significant bit of the Y register and the last-bit write stores
the least significant bit of the the X register. Each register value can be programmed from 1 to 1020.
When the option to program the offset registers serially is chosen, the IR remains low until all 20 bits are written.
IR is set high by the low-to-high transition of elKA after the last bit is loaded to allow normal FIFO operation.
FIFO write/read operation
The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (eSA) and the port-A
write/read select (W/RA). The AO-A35 outputs are in the high-impedance state when either eSA or W/RA is
high. The AO-A35 outputs are active when both eSA and W/RA are low.
Data is loaded into the FIFO from the AO-A35 inputs on a low-to-high transition of elKA when eSA and the
port-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the input-ready (IR) flag are high (see
Table 2). Writes to the FIFO are independent of any concurrent FIFO reads.

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA AO-A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L t In high-impedance state FIFO write
L H H H t In high-impedance state Maill write
L L L L X Active, mail2 register None
L L H L t Active, mail2 register None
L L L H X Active, mail2 register None
L L H H t Active, mail2 register Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A with the exception that the port-B write/read select
(W/RB) is the inverse of W/RA. The state of the port-B data (BO-B35) outputs is controlled by the port-B chip
select (eSB) and W/RB. The BO-B35 outputs are in the high-impedance state when either eSB is high orW/RB
is low. The BO-B35 outputs are active when eSB is low and W/RB is high.
Data is read from the FIFO to its output register on a low-to-high transition of elKB when eSB and the port-B
mailbox select (MBB) are low, W/RB, the port-B enable (ENB), and the output-ready (OR) flag are high (see
Table 3). Reads from the FIFO are independent of any concurrent FIFO writes.

-!/}TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-35
SN74ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

FIFO write/read operation (continued)

Table 3. Port·B Enable Function Table

CSB W/RB ENB MBB ClKB BO-B35 OUTPUTS PORT FUNCTION
H X X X X In high~impedance state None
L L L X X In high-impedance state None
L L H L i In high-impedance state None
L L H H i In high-impedance state Mail2write
L H L L X Active, FI FO output register None
L H H L i Active, FI FO output register FIFO read
L H L H X Active, maUl register None
L H H H i Active, maill register Maill read (set MBFl high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select can change states during the
setup- and hold-time window of the cycle.
When the OR is low, the next data word is sent to the FI FO output register automatically by the CLKB low-to-high
transition that sets OR high. When OR is high, an available data word is clocked to the FIFO output register only
when a FIFO read is selected by CSB, W/RB, ENB, and MBB.
synchronized FIFO flags
Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the
flags' reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate
asynchronously to one another (see the application report Metastability Performance of Clocked FIFOs in the
1996 High-Performance FIFO Memories Data Book, literature number SCAD003C). OR and AE are
synchronized to CLKB. IR and AF are synchronized to CLKA. Table 4 shows the relationship of each flag to the
number of words stored in memory.

Table 4. FIFO Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS IN TOClKB TOClKA
FIFOf*
OR AE AF IR
0 L L H H
1 toX H L H H
(X + 1) to [1024 - Cf + 1)) H H H H
(1024 - y) to 1023 H H L H
1024 H H l L
t x IS the almost-empty offset for AE. Y IS the almost-full offset for AF.
:j: When a word is present in the FIFO output register, its previous memory
location is free.

~TEXAS
INSTRUMENTS
11-36 POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
 SN74ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

output-ready flag (OR)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array (ClKS). When
the output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low,
the previous data word is present in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine
that controls an output-ready flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is empty, empty+ 1, or empty+2. From the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of ClKS; therefore, an output-ready flag is low if a word
in memory is the next data to be sent to the FIFO output register and three ClKS cycles have not elapsed since
the time the word was written. The output-ready flag ofthe FIFO remains low until the third low-to-high transition
of ClKS occurs, simultaneously forcing the output-ready flag high and shifting the word to the FIFO output
register.
A low-to-high transition on ClKS begins the first synchronization cycle of a write if the clock transition
occurs at time tsk(1), or greater, after the write. Otherwise, the subsequent ClKS cycle can be the first
synchronization cycle (see Figure 6).
input-ready flag (IR)
The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array (ClKA). When the
input-ready flag is high, a memory location is free in the SRAM to write new data. No memory locations are free
when the input-ready flag is low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pOinter is incremented. The state machine that controls an
input-ready flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM
status is full, full-1 , or full-2. From the time a word is read from a FIFO, its previous memory location is ready
to be written in a minimum of three cycles of ClKA; therefore, an input-ready flag is low if less than two cycles
of ClKA have elapsed since the next memory write location has been read. The second low-to-high transition
on ClKA after the read sets the input-ready flag high, and data can be written in the following cycle.
A low-to-high transition on ClKA begins the first synchronization cycle of a read if the clock transition
occurs at time tsk(1), or greater, after the read. Otherwise, the subsequent ClKA cycle can be the first
synchronization cycle (see Figure 7).
almost-empty flag (AE)
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array (ClKS). The
state machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that
indicates when the FIFO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty
state is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset,
programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset
programming). The almost-empty flag is low when the FIFO contains X or less words and is high when the FIFO
contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory.
Two low-to-high transitions of ClKS are required after a FIFO write for the almost-empty flag to reflect the new
level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1) or more words remains low if two cycles
of ClKS have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set
high by the second low-to-high transition of ClKS after the FIFO write that fills memory to the (X + 1) level.
A low-to-high transition of ClKS begins the first synchronization cycle if it occurs at time tsk(2), or greater, after
the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent ClKS cycle can be the first
synchronization cycle (see Figure 8).

~lEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-37
SN74ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS33BB - JANUARY 1994 - REVISED SEPTEMBER 1995

almost-full flag (AFJ

The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array (ClKA). The state
machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by
the contents of register Y. This register is loaded with a preset value during a FI FO reset, programmed from port
A, or programmed serially (see almost-empty flag and almost-full flag offset programming). The almost-full flag
is low when the number of words in the FIFO is greater than or equal to (1024 - V). The almost-full flag is high
when the number of words in the FIFO is less than or equal to [1024 - (Y + 1)]. A data word present in the FIFO
output register has been read from memory.
Two low-to-high transitions of ClKA are required after a FIFO read for its almost-full flag to reflect the new level
offill. Therefore, the almost-full flag of a FIFO containing [1024 - (Y + 1)] or less words remains low if two cycles
of ClKA have not elapsed since the read that reduced the number of words in memory to [1024 - (Y + 1)]. An
almost-full flag is set high by the second low-to-high transition of ClKA after the FIFO read that reduces the
number of words in memory to [1024 - (Y + 1)]. A low-to-high transition of ClKA begins the first synchronization
cycle if it occurs at time tsk(2), or greater, after the read that reduces the number of words in memory to
[1024 - (Y + 1)]. Otherwise, the subsequent ClKA cycle can be the first synchronization cycle (see Figure 9).
synchronous retransmit
The synchronous retransmit feature of the SN74ACT3641 allows FIFO data to be read repeatedly starting at
a user-selected position. The FIFO is first put into retransmit mode to select a beginning word and prevent
on-going FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three
words can retransmit repeatedly starting at the selected word. The FIFO can be taken out of retransmit mode
at any time and allow normal device operation.
The FIFO is put in retransmit mode by a low-to-high transition on ClKB when the retransmit mode (RTM) input
is high and OR is high. This rising ClKB edge marks the data present in the FIFO output register as the first
retransmit data. The FIFO remains in retransmit mode until a low-to-high transition occurs while RTM is low.
When two or more reads have been done past the initial retransmit word, a retransmit is initiated by a low-to-high
transition on ClKS when the read-from-mark (RFM) input is high. This rising ClKB edge shifts the first
retransmit word to the FIFO output register and subsequent reads can begin immediately. Retransmit loops can
be done endlessly while the FIFO is in retransmit mode. RFM must be low during the ClKB rising edge that takes
the FIFO out of retransmit mode.
When the FIFO is put into retransmit mode, it operates with two read pointers. The current read pointer operates
normally, incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE
flags. The shadow read pOinter stores the SRAM location at the time the device is put into retransmit mode and
does not change until the device is taken out of retransmit mode. The shadow read pOinter is used by the IR
and AF flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set low by the write that
stores (1024 - Y) words after the first retransmit word. The IR flag is set low by the 1024th write after the first
retransmit word.
When the FIFO is in retransmit mode and RFM is high, a rising ClKS edge loads the current read pointer with
the shadow read-pointer value and the OR flag reflects the new level of fill immediately. If the retransmit changes
the FIFO status out of the almost-empty range, up to two ClKB rising edges after the retransmit cycle are
needed to switch AE high (see Figure 11). The rising ClKS edge that takes the FIFO out of retransmit mode
shifts the read pOinter used by the IR and AF flags from the shadow to the current read pointer. If the change
of read pointer used by IR and AF should cause one or both flags to transition high, at least two ClKA
synchronizing cycles are needed before the flags reflect the change. A rising ClKA edge after the FIFO is taken
out of retransmit mode is the first synchronizing cycle of IR if it occurs at time tsk(1), or greater, after the rising
ClKB edge (see Figure 12). A rising ClKA edge after the FIFO is taken out of retransmit mode is the first
synchronizing cycle of AF if it occurs at time tsk(2), or greater, after the rising ClKS edge (see Figure 14).

-!!JTEXAS
INSTRUMENTS
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 SN74ACT3641
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

mailbox registers
Two 36-bit bypass registers are on the SN74ACT3641 to pass command and control information between port A
and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data
transfer operation. A low-to-high transition on ClKA writes AO-A35 data to the mail1 register when a port A write
is selected by CSA, W/RA, and ENA with MBA high. A low-to-high transition on ClKB writes BO-B35 data to
the mail2 register when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mail
register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while
its mail flag is low.
When the port-B data (BO-B35) outputs are active, the data on the bus comes from the FIFO output register
when the port-B mailbox select (MBB) input is low and from themail1registerwhenMBBishigh.Mail2 data
is always present on the port-A data (AO-A35) outputs when they are active. The mail1 register flag (MBF1)
is set high by a low-to-high transition on ClKB when a port-B read is selected by CSB, W/RB, and ENB with
MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on ClKA when a port-A read
is selected by CSA, W/RA, and ENA with MBA high. The data in a mail register remains intact after it is read
and changes only when new data is written to the register.

ClKA

ClKB
1 1 I It I
--.I ~ tsu(RS) 1 1 ~ h(FS) I
_ _ _ _~I 1 1 tsu(FS) 1:---'1 I I
RST" 1 II I
1 1 I I
FS1,FSO

~ tpd(C-IR) '---1 I tpd(C-IR) i--1

IR ~¥\\\\\\\~ : ,,.----
tpd(C-OR) 1.---.1
OR~~
tpd(R-F) ~
AE'S\\h~
tpd(R-F) '------i
AF vzzd;(z;/21
__ tpd(R-F) /4-----tI
~~F~ vzmzzzz;t
Figure 1. FIFO Reset Loading X and Y With a Preset Value of Eight

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INSTRUMENTS
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SN74ACT3641
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

CLKA
I I
I
RST
--'-4..J.,
~~~,~ ~~~
1
I
I
I
I
I
I
I
I
FS1,FSO ~ bw///Z/2//~fffZZZW//fll/ZZZZ
tpd(C-IR) ~ .1 I I
IR Y I
I tsu(EN1) _
I _II ,~ th(EN1)

AF Offset AE Offset First Word Stored In FIFO

(Y) (X)
NOTE A: CSA = L, WiRA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values From Port A

CLKA
I I
I I
RST _ _ --'I It
I ,
I I tpd(C-IR) ie-r-~.I
IR
............~:................................~~........................~(('~....~:~........................-J}r--
1- th(SP) ~ ~ I+- th(SEN) t I; -+I 1- th(SEN)
tsu(FS) I-i tsu(SEN) ~ 1 l..-.j 1
su(SEN)
FS1/SEN ~2222J:o-r::.-r.Iir-r-11---'-;;;';;=""'\ I..M<'>OS&. _ _ ~ nzzzzz??Z?lAZ
I :::;j ~ - Fth(SD)

FSO/SD ;;;F' AF Offset AE Offset

(Y) MSB (X) LSB
NOTE A: It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored untillR is set high.

Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially

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INSTRUMENTS
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 SN74ACT3641
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CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

I~ Ie ,I
tw(CLKH)

CLKA I
I~ ,~

"
I
': tw(CLKL)

tI
\ ,I
\ (
I
'--
I I I
IR High I
tsu(EN2) II~ ,: ~, th(EN2) I
I I
I 1/
CSA
tsu(EN2) I~
~ :~
'I ~ ~
th(EN2)
I
I
I
I
WiRA mzzzzzzzzq 'I:F tsu(EN2) I~ ~ ~ th(EN2)
I
I
I
: \\\§\\\\\
I
MBA I I I

ENA I
tsu!D) 14 ,I ~.! th(D)
AO-A35 'No Operation 2$8&$88&

Figure 4. FIFO Write-Cycle Timing

tw(CLKH)
11e-~- - - Ie ----.I"
I~~----tl~I+~
I,--I,,--_~';
tw(CLKL) ----tl':
ClKB
"-- 7
I
I
"
''----.Jf..
(
I
I
' ' '-------:' I
I
'-
OR High I
I
~I :I
W/RB //ZIlII
""",",,,,,,,,",.JI II
I I
MBB ---+-1- , !
I I tsu(EN1) tsu(EN1) tsu(EN1) I
I I It-----.: 14---.1 ~
I I I· ~ I+- th(EN1) I --tj l- th(EN1) I ~ I+- th(EN1)
ENB
/?//Z(W(IA :~ I K%\\\\« tvAVIZ'
I~I 'II I ~ ta -.11 1.1 ~ tdls
*
tpd(M-DV) Ope:tlon
~~~ ~ts~ rl
BO-B35 ----_~ W1 W2 *,..----:O:W='3---j

Figure 5. FIFO Read·Cycle Timing

~1ExAs
INSTRUMENTS
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SN74ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

ClKA
I
CSA ~lo~w~ ______.II ______ ~ __________________________________________________
I
W/RA High I
tsu(EN2) ~ 1.-. th(EN2)
MBA VZZThL I ~1"".%r-:Z~:?7"'-:/,"';Z""?Z""?2-:?Z-:?Z7Z7Z"rZ"rZ""Z""Zr-:Zr-:Zr-:v.""'/:'"'i:""?/:""'Z-:?Z-:?Z7Z7Z7Z"r;:""Z.,..;:,-;:r-:Zr-:V""'Z""'/:'"'/:""?Z""'Z-:?Z-:?Z7Z7Z72"'-;
tSU(EN1~ 14- th(EN1)
ENA IZlZld I ~~~..;,S:..;,S;-ToS:""'\~-------------------
: I
IR t=!! I
High tsu(D) I
AO-A35
~~
tsk(1)t I" .... I - - - ! ! tC
tW(ClKH)--I ~ I w(ClKl)
ClKB 1 2 3
tpd(C.OR) !4-1~---tl,--~!::::::::::~
OR Old Data in FIFO Output Register
------------------~~~----------~I----~ ~-----------
CSB ~l~ow~__________________________________~I
I ________~--------------------
I
W/RB High

j+- th(EN1)
ENB /llZ/?ZZZi/Vl/ZZl/Zl2VZlZT//?7pZ//ZJ
14-- ta --.j
BO-B35 ____________~O~I~d~D~at~a~ln~F~IF~O~O~u~t~pu~t~R~e9~ls~t~er___________J*~----------~W~1----------

t tsk(1) is the minimum time between a rising elKA edge and a rising elKB edge for OR to transition high and to clock the next word to the FIFO
output register in three elKB cycles. If the time between the rising ClKA edge and rising elKB edge is less than tsk(1). the transition of OR high
and the first word load to the output register can occur one ClKB cycle later than shown.

Figure 6. OR-Flag Timing and First-Data-Word Fallthrough When the FIFO Is Empty

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INSTRUMENTS
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 SN74ACT3641
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B-JANUARY 1994-REVISED SEPTEMBER 1995

Ie-- te -----tI
tw(CLKH) l~ ,~
-I tw(CLKL)
CLKB

CSB
I\.{ ' ......._...11
~Lo~w~_________~11
I
' ....._.....J ' ....._--'1 ' _-
.....
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _

I
W/RB High I
I
MBB -=Lo~w~_________rl~--------------------------------------------------
tsu(EN1) 1+=f+i;)h(EN1)
ENB
tIZZ7J I ~~~....:>:..$.., .......- - - - - - - - - - - - - - - - - - -
I
OR High I
'-ta---.l
BO-B35 FIFO Output ReS'Sfer *'"'.:.;;N_ext-..;.:w~or;.;d_F_ro_m_F_IF_O________________________________
jf- tsk(1)t --..114 te ----..I
tw(CLKH) 14 ~ ~ tw(CLKL)

CLKA ~'-_---J/~-~' ) 1 "

tpd(C-IR)
f~I~--~-I.__--~I~!:::==~-I
2 ''-_----'!f ,~---'r-
tpd(C-IR)
IR FIFO Full I I ,"--________
------------------------------ I -
CSA Low I
~~----------------------------------+I--------------
WiRA
I

ENA

AO-A35

t tsk(1) is the minimum time between a rising ClKB edge and a rising ClKA edge for IR to transition high in the next ClKA cycle. If the time between
the rising ClKB edge and rising ClKA edge is less than tsk(1). IR can transition high one ClKA cycle later than shown.

Figure 7. IR-Flag Timing and First Available Write When the FIFO Is Full

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INSTRUMENTS
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SN74ACT3641
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CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

ClKA

ENA
ts u (EN1)
~~1~~~.~.0.$.$.$\~
HI r- th(EN1)
_______________________________________
It- tsk(2)t -,j
ClKB
it----tl~ tpd(C-AE) ~14----.I
AE X Words In FIFO Y(X + 1) Words In FIFO
tsu(EN1) H
J.I4- '-
t h(EN1)

ENB ________________________ ~--------------£/.2.2.?.2.6~~ ~~

t tsk(2) is the minimum time between a rising ClKA edge and a risin~lKB edge for AE to transition high in the next ClKB cycle. lithe time between
the rising ClKA edge and rising C.!:KB edge is less than t s k(2), AE can tra~ition high one ClKB cycle later than shown.
NOTE A: FIFO write (CSA = l, WIRA = H, MBA = l), FIFO read (CSB = l, W/RB = H, MBB = l)

Figure 8. Timing for AE When FIFO Is Almost Empty

*- ts k(2)t -,j
ClKA / , ( '~__-.llr""""'+:....., Y"":"1-"'"'\, ; 2 ''-_..JI
t SU (EN1)H t th(EN1) I I
ENA IlZlfl/J I ""'-\\\~ I :
tpd(C-AF} I~ tpd(C-AF} I+I~---tl~
1,-----
AF [1024 - (Y + 1)] Words In FIFO

I
ClKB ----1 1
' .....- - - . 1 \
tsu(EN1)
J----..\
~ r th (EN1)
I 1
' ....._ - . 1

ENB ________________-&4f.2.2.2.2.2~/ ~~0.$.$.$.$.$\~ ______________________

t tsk(2) is the minimum time between a rising ClKA edge and a rising ClKB edge for AF to transition high in the next ClKA cycle. Ifthetime between
the rising ClKB edge and rising C.!:KA edge is less than ts k(2), AF can tra~tion high one CLKA cycle later than shown.
NOTE A: FIFO write (CSA = l, WIRA = H, MBA = l), FIFO read (CSB = l, W/RB = H, MBB = l)

Figure 9. Timing for AF When FIFO Is Almost Full

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INSTRUMENTS
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 SN74ACT3641
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CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

ClKB ! \ t \ I \ ~ \ t \
tsu(EN1) I~ th(EN1)
1
1
1
1 1
ENB
IVI
tsu(RM) ~ th(RM)
1 '&' 1
1 '$ tsu(RM) ~
1

th(RM)
1
RTM
IZll I ~ i
1 1
I ~ 1
1
h<xxx\
1 1 tsu(RM) ~ th(RM) 1
RFM 1
1
1
1
IIZJ I ~\ 1
1
1 1 1 1
1 1 1 1
OR High
1 1 1 1
I+- ta --.I ~ta-tl I4- ta-tl 14- ta -tI

* * * *
BO-B35 WO W1 W2 WO W1
Initiate Retransmit Mode Retransmit From End Retransmit
With WO as First Word Selected Position Mode

NOTE A: CSB = l, W/RB = H, MBB = L. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit.
Other enables are shown only to relate retransmit operations to the FIFO output register.

Figure 10. Retransmit Timing Showing Minimum Retransmit Length

ClKB / \ t
1
\ h \ ~2
1
\ ...._-..J! --
\ ....
1 1
RTM High 1 1
1 1
-I l-th(RM) 1
tsu(RM) --14--+1 I 1
RFM
mm7J \\\\\\\\ 1
1
I_+--+1.1- tpd(C-AE)
AE _ _ _ _ _ _X_
or_ __
Fewer __
Words _;....;.._ _ _ _ _ _ _ _ _ (X + 1) or More Words From Empty
_ Empty
From

NOTE A: X is the value loaded in the almost·empty flag offset register.

Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X

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INSTRUMENTS
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SN74ACT3641
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

' - tsk(1)t -+I

CLKA , /,---11....' j~1-""'" 12 ''-_-JI
I tpd(C-IR) ~
II"""'O-ne-or~M"o-re--w"rl-te-L-o-ca-t-lo-n-s-A-va"lI-a--ble

,
IR FIFO Filled to First Retransmllt Word

CLKB ----l I
I
I
I
, I , I , I '-
tsu(RM) I- -I" ~I th(RM)
RTM
~ M<xxAA.
t tsk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tsk(1). IR can transition high one CLKA cycle later than shown.

Figure 12. IR Timing From the End of Retransmit Mode When One or More Write Locations Are Available

CLKA ,"-_---J/,.-~I~'
' - ts k(2)t

I
-+I
j"'1-~'
tpd(C-AE)
12
~
''--_oJI ''''_-Jr
_(~1~02~4_-_Y~)~O~rM~o~r~e~w~o~rd~s~p~a~s~~F~I~rst~Re~t~re~n~sm~.~lt~W~o~rd~_ _ _ _ _ _JV~~+-1")-O-rM"o-r-e~w"r"IM-L"o-c-at"lo-n-s~A"v"al"la"b~le

CLKS '",, __.,,1 ''''_-J/ '-

RTM

t tsk(2) is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition high in the next CLKA cycle. Ifthetime between
the rising CLKB edge and rising CLKA edge is less than tsk(2). AF can transition high one CLKA cycle later than shown.
NOTE A: Y is the value loaded in the almost-full flag offset register.

Figure 13. AF Timing From the End of Retransmit Mode When (Y + 1)

or More Write Locations Are Available

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INSTRUMENTS
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 SN74ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

ClKA / \
~
tsU(EN2)
th(EN2)
I
I+-
''-__ I ..J ' ....._ _--'1 '--
------~~~-------------------------------

WiRA /l2ZZ??fl/J» I 1m>'

'I I I
I 1m>'
MBA
/I/lZ2ZZ//74I I
I I
ENA

AO-A35

ClKB /

W/RB

MBB

ENB

BO-B35
FIFO Output Register

Figure 14. Timing for Mail1 Register and MBF1 Flag

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INSTRUMENTS
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SN74ACT3641
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CLOCKED FIRST·IN, FIRST·OUT MEMORY

, ,r- ,\--_...1
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

1 , ' -_ _- JI
ClKB /
~ tsu(EN2)
th(EN2)
'--
------~~~I--------------------------------
I I
S\\\§\\\\\\'l l}m
r
W/RB
II
MBB
2lZl?Z2?/24I IS'
I I
ENB
VZZZZZZ2?I{ W 1

BO-B35
~ I
ClKA / ,'-_---.1_...11 , 1 ,'-----
IF -.j
------------~------~\
tpd(C-MF) r
I
tpd(C-MF) ....j
)~------
I 1

~ i I 1
WiRA ':""'\\~$~$~$~$~i i I {Z"'Z"'Z"'Z"'Z"'Z"'Z""Z""Z-"
MBA ??ZZZd(zmzw1
I I tsu(EN1) ~
i..,
.r th(EN1)
~~~
I
ENA I
I
I P220I ~~$.$.$~'~~I_______
- i
ten H 14 .1 tpd(C-MR) ldls i---.!
AO-A35 - - - - - _ W1 (remains valid In mall2 register after read) Y

Figure 15. Timing for Mall2 Register and MBF2 Flag

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INSTRUMENTS
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 SN74ACT3641
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Vecl ............................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vecl ........................................... ±50 mA
Continuous output current, 10 (Vo = 0 to Vecl ............................................. ±50 mA
Continuous current through Vee or GND ................................................. ±400 mA
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
lunctional operation 01 the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions lor extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current -4 mA
IOL Low-level output current 8 mA
TA Operating Iree-air temperature 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP:j: MAX UNIT
VOH Vee = 4.5 V, IOH =-4 mA 2.4 V
VOL Vee = 4.5 V, IOL=8 mA 0.5 V
II Vee = 5.5 V, VI = Vee orO ±5 vA
IOZ Vee=5.5V, VO= VeeorO ±5 vA
lee Vee = 5.5 V, VI=Vee-0.2VorO 400 vA
eSA=vIH AO-A35 0
eS8=VIH 80-835 0
Vee = 5.5 V, One input at 3.4 V,
Alee§ eSA=VIL AO-A35 1 mA
Other inputs at Vee or GND
eS8=VIL 80-835 1
All other inputs 1
ei VI = 0, 1=1 MHz 4 pF
eo VO=O, 1=1 MHz 8 pF
:j: All tYPical values are at Vee = 5 V, TA = 25°e.
§ This is the supply current when each input is at one 01 the specilied TIL voltage levels rather than 0 V or Vee.

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INSTRUMENTS
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SN74ACT3641
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CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 15)
'ACT3641-15 'ACT3641-20 'ACT3641-30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency, ClKA or ClKB 66.7 50 33.4 MHz
tc Clock cycle time, ClKA or ClKB 15 20 30 ns
tw(CH) Pulse duration, ClKA and ClKB high 6 8 12 ns
tw(Cl) Pulse duration, ClKA and ClKB low 6 8 12 ns
tsu(O) Setup time, AO-A35 before ClKA i and BO-B35 before ClKBi 5 6 7 ns
tsu (EN1) Setup time, ENA to ClKAi; ENB to ClKBi 5 6 7 ns
Setup time, CSA, W/RA, and MBA to ClKAi;
tsu(EN2) 7 7.5 8 ns
CSB, W/RB, and MBB to ClKBi
tsu(RM) Setup time, RTM and RFM to ClKBi 6 6.5 7 ns
tsu(RS) Setup time, RST low before ClKAi or ClKBit 5 6 7 ns
tsu(FS) Setup time, FSO and FS1 before RST high 9 10 11 ns
tsu(SD):f: Setup time, FSO/SD before ClKA i 5 6 7 ns
tsu(SEN):f: Setup time, FS1/SEN before ClKAi 5 6 7 ns
th(D) Hold time, AO-A35 after ClKAi and BO-B35 after ClKBi 0 0 0 ns
tn(EN1) Hold time, ENA after ClKAi; ENB after ClKBi 0 0 0 ns
Hold time, CSA, W/RA, and MBA after ClKAi;
tn(EN2) 0 0 0 ns
CSB, W/RB, and MBB after ClKBi
tn(RM) Hold time, RTM and RFM after ClKBi 0 0 0 ns
th(RS) Hold time, RST low after ClKAi or ClKBi t 5 6 7 ns
th(FS) Hold time, FSO and FS1 after RST high 0 0 0 ns
th(SP):f: Hold time, FS1/SEN high after RST high 0 0 0 ns
th(SD):f: Hold time, FSO/SD after ClKAi 0 0 0 ns
th(SEN):I: Hold time, FS1/SEN after ClKA i 0 0 0 ns
tskill§ Skew time between ClKAi and ClKBi for OR and IR 9 11 13 ns
ts k(2)§ Skew time between ClKAi and ClKBi for AE and AF 12 16 20 ns
t ReqUIrement to count the clock edge as one of at least four needed to reset a FIFO
:f: Only applies when serial load method is used to program flag-offset registers
§ Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and
ClKB cycle.

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INSTRUMENTS
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 SN74ACT3641
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 1 through 15)
'ACT3641-15 'ACT3641-20 'ACT3641-30
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency, CLKA or CLKB 66.7 50 33.4 MHz
ta Access time, CLKBi to BO-B35 3 11 3 13 3 15 ns
tpd{C-IR) Propagation delay time, CLKAi to IR 1 8 1 10 1 12 ns
tpd{C-OR) Propagation delay time, CLKBi to OR 1 8 1 10 1 12 ns
tpd{C-AE) Propagation delay time, CLKBi to AE 1 8 1 10 1 12 ns
tpd(C-AF) Propagation delay time, CLKAi to AF 1 8 1 10 1 12 ns
Propagation delay time, CLKAi to MBFl low or MBF2 high and
tpd{C-MF) 0 8 0 10 0 12 ns
CLKBi to MBF2 low or MBFl high
Propagation delay time, CLKAi to BO- B35t and CLKBi to
tpd{C-MR) 3 13.5 3 15 3 17 ns
AO-A35:t:
tpd{M-DV) Propagation delay time, MBB to BO-B35 valid 3 13 3 15 3 17 ns
tpd(R-F) Propagation delay time, RST low to AE low and AF high 1 15 1 20 1 30 ns
Enable time, eSA and W/RA low to AO-A35 active and CSB low
ten 2 12 2 13 2 14 ns
and W/RB high to BO-B35 active
Disable time, CSA or W/RA high to AO-A35 at high impedance
tdis 1 8 1 10 1 11 ns
and eSB high or W/RB low to BO-B35 at high impedance
t Writing data to the maill register when the BO-B35 outputs are active and MBB is high
:j: Writing data to the mail2 register when the AO-A35 outputs are active and MBA is high

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-51
SN74ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

SUPPLY CURRENT
vs
CLOCK FREQUENCY
250r---r---r---r---r---r---r---,

< 200
E
I
;:
~
0= 150
~
Q.
Q.
=
III
I 100
!E
0
0
50

10 20 30 40 50 60 70
fclock - Clock Frequency - MHz

Figure 16

calculating power dissipation

The ICC(f) current in Figure 16 was taken while simultaneously reading and writing the FIFO on the
SN74ACT3641 with ClKA and ClKS set to fclock' All data inputs and data outputs change state during each
clock cycle to consume the highest supply current. Data outputs are disconnected to normalize the graph to a
zero-capacitance load. Once the capacitive load per data-output channel and the number of SN74ACT3641
inputs driven by TTL high levels are known, the power dissipation can be calculated with the equation below.
With ICC(!) taken from Figure 16, the maximum power dissipation (PT) of the SN74ACT3641 can be calculated
by:
PT =VCC x [ICC(!) + (N x ~Icc x dc)] + I(CL x VCc 2 x fo)
where:
N = number of inputs driven by TTL levels
~Icc = increase in power supply current for each input at a TTL high level
dc = duty cycle of inputs at a TTL high level of 3.4 V
CL = output capacitive load
fo = switching frequency of an output
When no reads or writes are occurring on the SN74ACT3641 , the power dissipated by a single clock (ClKA
or ClKS) input running at frequency fclock is calculated by:
PT = Vcc x fclock x 0.29 mA/MHz

~TEXAS
INSTRUMENTS
11-52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

5V

1.1 leO
From Output
Under Test - - . - - - - .

6800 -:::~ 30pF

;;0 F- (see Note A)

LOAD CIRCUIT

-----.If~ --;.~
3V
Timing ~ High-Level - 3V
Input Ii 1.5 V Input ,.~. ~ GND
_ _--J..q.. - - - - - GND
tsu~th It- tw --+I
I I
Data, ~-:-::- 3V
~
I 3V
Enable ~ 1.5V ~ Low-Level 1.5 V 1.5 V
Input GND Input _ _ _ _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

3V
Output
Enable --'IL 1.5 V GND
-+I i~tPLZ
Low-Level
Output I
II~--~
_-+..JI
~3V

VOL
Input J(1.5V ~5-; --::D
~tPZH tpd --14--+1 i4----+l- tpd
VOH
High-Level
Output I I In-Phase 1/---.... I - - VOH
I I ~OV Output T 1.5 V
_ _....J.
\L~ 1.5 V
VOL
-+I l~tpHZ

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 17. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-53
11-54
 SN74ACT3651
2048 x36
CLOCKED FIRST FIRST·OUT MEMORY

• Free-Running ClKA and ClKB Can Be • Output-Ready (OR) and Almost-Empty (AE)
Asynchronous or Coincident Flags Synchronized by ClKB
• Clocked FIFO Buffering Data From Port A • low-Power O.B-Mlcron Advanced CMOS
to Port B Technology
• Synchronous Read-Retransmit Capability • Supports Clock Frequencies up to 67 MHz
• Mailbox Register In Each Direction • Fast Access Times of 11 ns
• Programmable Almost-Full and • Pin-to-Pin Compatible With the
Almost-Empty Flags SN74ACT3631 and SN74ACT3641
• Microprocessor Interface Control logic • Available in Space-Saving 120-Pin Thin
• Input-Ready (IR) and Almost-Full (AF) Flags Quad Flat (PCB) and 132-Pin Plastic Quad
Synchronized by ClKA Flat (PQ) Packages

description
The SN74ACT3651 is a high-speed, low-power, CMOS clocked FIFO memory that supports clock frequencies
up to 67 MHz and has read access times as fast as 12 ns. The 2048 x 36 dual-port SRAM FIFO buffers data
from port A to port S. The FIFO memory has retransmit capability, which allows previously read data to be
accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words is stored in memory. Communication
3:
between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal
when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths.
w
Expansion is also possible in word depth. 5>
w
The SN74ACT3651 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
a:
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
D..
coincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control. b
:::l
The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to ClKA. The
C
output-ready (OR) flag and almostcempty (A E) flag of the FIFO are two-stage synchronized to ClKS. Offset
values for the almost-full and almost-empty flags of the FIFO can be programmed from port A or through a serial oa:
input.
The SN74ACT3651 is characterized for operation from O°C to 70°C.
D..
For more information on this device family, see the application reports FIFO Patented Synchronous Retransmit:
Programmable DSP-Interface Application for FIR Filtering and FIFO Mailbox-Bypass Registers: Using Bypass
Registers to Initialize DMA Control in the 1996 High-Performance FIFO Memories DeSigner's Handbook,
literature number SCAA012A.

PRODUCT PREVIEW Information concema producta In the formative or Copyright ~ 1995. Texas Instruments Incorporated

~TEXAS
deSign phase of development. Characterlsdc data and other
spaclflcatlons ... design goals. T_lnstruments _MIl the ~ght fo
change or dlsconUn.. th... products without nOfIcs.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-55
 SN74ACT3651
2048x36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A-JUNE 1994- REVISED SEPTEMBER 1995

A35 90 B35
A34 89 B34
A33 88 B33
A32 87 B32
Vee 86 GND
A31 85 B31
A30 84 B30
GND 83 B29
A29 82 B28
A28 81 B27
A27 80 B26
A26 79 Vee
A25 78 B25
A24 77 B24
"tJ A23 76 GND
::D GND 75 B23
oC A22
Vee
A21
74
73
72
B22
B21
B20
c: A20 71 B19
o-I A19
A18
70
69
B18
GND
GND 68 B17
"tJ A17 67 B16
A16 66 Vee
::D A15 B15
m A14
65
64 B14

-
<
m
A13
Vee
63
62
B13
B12

:e A12 GND

~~~~~~~~~~~8~<~~~m~~~~~m8~~m~~
c:l c:l.::> c:l c:l::>
Ne - No internal connection

~1ExAs
INSTRUMENTS
11-56 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3651
2048 x36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

PQPACKAGEt
(TOP VIEW)

NC NC
635 NC
634 A35
633 A34
632 A33
GND A32
631 VCC
630 A31
629 A30
628 GND
627 A29
626 A28
VCC
625
A27
A26 3:
w
624
GND
623
A25
A24
A23
s:w
622
621
GND
A22
a:
Q.
620 VCC
619
618
GND
A21
A20
A19
b
::J
617 A18
616 GND
C
VCC A17 o
a:
615 A16
614 A15 Q.
613 A14
612 A13
GND VCC
NC A12
NC NC

NC - No internal connection
t Uses Yamaichi socket IC51-1324-828

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-57
 SN74ACT3651
2048 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS439A- JUNE 1994 - REVISED SEPTEMBER 1995

functional block diagram

.. I
•
Malll I
MBFl

T~
Register I
CLKA -
CSA - Port-A
W/RA - Control .....-
ENA - Logic I-- ~
.....- ~
1 ...
-
MBA I--

'5Q.
2048x36
SRAM
.. ~
:::I
Reset t~
+
Logic .5
'---

36 .c~(J
u CI')._
RTM
c c Cl
>-f!0 f+
II Pointer
Write II Read
Pointer
~
tn1)..J
II:
RFM

"tJ AO-A35
t t BO-B35

:D IR Status-Flag
Logic
I
OR
AE
0 AF

C
C
+
FSO/SD Flag-Offset
0
~ W/RB
FSl/SEN Register I-- CLKB
-I 10 - I--
Port-B CSB

~
Control
"tJ Mall2
Logic
ENB
:D L.c~ Register f-4- MBB
m
-<m MBF2
"
:e

~1EXAS
INSTRUMENTS
11-58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3651
2048 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A-JUNE 1994- REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME
AO-A35 .1/0 Port-A data. The 36-bit bidirectional data port for side A.
Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less
AE 0
than or equal to the value in the almost-empty offset register (X).
Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO
AF 0
is less than or equal to the value in the almost-full offset register (Y).
BO-B35 I/O Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
CLKA I
or coincident to CLKB. IRand AF are synchronous to the low-to-high transition of CLKA.
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
CLKB I
or coincident to CLKA. OR and AE are synchronous to the low-to-high transition of CLKB.
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
CSA I
AO-A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
CSB I
BO-B35 outputs are in the high-impedance state when CSB is high.
ENA I Port-A master enable. ENA must be high to enable a low-to-high transiiion of CLKA to read or write data on port A.

~
ENB I Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
Flag-offset select 1/serial enable, flag-offset select O/serial data. FS1/SEN and FSO/SD are dual-purpose inputs used
for flag-offset-register programming. During a device reset, FS1/SEN and FSO/SD select the flag-offset programming
method. Three offset-register programming methods are available: automatically load one of two preset values, parallel :;
FS1/SEN,
I
load from port A, and serial load. w
FSO/SD When serial load is selected for flag-offset-register programming, FS1/SEN is used as an enable synchronous to the a:
,
low-to-high transition of CLKA. When FS1/SEN is low, a rising edge on CLKA loads the bit present on FSO/SD into the
X and Y offset registers. The number of bit writes required to program the offset registers is 22. The first bit write stores
a..

IR 0
the V-register MSB and the last bit write stores the X-register LSB.
InpuFready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes to
its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point
b
::l
of the retransmit data and prevents further writes. IR is set low during reset and is set high aiter reset. C
MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
oa:
MBB I BO-B35 outputs are active; a high level on MBB selects data from the mail1 register for output and a low level selects
FIFO data for output.
a..
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. MBF1
MBF1 0 is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by a
reset.
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. MBF2
MBF2 0 is set high by a low-to-high transition of CLKA when·a port-A read is selected and MBA is high. MBF2 is set high by a
reset.
Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and
OR 0 reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during
the reset and goes high on the third low-to-high transition of CLKB aiter a word is loaded to empty memory.
Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to reset
RFM I
the read pointer to the beginning retransmit location and output the first selected retransmit data.
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
RST I
while RST is low. The low-to-high transition of RST latches the status of FSO and FS1 for AF and AE offset selection.
Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high
transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected
RTM I
word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low, taking the FIFO
out of retransmit mode.

-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-59
 SN74ACT3651
2048 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS439A-JUNE 1994- REVISED SEPTEMBER 1995

Terminal Functions (Continued)

TERMINAL
I/O DESCRIPTION
NAME
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a
WiRA I
low-ta-high transition of ClKA. The AO-A35 outputs are in the high-impedance state when WiRA is high.
Port-B write/read select. A Iowan W/RB selects a write operation and a high selects a read operation on port B for a
IN/RB I
low-to-high transition of ClKB. The BO-B35 outputs are in the high-impedance state when IN/RB is low.

detailed description
reset
The SN74ACT3651 is reset by taking the reset (RST) input low for at least four port-A clock (ClKA) and four
port-B clock (ClKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset
initializes the memory read and write pointers and forces the input-ready (IR) flag low, the output-ready (OR)
flag high, the almost-empty (AE) flag low, and the almost-full (AF) flag high. Resetting the device also forces
the mailbox flags (MBF1,MBF2) high. After a FIFO is reset, IRis set high after at least two clock cycles to begin
normal operation. A FIFO must be reset after power up before data is written to its memory.
almost-empty flag and almost-full flag offset programming
"tJ
:D Two registers in the SN74ACT3651 are used to hold the offset values for the almost-empty and almost-full flags.
o The almost-empty (AE) flag offset register is labeled X, and the almost-full (AF) flag offset register is labeled Y.
The offset registers can be loaded with a value in three ways: one of two preset values are loaded into the offset
C registers, parallel load from port A, or serial load. The offset-register-programming mode is chosen by the flag
C select (FS1, FSO) inputs during a low-to-high tranSition on RST (see Table 1).
o
-I Table 1. Flag Programming
"tJ FS1 FSO RST X AND Y REGISTERst
:D
m H H l' Serial load

S H l l'
l'
64

m l H
l'
8

~
l l Paralielload from port A
t X register holds the offset for AE; Y register holds the
offset for AF.

preset values
If a preset value of 8 or 64 is chosen by FS1 and FSO at the time of a RST low-to-high transition according to
Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is
necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on ClKA.
parallel load from port A
To program the X and Y registers from port A, the device is reset with FSO and FS1 low during the low-to-high
transition of RST. After this reset is complete, the IR flag is set high after two low-to-high transitions on ClKA.
The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X.
Each offset register of the SN74ACT3651 uses port-A inputs (A10-AO). The highest number input is used as
the most significant bit of the binary number in each case. Each register value can be programmed from 1 to
2044. After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM.

~TEXAS
INSTRUMENTS
11-60 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3651
2048 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

serial load
To program the X and Y registers serially, the device is reset with FSO/SD and FS1/SEN high during the
low-to-high transition of RST. After this reset is complete, the X and Y register values are loaded bitwise through
FSO/SD on each low-to-high transition of GlKA that FS1/SEN is low. Twenty-two-bit writes are needed to
complete the programming. The first-bit write stores the most significant bit ofthe Y register and the last-bit write
stores the least significant bit of the X register. Each register value can be programmed from 1 to 2044.
When the option to program the offset registers serially is chosen, the input-ready (IR) flag remains low until
all register bits are written. The IR flag is set high by the low-to-high transition of GlKA after the last bit is loaded
to allow normal FIFO operation.
FIFO write/read operation
The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (GSA) and the port-A
write/read select (WiRA). The AD-A35 outputs are in the high-impedance state when either GSA or W/RA is
high. The AD-A35 outputs are active when both GSA and W/RA are low.
Data is loaded into the FIFO from the AD-A35 inputs on a low-to-high transition of GlKA when GSA and the
port-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the input-ready (IR) flag are high
(see Table 2). Writes to the FIFO are independent of any concurrent FIFO reads.

Table 2. Port·A Enable Function Table 3:

W/RA ENA W
CSA
H X X
MBA
X
ClKA
X
AD-A35 OUTPUTS
In high-impedance state
PORT FUNCTION
None :;
l H L X X In high-impedance state None w
L H H L i In high-impedance state FIFO write £t
L H H H i In high-impedance state Mall1 write a..
L
L
L
L
L
L
L
H
L
L
L
H
X
i
X
Active, mail2 register
Active, mail2 register
Active, mail2 register
None
None
None
b
::l
L L H H i Active, mail2 register Mail2 read (set MBF2 high) C
The port-B control signals are identical to those of port A with the exception that the port-B write/read select
o£t
(W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (BO-B35) outputs is a..
controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The BO-B35 outputs are
in the high-impedance state when either GSB is high orW/RB is low. The BO-B35 outputs are active when GSB
is low and W/RB is high.
Data is read from the FIFO to its output register on a low-to-high transition of GlKB when GSB and the port-B
mailbox select (MBB) are low, W/RB, the port-B enable (ENB), and the output-ready (OR) flag are high
(see Table 3). Reads from the FIFO are independent of any concurrent FIFO writes.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 11-01
 SN74ACT3651
2048 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS439A-JUNE 1994- REVISED SEPTEMBER 1995

Table 3. Port-B Enable Function Table

CSB W/RB ENB MBB ClKB BO-B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L L L X X In high-impedance state None
L L H L l' In high-impedance state None
L L H H l' In high-impedance state Mail2write
L H L L X Active, FIFO output register None
L H H L l' Active, FIFO output register FIFO read
L H L H X Active, mail1 register None
L H H H l' Active, mail1 register Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-Chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select can change states during the
setup- and hold-time window of the cycle.
When OR is low, the next data word is sent to the FIFO output register automatically by the ClKB low-to-high
transition that sets OR high. When OR is high, an available data word is clocked to the FIFO output register only
'"C when a FIFO read is selected by the port-B chip select (CSB), write/read select (W/RB), enable (ENB), and
::c mailbox select (MBB).
oc synchronized FIFO flags
c Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the
o flags' reliability by reducing the probability of metastable events on their outputs when ClKA and ClKB operate
-I asynchronously to one another (see the application report Metastability Performance of Clocked FIFOs in the
1996 High-Performance FIFO Memories Data Book, literature number SCAD003C). OR and AE are
'"C
::c synchronized to ClKB. IR and AF are synchronized to ClKA. Table 4 shows the relationship of each flag to the
number of words stored in memory.
m
<
- Table 4. FIFO Flag Operation
m SYNCHRONIZED SYNCHRONIZED
:E NUMBER OF WORDS IN
FIFOti
TOClKB TOClKA
OR AE AF IR
0 L L H H
1 to X H L H H
(X + 1) to [2048 - (Y + 1)] H H H H
(2048 - Y) to 2047 H H L H
2048 H H L L
t X IS the almost-empty offset for AE. Y is the almost-full offset for AF.
t When a word is present in the FIFO output register, its previous memory
location is free.

-!I11ExA.s
INSTRUMENTS
11-62 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3651
2048 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

output-ready flag (OR)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array (ClKS). When
OR is high, new data is present inthe FIFO output register. When OR is low, the previous data word is present
in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine
that controls an output"ready flag monitors a write-·pointer and read-pointer comparator that indicates when the
FIFO SRAM status is empty, empty+ 1, or empty+2. From the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of ClKS; therefore, an output-ready flag is low if a word
in memory is the next data to be sent to the FIFO output register and three ClKS cycles have not elapsed since
the time the word was written. The output-ready flag of the FIFO remains low until the third low-to-high transition
of ClKS occurs, simultaneously forcing the output-ready flag high and shifting the word to the FIFO output
register.
A low-to-high transition on ClKS begins the first synchronization cycle of a write if the clock transition
occurs at time tsk(1), or greater, after the write. Otherwise, the subsequent ClKS cycle can be the first
synchronization cycle (see Figure 6).
input-ready flag (IR)
The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array (ClKA). When the
input-ready flag is high, a memory location is free in the SRAM to write new data. No memory locations are free
~
when the input-ready flag is low and attempted writes to the FIFO are ignored. w
Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an 5>
input-ready flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM w
status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready
a:
to be written in a minimum of three cycles of ClKA; therefore, an input-ready flag is low if less than two cycles
of ClKA have elapsed since the next memory write location has been read. The second low-to-high transition
a..
on ClKA after the read sets the input-ready flag high, and data can be written in the following cycle.
A low-to-high transition on ClKA begins the first synchronization cycle of a read if the clock transition
t;
occurs at time t sk(1), or greater, after the read. Otherwise, the subsequent ClKA cycle can be the first
::J
C
synchronization cycle (see Figure 7).
almost-empty flag (A E)
oa:
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array (ClKS). The a..
state machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that
indicates when the FIFO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty
state is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset,
programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset
programming). The almost-empty flag is low when the FI FO contains X or less words and is high when the FI FO
contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory.
Two low-to-high transitions of ClKS are required after a FIFO write for the almost-empty flag to reflect the new
level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1) or more words remains low if two cycles
of ClKS have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set
high by the second low-to-high transition of ClKS after the FIFO write that fills memory to the (X + 1) level.
A low-to-high transition of ClKS begins the first synchronization cycle if it occurs at time tsk(2), or greater, after
the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent ClKS cycle can be the first
synchronization cycle (see Figure 8).

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-63
 SN74ACT3651
2048 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

almost-full flag (AFJ

The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array (ClKA). The state
machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by
the contents of register Y. This register is loaded with a preset value during a FI FO reset, programmed from port
A, or programmed serially (see almost-empty flag and almost-full flag offset programming). The almost-full flag
is low when the number of words in the FIFO is greater than or equal to 2048 - V). The almost-full flag is high
when the number of words in the FIFO is less than or equal to [2048 - (Y + 1)]. A data word present in the FIFO
output register has been read from memory.
Two low-to-high transitions of ClKA are required after a FIFO read for its almost-full flag to reflect the new level
offill. Therefore, the almost-full flag ofa FIFO containing [2048 - (Y + 1)] or less words remains low if two cycles
of ClKA have not elapsed since the read that reduced the number of words in memory to [2048 - (Y + 1)]. An
almost-Jull flag is set high by the second low-to-high transition of ClKA after the FIFO read that reduces the
numberof words in memory to [2048 - (Y + 1)]. A low-to-high transition of ClKA begins the first synchronization
cycle if it occurs at time tsk(2), or greater, after the read that reduces the number of words in memory to
[2048 - (Y + 1)]. Otherwise, the subsequent ClKA cycle can be the first synchronization cycle (see Figure 9).
synchronous retransmit
The synchronous-retransmit feature of the SN74ACT3651 allows FIFO data to be read repeatedly starting at
"C a user-selected position. The FIFO is first put into retransmit mode to select a beginning word and prevent
JJ
o on-going FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three
words can retransmit repeatedly starting at the selected word. The FIFO can be taken out of retransmit mode
C at any time and allow normal device operation.
C
o-I The FIFO is put in retransmit mode by a low-to-high transition on ClKB when the retransmit-mode (RTM) input
is high and OR is high. This rising ClKB edge marks the data present in the FIFO output register as the first
retransmit data. The FIFO remains in retransmit mode until a low-to-high transition occurs while RTM is low.
"C
JJ When two or more reads have been done past the initial retransmit word, a retransmit is initiated by a low-to-high
m transition on ClKB when the read-from-mark (RFM) input is high. This rising ClKB edge shifts the first

-m< retransmit word to the FIFO output register and subsequent reads can begin immediately. Retransmit loops can
be done endlessly while the FIFO is in retransmit mode. RFM must be low during the ClKB rising edge that takes
the FiFO out of retransmit mode.
~ When the FIFO is put into retransmit mode, it operates with two read pOinters. The current read pOinter operates
normally, incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE
flags. The shadow read pOinter stores the SRAM location at the time the device is put into retransmit mode and
does not change until the device is taken out of retransmit mode. The shadow read pointer is used by the IR
and AF flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set low by the write that
stores (2048 - Y) words after the first retransmit word. The IR flag is set low by the 2048th write after the first
retransmit word.
When the FIFO is in retransmit mode and RFM is high, a rising ClKB edge loads the current read pOinter with
the shadow read-pointer value and the OR flag reflects the new level of fill immediately. If the retransmit changes
the FIFO status out of the almost-empty range, up to two ClKB rising edges after the retransmit cycle are
needed to switch AE high (see Figure 11). The rising ClKB edge that takes the FIFO out of retransmit mode
shifts the read pOinter used by the IR and AF flags from the shadow to the current read pOinter. If the change
of read pointer used by IR and AF should cause one or both flags to transition high, at least two ClKA
synchronizing cycles are needed before the flags reflect the change. A rising ClKA edge after the FI FO is taken
out of retransmit mode is the first synchronizing cycle of IR if it occurs at time tsk(1), or greater, after the rising
ClKB edge (see Figure 12). A rising ClKA edge after the FIFO is taken out of retransmit mode is the first
synchronizing cycle of AF if it occurs at time t sk(2), or greater, after the rising ClKB edge (see Figure 14).

~TEXAS
INSTRUMENTS
11-64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3651
2048 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

mailbox registers
Two 36-bit bypass registers pass command and control information between port A and port B. The
mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation.
A low-to-high transition on GlKA writes AO-A35 data to the mail1 register when a port-A write is selected by
GSA, W/RA, and ENA with MBA high. A low-to-high transition on GlKB writes BO-B35 data to the mail2 register
when a port-B write is selected by GSB, W/RB, and ENB with MBB high. Writing data to a mail register sets its
corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while its mail flag is
low.
When the port-B data (BO-B35) outputs are active, the data on the bus comes from the FIFO output register
when the port-B mailbox select (MBB) input is low and from themail1registerwhenMBBishigh.Mail2 data
is always present on the port-A data (AO-A35) outputs when they are active. The mail1 register flag (MBF1)
is set high by a low-to-high transition on GlKB when a port-B read is selected by GSB, W/RB, and ENB with
MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on GlKA when a port-A read
is selected by GSA, W/R.A, and ENA with MBA high. The data in a mail register remains intact after it is read
and changes only when new data is written to the register.

CLKA

CLKB
1 I It
3:
w
-..I ~ tsu(RS) 1 1 I...~ h(FS) 1
_ _ _ _......,1 1 1 tsu(FS) 1:--"1 I I 5>
RST).
1 1
1
1
II
I
I w
a:
FS1, FSO
a..
~ tpd(C-IR) ~ I tpd{C-IR) ~ t-
IR ~~ : ,,----
O
tpd(C-OR) 1.-.1 ::J
OR~~\\\~~ C
tpd{R-F) !----i oa:
AE \\\\\\\S\~ a..
tpd(R-F) '---i
AF vzz;rA/ZTa
__ tpd(R-F) !+----.I
~~F~ mzmzzzz/
Figure 1. FIFO Reset Loading X and Y With a Preset Value of Eight

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-65
 SN74ACT3651
2048 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A-JUNE 1994- REVISED SEPTEMBER 1995

CLKA

ENA 2ZZZZZZZ/Z/ZZZZ/ZZ///Z?//ldJ' ! WQQQ? ~ W\\§

-.. j+-.: th(D)

AO-A35
AF Offset AE Offset First Word Stored In FIFO
(Y) (X)

NOTE A: CSA = L, WiRA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.

"'C Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values From Port A
:IJ
o
C CLKA
c: 1 I
o-I RST _ _........ t 1
1
I
I
1 1 tpd(C-IR) *"~_--.1.1
"'C
:IJ IR
~:____________~__--------~,,~----~i~---------Jy--
______1
m - ~ ~ t- th(SP) 1- th(SEN) t )' --.j th(SEN)
tsu(FS) 1++1 tsu(SEN) H 1 su(SEN) 14-+1 1
~ FSl/SEN 2ZZZJ~~"""';'II---""";;';;;~\ I.M&>$& ~~ Y4""'/"":;:~211'"":?/:""'/""2"",?:;:""2""2""211'"":2""'?/""
m =ii ~ - Ji= th(SD)
:E ..,~..,U~(F,..S),...,.~_...,
FSO/SD
AF Offset AE Offset
(y)MSB (X)LSB

NOTE A: It is not necessary to program offset-register bits on consecutive clock cycles. FIFO write attempts are ignored untillR is set high.

Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially

~ThXAS
INSTRUMENTS
11-66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3651
2048 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

I. Ie tI
Iw(CLKH} I· .1. .: Iw(CLKL}

r
I
CLKA 1 '\ \ I
I
\ ( '--
I I
I I I
IR High
I I
Isu(EN} I14 .:., Ih(EN)
I I

~14 I~
I
CSA
I
1/
I I
Isu(EN} .1 4 ~ Ih(EN} I I
W/RA 7!ZlZ2?//Zl/f
Isu(EN} ~
IF
.1 4 ~ Ih(EN}
I
I
I
I \\\\\\\\~
I
MBA I 1 I

ENA I
Isu(D) 14 .1 ..1Ih(D}
AO-A35 'No Operallon $8888888?
3:
Figure 4. FIFO Write-Cycle Timing
->w
W

Iw(CLKH}
CLKB
----+I.:
J..'4----1c ---~.I
::+4- - -....11+4

1.-----.\'--__ ~1
Iw(CLKL)
\ ( \ yr----..'--
0::
a..
I-
I 1 I o
1 I I ::J
OR High I I I C
}
1
I
I
I
I
: /
o0::
I I I a..
WIRB
22/4:I I
:I \S\\\\\"-~
MBB ---+-1---'\, I I

: i l:sU(EJ I:SU(EN~ ~U(EN~:

I I I I+- Ih(EN} I ---+j j4---- Ih(EN} I ---tI 14- Ih(EN}
ENB
0?2?p7flZ1 :~ : \\\\\\\\\\j /??fiZ2Zl/
1 14 ·1 :'-ta -J 1 OP:~llon u
*
Ipd(M-DV} I _I Idls
j4" l en.l 1 1 j+-a-" Ii
BO-B35 -----~ W1 W2 X W3 j

Figure 5. FIFO Read-Cycle Timing

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-67
 SN74ACT3651
2048 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

ClKA
I
CSA ~lo~w~ ____ ~I
I______+-________________________________________________
I
WiRA High ~ I
Isu(EN) i -+' I.-- Ih(EN)

MBA 07/TAJ WAT/ZZ2?!ZZ/2?ZZZZ///ZZZ/l/2ZZZlV?ZZ0

ISU(EN? 14-- th(EN)
ENA IZZZZd I ~\",;l\:",;:~",;:~,",~..,;:"~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
I I
IR High I I

AO-A35 ~ tsk(1)t 14 ~4 I~ te
Iw(ClKH)---tj j+- I tw(ClKl)
ClKB 2
"C tpd(C-OR) "'I~---.t.---l!=::::::~
:D OR Old Data In FIFO Output Register
oC --------------~_~ _ _ _ _ __+I---J ~-------

CSB lO_w__________________________________
__
I +I---------+-------------------
C I
o W/RB High I I
-f
"C MBB low
I
I J I

:D 7. I
ISU;N~
.-
I- Ih(EN)
m
S BO-B35 _____________0~I~d~D~at~a~ln~F~IF~O~O~u~tp~u~tR~e~9~ls~te~r__________~*----------~W~1---------
m
:e t tsk(1) is the minimum time between a rising ClKA edge and a rising ClKS edge for OR to transition high and 10 clock the next word to the FIFO
output register in three ClKS cycles. If the time between the rising ClKA edge and rising ClKS edge is less than t5 k(I). then the transition of
OR high and the first word load to the output register can occur one ClKS cycle later than shown.

Figure 6. OR-Flag Timing and Flrst-Data-Word Fallthrough When the FIFO Is Empty

~lExAs
INSTRUMENTS
11-68 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3651
2048 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

I . - - Ie -----tI
1
14
tw(ClKH)
.,
,41
-I tw(ClKl)
ClKBI , __JII ~ \ ~ __J / \""'____oJ/ \""'____oJ/ ---
\ ....
CSB ~lO~W~________+I__________________________________________________

1
W/RB High 1
MBB ~lO~W~ ________ 1
~I~ ________________________________________________
tsu(EN) I+=f':;IJc\t!(EN)

~ 1~~0~$~$~~~~----------------------------------------_
ENB

OR High I
'-ts-.l
BO-B35 FIFO Output ReSl1er ~r~Ne-xt~W~o-r"":'d'=Fr-om"""":FI:":FO=------------------------------
j4- tsk(1)t -.I I

~""__---Jlr---....\
tw(ClKH) 14
14

l1
Ie-
~
'l
t.,- tw(ClKl)
\ ...._~I \'-__---J~ 3:
ClKA 2
w
IR FIFOFuU
tpd(C-IR) rI4--~-1,.....__--l:14!::::=~~ tpd(C-IR)
I I \ :;:
----------~~~----------------~ 1 '--------- W
CSA low 1 II:
~~----------------------~I-------------- a.
High 1
W/RA
t;
MBA
::J
C
ENA
oII:
AO-A35 a.
t tsk(1) is the minimum time between a rising ClKS edge and a rising ClKA edge for IR to transition high in the next ClKA cycle. lithe time between
the rising ClKS edge and rising ClKA edge is less than tsk(1). then IR can transition high one ClKA cycle later than shown.

Figure 7. IR-Flag Timing and First Available Write When the FIFO Is Full

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-e9
 SN74ACT3651
2048 x 36 •
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A- JUNE 1994 - REVISED SEPTEMBER 1995

ClKA
tsu EN I ~ ~ th(EN)
ENA
«??~~~$.$.$~~~'~--------------------------------
If- tsk(2)t -t/
_ _--,:2
ClKB
~ tpd(C-AE) -tj tpd(C-AE) 14 "I
AE X Words In FIFO Y(X + 1) Words In FIFO j '-
tsu(EN) i+---"I ~ th(EN)
ENB ______________________________________________~~~/.~~2.?~?~?~4' ~~
t tsk(2) is the minimum time between a rising ClKA edge and a rising ClKB edge lor AE to transition high in the next ClKB cycle. If the time between
the rising ClKA edge and rising C.!,KB edge is less than tsk(2). then AE ca.!!..transition high one ClKB cycle later than shown.
NOTE A: FIFO write (CSA = l. W/RA = H. MBA =l). FIFO read (CSB = l. W/RB. H. MBB =l)

Figure 8. Timing for AE When FIFO Is Almost Empty

I.- tsk(2)t -t/

"tJ
:D
oC
ClKA / ,
tsu(EN)
t
~ I+- th(EN)
, /"'--+-I. . .,
1
Y....1 - " " ' \ \ Y2
1
,'----',
ENA «ZlZT~~ 1 I
C tpd(C.AF) 14 tpd(C-AF) 141"--",,-1
o AF [2048 - (Y + 1)] Words In FIFO
ir----
-I
"tJ
:D
m
ClKB---I
'----
< ENB ____________________~~~/.~~?~??~2~ ~0~~~~~~$.~~~~ ___________________________
-
m t tsk(2) is the minimum time between a rising ClKA edge and a rising ClKB edge lor AFto transition high in the next ClKAcycle.lfthetime between
~ the rising ClKB edge and rising C.!,KA edge is less than tsk(2). then AF ca.!!..transition high one ClKA cycle later than shown.
NOTE A: FIFO write (CSA =l. W/RA = H. MBA _ l). FIFO read (CSB =l. W/RB = H. MBB _ l)

Figure 9. Timing for AF When FIFO Is Almost Full

-!!1lExAs
INSTRUMENTS
11-70 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

•
 SN74ACT3651
2048 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A-JUNE 1994- REVISED SEPTEMBER 1995

ClKB / ,
tsu(EN) I~
t
th(EN)
'. . . _-J 1
I
,
tsu(EN)
I
J::t:L th(EN)
\ t
I
'----
ENB _ _......«"""/."""/.'-J7 I 'W' ~
tsu(EN) ~ th(EN) tsu(EN) ~ th(EN)
RTM _ _......~'..J 1'7/7 I ~ I \\,,~ II~
I tsu (EN) I+-+j4+I th(EN) I
RFM -------rl-----..,.---,(;../.. . /:<.JI'J : t\\\ I
I I I
OR HIgh
I I I I
I I I I
~ts~ ~ts~ ~ts~ ~ts~
BO-B35 -----:W~0:-----*--":':W:":"'1--*--~W::::2--* WO *'---:':W~1-
InItIate RetransmIt Mode RetransmIt From End RetransmIt
WIth WO as FIrst Word Selected PosItIon Mode

NOTE A: CSB = L, iN/RB =H, MBB =L. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit.
Other enables are shown only to relate retransmit operations to the FIFO output register.

Figure 10. Retransmit Timing Showing Minimum Retransmit Length ~

W
:;
ClKB / \ t
I
I
\ h \ ~2
I
'....._ - / ''--- w
a:
D..
I
RTM High I I t-
I I O
-I
l_th(RM) I ::l
tSU(RM)~1 I I
mm?J \\\\\\\\ C
RFM

I__-..,~~I- tpd(C-AE)
I
I oa:
AE _ _ _ _ _ _X
_ or_
Fewer
__ Words
__ From
__ Empty
.;...;._ _ _ _ _ _ _ _ _ (X + 1) or More Words From Empty D..
NOTE A: X is the value loaded in the almost-empty flag offset register.

Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265 11-71
 SN74ACT3651
2048x36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A-JUNE 1994 - REVISED SEPTEMBER 1995

' - tsk(1)t -.j

ClKA \ I~----ll"""\ )-1- .....\ 12 \""_---'1 \ ..._---'1
, tpd(C-IR) ~
IR FIFO Filled to First Retransmllt Word J--O-ne-o-r-:M~o-re~W~rl-te-:l-o-ca-t":"'lo-n-s~Ay-a~lI-ab~le
,,
ClKB ~ \ I, \ 1 \ I \ I '--
tsu(EN) ,. ~,. -, th(EN)
RTM
~ ~
t tsk(1) is the minimum time between a rising elKS edge and a rising elKA edge for IRto transition high in the next elKA cycle. lithe time between
the rising elKS edge and rising elKA edge is less than tsk(1). then IR can transition high one elKA cycle later than shown.

Figure 12. IR Timing From the End of Retransmit Mode When One or More Write Locations Are Available

' - ts k(2)t -.j

"tJ
ClKA \""_--J/~----l:I-\\ )'"":1--""'\ 12 \1.-_.,,1 \~_....Jr
:D , tpd(C-AE) ~
o _(~20.;.,4..;,8_-_Y~)..;.or..;.M..;,o.;.,r..;.e..;.w..;,o...rd...s..;,p..;,a;,;;,st~'F..;,lr..;,s...t R...et~ra...n...
,
W.;,o;.;rd~_ _ _ _ _ _" 1I'-(Y-+-1-)-0-rM-or-e-W-r-Ite-lo-ca-t-Io-n-s-A-Y-al-Ia-b-Ie
sm,;,;,l;;.t...
C
C
o-I ClKB
\ k, \""_--JI \\-_-....JI \\-_--J1
tsu(EN) 14 _,4 .1 th(EN)
"tJ RTM ----~~:$=~~$~~~~~~~~~----------------------------
:D
m t tsk(2) is the minimum time between a rising elKS edge and a rising elKA edge for AF to transition high in the next elKA cycle.lfthetime between
the rising elKS edge and rising elKA edge is less than tsk(2). then AF can transition high one elKA cycle later than shown.

-<
m
NOTE A: Y is the value loaded in the almost-full flag offset register.

:e Figure 13. AF Timing From the End of Retransmit Mode When (Y + 1)

or More Write Locations Are Available

~1ExAs
INSTRUMENTS
11-72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3651
2048 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

I \ I 'I...__ I
CLKA
tsu(EN) H
------=~~I~----------------
r- th(EN)
.J ''-__---1

I I
WiRA ?l!ZlZl//zzz?I II M
I
MBA
wzzzzzzzzzr 1M
ENA 2/71Z?/ZZZZ4 I_

AO-A35
~ I
I 'I..._--;I_....JI ''-----1~ ,'-----
CLKB
tpd(C-MF) -.\
-------~I--~\"__
F _ _ _ _ _+I_ _ _~)~---
tpd(C-MF) ....j

I I
3:
1------~1--------------------~1-------.J1
W/RB
//ZZ/Z/f: : }\\\~ ->w
_ _ _~I_ _~/I i. _, ~
w
MBB
I II tsu(EN)~ .r th(EN) I
a:
D..
ENB : I I! IZTdl ~\"":\\':
.....:.....--"::\~-;-..I_ _ __
len
I
H 141141f----.l.1 tpd(M-OV)
14 I .1 tpd(C-MR) tdls
I
j+---.I b
:::J
BO-B35 WI remains valid In mall I re Ister after read)
C
FIFO Output Register
oa:
Figure 14. Timing for Mail1 Register and MBF1 Flag
D..

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-73
 SN74ACT3651
2048 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS439A-JUNE 1994- REVISED SEPTEMBER 1995

ClKB
I \ I \1--_-.J1 \ ....__~I '-
---....;..;;.:..-.:,~I
tsu(EN) H r-..--t_h(_EN_)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CSB
I I
W/RB
~ Ira
I I I
MBB
2lZ?fll?1221 I W
ENB 0?ZZTIllZl{ I. .
BO-B35
~ I
CLKA
I \~___~I__JI \~-----1 \~---------
-.J r-- -+i
MBF2 -------------~I------~\~
;..- tpd(C-MF)

I
__________ I tpd(C-MF)
~I-------J)..---------
"'tJ
:c CSA
~ I I 1
0
C
WiRA ....\\:-OO:s~s-.::s-.:'s~i I I p"'z"'z",z"'z"'z",z"'z"'z-r
C MBA
0 I I Isu(EN)~ th(EN) I
-I ENA I
I
I
I
R22Z? t~s~S~S~\__~I________
- I
"'tJ
:c ten H !.----.._II tpd(C-MR) tdls j.-----.I
m AO-A35 Wi (remains valid In mall2 re Ister after read)

<
-
m Figure 15. Timing for Mail2 Register and MBF2 Flag

:e

~TEXAS
INSTRUMENTS
11-74 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3651
2048 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Va (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Vecl ............................................... ±20 mA
Output clamp current, 10K (Va < 0 or Va > Vecl ........................................... ±50 mA
Continuous output current, 10 (Va = 0 to Vecl ............................................. ±50 mA
Continuous current through Vee or GND ................................................. ±400 mA
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
VIH
Vil
High-level input voltage
low-level input voltage
2
0.8
V
V
3:
w
IOH
IOl
High-level output current
low-level output current
-4
8
mA
mA
>
w
TA Operating free-air temperature 0 70 °e a:
a.
electrical characteristics over recommended operating free-air temperature range (unless I-
otherwise noted) 0
PARAMETER TEST CONDITIONS ,MIN TYP:j: MAX UNIT ~
VOH Vee=4.5V, IOH =-4 mA 2.4 V C
VOL
II
Vee = 4.5 V,
Vee =5.5 V,
IOl=8mA
VI=Vee orO
0.5
±5
V
IJA
oa:
IOZ Vee = 5.5 V, Vo=Vee orO ±5 IJA a.
lee Vee = 5.5 V, VI = Vee - 0.2 V or 0 400 IJA
eSA= VIH AO-A35 0
eSB = VIH BO-B35 0
Vee =5.5 V, One input at 3.4 V,
Lllee§ eSA= Vil AO-A35 1 mA
Other inputs at Vee or GND
eSB=vll BO-B35 1
All other inputs 1
ei VI =0, f= 1 MHz 4 pF
eo Vo=O, f= 1 MHz 8 pF
:I: All typical values are at Vee = 5 V, TA = 25°e.
§ This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or Vee.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-75
 SN74ACT3651
2048 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 15)
'ACT3651·15 'ACT3651·20 'ACT3651·30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency, CLKA or CLKB 66.7 50 33.4 MHz
tc Clock cycle time, CLKA or CLKB 15 20 30 ns
tw(CH) Pulse duration, CLKA and CLKB high 6 8 12 ns
tw(CL) Pulse duration, CLKA and CLKB low 6 8 12 ns
tsu(D) Setup time, AO-A35 before CLKAi and BO-B35 before CLKBi 4 5 6 ns
Setup time, CSA, W/RA, ENA, and MBA before CLKAi;
tsu(EN) 4 5 6 ns
CSB, \iV/RB, ENB, MBB, RTM, and RFM before CLKBi
tsu(RS) Setup time, RST low before CLKAi or CLKBit 5 6 7 ns
tsu(FS) Setup time, FSO and FS1 before RST high 5 6 7 ns
tsu(SD):j: Setup time, FSO/SD before CLKA i 4 5 6 ns
tsu(SEN):j: Setup time, FS 1/SEN before CLKA i 4 5 6 ns
th(D) Hold time, AO-A35 after CLKAi and BO-B35 afterCLKBi 0 0 0 ns
Hold time, CSA, W/RA, ENA, and MBA after CLKA i;
th(EN) 0 0 0 ns
CSB, \iV/RB, ENB, and MBB after CLKBi
"'0
:xJ th(RS) Hold time, RST low after CLKAi or CLKBit 5 6 7 ns

oC th(FS)
th(SP~+
Hold time, FSO and FS1 after RST high
Hold time, FS1/SEN high after RST high
2
15
3
20 30
3 ns
ns

C th(SD)+ Hold time, FSO/SD after CLKA i 0 0 0 ns

o th(SEN)+ Hold time, FS1/SEN after CLKAi 0 0 0 ns

-f tsk(1)§ Skew time between CLKAi and CLKBi for OR and IR 6 8 10 ns

"'0 t sk(2)§ Skew time between CLKAi and CLKBi for AE and AF 12 16 20 ns

:xJ t Requirement to count the clock edge as one of at least four needed to reset a FIFO
m + Only applies when serial load method used to program flag offset registers

<
-
§ Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
m
~

~TEXAS
INSTRUMENTS
11-76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3651
2048 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 30 pF (see Figures 1 through 15)
'ACT3651-15 'ACT3651-20 'ACT3651-30
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
ta Access time, CLKB'I to BO-B35 11 13 15 ns
tpd(C-IR) Propagation delay time, CLKA'I to IR 11 13 15 ns
tpd(C-OR} Propagation delay time, CLKB'I to OR 11 13 15 ns
tpd(C-AE) Propagation delay time, CLKB'I to AE 11 13 15 ns
.tpd(C-AF~ Propagation delay time, CLKA'I to AF 11 13 15 ns
Propagation delay time, CLKA'I to MBF1 low or MBF2 high and
tpd(C-MF) 11 13 15 ns
CLKB'I to MBF2 low or MBF1 high
Propagation delay time, CLKA'I to BO-B35t and CLKB'I to
tpd(C-MR) 11 13 15 ns
AO-A35:1:
tpdlM-DVI Propagation delay time, MBB to BO-935 valid 9 11 13 ns
Ipd(R-F) Propagation delay time, RST low to AE low and AF high 15 20 30 ns
Enable time, CSA and W/RA low to AO-A35 active and CSB low
ten 10 12 14 ns
and W/RB high to BO-B35 active

!dis
Disable time, CSA or W/RA high to AO-A35 at high impedance
and CSB high or W/RB low to BO- B35 at high impedance
10 12 14 ns ;:
"
t Wrltmg data to the mal11 register when the BO-B35 outputs are active and MBB IS high
:I: Writing data to the mail2 register when the AO-A35 outputs are active and MBA is high ->w
W

a:
D..
b
::J
a
oa:
D..

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-77
 SN74ACT3651
2048 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439A-JUNE 1994- REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
300
fdata = 1/2 fclock '
TA=75°C
250 f- CL=OpF
1I

~
:::I
200
0
b DATA TO BE SUPPLIED _
8: 150 r---
AT PRODUCT RELEASE
-
8lI
5: 100
0
0

50
"lJ
::tJ o
o o 10 20 30 40 50 60 70 60
C fclock - Clock Frequency - MHz
c:
o-t Figure 16

"lJ calculating power dissipation

::tJ With ICC (f) taken from Figure 16, the maximum power dissipation (Pr) of the SN74ACT3651 can be calculated
m by:
S Pr = Vee x [Iee(f) + (N x ~Ice x dc)] + L(CL x Vee2 x fo)
m
:e where:
N = number of inputs driven by TIL levels
~Icc = increase in power supply current for each input at a TIL high level
dc = duty cycle of inputs at a TIL high level of 3.4 V
CL = output capacitive load
fo = switching frequency of an output

~1ExAs
INSTRUMENTS
11-78 POST OFFICE BOX 655303. DAlLAS. TEXAS 75265
 SN74ACT3651
2048 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCAS439A - JUNE 1994 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

5V

?> 1.1 k!l

From Output
Under Test - - . - - - - .

6800 ""r:
r
30 pF
(see Note A)

LOAD CIRCUIT

~
--3V
Timing 1. 3V High-Level 1.5 V 1.5 V
Input Jr 1.5 V
__--J.q. - - - - - GND Input I I GND

tsu~th 14- tw --+I

Data, ~-:;:- 3V
I I
==
W
~
I
Enable --f 1.5 V ~ Low-Level 1.5 V 1.5 V
3V
:;
Input GND Input _ _ _ _ GND
w
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS a::
SETUP AND HOLD TIMES PULSE DURATIONS a.
Output
Enable -.I]
L
1.5 V
3V

GND
t>
::J
-+I ~tPLZ C
oa::
Low-Level
Output
11---"';'-';
1
_-+-.JI
I4--tPZH
-3V

VOL
Input -/1.5 V ~5~-- ::0 a.
I VOH
tpd -l4---+I i4---+I- tpd
High-Level
1 1 In-Phase I/.......--~ 1- - VOH
Output
1 I -OV Output
_ _-.oJ.
T 1.5 V )L
'C 1.5 V
VOL
-+I l~tpHZ

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 17. Load Circuit and Voltage Waveforms

~lEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-79
11-80
 SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
- AUGUST 1993 - 1995

• Free-Running ClKA and ClKB Can Be • IRB, ORB, AEB, and AFB Flags
Asynchronous or Coincident Synchronized by ClKB
• Two Independent Clocked FIFOs Buffering • low-Power O.8-Mlcron Advanced CMOS
Data in Opposite Directions Technology
• Mailbox-Bypass Register for Each FIFO • Supports Clock Frequencies up to 67 MHz
• Programmable Almost-Full and • Fast Access Times of 11 ns
Almost-Empty Flags • Pin-to-Pin Compatible With the
• Microprocessor Interface Control logic SN74ACT3632 and SN74ACT3642
• IRA, ORA, AEA, and AFA Flags • Available in Space-Saving 120-Pin Thin
Synchronized by ClKA Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages

PCB PACKAGE
(TOP VIEW)

~~~~~~;E~E§~~~~~~~~§§m~~~~~~~~
A35 90 B35
A34 2 89 B34
A33 3 88 B33
A32 4 87 B32
Vee 5 86 GND
A31 6 85 B31
A30 7 84 B30
GND 8 83 B29
A29 9 82 B28
A28 10 81 B27
A27 11 80 B26
A26 12 79 Vee
A25 13 78 B25
A24 14 77 B24
A23 15 76 GND
GND 16 75 B23
A22 17 74 B22
Vee 18 73 B21
A21 19 72 B20
A20 20 71 B19
A19 70 B18
A18 69 GND
GND 68 B17
A17 67 B16
A16 66 Vee
A15 65 B15
A14 64 B14
A13 63 B13
Vee 62 B12
A12 GND

Copyright © 1995, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-81
SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

PQPACKAGEt
(TOP VIEW)

NC NC
835 NC
834 ASS
833 A34
832 A33
GND A32
831 Vec
830 A31
829 A30
828 GND
827 A29
826 A28
Vee A27
825 A26
824 A25
GND A24
823 A23
822 GND
821 A22
820 Vec
819 A21
818 A20
GND A19
817 A18
816 GND
Vee A17
815 A16
814 A15
813 A14
812 A13
GND Vec
NC A12
NC NC

NC - No internal connection
t Uses Yamaichi socket IC51-1324-828

~1ExAs
INSTRUMENTS
11-82 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3622
256 x 36x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C -AUGUST 1993 - REVISED SEPTEMBER 1995

description
The SN74ACT3622 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock
frequencies up to 67 MHz with read access times of 11 ns. Two independent 256 x 36 dual-port SRAM FIFOs
on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags (almost full and almost empty) to indicate when a selected number of words is
stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used
in parallel to create wider data paths.
The SN74ACT3622 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port cloCk by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the
port crock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag
of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the
almost-full and almost-empty flags of the FIFO can be programmed from port A.
The SN74ACT3622 is characterized for operation from O°C to 70°C.
For more information on this device family, see the application report FIFO Mailbox-Bypass Registers: Using
Bypass Registers to Initialize DMA Control in the 1996 High-Performance FIFO Memories DeSigner's
Handbook, literature number SCAA012A.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-83
SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

functional block diagram

jr------------------------------ MBF1
Mall1
CLKA -- I Register
CSA
WiRA
--
--
Port-A
Control r-~-----------~l~
ENA
MBA
--
--
Logic r- I--
r- tj
, I...
~fL.,~
256x36 .. I ,
f-to+t+-Hil+i 'S SRAM i ,
" ~ 8~
FIF01,
36
Mall1
RST1 - Reset ,- r- -,
Logic

I, I Write
I Pointer
II Read
Pointer
I
I I,
I
IRA - - -....--++-11-+-+-+-+-------1
t tl
Status-Flag 1-------;----11-+-+-1--+-------- ORB
AFA Logic AEB
, FIF01 ... ,
36
L~L====~.~~;::.::~.~~----.-~
Programmable-
FSO --------+-HH-+----------I Flag
FS1 --------+-HH-+-~~-----I
AO_A35 ____4-+--t1H-rt-_~1~:===~b;0;ff;se;t~Re~g~ls~te;rs;d__. ____ _
r --.:t.- ,
,A~2 T ,
ORA I Status-Flag i
AEA - - -....---t1H-rt---r------1~~L~og~lc~~----------ttilHtt_--------
I + + !
!I I, Pointer
Read II Write ....
' ------,

, Pointer
~
I

~ ~
I-=- ~
~
~
,, I......
~:r
256 x 36
SRAM
r
L........
rr-

~
~ i i
o
L== ___________ B __ ~

Mall2 '----+-1
I Register

MBF2------------------------------~1

~TEXAS
INSTRUMENTS
11-84 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3622
256 x36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME
AO-A35 1/0 Port-A data. The 36-bit bidirectional data port for side A.
0 Port-A almost-empty flag. Programmable almost-empty flag synchronized to ClKA. AEA is low when the number of
AEA
(portA) words in FIF02 is less than or equal to the value in the almost-empty A offset register, X2.
0 Port-B almost-empty flag. Programmable almost-empty flag synchronized to ClKB. AEB is low when the number of
AEB
(port B) words in FIFOI is less than or equal to the value in the almost-empty B offset register, XI.
0 Port-A almost-full flag. Programmable almost-full flag synchronized to ClKA. AFA is low when the number of empty
AFA
(portA) locations in FIFOI is less than or equal to the value in the almost-full A offset register, Yl.
0 Port-B almost-full flag. Programmable almost-full flag synchronized to ClKB. AFB is low when the number of empty
AFB
(port B) locations in FIF02 is less than or equal to the value in the almost-full B offset register, Y2.
BO-B35 1/0 Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
ClKA I
or coincident to ClKB. IRA, ORA, AFA, and AEA are all synchronized to the low-to-high transition of ClKA.
Port-B Clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
ClKB I
or coincident to ClKA. IRB, ORB, AFB, and AEB are synchronized to the low-te-high transition of ClKB.
Port-A chip select. CSA must be low to enable a low-to-high transition of ClKA to read or write data on port A. The
CSA I
AO-A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of ClKB to read or write data on port B. The
CSB I
BO-B35 outputs are in the high-impedance state when CSB is high.
ENA I Port-A enable. ENA must be high to enable a low-te-high transition of ClKA to read or write data on port A.
ENB I Port-B enable. ENB must be high to enable a low-te-high transition of ClKB to read or write data on port B.
Flag offset selects. The low-te-high transition of a FIFO's reset input latches the values of FSO and FSI. If either FSO
or FSI is high when a reset input goes high, one of three preset values is selected as the offset for the FIFO almost-full
FS1, FSO I
and almost-empty flags. If both FIFOs are reset simultaneously and both FSO and FS 1 are low when RSTI and RST2
go high, the first four writes to FIFOI program the almost-full and almost-empty offsets for both FIFOs.
Input-ready flag. IRA is synchronized to the low-te-high transition of ClKA. When IRA is low, FIFOI is full and writes
0
IRA to its array are disabled. IRA is set low when FI FOI is reset and is set high on the second low-to-high transition of ClKA
(portA)
after reset.
Input-ready flag. IRB is synchronized to the low-te-high transition of ClKB. When IRB is low, FIF02 is full and writes
0
IRB to its array are disabled. IRB is set low when FIF02 is reset and is set high on the second low-to-high transition of ClKB
(port B)
after reset.
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
MBA I AO-A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects
FIF02 output-register data for output.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
MBB I BO-B35 outputs are active, a high level on MBB selects data from the mail 1 register for output and a low level selects
FIFOI output-register data for output.
Maill register flag. MBFl is set low by a low-to-high transition of ClKA that writes data to the maill register. Writes to
MBFl 0 the maill register are inhibited while MBFl is low. MBFl is set high by a low-to-high transition of ClKB when a port-B
read is selected and MBB is high. MBFl is set high when FIFOI is reset.
Mail2 register flag. MBF2 is set low by a low-to-high transition of ClKB that writes data to the mail2 register. Writes to
MBF2 0 the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of ClKA when a port-A
read is selected and MBA is high. MBF2 is also set high when FIF02 is reset.
Output-ready flag. ORA is synchronized to the low-te-high transition of ClKA. When ORA is low, FIF02 is empty and
0 reads from its memory are disabled. Ready data is present on the output register of FIF02 when ORA is high. ORA
ORA
(portA) is forced low when FIF02 is reset and goes high on the third low-to-high transition of ClKA after a word is loaded to
empty memory.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-85
SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

Terminal Functions (continued)

TERMINAL
110 DESCRIPTION
NAME
Output-ready flag. ORB is synchronized to the low-to-high transition of elKB. When ORB is low, FI F01 is empty and
0 reads from its memory are disabled. Ready data is present on the output register of FIF01 when ORB is high. ORB
ORB
(port B) is forced low when FIF01 is reset and goes high on the third low-to-high transition of elKB after a word is loaded to
empty memory.
FIF01 reset. To reset FIF01, four low-to-high transitions of elKA and four low-Io-high transitions of elKB must occur
RST1 I while RST1 is low. The low-te-high transition of RST1 latches the status of FSO and FS1 for AFA and AEB offset
selection. FIF01 must be reset upon power up before data is written to its RAM.
FIF02 reset. To reset FIF02, four low-to-high transitions of elKA and four low-to-high transitions of elKB must occur
RST2 I while RST2 is low. The low-to-high transition of RST2 latches the status of FSOand FS1 for AFB and AEA offset
selection. FIF02 must be reset upon power up before data is written to its RAM.
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a
WiRA I
low-to-high transition of elKA. The AO-A35 outputs are in the high-impedance state when WiRA is high.
Port-B writelread select. A low on W/RB selects a write operation and a high selects a read operation on port B for a
W/RB I
low-to-high transition of elKB. The BO-B35 outputs are in the high-impedance state when W/RB is low.

detailed description
reset
The FI FO memories of the SN74ACT3622 are reset separately by taking their reset (RST1 , RST2) inputs low
for at least four port-A clock (ClKA) and four port-B clock (ClKB) low-to-high transitions. The reset inputs can
switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the
input-ready (IRA, IRB) flag low, the output-ready (ORA, ORB) flag low, the almost-empty (AEA, AEB) flag low,
and the almost-full (AF, AFB) flag high. Resetting a FIFO also forces the mailbox (MBF1, MBF2) flag of the
parallel mailbox register high. After a FIFO is reset, its input-ready flag is set high after two clock cycles to begin
normal operation. A FIFO must be reset after power up before data is written to its memory.
A low-to-high transition on a FIFO reset (RST1, RST2) input latches the value of the flag-select (FSO, FS1)
inputs for choosing the almost-full and almost-empty offset programming method (see almost-empty flag and
almost-full flag offset programming).
almost-empty flag and almost-full flag offset programming
Four registers in the SN74ACT3622 are used to hold the offset values for the almost-empty and almost-full flags.
The port-B almost-empty (AEB) flag offset register is labeled X1 and the port-A almost-empty (AEA) flag offset
register is labeled X2. The port-A almost-full (AFA) flag offset register is labeled Y1 and the port-B almost-full
(AFB) flag offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The
offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from
port A (see Table 1).
Table 1. Flag Programming
FS1 FSO RST1 RST2 X1 AND Y1 REGISTERSt X2 AND Y2REGISTERS:j:
H H i X 64 X
H H X i X 64
H l i X 16 X
H L X i X 16
L H i x 8 X
L H X i x 8
l L i i Programmed from port A Programmed from port A
t X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
:j: X2 register holds the offset for AEA; Y2 register holds the offset for AFB.

~TEXAS
INSTRUMENTS
11-86 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

almost-empty flag and almost-full flag offset programming (continued)

To load the FI FO almost-empty flag and almost-full flag offset registers with one of the three preset values listed
in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset input.
For example, to load the preset value of 64 intoX1 and Y1, FSO and FS1 must be high when FIF01 reset (RST1)
returns high. Flag-offset registers associated with FIF02 are loaded with one of the preset values in the same
way with FIF02 reset (RST2). When using one of the preset values for the flag offsets, the FIFOs can be reset
simultaneously or at different times.
To program the X1 , X2, Y1 , and Y2 registers from port A, both FIFOs should be reset simultaneously with FSO
and FS 1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes
to FIF01 do not store data in RAM but load the offset registers in the order Y1 , X1, Y2, X2. Each offset register
uses port-A inputs (A7 -AO). The highest numbered input is used as the most significant bit of the binary number
in each case. Valid programming values for the registers range from 1 to 252. After all the offset registers are
programmed from port A, the port-B input-ready (IRB) flag is set high and both FIFOs begin normal operation.
FIFO write/read operation
The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (GSA) and the port-A
write/read select (W/RA). The AO-A35 outputs are in the high-impedance state when either GSA or W/RA is
high. The AO-A35 outputs are active when both GSA and W/RA are low.
Data is loaded into FIF01 from the AO-A35 inputs on a low-to-high transition of GlKA when GSA is low, W/RA
is high, ENA is high, MBA is low, and IRA is high. Data is read from FIF02 to the AO-A35 outputs by a low-to-high
transition of GlKA when GSA is low, W/RA is low, ENA is high, MBA is low, and ORA is high (see Table 2). FIFO
reads and writes on port A are independent of any concurrent port-B operation.

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA AO-A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L i In high-impedance state FIF01 write
L H H H i In high-impedance state Mail1 write
L L L L X Active, FIF02 output register None
L L H L i Active, FI F02 output register FIF02 read
L L L H X Active, mail2 register None
L L H H i Active, mail2 register Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A with the exception that the port-B write/read select
(W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (BO-B35) outputs is
controlled by the port-B chip select (GSB) and the port-B write/read select (W/RB). The BO-B35 outputs are
in the high-impedance state when either GSB is high or W/RB is low. The BO-B35 outputs are active when GSB
is low and W/RB is high.
Data is loaded into FIF02 from the BO-B35 inputs on a low-to-high transition of GlKB when GSB is low, W/RB
is low, ENB is high, MBB is low, and IRB is high. Data is read from FIF01 to the BO-B35 outputs by a low-to-high
transition of GlKB when GSB is low, W/RB is high, ENB is high, MBB is low, and ORB is high (see Table 3). FIFO
reads and writes on port B are independent of any concurrent port-A operation.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-87
SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

CSB W/RB ENB MBB ClKB BO-B3S OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L L L X X In high-impedance state None
L L H L i In high-impedance state FIF02write
L L H H i In high-impadance state MaU2write
L H L L X Active, FIFOl output register None
L H H L i Active, FIFOl output register FIFOl read
L H L H X Active, maUl register None
L H H H i Active, maUl register MaUl read (set MBFl high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select may change states during the
setup- and hold-time window of the cycle.
When a FIFO output-ready flag is low, the next data word is sent to the FIFO output register automatically by
the low-to-high transition of the port clock that sets the output-ready flag high. When the output-ready flag is
high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the
port's chip select, write/read select, enable, and mailbox select.
synchronized FIFO flags
Each FIFO is synchrOnized to its port clock through at least two flip-flop stages. This is done to improve
flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate
asynchronously to one another (see the application report Metastability Performance of Clocked FIFOs in the
1996 High-Performance FIFO Memories Data Book, literature number SCAD003C). ORA, AEA,IRA, and AFA
are synchronized to CLKA. ORB, AEB, IRB, and AFB are synchronized to CLKB.Tables 4 and 5 show the
relationship of each port flag to FIF01 and FIF02.

Table 4. FIF01 Flag Operation

SYNCH.RONIZED SYNCHRONIZED
NUMBER OF WORDS IN TOClKB TOClKA
FIF01t*
ORB AEB AFA IRA
0 L L H H
1 to Xl H L H H
(Xl + 1) to [256 - (Yl + 1)) H H H H
(256 - Yl) to 255 H H L H
256 H H L L
t X1 is the almost-empty offset for FIFOl used by AEB. Yl is the almost-full
offset for FIFOl used by AFA. Both Xl and Y1 are selected during a reset
of FIFOl or programmed from port A.
:I: When a word loaded to an empty FIFO is shifted to the output register, Hs
previous FIFO memory location is free.

·~TEXAS
INSTRUMENTS
11-88 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

synchronized FIFO flags (continued)

Table 5. FIF02 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS IN TOCLKA TOCLKB
FIF02t:l:
ORA AEA AFB IRB
0 L L H H
1 toX2 H L H H
(X2 + 1) to [256- (Y2 + 1)] H H H H
(256 - Y2) to 255 H H L H
256 H H L L
t X2 IS the almost-empty offset for FIF02 used by AEA. Y2 IS the almost-full
offset for FIF02 used by AFB. Both X2 and Y2 are selected during a reset
of FIF02 or programmed from port A.
:I: When a word loaded to an empty FIFO is shifted to the output register, its
previous FIFO memory location is free.

output-ready flags (ORA, ORB)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the
output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low, the
previous data word is present in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pOinter is incremented each time a new word is clocked to its output register. The state machine
that controls an output-ready flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is empty, empty+ 1, or empty+2. From the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of the output-ready flag synchronizing clock; therefore,
an output-ready flag is low if a word in memory is the next data to be sent to the FIFO output register and three
cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written.
The output-ready flag of the FIFO remains low until the third low-to-high transition of the synchronizing clock
occurs, simultaneously forcing the output-ready flag high and shifting the word to the FIFO output register.
A low-to-high transition on an output-ready flag synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 7 and 8).
Input-ready flags (IRA, IRB)
The input-ready flag of a FI FO is synchronized to the port clock that writes data to its array. When the input-ready
flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when
the input-ready flag is low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an
input-ready flag monitors a write pOinter and read pointer comparator that indicates when the FI FO SRAM status
is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be
written in a minimum of two cycles of the input-ready flag synchronizing clock; therefore, an input-ready flag is
low if less than two cycles of the input-ready flag synchronizing clock have elapsed since the next memory write
location has been read. The second low-to-high transition on the input-ready flag synchronizing clock after the
read sets the input-ready flag high.
A low-to-high transition on an input-ready flag synchronizing clock begins the first synchronization cycle of a
read if the clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 9 and 10).

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-89
SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

almost-empty flags (AEA, AEB)

The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state
machine that controls an almost-empty flag monitors a write pOinter and read pointer comparator that indicates
when the FIFO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty state is
defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset
values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset
programming). An almost-empty flag is low when its FIFO contains X or less words and is high when its FIFO
contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory.
Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for its
almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1)
or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled
the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of its
synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an
almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2' or greater,
after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figures 11 and 12).
almost-full flags (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine
that controls an almost-full flag monitors a write pointer and read pointer comparator that indicates when the
FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the contents
of register V1 for AFA and register V2 for AFB. These registers are loaded with preset values during a FIFO reset
or programmed from port A (see almost-empty flag and almost-full flag offset programming). An almost-full flag
is low when the number of words in its FIFO is greater than or equal to (256 - V). An almost-full flag is high when
the number of words in its FIFO is less than or equal to [256 - (V + 1)]. A data word present in the FIFO output
register has been read from memory.
Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for its
almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [256 - (V + 1)]
or less words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced
the number of words in memory to [256 - (V + 1)]. An almost-full flag is set high by the second low-to-high
transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to
[256 - (V + 1)]. A low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization
cycle if it occurs at time tsk2, or greater, after the read that reduces the number of words in memory to
[256 - (V + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see
Figures 13 and 14).
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port data transfer operation. A low-to-high transition on ClKA writes AO-A35 data to the mail1 register
when a port-A write is selected by CSA, W/RA, and ENA and with MBA high. A low-to-high transition on ClKB
writes BO-B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and with MBB
high. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail
register are ignored while the mail flag is low.
When data outputs of a port are active, the data on the bus comes from the FIFO output register when the
port-mail box-select input is low and from the mail register when the port-mailbox-select input is high. The mail1
register flag (MBF1) is set high by a low-to-high transition on ClKB when a port-B read is selected by CSB,
W/RB, and ENB and with MBB high. The mail2 r~ister flag (MBF2) is set high by a low-to-high transition on
ClKA when a port-A read is selected by CSA, W/RA, and ENA and with MBA high. The data in a mail register
remains intact after it is read and changes only when new data is written to the register.

~TEXAS
INSTRUMENTS
11-90 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3622
256 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C- AUGUST 1993 - REVISED SEPTEMBER 1995

ClKA

ClKB
1 I It
....I ~ tsu(RS) I 1 ~ h(FS) I
_ _ _~I I 1 tsu(FS) 1:---"1 I 1
RST1 \. I 1 I I I
1 1 I
FS1,FSO

1 tpd(C-IR) I---l I tpd(C-IR) ;.----:

IRA S\\\\\)S\\\\\\~~ I Ir - - -
1 tpd(C-OR) ~
ORB ~~~\\\\S\\~~
tpd(R-F) ~

AEB @"\\)\~
tpd(R-F) ~
AFA /l22ZZZ{W1
tpd(R-F)~
MBF1 if/2/Tk1
Figure 1. FIF01 Reset Loading Xi and Vi With a Preset Value of Eightt
t FIF02 is reset in the same manner to load X2 and Y2 with a preset value.

ClKA

FS1,FSO

ENA
2Z2ZI?ZI?ZlZ2Zl ~ ~ ~ *~
AO-A35
AFA(Y~~I AEB{X~••I AFB(Y~~"I AE~~••I I First Word 10 FIF01

ClKB
1 I 2
tpd(C-IR) ~r
IRB

t tsk1 is the minimum time between the rising ClKA edge and a rising ClKB edge for IRB to transition high in the next cycle. If the time between
the rising edge of ClKA and rising edge of ClKB is less than tsk1, IRB may transition high one cycle later than shown.
NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values After Reset

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-91
SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

14 Ie .1
I .~ .: Iw(ClKl)
Iw(ClKH) 14

ClKA 1 ~
1

rI
\ y
I
I
\ (
1
'-
IRA
I 1
1
Isu(EN) :4 .:4,lh(EN) 1 1
I I
CSA
tsu(EN) 14
~ i~
.1 4 ~ Ih(EN)
I
I
1/
1
I I
WiRA
??llZZZZZZZ2{
Isu(EN) 14
IF
.14 ~ Ih(EN)
1
I I
I~"",,-~

I 1 I
MBA

ISU(EN) ~ ~ Ih(EN) Isu(EN) ~ , - Ih(EN)

ENA vzzz;zzzzz;f 10s\\\\\\\\,\ Vzzzzm2
Isu(D) 14 +- ~ Ih(D)
AO-A35 No Operallon ;XXXXXXXX
t Written to FIF01
Figure 3. Port-A Write-Cycle Timing for FIF01

r~------Ie------~.I
4
Iw(ClKH) 1+ ------..,.~rl----------t!.: Iw(ClKl)

ClKB 1""--""~"----...IIr \I....-_~y '\---...Ji( '-

I I
I !
~:4--t.0!4:4-t!' Ih(EN)
IRB
Isu(EN) :

CSB ----------~~~-+!~~~~--------~:--------------~I
~ ~
_______
tsu(EN) .1 4 Ih(EN) 1

WIRB . lo\ . lo$. lo$. lo$. lo$. lo:'. .:. lo:'. .:. lo:'. .:. .:l:'. .:. .:l:'. .:. .:l:'. .:. .:l~"T,- -+i~~~~-----l-: -!-'"t..o/:""'z""'z""'z""'z""'z""'z""'z""/'--
Isu(EN) 14 .1 4 ~ Ih(EN) I
MBB -.:"""~~~~~~ I I

BO-B35

t Written to FIF02
Figure 4. Port-B Write-Cycle Timing for FIF02

-!!1
TEXAS
INSTRUMENTS
11-92 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3622
256x36x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

~14- - - te ---~.I
:4 ---~~14-4---~.: tw(ClKl)
tw(ClKH) ...

elKB I.----.........\'-__~I \ ( \ I '-

I I I
I I I
ORB I I I
I I I
-CSB --...., I I II / r - - - -
I I I
I I I I
WIRB WLI{: : \\\\\\\\\';
I
I ~ tsu(EN) I
MBB ---+-I~, I I I I

ENB
l ' l -1I ~'-8th(EN)
V222f24V» ~
tSU(EN)~-Ith(EN)
I \§\\\\\\\'\ ~""?';"?-??"'?"'?"'?"'?"'2""
I 14 ·1 : : ope~~tlon 1-1
tpd(M-OV)
14 .: I r= -.I t I Is -.I
Idls

BO-B35 -----~
len
w1f'
Is
* w2f X W3t j
t Read from FIFOI
Figure 5. Port-B Read-Cycle Timing for FIF01

It Ie ·1
Iw(ClKH) I. ~4 ~I tw(ClKl)
ClKA I
1
\ I
r \ (
I
\'----_~I
I
'-
I I I
ORA I I I
I I I
I I I
CSA
~ I
I
I
1/
I
I I
I
W/RA
~~ I
I : IllZllZV/
~ Isu(EN)
MBA

j4- th(EN) Isu(EN)

t Read from FIF02

Figure 6. Port-A Read-Cycle Timing for FIF02

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-93
SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

ClKA
1
CSA ~lo~w~ ______ 1 ______ 1 _____________________________________________________
~I ~1

1 1
WiRA High I 1

~
tsu(EN) I.-- th(E~)
MBA \§\\\\.:'\J VI""J/:,..,~.-io2...,.?.;.,.?~?..,..2..,..2"7"?"7"2.,..0.,..?~~~V:>'"':/:,..,/:,..,/:..,?..,2~?..,..?..,..?..,..?"7"?.,..?~?~
2:>'"':'//,:>'"':/:,..,/:..,/:..,2..,2~2~2..,..2..,..2"7"'/,"7"'/,.,..2.,..2~2~'//~
tsu(EN):-:::I t. th(EN)
ENA /Z//'/J; i ~\\~
1 ~~r~~-------------------------------------------------------------------------------
IRA High 1 1
~W~
AO-A35_W1.
4 .1 te
tsk1 t 14 """"!I I~t
tw ClKH) --, j+- I w(ClKl)
ClKB 1 2 3
tpd(C.OR) ~1'4----.t ,..-----l!:==~
ORB ...._______O_I_d_D_at_a_ln_F_IF_O_1_0_u~tp_u_tR_e~g~ls_te_r__________+I ----J ~___________ _

1
CSB ~lo~w~___________________________________I~--------~------------------

1
W/RB High I
1 1
MBB low 1 i

ENB
~ tS~N7~
VZ!/'l/fl/Z///?VZ2V/VZZZ2lZ72/7;;:
I+- ta ---.j
BO-B35 ------------~O~ld~D~a~ta~l~n~F~IF~O~1~O-ut~p~ut~R~e-9~1~~e-r-----------*------------W~1-----------

t tsk1 is the minimum time between a rising eLKA edge and a rising elKB edge for ORB to transition high and to clock the next word to the FIF01
output register in three elKB cycles. If the time between the rising elKA edge and rising elKB edge is less than tsk1. the transition of ORB high
and load of the first word to the output register may occur one elKB cycle later than shown.

Figure 7. ORB-Flag Timing and First-Data-Word Fallthrough When FIF01 Is Empty

~ThxAs
INSTRUMENTS
11-94 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3622
256x36 x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

ClKB

I
CSB low
I
W/RB~~ ____ ~~ ____-+I
I _________________________________________________
I
I.-- th(EN)

ClKA

ORA Old Data In FIF02 Output Register

CSA low

WiRA low
~~------------------------------~---------+------------------

AO-A35 ____________~O~ld~D~m=a~ln~F~IF~O~2~O~ut=p~ut~R=e~91~~~er~________~~___________W~1_________
t tskl is the minimum time between a rising ClKS edge and a rising ClKA edge for ORA to transition high and to clock the next word to the FIF02
output register in three ClKA cycles. If the time between the rising ClKS edge and rising ClKA edge is less than tskl. the transition of ORA high
and load of the first word to the output register may occur one CLKA cycle later than shown.

Figure 8. ORA-Flag Timing and First·Data-Word Fallthrough When FIF02 Is Empty

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-95
SN74ACT3622
256x36 x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

I.--- te ----.I
tw(CLKH) I_ ~_ ~I tw(CLKL)

CLKB I \. . ._....J{
CSB ~Lo~w~_________I~
''--_..J ' ....._....J1 ,'----___
' ....._....J1
________________________________________________
1

I
W/RB High I
I
MBB _~L~OW~~~~E:~I~~~~--------------------------------------------
tsu(EN) I- ~I- ~l th(EN)
ENB _ _..1.';...:6""2,,,,2-'17 I \.,,\,.;~. . :.- .- :.- .~~: ___________________
ORB High I
Next Word From FIF01

j4- tsk1t -J~14_ _ te ----.I

tw(CLKH) 14 ~ , tw(CLKL)
CLKA ~'-_....JI"-~\ 11 "
tpd(C-IR)
12
I.
,'-_----:(
~I l_
''-_...Jr----
~ tpd(C-IR)
IRA FIF01 Full I I
\ .....------
-------------------------~
I
CSA

WiRA
Low I
---------------------~I
I
----------
ENA

AO-A35

t tskl is the minimum time between a rising ClKS edge and a rising ClKA edge for IRA to transition high in the next ClKA cycle. lithe time between
the rising ClKS edge and rising ClKA edge is less than tsk1, IRA may transition high one ClKA cycle later than shown.

Figure 9. IRA-Flag Timing and First Available Write When FIF01 Is Full

"!11 TEXAS
INSTRUMENTS
11-96 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

I.-- Ie:: -----J/

IW(CLKH) 14 ~.. ~I Iw(CLKL)

CLKA I \. I
1
'Io.._--J/ 'Io.._--J/ 'Io.._--J/ '10..__
CSA __
LO_W__________ ~I

1 ____________________________________________________

WffiA ~Lo~w __________ ~1

1 ____________________________________________________

MBA ~LO~W~________~I----------------------------------------------------
Isu(EN) l;::::;PcGih(EN)
ENA IT!//} 1 ~'""':--..:~s:.$;o.;2\:to.__ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

1
ORA High 1
I.- la-.l
1
AO-A35 Previous Word in FIF02 Output Re ISler Next Word From FIF02

I f - - - Ie:: ---.I
~ , Iw(CLKL)
CLKB """""\'-____...,/
~I~----ll!
'l 12 ',-_~( ''-_.Jr-
Ipd(C-IR) 14
IRB ______________F~IF~O~2~F~U~II____________________~1 I.. ::::::::::t!~1\~
Ipd(C-IR)
_________
1
CSB Low 1

~~-------------------+I---------
W/RB ~Lo~w~__________________________________~--~--~1~----------------
tsu(EN) ~--+-~ Ih(EN)
MBB -O::'$~$~0~:":"<:"$"<:":":-::-$-::-:\\,,:~~~:-.,:::""':--..:::""'s:~s:~s:~s:-O::$~$~$~s:"<:"s:"<:"s:~$~:'0.:::""':-.,:::""':-.,:~$~$:""<:$-O::$-O::$~$~$"<:"$~$~0~~ I ~--7Z:..,.Z..,..Z"7'~"7'Z.,..Z.,..Z.,..Z.,..Z.,..Z.,..Z.,..?/~
Isu(EN) ~~ Ih(EN)
ENB

BO-B35

t tsk1 is the minimum time between a rising ClKA edge and a rising ClKB edge for IRB to transition high in the next ClKB cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than t sk1. IRB may transition high one ClKB cycle later than shown.

Figure 10. IRB-Flag Timing and First Available Write When FIF021s Full

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-97
SN74ACT3622
256 x 36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

ClKA
tsu(EN) :'-=:1 r- th(EN)

ClKB
~----Jl~ tpd(C-AE) 14 .1
AEB X1 Words In FIF01 Y (X1 + 1) Words In FIF01J '-
tSU(ENtd ~ th(EN)
ENB __________________________________________________~I/.~~/j.~~~~~~~~ ~~
t tsk2 is the minimum time between a rising ClKA edge and a rising ClKB edge for AEB totransition high in the next ClKB cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tsk2. AEB may transition high one ClKB cycle later than shown.
NOTE A: FIF01 write (CSA = l. WiRA = H. MBA = l). FIF01 read (CSB = l. W/RB = H. MBB = l). Data in the FIF01 output register has been
read from the FIFO.

Figure 11. Timing for AEB When FIF011s Almost Empty

\,"_~I \ ...._~I

ClKA
-!f----tl~ tpd(C-AE) I.. ~
AEA X2 Words In FIF02 Y (X2 + 1) Words In FIF02j "'--
tsu(EN) d ~ th(EN)
ENA _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~G~~~~~~~~~~~~ ~
t tsk2 is the minimum time between a rising ClKB edge and a rising ClKA edge for AEA to transition high in the next ClKA cycle. If the time between
the rising ClKB edge and rising ClKA edge is less than tsk2. AEA may transition high one ClKA cycle later than shown.
NOTE A: FIF02 write (eSB =l. W/RB = l. MBB = l). FIF02 read (CSA =l. WiRA = l. MBA = l). Data in the FlF02 output register has been
read from the FIFO.

Figure 12. Timing for AEA When FIF021s Almost Empty

-!!1
TEXAS
INSTRUMENTS
11-98 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

I.- tsk2t -I
I \ \ t :\ Y1 Y2
ClKA

ENA
0
tsu(EN) ~
r/;/7~ ,,""""'~'"
th(EN)
1
I
I
\ I
I
\ I
I I I
tpd(C-AF) 14 .1 I tpd(C-AF) 14 'i
I
AFA [256 - (Y1 + 1)] Words In FIF01 (256 - Y1) Words In FIF01

I
ClKB--f ' ..._---JI \ .J.~~\ 1 ' ....._---'1 '--
tSU(EN)~ 1- Ih(EN)
ENB _ _ _ _ _ _ _ _ _ _ -"t?2.2.2./.2~~ ~~S~0~0~0~S~~~~~______________________
t tsk2 is Ihe minimum lime between a rising ClKA edge and a rising ClKB edge for AFA totransition high in the next ClKA cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tsk2. AFA may transition high one ClKB cycle later than shown.
NOTE A: FIF01 write (CSA = L. W/RA = H. MBA = L). FIF01 read (CSB = L. W/RB = H. MBB = L). Data in the FIF01 output register has been
read from the FIFO.

Figure 13. Timing for AFA When FIF01 Is Almost Full

ClKB I \ (
ISU(EN)~ I+- Ih(EN)
~tsk2t
' . . ._-J1'--+:""'....._-Jy~1
I
-I
-""'I,. . _-JY 2
I
'\-_oJl
ENB 1Zl?ZT~ \s\~ I :
4 ---tl~
Ipd(C-AF) 14
AFB [256 - (y2 + 1)] Words In FIF02
tpd(C-AF) ,.1
1,-------
ClKA--f
' ....._-JI '--
ENA __________________&i?2.2~2~/~2~ ~~~S~S~S~S~S.,~ _______________________
t tsk2 is the minimum time between a rising ClKS edge and a rising ClKA edge for AFB to transnion high in the next ClKB cycle. Ifthetime between
the rising ClKS edge and rising ClKA edge is less than tsk2. AFS may transition high one ClKA cycle later than shown.
NOTE A: FIF02 write (CSS = l. W/RS= l. MBS = ll. FIF02 read (CSA = l. W/RA = l. MSA = l). Data in the FIF02 output register has been
read from the FIFO.

Figure 14. Timing for AFB When FIF02 Is Almost Full

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-99
SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST-IN,FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

I \ 'I....__J/ 'I...__---J/
I '-
ClKA
r-
tsu(EN) ~ th(EN)
------~~~I---------------------------------
. I I
WIRA
VWT//IT4
I
IW
I I
MBA
2Z2ZZZILTJ4 IW·
ENA

AO-A35

ClKB I

W/RB
I I I I
MBB ------~I______~/I I
I II tSU(EN)~1.--.j th(EN) I
ENB I II P?22I '~S.S.S~\__~I_______
~
I
ten H \.. \ tpd(M-OV)
j 4 - - - + - - - . I tpd(C-MR)
I
-11..-----.1
BO..,.B35
FIF01 Output Register

Figure 15_ Timing for Mail1 Register and MBF1 Flag

~TEXAS
.INSTRUMENTS
11-100 POST OFFICE BOX 655303- DALLAS. TEXAS 75265
 SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

I , I '"",,:__-,I '~_ _--II

ClKB
tsu(EN) H
------~~~I~------------------------------
r- th(EN)

I I
W/RB
S\\\\\~~ II 'eo
I I
MBB
V.IT/l/Zl/4 IS
ENB
//ZlZZT/?2/Z{ I..
BO-B35
~ I
ClKA I ,. . .--~I--~I
'''''''------~1 '''''''-------
~- tpd(C-MF) --I
I+- tpd(C-MF) -..:
-----------rl-----~\"""___________~i----J)--------
I I
,\_--_---+II-------_ _----~I_ _ _~I
I I I
WiRA """'//'""2"7'7"7"27":4 i I ~
I I I I
MBA
------~I------'/I
I II tSU(EN)1.------.i1.-.j th(EN)
iI
ENA I II #'/201 t~$.$~~~\__~1________
j 141 .1 tpd(M-OV) I _I
ten r----.I j + - - - l - - - - . I tpd(C-MR) tdls -+14_~.
AO-A35 W1 (remains valid In mall2 r Ister after read)
FI F02 Output Register

Figure 16. Timing for Mail2 Register and MBF2 Flag

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-101
SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI> Vecl ............................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vecl ........................................... ±50 mA
Continuous output current, 10 (VO = 0 to Vecl ............................................. ±50 mA
Continuous current through Vee or GND ................................................. ±400 mA
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under"absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability,
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
Vil lOW-level input voltage 0.8 V
IOH High-level output current -4 mA
IOl low-level output current 8 mA
TA Operating free-air temperature a 70 ·e

~TEXAS
INSTRUMENTS
11-102 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3622
256 x36x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VOH VCC = 4.5 V, IOH =-4 mA 2.4 V
VOL VCC= 4.5 V, IOl= 8 mA 0.5 V
II VCC= 5.5 V, VI = VCC or 0 ±5 IJA
IOZ VCC= 5.5 V, Vo=VccorO ±5 IJA
ICC VCC= 5.5 V, VI = VCC - 0.2 V or 0 400 IJA
CSA=VIH AO-A35 0
CSB = VIH BO-B35 0
VCC=5.5 V, One input at 3.4 V,
~ICC:j: CSA= Vil AO-A35 1 mA
Other inputs at VCC or GND
CSB = Vil BO-B35 1
All other inputs 1
Ci VI=O, f= 1 MHz 4 pF
Co VO=O, f= 1 MHz 8 pF
t All tYPical values are at VCC = 5 V, TA = 25'C.
:j: This is the supply current when each input is at one of the specified TIL voltage levels rather than 0 V or VCC.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 16)
'ACT3622·15 'ACT3622·20 'ACT3622·30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency, ClKA or ClKB 66.7 50 33.4 MHz
tc Clock cycle time, ClKA or ClKB 15 20 30 ns
tw(ClKH) Pulse duration, ClKA and ClKB high 6 8 10 ns
tw(ClKl) Pulse duration, ClKA and ClKB low 6 8 10 ns
tsulD) Setup time, AO- A35 before ClKAI and BO- B35 before ClKBI 4 5 6 ns
Setup time, CSA, W/RA, ENA, and MBA before ClKAI; CSB,
tsu(EN) 4.5 5 6 ns
IN/RB, ENB, and MBB before ClKBI
tsulRS) Setup time, RST1 or RST2 low before ClKAI or ClKBI§ 5 6 7 ns
tsu(FS) Setup time, FSO and FS1 before RST1 and RST2 high 7.5 8.5 9.5 ns
th(D) Hold time, AO-A35 after ClKAI and BO-B35 after ClKBI 0 0 0 ns
Hold time, CSA, W/RA, ENA, and MBA after ClKAI; CSB, W/RB,
th(EN) 0 0 0 ns
ENB, and MBB after ClKBI
th{RS) Hold time, RST1 or RST2 low after ClKAI or ClKBI§ 4 4 5 ns
tt1(FS~ Hold time, FSO and FS1 after RST1 and RST2 high 1 2 2 ns
Skew time between ClKAI and ClKBI for ORA, ORB, IRA, and
tsk1~ 7.5 9 11 ns
IRS
Skew time between ClKAI and ClKSI for AEA, AEB, AFA, and
tSk2~ 12 16 20 ns
AFB
§ Requirement to count the clock edge as one of at least four needed to reset a FIFO
~ Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and
ClKB cycle.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-103
SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 1 through 16)
'ACT3622-15 'ACT3622-20 'ACT3622-30
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
ta Access time, CLKA ito AO-A35 and CLKBi to BO-B35 3 11 3 13 3 15 ns
tpd(C-IR) Propagation delay time, CLKAi to IRA and CLKBi to IRB 2 8 2 10 2 12 ns
tod(C-OR) Propagation delay time, CLKA i to ORA and CLKBi to ORB 1 8 1 10 1 12 ns
tpd(C-AE) Propagation delay time, CLKA ito AEA and CLKBi to AEB 1 8 1 10 1 12 ns
tod(C-AF) Propagation delay time, CLKA ito AFA and CLKBi to AFB 1 8 1 10 1 12 ns
Propagation delay time, CLKA i to MBF1 low or MBF2 high and
tpd(C-MF) 0 8 0 10 0 12 ns
CLKBi to MBF2 low or MBF1 high
Propagation delay time, CLKAito BO- B35t and CLKBi to
tpd(C-MR) 3 13.5 3 15 3 17 ns
AO-A35+
Propagation delay time, MBA to AO-A35 valid and MBB to
tpd(M-DV) 3 11 3 13 3 15 ns
BO-B35 valid
Propagation delay time, RST1 low to AEB low, AFA high, and
tpd(R-F) 1 15 1 20 1 30 ns
MBF1 high, and RST2 low to AEA low, AFB high, and MBF2 high
Enable time, CSA and W/RA low to AO-A35 active and CSB low
ten 2 12 2 13 2 14 ns
and W/RB high to BO-B35 active
Disable time, CSA or W/RA high to AO-A35 at high impedance
tdis 1 11 1 12 1 14 ns
and CSB high or W/RB low to BO-B35 at high impedance
t Writing data to the mal11 register when the BO-B35 outputs are active and MBB IS high
+ Writing data to the mail2 register when the AO-A35 outputs are active and MBA is high

~1ExAs
INSTRUMENTS
11-104 POST OFFICE eox 655303 • DALLAS. TEXAS 75265
 SN74ACT3622
256x36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS247C-AUGUST 1993- REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

SUPPLY CURRENT
vs
CLOCK FREQUENCY
300,---,---,---,---,---,---,---,
fdata =1/2 fclock
250 TA=75'C
< CL=OPF-r---r---r---r---r~~
E
I

~
8,.,
~ 150r---r---r---r--7~~~--+-~
ell
I
S 100 f---t---h41-7"~+---+---+----j
u
u
50r---~~r---+---+---+---+---4

OL-__L -_ _L -_ _L -_ _L -_ _L -_ _ L-~

o 10 20 30 40 50 60 70
fclock - Clock Frequency - MHz

Figure 17

calculating power dissipation

With ICC(f) taken from Figure 17, the dynamic power (Pd) based on all data outputs changing states on each
read can be calculated by:
Pd = VCC x [lCC(f) + (N x dlcc x dc)] + I(CL x VCc2 x fal

A more accurate total power (PT) can be calculated if quiescent power (Pq) is also taken into consideration.
Quiescent power (Pq) can be calculated by:
Pq = VCC x [lCC(I) + (N x ~Icc x dc)]

Total power would be:

PT= Pd + Pq

The above equations provide worst-case power calculations.

Where:
N = number of inputs driven by TIL levels
~Icc = increase in power supply current for each input at a TIL high level
dc = duty cycle of inputs at a TIL high level of 3.4 V
CL output capacitance load
fo switching frequency of an output
ICC(I) idle current, supply current when FIFO is idle,., pF x fclock = 0.2 x fclock
(current is due to free-running clocks)
pF power factor
ICC(f) active current, supply current when FIFO is transferring data

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-105
SN74ACT3622
256x'36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS247C - AUGUST 1993 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

5V

1.1 k.O
From Output _-+_____
Under Test

6800 ;::=- 30pF

" (see Note A)

LOAD CIRCUIT

Timing i ~~ __ _
3V High-Level
--Ii~~.~-
..... ~ QND
3V
Input
------J-
tsu~th
fI
T QND
Input

14- tw --.I
I I
Data. ~-:,.-:;- 3V
Enable --.f 1.5 V ~ Low-Level ~ 1.5 V ~ 3V
Input QND Input ~~v.:..._ QND

VOLTAQE WAVEFORMS VOLTAQE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

~~:~~ .J(1.5V \~.;-V--- ::D

~ I..... tPLZ ---.: i4-- tpZL

II ---~~--- ~3V

\~5-; -
Low-Level
Output I I Input .J(1.5V
_-+..JI I VOL
- ::D
--+I j4- tpZH tpd ~ i+---+I- tpd
VOH
High-Level
I I In-Phase / __ .......,.1- - VOH
~ ~
Output
~OV
I I Output _ _ 1.5V VOL
~ l..... tPHZ

VOLTAQE WAVEFORMS VOLTAQE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAQATION DELAY TIMES
NOTE A: Includes probe and jig capacitance

Figure 18. Load Circuit and Voltage Waveforms

~1ExAs
INSTRUMENTS
11-106 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3638
512 x 32 x 2
FIRST·OUT MEMORY

• Free-Running ClKA and ClKB Can Be • IRA, ORA, AEA, and AFA Flags
Asynchronous or Coincident Synchronized by ClKA
• Two Independent 512 x 32 Clocked FIFOs • IRB, ORB, AEB, and AFB Flags
Buffering Data In Opposite Directions Synchronized by ClKB
• Read Retransmit Capability From FIFO on • low-Power O.8-Mlcron Advanced CMOS
Port B Technology
• Mailbox-Bypass Register for Each FIFO • Supports Clock Frequencies up to 67 MHz
• Programmable Almost-Full and • Fast Access Times of 11 ns
Almost-Empty Flags • Available in Space-Saving 120-Pin Thin
• Microprocessor Interface Control logic Quad Flat (PCB) and 132-Pin Quad Flat
(PQ) Packages
PCB PACKAGE
(TOP VIEW)

CSA 1 90 CS8
WiRA 2 89 VV/RB
ENA 3 88 EN8
ClKA 4 87 ClKB
Vee 5 86 GND
A31 6 85 831
A30 7 84 830
GND 8 83 829
A29 9 82 828
A28 10 81 B27
A27 11 80 826
A26 12 79 Vee
A25 13 78 825
A24 14 77 824
A23 15 76 GND
GND 16 75 823
A22 17 74 822
Vee 18 73 821
A21 19 72 820
A20 20 71 B19
A19 21 70 B18
A18 22 69 GND
GND 23 68 817
A17 24 67 816
A16 25 66 Vee
A15 26 65 815
A14 27 64 B14
A13 28 63 813
Vee 29 62 812
A12 30 61 GND

Ne - No internal connection

Copyright © 1995. Texas Instruments Incorporated

~~~~~;r:~o~1: a=r::~81~~:r!r::" ~~~~:r~m:
standard warranty. Production processing does not ll8C8888rlly Include
testing of all parameters. ~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-107
SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

PQPACKAGEt
rrOPVIEWj

NC NC
CSB NC
W/RB CSA
ENB WiRA
ClKB ENA
GND ClKA
B31 Vcc
B30 A31
B29 A30
B28 GND
B27 A29
B26 A28
Vcc A27
B25 A26
B24 A25
GND A24
B23 A23
B22 GND
B21 A22
B20 Vcc
B19 A21
B18 A20
GND A19
B17 A18
B16 GND
Vcc A17
B15 A16
B14 A15
B13 A14
B12 A13
GND Vec
NC A12
NC NC

NC - No internal connection
t Uses Yamaichi socket IC51-1324-828

~TEXAS
INSTRUMENTS
11-108 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C-JUNE 1992 - REVISED SEPTEMBER 1995

description
The SN74ACT3638 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock
frequencies up to 67 MHz and has read access times as fast as 11 ns. Two independent 512 x 32 dual-port
SRAM FIFOs on board the chip buffer data in opposite directions. The FIFO memory buffering data from port
A to port B has retransmit capability, which allows previously read data to be accessed again. Each FIFO has
flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate
when a selected number of words is stored in memory. Communication between each port can bypass the
FIFOs via two 32-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been
stored. Two or more devices can be used in parallel to create wider data paths.
The SN74ACT3638 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
cOincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The input-ready (IRA, IRB) flags and almost-full (AFA, AFB) flags of the SN74ACT3638 are two-stage
synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flags and almost-empty
(AEA, AEB) flags of the SN74ACT3638 are two-stage synchronized to the port clock that reads data from its
array. Offsets for the almost-full and almost-empty flags of both FIFOs can be programmed from port A.
The SN74ACT3638 is characterized for operation from O°C to 70°C.
For more information on this device family, see the application report FIFO Mailbox-Bypass Registers: Using
Bypass Registers to Initialize DMA Control in the 1996 High-Performance FIFO Memories Designer's
Handbook, literature number SCAA012A.

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS. TeXAS 75265 11-109
SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

functional block diagram

, . - - - - - - - - - - - - - - - - - MBF1
Mall1

Sl=~il ,._~----R::~---~~
CLKA -
CSA - Port-A
WiRA - Control
ENA
MBA
-
-
Logic -- - ~ II
.~ 512x32
~~
.S' 1
a: ~ SRAM ff- a: 1
'5 '5 1
RST1 -
FIF01,
Mall 1
Reset
~ ! I-T-!,+-..., 32

Logic 1
1
~ ...!.......I--++++I------ RTM

~.~
Gi C)
!
H,I-+__
a:.3 1
g i
' + - - -.....1 Write
! I Pointer
Il Read.
Pointer ~ I -
>0
II)
1+.--+++-1+-----
1~
1
RFM

.....; i
TTl
IRA Status-Flag i ORB
AFA Logic I AEB

FSO

AO-A31
..
1
L
Programmable-
FS1 -----t-t+-H-t"'l"'rl,---I OffsetFlag
~~
~-------~------- .J

Registers
rft
1

P--t++f-+----- ROYB
BO-B31

ROYA
--.---HH-+-+""I1 J=fi-;;~----i------- -1
ORA Status-Flag 1 - - -____-+1-+++++----- IRB
AEA Logic AFB
!
I + +
...._--11__.....1 Read
1 I Pointer
II Write
Pointer
1...----,
I~
32

1
I~ ~ FIF02,
.. I II
~-'H! 0
~. l.....L.
_ ~
Mall2
Reset -+- RST2
1 .S' 512x32 .!Il Logic

'i""
~
r+f i SRAM
-
= __ .J
L=___________'=
- -4- CLKB
o
'---1--1
Port-B
- - Control
Logic
::= CSB
W/RB
Mall2
Register
I '----1--1
:!= ENB
MBB

MBF2 - - - -_ _ _ _ _ _ _ _ _ _ _ ...J'

~TEXAS
INSTRUMENTS
11-110 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME
AO-A31 I/O Port-A data. The 32-bit bidirectional data port for side A.
0 Port-A almost-empty flag. Programmable almost-empty flag synchronized to ClKA. AEA is low when the number of
AEA
(portA) words in FIF02 is less than or equal to the value in the almost-empty A offset register, X2.
0 Port-B almost-empty flag. Programmable almost-empty flag synchronized to ClKB. AEB is low when the number of
AEB
(port B) words In FIFOI is less than or equal to the value in the almost-empty B offset register, XI.
0 Port-A almost-full flag. Programmable almost-full flag synchronized to ClKA. AFA is low when the number of empty
AFA
(portA) locations in FIFOI is less than or equal to the value in the almost-full A offset register, VI.
0 Port-B almost-full flag. Programmable almost-full flag synchronized to ClKB. AFB is low when the number of empty
AFB
(port B) locations in FIF02 is less than or equal to the value In the almost full B offset register, V2.
BO-831 1/0 Port-B data. The 32-bit bidirectional data port for side B.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
CLKA I
or coincident to ClKB. IRA, ORA, AFA, and AEA are synchronous to the low-to-high transition of ClKA.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
ClKB I
or coincident to ClKA. IRB, ORB, AFB, and AEB are synchronous to the low-to-high transition of ClKB.
Port-A chip select. CSA must be low to enable a low-to-high transition of ClKA to read or write data on port A. The
CSA I
AO-A31 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of ClKB to read or write data on port B. The
CSB I
BO -B31 outputs are in the high-impedance state when CSB is high.
ENA I Port-A enable. ENA must be high to enable a low-to-high transition of ClKA to read or write data on port A.
ENB I Port-B enable. ENB must be high to enable a low-to-high transition of ClKB to read or write data on port B.
Flag-offset selects. The low-to-high transition of a FIFO reset Input latches the values of FSO and FSI. I! either FSO
or FSI is high when a reset input goes high, one ofthree preset values is selected as the offset forthe FIFO almost-full
FS1,FSO I
and almost-empty flags. I! both FIFOs are reset simultaneously and both FSO and FSI are low when RST1 and RST2
g'o high, the first four writes to FIFOI program the almost-full and almost-empty offsets for both FIFOs.
Port-A input-ready flag. IRA is synchronized to the low-to-high transition of ClKA. When IRA Is low, FIFOI is full and
0 writes to its array are disabled. When FIFOI is in retransmit mode, IRA indicates when the memory has been filled
IRA
(portA) to the pOint of the retransmit data and prevents further writes. IRA is set low when FIFOI is reset and is set high on
the second low-to-high transition of ClKA after ~eset.
Port-B input-ready flag.IRB is synchronized to the low-to-high transition of ClKB. When IRB is low, FIF02 is full and
0
IRB writes to its array are disabled. IRB is set low when FIF02 is reset and is set high on the second low-to-high transition
(port B)
of ClKB after reset.
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
MBA I AQ-A31 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects
FI F02 output-register data for output.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
MBB I BO-831 outputs are active, a high level on MBB selects data from the mail 1 register for output and a low level selects
FIFOI output-register data for output.
Maill register flag. MBFl is set low by the low-to-high transition of ClKA thai writes data to the maill register. Writes
MBFl 0 tothe mail 1 register are inhibited while MBFl is low. MBFl is set high by a low·to-high transition of ClKB when a port-B
read is selected and MBB is high. MiWf is set high when FIFOI is reset.
Mail2 register flag. MBF2 is set low by the low-to-hlgh transition of ClKB that writes data to the mail2 register. Writes
MBF2 0 to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of ClKA when a port-A
read is selected and MBA is high. MBF2 is set high when FIF02 is reset.
Port-A output-ready flag. ORA Is synchronized to the low-to-high tranSition ofClKA. When ORA is low, FIF02 is empty
0 and reads from its memory are disabled. Ready data is present on the output register of FIF02 when ORA is high.
ORA
(portA) ORA is forced low when FIF02 is reset and goes high on the third low-to-high transition of ClKA after a word is loaded
to empty memory.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-111
SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

Terminal Functions (Continued)

TERMINAL
1/0 DESCRIPTION
NAME
Port-B output-ready flag. ORB is synchronized tothe low-to-high transition 01 ClKB. When ORB is low, FIF01 is empty
0 and reads lrom its memory are disabled. Ready data is present on the output register 01 FIF01 when ORB is high.
ORB
(port B) ORB is lorced low when FIF01 is reset and goes high on the third low-to-high transition 01 ClKB after a word is loaded
to empty memory.
0 Port-A ready. A high on W/RA selects the inverted state 01 IRA lor output on ROYA, and a low on W/RA selects the
ROYA
(portA) inverted state 01 ORA lor output on ROYA.
0 Port-B ready. A low on W/RB selects the inverted state 01 IRB lor output on ROYB, and a high on W/RB selects the
ROYB
(port B) inverted state 01 ORB lor output on ROYB.
FIF01 read Irom mark. When FIF01 is in retransmit mode, a high on RFM enables a low-to-high transition 01 ClKB
RFM I
to reset the FIF01 read pOinter to the retransmit location and output the first retransmit data.
FIF01 reset. To reset FIF01, lour low-to-high transitions 01 ClKA and lour low-to-high transitions 01 ClKB must occur
RST1 I while RST1 is low. The low-to-high transition 01 RST1 latches the status 01 FSO and FS1 lor AFA and AEB offset
selection. FIF01 must be reset upon power up belore data is written to its RAM.
FIF02 reset. To reset FIF02, lourlow-to-high transitions 01 ClKA and lour low-to-high transitions 01 ClKB must occur
RST2 I while RST2 is low. The low-to-high transition 01 RST2 latches the status 01 FSO and FS1 lor AFB and AEA offset
selection. FIF02 must be reset upon power up belore data is written to its RAM.
FIF01 retransmit mode. When RTM is high and valid data is present on the output 01 FIF01, a low-to-high transition
RTM I 01 ClKB selects the data lor the beginning 01 a FIF01 retransmit. The selected position remains the initial retransmit
point until a low-to-high transition 01 ClKB occurs while RTM is low, which takes FIFO out 01 retransmit mode.
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A lor
WiRA I
a low-to-high transition 01 ClKA. The AO-A31 outputs are in the high-impedance state when WiRA is high.
Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B lor
W/RB I
a low-to-high transition 01 ClKB. The BO-B31 outputs are in the high-impedance state when W/RB is low.

detailed description
reset
The FIFO memories of the SN74ACT3638 are reset separately by taking their reset (RST1, RST2) inputs low
for at least four port-A clock (ClKA) and four port-B clock (ClKB) low-to-high transitions. The reset inputs can
switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pOinters and forces the
input-ready flag (IRA, IRB) low, the output-ready flag (ORA, ORB) low, the almost-empty flag (AEA, AEB) low,
and the almost-full flag (AFA, AFB) high. Resetting a FIFO also forces the mailbox flag (MBF1, MBF2) of the
parallel mailbox register high. After a FI FO is reset, its input-ready flag is set high after two clock cycles to begin
normal operation. A FIFO must be reset after power up before data is written to its memory.
A low-Io-high transition on a FIFO reset (RST1, RST2) input latches the value of the flag-select (FSO, FS1)
inputs for choosing the almost-full and almost-empty offset programming method (see almost-empty and
almost-full flag offset programmin{j).
almost-empty flag and almost-full flag offset programming
Four registers in the SN74ACT3638 are used to hold the offset values for the almost-empty and almost-full flags.
The port-B almost-empty flag (AEB) offset register is labeled X1, and the port-A almost-empty flag (AEA) offset
register is labeled X2. The port-A almost-full flag (AFA) offset register is labeled Y1 , and the port-B almost-full
flag (AFB) offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The
offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from
port A (see Table 1).

~TEXAS
INSTRUMENTS
11-112 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3638
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

almost-empty flag and almost-full flag offset programming (continued)

Table 1. Flag Programming

FS1 FSO RST1 RST2 X1 AND Y1 REGISTERSt X2 AND Y2 REGISTERS:!:
H H i X 64 X
H H X i X 64
H L i X 16 X
H L X i X 16
L H i x 8 X
L H X i x 8
L L i i Programmed from port A Programmed from port A
tX1 register holds the offset for AEB; Yl register holds the offset for AFA.
X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
:1=

To load the almost-empty flag and almost-full flag offset registers of a FIFO with one of the three preset values
listed in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset
input. For example, to load the preset value of 64 into Xi and Vi, FSO and FS1 must be high when FIF01 reset
(RST1) returns high. Flag-offset registers associated with FIF02 are loaded with one of the preset values in the
same way with FIF02 reset (RST2). When using one of the preset values for the flag offsets, the FIFOs can
be reset simultaneously or at different times.
To program the Xi, X2, Vi, and V2 registers from port A, both FIFOs should be reset simultaneously with FSO
and FS 1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes
to FIF01 do not store data in RAM but load the offset registers in the order Vi, Xi, V2, X2. Each offset register
uses port-A (AS-AO) inputs, with AS as the most-significant bit. Each register value can be programmed from
1 to 50S. After all the offset registers are programmed from port A, the port-B input-ready flag (IRB) is set high
and both FIFOs begin normal operation.
FIFO write/read operation
The state of the port-A data (AO-A31) outputs is controlled by the port-A chip select (GSA) and the port-A
write/read select (WiRA). The AO-A31 outputs are in the high-impedance state when either GSA or W/RA is
high. The AO-A31 outputs are active when both GSA and W/RA are low.
Data is loaded into FIF01 from the AO-A31 inputs on a low-to-high transition of GLKA when GSA is low, W/RA
is high, ENA is high, MBA is low, and IRA is high. Data is read from FIF02 tothe AO-A31 outputs by a low-to-high
transition of GLKA when GSA is low, WiRA is low, ENA is high, MBA is low, and ORA is high (see Table 2). FIFO
reads and writes on port A are independent of any concurrent port-B operation.

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA AO-A31 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L i In high-impedance state FIFOI write
L H H H i In high-impedance state Mail1 write
L L L L X Active, FI F02 output register None
L L H L i Active, FIF02 output register FIF02 read
L L L H X Active, mail2 register None
L L H H i Active, mail2 register Mail2 read (set MBF2 high)

~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-113
SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

FIFO write/read operation (continued)

The port-B control signals are identical to those of port A with the exception that the port-B write/read select
(W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (BO-B31) outputs is
controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The BO-B31 outputs are
in the high-impedance state when either CSB is high or W/RB is low. The BO-B31 outputs are active when CSB
is low and W/RB is high.
Data is loaded into FIF02 from the BO-B31 inputs on a low-to-high transition of ClKB when CSB is low, W/RB
is low, ENB is high, MBB is low, and IRB is high. Data is read from FIF01 to the BO-B31 outputs by a low-to-high
transition of ClKB when CSB is low, W/RB is high, ENB is high, MBB is low, and ORB is high (see Table 3). FIFO
reads and writes on port B are independent of any concurrent port-A operation.

Table 3. Port-8 Enable Function Table

CSB W/RB ENB MBB ClKB BO-B31 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L L L X X In high-impedance state None
L L H L i In high-impedance state FIF02write
L L H H i In high-impedance state Mail2write
L H L L X Active, FIF01 output register None
L H H L i Active. FIF01 output register FIF01 read
L H L H X Active, mail1 register None
L H H H i Active, mail1 register Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select can change states during the
setup- and hold-time window of the cycle.
When a FIFO output-ready flag is low, the next data word is sent to the FIFO output register automatically by
the low-to-high transition of the port clock that sets the output-ready flag high. When the output-ready flag is
high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the
port-chip select, write/read select, enable, and mailbox select.
synchronized FIFO flags
Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve
flag-Signal reliability by reducing the probability of metastable events when ClKA and ClKB operate
asynchronously to one another (see the application report Metastability Performance of Clocked FIFOs in the
1996 High-Performance FIFO Memories Data Book, literature number SCAD003C). ORA, AEA, IRA, and AFA
are synchronized to ClKA. ORB, AEB, IRB, and AFB are synchronized to ClKB. Tables 4 and 5 show the
relationship of each port flag to FIF01 and FIF02.

~TEXAS
INSTRUMENTS
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 SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

synchronized FIFO flags (continued)

Table 4. FIF01 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS TOCLKB TOCLKA
IN FIF01'H:
ORB AEB AFA IRA
0 L L H H
1 to X1 H L H H
(X1 + 1) to [512 - (Y1 + 1)] H H H H
(512 - Y1) to 511 H H L H
512 H H L L
t X1 IS the almost-empty offset lor FIF01 used by AEB. Y1 IS the almost-lull
offset lor FIF01 used by AFA. Both X1 and Y1 are selected during a reset 01
FIF01 or programmed Irom port A.
:I: When a word loaded to an empty FIFO is shifted to the output register, its
previous FI FO memory location is Iree.

Table 5. FIF02 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS TOCLKA TOCLKB
IN FIF02:1:§
ORA AEA AFB IRB
0 L L H H
1 to X2 H L H H
(X2 + 1) to [512 - (Y2 +1)] H H H H
(512- Y2) to 511 H H L H
512 H H L L
:I: When a word loaded to an empty FIFO IS shifted to the output register, ItS
previous FIFO memory location is Iree.
§ X2 is the almost-empty offset lor FIF02 used by AEA. Y2 is the almost-lull
offset lor FIF02 used by AFB. Both X2 and Y2 are selected during a reset
01 FIF02 or programmed lrom port A.

output-ready flags (ORA, ORB)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the
output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low, the
previous data word is present in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine
that controls an output-ready flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is empty, empty+ 1, or empty+2. From the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of the output-ready flag synchronizing clock; therefore,
an output-ready flag is low if a word in memory is the next data to be sent to the FIFO output register and three
cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written.
The output-ready flag of the FIFO remains low until the third low-to-high transition of the synchronizing clock
occurs, simultaneously forcing the output-ready flag high and shifting the word to the FIFO output register.
A low-to-high transition on an output-ready flag synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 7 and 8).

~TEXAS
INSTRUMENTS
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SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

input-ready flags (IRA, IRB)

The input-ready flag of a FI FO is synchronized to the port clock that writes data to its array. When the input-ready
flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when
the input-ready flag is low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an
input-ready flag monitors a write-painter and read-painter comparator that indicates when the FIFO SRAM
status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready
to be written in a minimum of two cycles of the input-ready flag synchronizing clock; therefore, an input-ready
flag is low if less than two cycles of the input-ready flag synchronizing clock have elapsed since the next memory
write location has been read. The second low-to-high transition on the input-ready flag synchronizing clock after
the read sets the input-ready flag high.
A low-to-high transition on an input-ready flag synchronizing clock begins the first synchronization cycle of a
read if the clock transition occurs at time tsk1' or greater, after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 9 and 10).
ready flags (RDYA, RDYB)
A ready flag is provided on each port to show if the transmitting or receiving FI FO chosen by the port write/read
select is available for data transfer. The port-A ready flag (ROYA) outputs the complement of the IRA flag when
WiRA is high and the complement of the ORA flag when WiRA is low. The port-B ready flag (ROYB) outputs
the complement of the IRB flag when W/RB is low the the complement of the ORB flag when W/RB is high (see
Figures 11 and 12).
almost-empty flags (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state
machine that controls an almost-empty flag monitors a write-painter and read-pointer comparator that indicates
when the FIFO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty state is
defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset
values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset
programming). A FIFO is almost empty when it contains X or less words in memory and is no longer almost
empty when it contains (X + 1) or more words. Note that a data word present in the FIFO output register has
been read from memory.
Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for its
almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1)
or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled
the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of its
synchronizing clock after the FI FO write that fills memory to the (X + 1) level. A low-to-high transition of an
almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater,
after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figures 13 and 14).
almost-full flags (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine
that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the contents
of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FIFO reset
or programmed from port A (see almost-empty flag and almost-full flag offset programming). A FIFO is almost
full when it contains (512 - Y) or more words in memory and is not almost full when it contains [512 - (Y + 1))
or less words. A data word present in the FIFO output register has been read from memory.

~TEXAS
INSTRUMENTS
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 SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C- JUNE 1992 - REVISED SEPTEMBER 1995

almost-full flags (AFA, AFB) (contInued)

Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for its
almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [512 - (Y + 1)]
or less words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced
the number of words in memory to [512 - (Y + 1)]. An almost-full flag is set high by the second low-to-high
transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to
[512 - (Y + 1)]. A low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization
cycle if it occurs at time tsk2, or greater, after the read that reduces the number of words in memory to
[512 - (Y + 1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle
(see Figures 15 and 16).
synchronous retransmit
The synchronous retransmit feature of the SN74ACT3638 allows FIF01 data to be read repeatedly starting at
a user-selected position. FIF01 is first put into retransmit mode to select a beginning word and prevent on-going
FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three words can
retransmit repeatedly starting at the selected word. FIF01 can be taken out of retransmit mode at any time and
allow normal operation.
FIF01 is put in retransmit mode by a low-to-high transition on ClKB when the retransmit-mode (RTM) input is
high and ORB is high. This rising ClKB edge marks the data present in the FIF01 output register as the first
retransmit data. FIF01 remains in retransmit mode until a low-to-high transition occurs while RTM is low.
When two or more reads have been completed past the initial retransmit word, a retransmit is initiate.d by a
low-to-high transition on ClKB when the read-from-mark (RFM) input is high. This rising ClKB edge shifts the
first retransmit word to the FIF01. output register and subsequent reads can begin immediately. Retransmit
loops can be done endlessly while FIF01 is in retransmit mode. RFM should not be high during the ClKB rising
edge that takes the FIF01 out of retransmit mode.
When FIF01 is put into retransmit mode, it operates with two read pOinters. The current read pointer operates
normally, incrementing each time a new word is shifted to the FIF01 output register and used by the ORB and
AEB flags. The shadow read pointer stores the SRAM location at the time FIF01 is put into retransmit mode
and does not change until FIF01 is taken out of retransmit mode. The shadow read pOinter is used by the IRA
and AFA flags. Data writes can proceed while FIF01 is in retransmit mode, AFA is set low by the write that stores
(512 - Y1) words after the first retransmit word, and IR is set low by the 512th write after the first retransmit word.
When FIF01 is in retransmit mode and RFM is high, a rising ClKB edge loads the current read pOinter with the
shadow read-pointer value and the ORB flag reflects the new level of fill immediately. If the retransmit changes
the FIF01 status out of the almost-empty range, up to two ClKB rising edges after the retransmit cycle are
needed to switch AEB high (see Figure 18). The rising ClKB edge thattakes FIF01 out of retransmit mode shifts
the read pOinter used by the IRA and AFA flags from the shadow to the current read pointer. If the change of
read pointer used by IRA and AFA should cause one or both flags to transition high, at least two ClKA
synchronizing cycles are needed before the flags reflect the change. A rising ClKA edge after FIF01 is taken
out of retransmit mode is the first synchronizing cycle of IRA if it occurs at time tsk1 or greater after the rising
ClKB edge (see Figure 19). A rising ClKA edge after FIF01 is taken out of retransmit mode is the first
synchronizing cycle of AFA if it occurs at time tsk2' or greater, after the rising ClKB edge (see Figure 20).
mailbox registers
Each FIFO has a 32-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port-data-transfer operation. A low-to-high transition on ClKA writes AO-A31 data to the mail1 register
when a port-A write is selected by CSA, WiRA, and ENA and with MBA high. A low-to-high transition on ClKB
writes BO-B31 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and with MBB
high. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail
register are ignored while the mail flag is low.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-117
SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

mailbox registers (continued)

When data outputs of a port are active, the data on the bus comes from the FIFO output register when the
port-mailbox-select input is low and from the mail register when the port-mailbox-select input is high. The mail1
register flag (MBF1) is set high by a low-to-high transition on GlKB when a port-B read is selected by GSB,
W/RB, and ENS and with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on
GlKA when a port-A read is selected by GSA, WiRA, and ENA and with MBA high. The data in a mail register
remains intact after it is read and changes only when new data is written to the register.

ClKA
--tI '- th(RS)
ClKB
1 I It
_ _ _ _-..1
-.I. r- tsu(RS) I
I
1
1 tsu(FS)
~
,:--"1 I h(FS) 1
1
RST1 \.
1
I I
,
I I
I
FS1, FSO

~~I· ~
IRA S\\\\\'S)\\\\\\\\~ I I
1 tpd(C-OR) ~
O.RB~~~~
tpd(R-F) j4-----r
AEB~~\1
tpd(R-F) ~
AFA VZZZZTf'2Z{
tpd(R-F) ~

Figure 1. FIF01 Reset Loading X1 and Y1 With a Preset Value of Eightt

t FIF02 is reset in the same manner to load X2 and Y2 with a preset value.

-!/} TEXAS
INSTRUMENTS
11-118 POST OFFICE eox 655303 • DALLAS, TEXAS 75265
 SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C-JUNE 1992 - REVISED SEPTEMBER 1995

ClKA

IRA

ClKB
1 I 2
Ipd(C-IR)~r
IRB

t tsk1 is the minimum time between the rising ClKA edge and a rising ClKB edge for IRB to transition high in the next cycle. If the time between
the rising edge of ClKA and rising edge of ClKB is less than tsk1 , then IRB may transition high one cycle later than shown.
NOTE A: CSA = l, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles ..

Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values After Reset

~ to ~I
i+ IW(ClKH)....I.-1 tW(ClKl).., --.I 14- Ih(EN)
ClKA } " r,--~\
I
. . .__...JY'--~\
I
Isu(EN)~
I
I
I
YrTl--"""',-
I I
I I I I I
IRA I I I I
Isu(EN) "'r--t~o!<II4"" Ih(EN) I I ~ I+- Ih(EN)
I I I II~_ _ _-

~ I~ I I II
Isu(EN) 14 ~14 ~ Ih(EN) I I ~ I.- Ih(EN)
W/RA
I7?Z/ZZIlZZZ{ iF i ii b~
...~~~~I~SU~(E~N~)r ~I.~ Ih(EN) I I -I I.- Ih(EN)
MBA I I I I I~~~.,..,..~
Isu(EN) Ih(EN) Isu(EN) I+- Ih(EN) Isu(EN) I+------ij 1 - Ih(EN)
ENA vz;zr//lZZll I ~ ~ tvzz;va
Isu(D) I. ~Iul Ih(D)
AO-A31 fOlo dperalfon X>OOO<>O<X
t Written to FI F01
Figure 3. Port-A Write-Cycle Timing for FIF01

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-119
SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C- JUNE 1992 - REVISED SEPTEMBER 1995

I. te ~
r- tw(ClKH) ...1..1 tw(ClKl) -+I
tsu(EN)
-I
1+-----'1
~ thlEN)
I
ClKS )I '\ (~--""'\\'----JiY""""-~' I V"';-I--"""\,-
II I
I
I
1
II
I 1
IRS

Figure 4, Port-B Write-Cycle Timing for FIF02

I. Ie .1
~ tw(ClKH) • tw(ClKl) -.I
ClKS )I \. },----, (,----, I '-
1 '------"I '-----'!'I
I 1 I
ORS
I 1 I
I I -tI 14- th(EN)
}~----+:------~:~-----~:~~
I I II 1

W/RS 7lTq : : : }\%\N

1 1.-----.1 tsu(EN) 1 I
MSS I I. 1 I

ENS ~Z22222~~~""-rI~888888~~....-t~~~~~~~~~~~ ~~~~4444~

tpd(M-OV) 1 I· ·1 I
__
No !.......J t
.. ten .I 1 I~ Ie --./ Operation r--:I dis
1- "-.~ _ J,.--~~..I.-"""", .
SO-S31 -----~ WI X'--..........:w::.:2:.:.f.............JL........~W~3~f~........}j....- ....-
t Read from FIFOI
Figure 5. Port-B Read-Cycle Timing for FIF01

~TEXAS
INSTRUMENTS
11-120 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

I. Ie _I
i+- Iw(CLKH) .... tw(CLKL) -.I
CLKA )I {. }
I
\ (
I
\ rI L.
I I I
ORA I I
I
I I -I
I I I
CSA
} I I I
I I I I
I I I
W/RA
\\\\\) I I
I 1.-----.1 Isu(EN) I
MBA I I I I I
I
I I l+- Ih(EN) Isu(EN) I---~ Ih(EN)
I I
I I I
i++!I Idls
tla ~X No

*
Operallon
bla --.I
AO-A31 W2T W3t ~
W1
t Read from FIF02
Figure 6. Port-A Read-Cycle Timing for FIF02

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-121
SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

ClKA

CSA low

W/RA High I
tsu(EN) ~ I.-- th(E~)
MBA S\\\\\~ ~172~6~2""2'r?:r2:>"":2:OO-::V"":/~2~/j~?:~2'r2'r2:>"":2:OO-::V""/':~2~/j~2~2'r2r2:>"":2:>"":V""/':"'2~2~2~27"27"2"-:2:>""://'''''/':'''2"'''72~2~27"2772
tSU(E:..r-s Jt ihlEN)
40(/~
I ~~.0.$~0.~~---------------------------------------
ENA
1
I
IRA High t 1• .1 I

AO-A31

tw(ClKH) t::::::!! I w(ClKl)

ClKB 1 2

tpd(C-OR)
oRB _________o~I_d_D_at_a_ln_F_IF_O~1~O~U~tp_u~tR_e~g~ls~te~r__________~I----~
I4-r- -.---+:r1 =~
tpd(C-R) ~/4--~ 14
1
I
CSB -=Lo~w~ ________________________________ ~~ ________.I1 ____________________
1
1
W/RB High 1
1
MBB Low 1 1
1 tsu(EN) 1.::1 !+- th(EN)
ENB V/Zl/ZZ2ZZZZZZZZZZZ/ZZZZl/!Z2/(zzzZd t\~\\\\'\\\\\":
~ta - '
BO-B31 ____________~O~ld~Da~ta~ln~F~IF~O~1~O~u~tp~ut~R~e~9~ls=te~r__________J*------------~W~1----------
t tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition high and to clock the next word to the FIF01
output register in three CLKB cycles. If the time between the rising ClKA edge and rising CLKB edge is less than tsk1, then the transition of ORB
high and load of the first word to the output register may occur one CLKB cycle later than shown.

Figure 7. ORB-Flag Timing and Flrst-Data-Word Fallthrough When FIF01 Is Empty

~TEXAS
INSTRUMENTS
11-122 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C- JUNE 1992 - REVISED SEPTEMBER 1995

I.-- te -----+I
tw(ClKH) I. ~. ~I tw(ClKl)
ClKB

CSB-=lo~w~ ____ ~I I______ I _________________________________________________

~I

I I
W/RB low I I
I

ClKA

I--th(EN)

ENA ?lZZZ?/lZZZ7az;~21/!Z21 ~
It- ta --.!
AO-A31 -------------=O~ld~D~am~ln~F=IF~O~2~O~ut~p~ut~R~S~I~~~~-----------*----------~W~1----------

t tsk1 is the minimum time between a rising ClKS edge and a rising ClKA edge for ORA to transition high and to clock the next word to the FIF02
output register in three ClKA cycles. If the time between the rising ClKS edge and rising ClKA edge Is less than tsk1. then the transition of ORA
high and load of the first word to the output register may occur one ClKA cycle later than shown.
Figure 8. ORA-Flag Timing and Flrst-Data-Word Fallthrough When FIF02 Is Empty

~1ExAs
INSfRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-123
SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C- JUNE 1992 - REVISED SEPTEMBER 1995

I.----- Ie -----tI
1 1
Iw(CLKH) ~ ~4 ~I tw(CLKL)

CLKB 1 \. " \ . . ._--J1 \ ....._--'1 \ ....._--J1 \----

1
CSB -=LO~W~................~I....................................................................................................__
I
W/RB High 1
1
MBB Low I
-=~....................~I ....................................................................................................--
ISU(EN)I+---+I++IJ.}h(EN)
ENB _ _....//"""/"""/"""Z"-J1 : '\,;0~S~S~S:..J\'--___________________
1

ORB High

Next Word From FIF01

r- Isk1 t --J~i'I-- Ie ------IIi

Iw(CLKH) 14 ~ ~ Iw(CLKL)
CLKA ~\,;_--JI \ /1 " (2 \~_...J( \\,;._...Jr-
1 1 1 ~I Ipd(C-IR)
FI_FO_1_F_U_II____....__...._Ip_d_(C_-I_R)4r........
IRA __............_ _ _ _ _ -J) :i.4----~{~............_____
14 ~I ~ Ipd(C-R)
RD~----------------------------~~~-----\
Ipd(C-R)
:14 1~--------
1
CSA Low 1
---------------------------------~I------------
I
W/RA

ENA
?ZZ/?Zl?ZZZlZ/?fl/2VZ//AVZ27~~~
AO-A31
To FIF01
t tsk1 is the minimum time between a rising ClKB edge and a rising ClKA edge for IRA to transition high in the next ClKA cycle. If the time between
the rising ClKB edge and rising ClKA edge is less than tsk1. then IRA may transition high one ClKA cycle later than shown.

Figure 9. IRA-Flag Timing and First Available Write When FIF01 Is Full

~TEXAS
INSTRUMENTS
11-124 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

It--- te ----.I
1 1
~4 ~I tw(CLKL)
tw(CLKH) 14

CLKA I \. j ''-_---'I I ''-_---'I ,'-_--J ''---

CSA ________-r____________________________________________________
~
L
o
~
w
~
WffiA ~Lo~w~ ________ -r____________________________________________________
MBA ~LO~W~ ________ ~ ____________________________________________________

tsu(EN) l-t.t~(EN)
ENA Il!ZZ) 1 ~IO>..~;:"';S;:",;S:",;:~",,---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

1
ORA High

Next Word From FIF02

J- tsk1t --'\011I4---tc---'
tw(CLKH) \4 .,. , tw(CLKL)
CLKB ~,-_---,/"'-~\ j 1 \ /2 ,'-_----:( \\-_.J~
i l I,~._ _-.;1 t
t
.~~~ ~ r ~ ~~~
)---+1- -.....,,'--____
IRB
---------------~I--~
FIF02 Full

tpd(C-R) 14
1

~I
1 -
14-4--~~I tpd(C-R)
RDYB------------------~\~_~I----J)
- I
1
CSB Low 1
-----------------------~I--------
1
W/RB Low 1
1
tsu(EN) I.--M+\ th(EN)
MBB &\\\\\\\\\~\\\~ I Wffi'l272llZ?2
tsu(EN) I.----.I~ th(EN)
ENB

BO-B31

t tskl is the minimum time between a rising CLKA edge and a rising ClKB edge for IRB to transition high in the next ClKB cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tskl. then IRB may transition high one ClKS cycle later than shown.

Figure 10. IRB-Flag Timing and First Available Write When FIF021s Full

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-125
SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

W/RA <2(>~~ \ _____________________________

RDYA
~ tpd(W-R)
~--------~ln-ve-r-se-o~f~IR~A~--~----*~~~~ln-v-e-rs-e-o~f~O~RA~------
I-----+! tpd(W- R)

Figure 11. WiRA to ROVA Timing

W/RB
~\S~S~0.S.S~$~~~$~~~$.~~------------------1
~ tpd(W-R)
~--------~ln~v~e~rs~e~o~f~IR~B~~----*~~~--~ln-ve-r-se-o~f~O~R~B~-----
I-----+! tpd(W- R)

Figure 12. W/RB to ROVB Timing

ClKA

ENA IZZTX.~ \:10..:$:...:$:"':0"'....::::--..:....:::~...:::.~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

If- tsk2t -tI

ClKB
!4-----tltj tpd(C-AE) 14 ~I
AEB Xl Words In FIFOl Y(Xl + 1) Words In FIFOl J \...
tsu(EN) b ~ th(EN)
ENB ________________________________________ ~?~2~2~2~2~2~~ ~'\\~
t tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition high in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tsk2, then AEB may transition high one CLKB cycle later than shown.
NOTE B: FIFOl write (CSA = L, WiRA = H, MBA = L), FIF01 read (CSB = L, W/RB = H, MBB = L). Data in the FIF01 output register has been
read from the FIFO.

Figure 13. Timing for AEB When FIF01 Is Almost Empty

ClKB

ENB

'--___: 2
ClKA
~ tpd(C-AE)-tj tpd(C-AE) i4 ~I
Y(X2 + 1) Words In FIF02 J
AEA X2 Words In FIF02

ENA ____________________________________~AV~2~2~?~2~2~~
tsu(EN) H r- "-
th(EN)
\S\~

t tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA totransition high in the next CLKA cycle. Ifthetime between
the rising CLKB edge and rising CLKA edge is less than tsk2, then AEA may transition high one CLKA cycle later than shown.
NOTE A: FIF02 write (CSB = L, W/RB = L, MBB = L), FIF02 read (CSA = L, W/RA = L, MBA = L). Data in the FIF02 output register has been
read from the FI FO.

Figure 14. Timing for AEA When FIF02 Is Almost Empty

~TEXAS
INSTRUMENTS
11-126 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

ClKA I \
tsU(EN)!..-.:::I
I
I+- th(EN)
I.-

I
tSk2t
,'-_--J1r-+1""\'\..o-.--JY~1-"'"'
-t!
, Y2
I
, I
ENA ~~~~~~S~0~S~S~S·\~____~I __________________+-_____________ I
I
I
tpd(C-AF) I_ I tpd(C-AF) 1'- ~
AFA [512 - (Vi + 1)] Words In FIF01 (512 - Y1) Words In FIF01

ClKB--./
'\-_...JI \ H
tsu(EN)
1 \
If- th(EN)
I \'-_--JI '--
ENB ________________ -&At~2~2~2~2~2~~ ~~S~S~S~S~S~,~______________________
t tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA totransition high in the next ClKA cycle. lithe time between
the rising CLKA edge and rising CLKB edge is less than t sk2, then AFA may transition high one CLKB cycle later than shown.
NOTE A: FIF01 write (GSA = L, WIRA = H, MBA = L), FIF01 read (CSB = L, WIRS = H, MBS = l). Data in the FIF01 output register has been
read from the FIFO.

Figure 15. Timing for AFA When FIF011s Almost Full

I.- tsk2t -t!

ClKS I \ ( \'-_--'1,..-+1"'\Io.._--JY-1-"'"\ 12 \ I
tsu(EN)!..-.:::I I+- th(EN) I 1
ENS ~~~~~S~S~~~~~~~'~______~I __________________I __________ 1~

tpd(C-AF) 14-14- - - . t I tpd(C-AF) 14 ~

AFS [512 - (V2 + 1)] Words In FIF02 (512 - Y2) Words In FIF02

I
ClKA--./ \'-----'1 \
tsu(EN) ~
1-·-"'"'\ tth(EN)
/ \'----'/ '--
t tsk2 is the minimum time between a rising CLKB edge and a rising GLKA edge for AFB to transition high in the next GLKB cycle. lithe time between
the rising CLKB edge and rising GLKA edge is less than tsk2, then AFB may transition high one CLKA cycle later than shown.
NOTE A: FIF02 write (CSB = L, WIRB = L, MBB = L), FIF02 read (CSA = L, WIRA = L, MBA = L). Data in the FIF02 output register has been
read from the FIFO.

Figure 16. Timing for AFB When FIF021s Almost Full

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS, TeXAS 75265 11-127
SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

ClKB / \ I \~ __~I \ 1\/ \~___

tsu(EN) I~ th(EN) tsu(EN) d, th(EN) :
ENB _ _--I.I':;...:2;...:2J1 I '& %¥ 1

tsu(RM) ~ th(RM) I tsu(RM) ~ th(RM)

RTM _--";'--Lt~V'-fl? I ~ ';'S~-"l&""---I~I888&..ii..oIi...O~_ __
\:'I..:$\:O';.....
I I - 1
1 tSU(RML.'-+j4+I;. th(RM) I

RFM -------i-I------i---"I/:.../r..6J-4'
1 I
1
I
~~ I
I
1 1 I 1
ORB High 1 I 1 1
I I I I
~~~ ~~~ ~~~ ~~~
BO-B31 ---......,."W~O- - - * W1 * W2 * WO *--:"W~1-
Initiate Retransmit Mode Retransmit From End Retransmit
With WO as First Word Selected Position Mode

NOTE A: CSB= L. W/RB= H. MBB= L. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit.
Other enables are shown only to relate retransmit operations to the FIFOI output register.

Figure 17. FIF01 Retransmit Timing Showing Minimum Retransmit Length

ClKB / \ I
1
\ /1 \ ~2
1
\ ...._-J/ _-
\ .....
I 1
RTM High 1 1
1 1
-I l_th(RM) 1
tSu(RM)~11 1
RFM I!ZZ?lZ) t\\\\\\\ 1
1
I_I_-~.I- tpd(C.AE)
AEB _ _ _ _ _ _X1
_or_Fewer
__ Words
__ From
__ Empty
..;...;_ _ _ _ _ _ _ _--' (X1 + 1) or More Words From Empty

NOTE A: XI is the value loaded in the almost·full flag offset register.

Figure 18. AEB Maximum Latency When Retransmit Increases the Number of Stored Words Above X1

~TEXAS
INSTRUMENTS
11-128 POST OFFICE BOX 65530~ • DALLAS. TEXAS 75265
 SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

14- tsk1 t -+I

ClKA , /,...---+i'""\''-_.....J)''":'1-~' /2 ''-_.....J/ ''-_.....J/
1 tpd(C-IR) I---!
IRA FIF01 Filled to First RBtrans~lt Word Ir-O'="'n-e-o-r~M~0-re~F~I'="'FO'="'1~W~rlt-e~l-oc-a-tl~0-ns-
1 Available
1
ClKB ---1 \ /
1
\ / \ 1 ' ..._.....JI '-
tsu(RM) I~ -I' ~I th(RM)
RTM \\S\« .&<;xx8&
t tsk1 is the minimum time between a rising ClKB edge and a rising ClKA edge for IRA to transition high in the next ClKA cycle. lithe time between
the rising ClKB edge and rising ClKA edge is less than tsk1. then IRA may transition high one ClKA cycle later than shown.
Figure 19. IRA Timing From the End of Retransmit Mode When One or More
FIF01 Write Locations Are Available

14- tsk2t -+I

ClKA \ 1""---+1'""\\ )"":'1-~\ /2 ''-_.....JI ''-_.....J1
1 Ipd(C-AE) I---!
I r.;.st.;.R.;.Bt.;.ra.;.;.;.ns.;.m;.;;l.;.tW.;..;.or;.;d~_ _ _ _ _....1~------~---~------~---~~
-.:(5.;.1;.;2~-_Y;.;1.:..)o.;.r;.;M;.;.o.;.r.;.e.;.w;.;o.;.rd;.;s.;.p.;.a+Bt.;.F.;.l (V1+ 1) or More Write locations Available
1

elKB ---1 \ k
~I,
\ 1 \ 1 \ 1 '--
lsu(RM)I~ I ~I th(RM)
RTM ~~ is&QQs&.
t tsk2 is the minimum time between a rising ClKB edge and a rising ClKA edge for AFA to transition high in the next ClKA cycle. lithe time between
the rising ClKB edge and rising ClKA edge is less than tsk2. then AFA may transition high one ClKA cycle later than shown.
NOTE A: Y is the value loaded in the almost-full flag offset register.

Figure 20. AFA Timing From the End of Retransmit Mode When (Y1 + 1) or More
FIF01 Write Locations Are Available

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-129
SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

I '- I
' ....__...,,/
ClKA
~ th(EN)
tsu(EN) H ,'----'/ '-
------~~~I--------------------------------
I I
WiRA
VZlA2VlZ4f :W
MBA
I : I
ENA

AO-A31

ClKB I

WIRB vzm I I
I
I
I
j'\\"S\\\\;
I
MBB --_ _~----~/I
: II tsu(EN) ~ .~ th(EN) :
ENB I II Il?Z!) t\lo,S.;,.,S.S~:\_;-1____
~:
ten H
I I
1+ tdls ..j
BO-B31
FIF01 Output Register

Figure 21. Timing for Mail1 Register and MBF1 Flag

~ThXAS
INSTRUMENTS
11-130 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C- JUNE 1992 - REVISED SEPTEMBER 1995

I \ I \"" __..J/ \\... _ _---J/

ClKB

------~-~I-----------------
tsu(EN) H r- th(EN)
'--
I I
WIRB
ZZZZZZZVZZ4 1m
MBB

ENB
W/llIZZZ2Z{ I~
BO-B3t
~ I
ClKA I \ ....---.,1--'/ ----1
\ .... \. . ____
-------+--~\
IF tpd(C-MF) -..J r
...._____ _ _ _- ' ) - - - - - -
~I
tpd(C-MF) --./

I I
\""-----~I----------------------rl-------JI
1- I I I
WiRA "'2""2""2""7/1""l/.,",?) I I ~
I I I I
MBA _--_---+-1_...;...._ _,/1 I
I II t SU (EN)4------I1.--.j th(EN) I
ENA I II IlZlA :S:.0~~_i-1_____
t\;>,,:S:...
ten H
I 141 t
1+ tdls ..j
AO-A31 W1 (remains valid In mall2 re Ister after read)
FIF02 Output Register

Figure 22. Timing for Mail2 Register and MBF2 Flag

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-131
SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C-JUNE 1992 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Vecl ............................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vecl ........................................... ±50 mA
Continuous output current, 10 (VO = 0 to Vecl ............................................. ±50 mA
Continuous current through Vee or GND ................................................. ±400 mA
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current -4 rnA
IOL Low-level output current 8 rnA
TA Operating free-air temperature 0 70 ·e

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
VOH Vee=4.5 V, IOH =-4 rnA 2.4 V
VOL Vee=4.5 V, IOL=8 rnA 0.5 V
II Vee=5.5 V, VI =veeorO ±5 I!A
loz Vee = 5.5 V, Vo=Vee orO ±5 I!A
ICC Vee=5.5V, VI =Vee-0.2VorO 400 I!A
eSA=vIH AO-A31 0
eS9=VIH 90-931 0
Vee= 5.5 V, One input at 3.4 V,
t.lee§ eSA=vIL AO-A31 1 rnA
Other inputs at Vee or GND
eS9=v1L 90-931 1
All other inputs 1
ei VI =0, f = 1 MHz 4 pF
Co VO=O, f = 1 MHz 8 pF
:j:AII tYPical values are at Vee = 5 v, TA = 25·e.
§ This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or Vee.

~TEXAS
INSTRUMENTS
11-132 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 22)
'ACT3638-15 'ACT3638-20 ' ACT3638-30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency, ClKA or ClKB 66.7 50 33.4 MHz
tc Clock cycle time, ClKA or ClKB 15 20 30 ns
tw(ClKH) Pulse duration, ClKA and ClKB high 6 8 10 ns
tw~ClKl) Pulse duration, ClKA and ClKB low 6 8 10 ns
tsu(D) Setup time, AO- A31 before ClKAi and BO- B31 before ClKBi 4.5 5 6 ns
Setup time, CSA, W/RA, ENA, and MBA before ClKAi; CSB,
tsu(EN) 5 6 7 ns
W/RB, ENB, and MBB before ClKBi
tsu(RMl Setup time, RTM and RFM before ClKBi 6 6.5 7 ns
tsu(RS) Setup time, RST1 or RST2 low before ClKAi or ClKBit 5 6 7 ns
tsu(FS) Setup time, FSO and FSI before RSTI and RST2 high 7 8 9 ns
th(D) Hold time, AO-A31 after ClKAi and BO-B31 after ClKBi 0 0 0 ns
Hold time, CSA, W/RA, ENA, and MBA after ClKAi; CSB, W/RB,
th(EN) 0 0 0 ns
ENB, and MBB after ClKBi
th(RM) Hold time, RTM and RFM after ClKBi 0 0 0 ns
th(RSl Hold time, RSTI or RST2 low after ClKAi or ClKBit 4 4 5 ns
th(FS) Hold time, FSO and FSI after RST1 and RST2 high 2 3 3 ns
Skew time between ClKAi and ClKBi for ORA, ORB, IRA, and
ts kl+ 8 9 11 ns
IRB
Skew time between ClKAi and ClKBi for AEA, AEB, AFA, and
tsk2+ 12 16 20 ns
AFB
t Requirement to count the clock edge as one of at least four needed to reset a FIFO
+ Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and
ClKB cycle.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265 11-133
SN74ACT3638
512x32x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 1 through 22)
'ACT3638-15 'ACT3638-20 'ACT3638-30
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
ta Access time, CLKAi to AO-A31 and CLKBi to BO-B31 3 11 3 13 3 15 ns

tpd{C-IR) Propagation delay time, CLKAi to IRA and CLKBi to IRB 1 8 1 10 1 12 ns

tpdlC-ORl Propagation delay time, CLKAi to ORA and CLKBi to ORB 1 8 1 10 1 12 ns

tpd{C-R) Propagation delay time, CLKAi to RDVA and CLKBi to RDVB 1 8 1 10 1 12 ns
tpdIW-R) Propagation delay time, W/RA to RDVA and W/RB to RDVB 1 8 1 10 1 12 ns
tpd{C-AE) Propagation delay time, CLKA ito AEA and CLKBi to AEB 1 8 1 10 1 12 ns
tpdlC-AFl Propagation delay time, CLKAi to AFA and CLKBi to AFB 1 8 1 10 1 12 ns
Propagation delay time, CLKAi to MBF1 low or MBF2 high and
tpd(C-MF) 0 8 0 10 0 12 ns
CLKBi to MBF2 low or MBF1 high
Propagation delay time, CLKAito BO-B31t and CLKBi to
tpd(C-MR) 3 13.5 3 15 3 17 ns
AO-A3fl:
Propagation delay time, MBA to AO-A31 valid and MBB to
tpd(M-DV) 3 13 3 15 3 17 ns
BO-B31 valid
Propagation delay time, RST1 low to AEB low, AFA high, and
tpd(R-F) 1 15 1 20 1 30 ns
MBF1 high, and RST2 low to AEA low, AFB high, and MBF2 high
Enable time, CSA and W/RA low to AO-A31 active and CSB low
ten 2 12 2 13 2 14 ns
and W/RB high to BO-B31 active
Disable time, CSA or W/RA high to AO-A31 at high impedance
tdis 1 13 1 14 1 15 ns
and CSB high or W/RB low to BO-B31 at high impedance
..
tWnbng data to the mal11 register when the BO-B31 outputs are active and MBB IS high
:j: Writing data to the mail2 register when the AO-A31 outputs are active and MBA is high

~1ExAs
INSTRUMENTS
11-134 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228C- JUNE 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY

=
'data 112 'clock
TA=75°C
250 =
CL 0 pF +--+--+--+--t---7"-i

g
I
100

501------I#~---+--+-_+--+----1

O~~~~-~-~-~--L-~

o 10 20 30 40 50 60 70

'clock - Clock Frequency - MHz

Figure 23

calculating power dissipation

The ICC(f) current for the graph in Figure 23 was taken while simultaneously reading and writing a FIFO on the
SN74ACT3638 with ClKA and ClKB set to fclock' All data inputs and data outputs change state during each
clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to
a zero-capacitance load. Once the capacitive load per data-output channel and the number of SN74ACT3638
inputs driven by TIL high levels are known, the power dissipation can be calculated with the equation below.
With ICC(f) taken from Figure 23, the maximum power dissipation (Pr) of the SN74ACT3638 can be calculated
by:
PT = VCC x [ICC(f) + (N x alcc x dc)] + L(CL x VCc2 x fO>
where:
N = number of inputs driven by TIL levels
alcc = increase in power supply current for each input at a TIL high level
dc = duty cycle of inputs at a TIL high level of 3.4 V
CL = output capacitive load
fo = switching frequency of an output
When no reads or writes are occurring on the SN74ACT3638, the power dissipated by a single clock (ClKA
or ClKB) input running at frequency fclock is calculated by:
Pr = VCC x fclock x 0.184 mA/MHz

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-135
SN74ACT3638
512 x 32 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

5V

1.1 kn
From Output
Under Test --4J..-----....
680n :;::r:: 30 pF
(see Note A)

LOAD CIRCUIT

Timing 1. 3V Hlgh-Level~~.~- 3V
Input ---.J4 ~ ~ ___ GND Input ----.If ,..... ~ GND

tsu~th 14- tw ---.I

I 1
Data, ~~::- 3V
~
I 3V
Enable - - - " 1.5 V ~ Low-Level 1.5 V 1.5 V
Input GND Input _ _ _ _ GND .

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

3V
Output
Enable --'i.L1.5 V GND
-+i i4-IPLZ
~3V
I I ------;.~
Low-Level
Output -~lf-lI
~tPZH
VOL
Input
-A
tpd
1•5V

--l4---+I
\11-5-; - -
.
1+------+1- tpd
3V
GND

VOH _ _~I_- VOH

High-Level
Output I I
I I ~OV
In-Phase
Output
_ _--J.
11.5V ~~
1.5V
VOL
-+i l4-tPHZ

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 24. Load Circuit and Voltage Waveforms

~1ExAs
INSTRUMENTS
11-136 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3632
512 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C - JUNE 1992 - REVISED

• Free-Running ClKA and ClKB Can Be • IRB, ORB, AEB, and AFB Flags
Asynchronous or Coincident Synchronized by ClKB
• Two Independent 512 x 36 Clocked FIFOs • low-Power O.8-Mlcron Advanced CMOS
Buffering Data In Opposite Directions Technology
• Mailbox-Bypass Register for Each FIFO • Supports Clock Frequencies up to 67 MHz
• Programmable Almost-Full and • Fast Access Times of 11 ns
Almost-Empty Flags • Pin-to-Pln Compatible With the
• Microprocessor Interface Control logic SN74ACT3622 and SN74ACT3642
• IRA, ORA, AEA, and AFA Flags • Available in Space-Saving 120-Pin Thin
Synchronized by ClKA Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages

PCB PACKAGE
(TOP VIEW)

O~~~~~~MN~O~~~~~~MN~O~~~~~~MN~
~~~~~~~~~~~~~~~~~~~~~~m~mmmmmm
A35 90 B35
A34 89 B34
A33 88 B33
A32 87 B32
Vee 86 GND
A31 85 B31
A30 84 B30
GND 83 B29
A29 82 B28
A28 81 B27
A27 80 B26
A26 79 Vee
A25 78 B25
A24 B24
A23 GND
GND B23
A22 B22
Vee B21
A21 B20
A20 B19
A19 B18
A18 GND
GND B17
A17 B16
A16 Vee
A15 B15
A14 B14
A13 B13
Vee B12
A12 61 GND

Copyright © 1995. Texas Instruments Incorporated

~~~:~:O~1:S=r::~SI~~!r:::~:-:::m=
standard warranty. Production procesBlng dOlI not necessarily Include
testing of all paramaters. ~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-137
SN74ACT3632
512x36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

PQPACKAGEt
(TOP VIEW)

NC NC
835 NC
834 A35
833 A34
832 A33
GND A32
831 VCC
830 A31
829 A30
828 GND
827 A29
826 A28
VCC A27
825 A26
824 A25
GND A24
823 A23
822 GND
821 A22
820 VCC
819 A21
818 A20
GND A19
817 A18
816 GND
VCC A17
815 A16
814 A15
813 A14
812 A13
GND VCC
NC A12
NC NC

NC - No internal connection
t Uses Yamaichi socket IC51-1324-828

~TEXAS
INSTRUMENTS
11-138 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3632
512x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

description
The SN74ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock
frequencies up to 67 MHz and has read access times as fast as 11 ns. Two independent 512 x 36 dual-port
SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and
full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number
of words are stored in memory. Communication between each port can bypass the FI FOs via two 36-bit mailbox
registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can
be used in parallel to create wider data paths.
The SN74ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the
port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag
of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the
almost-full and almost-empty flags of both FIFOs can be programmed from port A.
The SN74ACT3632 is characterized for operation from O°C to 70°C.
For more information on this device family, see the application reports FIFO Mailbox-Bypass Registers: Using
Bypass Registers to Initialize DMA Control and Interfacing TI Clocked FIFOs With TI Floating-Point Digital
Signal Processors in the 1996 High-Performance FIFO Memories Designer's Handbook, literature number
SCAA012A.

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS, TeXAS 75265 11-139
SN74ACT3632
512 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

functional block diagram

Ir------------------------------ MBF1
Mall1 1 4-----------------,
.......
CLKA - -
.... I Reg Isler I
CSA --Port-A
WiRA -- Control r-~-----------;;l~
ENA - - Logic I-- r--
MBA --
r--- ~~
.j.1 i~ fL.~
I.~...
512x36
SRAM .. i I
RST1 - -
FIF01,
Mall1 t++++-++!,'" ~ a~ 36
Reset 1- ~ "--I
Logic
I
I I Write
I Pointer
II Read
Pointer
I
I
I
I
1 ttl
IRA i Status-Flag I I - - - - ; I - - I + - H - t - - - - - ORB
AFA - -........--++-+-t-H--11-------t Logic 1 AEB
1L _AF~
_ _ _ _ _ _ _ ~----_--J
I
36
Programmable-
FSO - - - - - + + - + - t - I - - - - - - - I Flag
FS1 ------++-+-t-I---..-----I
AO_A35 ____~+-_t1H-rt___9::,::::~;O;ff;se;t~Re~g;ls;te;rs~___ .___ _
FIF02 --;-r
ORA ---4----+++-+-I-~I-----I Status-Flag
AEA - - -....--rt111~~r----t-r~LO~9~IC~r1----------tttillj--------
I + +
II
._---1I ---...-t1 Read
I Pointer II Write
Pointer
..
1 ----,
I
I

~
IT ji
r-
~ ~
I ~ 512x36 ~

~L==___________
"i-+ SRAM-+i

o £
~ __
Mall2 I......I-------I-----i
Register I
MBF2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....JI

~TEXAS
INSTRUMENTS
11-140 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3632
512 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME
AO-A35 1/0 Port-A data. The 36-bit bidirectional data port for side A.
0 Port-A almost-empty flag. Programmable almost-empty flag synchronized to ClKA. AEA is low when the number of
AEA
(portA) words in FIF02 is less than or equal to the value in the almost-empty A offset register, X2.
0 Port-B almost-empty flag. Programmable almost-empty flag synchronized to ClKB. AEB is low when the number of
AEB
(port B) words in FIF01 is less than or equal to the value in the almost-empty B offset register, X1.
0 Port-A almost-full flag. Programmable almost-full flag synchronized to ClKA. AFA is low when the number of empty
AFA
(portA) locations in FIF01 is less than or equal to the value in the almost-full A offset register, Y1.
0 Port-B almost-full flag. Programmable almost-full flag synchronized to ClKS. AFS is low when the number of empty
AFB
(port B) locations in FIF02 is less than or equal to the value in the almost-full B offset register, Y2.
BO-B35 1/0 Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
ClKA I
or coincident to ClKB. IRA, ORA, AFA, and AEA are all synchronized to the low-to-high transition of ClKA.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
ClKB I
or coincident to ClKA. IRB, ORB, AFB, and AEB are synchronized to the low-to-high transition of ClKB.
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
CSA I
AO-A35 outputs aTe in the high-impedance state when CSA is high.
Port-S chip select. CSB must be low·to enable a low-ta-high transition of ClKB to read or write data on port B. The
CSB I
BO-B35 outputs are in the high-impedance state when CSB is high.
ENA I Port-A enable. ENA must be high to enable a low-to-high transition of ClKA to read or write data on port A.
ENB I Port-B enable. ENB must be high to enable a low-ta-high transition of ClKS to read or write data on port B.
Flag-offset selects. The low-ta-high transition of a FIFO reset input latches the values of FSO and FS1. If either FSO
or FS1 is high when a reset input goes high, one of three preset values is selected as the offset for the FIFO almost-full
FS1, FSO I
and almost-empty flags. If both FIFOs are reset simultaneously and both FSO and FS 1 are low when RST1 and RST2
go high, the first four writes to FIF01 program the almost-full and almost-empty offsets for both FIFOs.
Input-ready flag. IRA is synchronized to the low-ta-high transition of ClKA. When IRA is low, FIF01 is full and writes
0
IRA to its array are disabled. IRA is set low when FI F01 is reset and is set high on the second low-to-high transition of ClKA
(portA)
after reset.
Input-ready flag. IRB is synchronized to the low-ta-high transition of ClKB. When IRB is low, FIF02 is full and writes
0
IRB to its array are disabled. IRB is set low when FIF02 is reset and is set high on the second low-to-high transition of elKB
(port B)
after reset.
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
MBA I AO-A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects
FIF02 output-register data for output.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
MBB I BO-B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
FIF01 output-register data for output.
Mail1 register flag. MBF1 is set low by the low-ta-high transition of ClKA that writes data to the mail1 register. Writes
MBF1 0 to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of ClKB when a port-B
read is selected and MBB is high. MBF1 is sethigh when FIF01 is reset.
Mail2 register flag. MBF2 is set low by the low-ta-high transition of ClKB that writes data to the mail2 register. Writes
MBF2 0 to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of ClKA when a port-A
read is selected and MBA is high. MBF2 is also set high when FIF02 is reset.
Output-ready flag. ORA is synchronized to the low-to-high transition of ClKA. When ORA is low, FIF02 is empty and
0 reads from its memory are disabled. Ready data is present on the output register of FIF02 when ORA is high. ORA
ORA
(portA) is forced low when FIF02 is reset and goes high on the third low-to-high transition of ClKA after a word is loaded to
empty memory.

-!II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-141
SN74ACT3632
512 x36x2
CLOC~ED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

Terminal Functions (Continued)

TERMINAL
110 DESCRIPTION
NAME
Output-ready flag. ORB is synchronized to the low-ta-hlgh transition of ClKB. When ORB is low, FIF01 is empty and
0 reads from its memory are disabled. Ready data is present on the output register of FIF01 when ORB Is high. ORB
ORB
(port B) is forced low when FIF01 Is reset and goes high on the third low-to-high trensition of ClKB after a word is loaded to
empty memory.
FiF01 reset. To reset FIF01, four low-ta-high trensitions of ClKA and four low-to-high transitions of ClKB must ooeur
RST1 I while RST1 is low. The low-to-high transition of RST1 latches the status of FSO and FS1 for AFA and AEB offset
selection. FIF01 must be reset upon power up before data is written to its RAM.
FIF02 reset. To reset FIF02, four low-ta-hlgh transitions of ClKA and four low-ta-high transitions of ClKB must ooeur
RS'f2 I while RST2 is low. The low-ta-high transition of RST21atches the status of FSO and FS1 for AFB and AEA offset
selection. FIFOl! must be reset upon power up before data is written to its RAM.
Port-A write/read select. Po. high on W/RA selects a write operation and a low selects a raad operation on port A for a
WiRA I
low-ta-high transition of ClKA. The AO-A35 outputs are in the high-impedance state when WiRA is high.
Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a
W/RB I
low-ta-high transition of ClKB. The BO-B35 outputs are in the high-impedance state when W/RB is low.

detailed description
reset
The FIFO memories of the SN74ACT3632 are reset separately by taking their reset (RST1, RST2) inputs low
for at least four port-A clock (ClKA) and four port-B clock (ClKB) low-to-high transitions. The reset inputs can
switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pOinters and forces the
input-ready flag (IRA, IRB) low, the output-ready flag (ORA, ORB) low, the almost-empty flag (AEA, AEB) low,
and the almost-full flag (AFA, AFB) high. Resetting a FIFO also forces the mailbox flag (MBF1, MBF2) of the
parallel mailbox register high. After a FIFO is reset, its input-ready flag is set high after two clock cycles to begin
normal operation. A FIFO must be reset after power up before data is written to its memory.
A low-to-high transition on a FIFO reset (RSn, RST2) input latches the value of the flag~select (FSQ, FS1)
inputs for choosing the almost-full and almost-empty offset programming method.
almost-empty flag and almost-full flag offset programming
Four registers in the SN74ACT3632 are used to hold the offset values for the almost-empty and almost-full flags.
The port-B almost-empty flag (AEB) offset register is labeled X1 and the port-A almost-empty flag (AEA) offset
register is labeled X2. The port-A almost-full flag (AFA) offset register is labeled Y1 and the port-B almost-full
flag (AFB) offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The
offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from
port A (see Table 1).
Table 1. Flag Programming
FSi FSO RSTi RST2 Xi AND Yi REGISTERSt X2 AND Y2 REGISTERs*
H H i X 64 X
H H X i X 64
H l i X 16 X
H L X i X 16
L H i X 8 X
L H X i X 8
l l i i Programmed from port A Programmed from port A
t Xl register holds the offset for AEB; Yl register holds the offset for AFA.
:I: X2 register holds the offset for AEA; Y2 register holds the offset for AFB.

~1ExAs
INSTRUMENTS
11-142 POST OFFICE BOX 855303 • DALlAS. TEXAS 75265
 SN74ACT3632
512x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C-JUNE 1992 - REVISED SEPTEMBER 1995

almost-empty flag and almost-full flag offset programming (continued)

To load the almost-empty flag and almost-full flag offset registers of a FIFO with one of the three preset values
listed in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset
input. For example, to load the preset value of 64 into X1 and Y1, FSO and FS1 must be high when FIF01 reset
(RST1) returns high. Flag-offset registers associated with FIF02 are loaded with one of the preset values in the
same way with FIF02 reset (RST2). When using one of the preset values for the flag offsets, the FIFOs can
be reset simultaneously or at different times.
To program the X1, X2, Y1, and Y2 registers from port A, both FIFOs should be reset simultaneously with FSO
and FS1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes
to FIF01 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. Each offset register
uses port-A (AS-AO) inputs, with AS as the most significant bit. Each register value can be programmed from
1 to 50S. After all the offset registers are programmed from port A, the port-B input-ready flag (IRB) is set high
and both FIFOs begin normal operation.
FIFO write/read operation
The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (WiRA). The AO-A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The AO-A35 outputs are active when both CSA and W/RA are low.
Data is loaded into FIF01 from the AO-A35 inputs on a low-to-high transition of ClKA when CSA is low, W/RA
is high, ENA is high, MBA is low, and IRA is high. Data is read from FIF02 to the AO-A35 outputs by a low-to-high
transition of ClKA when CSA is low, W/RA is low, ENA is high, MBA is low, and ORA is high (see Table 2). FIFO
reads and writes on port A are independent of any concurrent port-B operation.

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA AO-A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L i In high-impedance state FIFOI write
L H H H i In high-impedance state Maill write
L L L L X Active, FIF02 output register None
L L H L i Active, FIF02 output register FIF02 read
L L L H X Active, mail2 register None
L L H H i Active, mail2 register Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A with the exception that the port-B write/read select
(W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (BO-B35) outputs is
controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The BO-B35 outputs are
in the high-impedance state when either CSB is high or W/RB is low. The BO-B35 outputs are active when CSB
is low and W/RB is high.
Data is loaded into FIF02 from the BO-B35 inputs on a low-to-high transition of ClKB when CSB is low, W/RB
is low, ENB is high, MBB is low, and IRB is high. Data is read from FIF01 to the BO-B35 outputs by a low-to-high
transition of ClKB when CSB is low, W/RB is high, ENB is high, MBB is low, and ORB is high (see Table 3). FIFO
reads and writes on port B are independent of any concurrent port-A operation.

~TEXAS
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SN74ACT3632
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

CSB W/RB ENB MBB ClKB BO-B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L L L X X In high-impedance state None
L L H L i In high-impedance state FIF02write
L L H H i In high-impedance state Mail2write
L H L L X Active, FIFOl output register None
L H H L i Active, FIFOl output register FIFOl read
L H L H X Active, maill register None
L H H H i Active, maill register Maiil read (setMBFl high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select may change states during the
setup- and hold-time window of the cycle.
When a FIFO output-ready flag is low, the next data word is sent to the FIFO output register automatically by
the low-to-high transition of the port clock that sets the output-ready flag high. When the output-ready flag is
high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the
port's chip select, write/read select, enable, and mailbox select.
synchronized FIFO flags
Each FiFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve
flag-signal reliability by reducing the probability of metastable events when ClKA and ClKB operate
asynchronously to one another (see the application report Metastability Performance of Clocked F/FOs in the
1996 High-Performance FIFO Memories Data Book, literature number SCADCi03C). ORA, AEA, IRA, and AFA
are synchronized to ClKA. ORB, AEB, IRB, and AFB are synchronized to ClKB. Tables 4 and 5 show the
relationship of each port flag to FIF01 and FIF02.

Table 4. FIF01 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS TOClKB TOCLKA
IN FIF01f*
ORB AEB AFA IRA
0 L L H H
1 to Xl H L H H
(Xl + 1) to [512 - (yl + 1)1 H H H H
(512-Yl)t0511 H H L H
512 H H L L
t Xl IS the almost-empty offset for FIFOl used by AEB. Yl IS the almost-full
offset for FIFOl used by AFA. Both Xl and Yl are selected during a reset of
FIFOl or programmed from port A.
:j:When a word loaded to an empty FIFO is shifted to the output register, its
previous FIFO memory location is free.

~1ExAs
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 SN74ACT3632
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

synchronized FIFO flags (continued)

Table 5. FIF02 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS TOCLKA TOCLKB
IN FIF02f*
ORA AEA AFB IRB
0 L L H H
1 toX2 H L H H
(X2 + 1) to [512 - (Y2 + 1)) H H H H
(512 - Y2) to 511 H H L H
512 H H L L
t X2 IS the almost-empty offset for FIF02 used by AEA. Y2 IS the almost-full
offset for FIF02 used by AFB. Both X2 and Y2 are selected during a reset
of FIF02 or programmed from port A.
=1= When a word loaded to an empty FIFO is shifted to the output register, its

previous FIFO memory location is free.

output-ready flags (ORA, ORS)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the
output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low, the
previous data word is present in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pOinter is incremented each time a new word is clocked to its output register. The state machine
that controls an output-ready flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is empty, empty+ 1, or empty+2. From the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of the output-ready flag synchronizing clock; therefore,
an output-ready flag is low if a word in memory is the next data to be sent to the FI FO output register and three
cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written.
The output-ready flag of the FIFO remains low until the third low-to-high transition of the synchronizing clock
occurs, simultaneously forcing the output-ready flag high and shifting the word to the FIFO output register.
A low-to-high transition on an output-ready flag synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 7 and 8).
input-ready flags (IRA, IRS)
The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array. When the input-ready
flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when
the input-ready flag is low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pOinter is incremented. The state machine that controls an
input-ready flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM
status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready
to be written in a minimum of two cycles of the input-ready flag synchronizing clock; therefore, an input-ready
flag is low if less than two cycles of the input-ready flag synchronizing clock have elapsed since the next memory
write location has been read. The second low-to-high transition on the input-ready flag synchronizing clock after
the read sets the input-ready flag high.
A low-to-high transition on an input-ready flag synchronizing clock begins the first synchronization cycle of a
read if the clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 9 and 10).

~TEXAS
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C-JUNE 1992 - REVISED SEPTEMBER 1995

almost-empty flags (AEA, AEB)

The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state
machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty state is
defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset
values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset
programming). An almost-empty flag is low when its FIFO contains X or less words and is high when its FIFO
contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory.
Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for its
almost-empty flag to reflect the new level of fill. Therefore, the almost-empty flag of a FIFO containing (X + 1)
or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled
the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of its
synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an
almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time ts k2, or greater,
after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figures 11 and 12).
almost-full flags (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine
that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the contents
of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FI FO reset
or programmed from port A (see almost-empty flag and almost-full flag offset programming). An almost-full flag
is low when its FIFO contains (512 - Y) or more words and is high when its FIFO contains [512 - (Y + 1)] or less
words. A data word is present in the FIFO output register has been read from memory.
Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for its
almost-full flag to reflect the new level of fill. Therefore, the almost-full flag of a FIFO containing [512 - (Y + 1)]
or less words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced
the number of words in memory to [512 - (Y + 1)]. An almost-full flag is set high by the second low-to-high
transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to
[512 - (Y + 1)]. A low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization
cycle if it occurs at time ts k2, or greater, after the read that reduces the number of words in memory to
[512 - (Y + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see
Figures 13 and 14).
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port-data-transfer operation. A low-to-high transition on ClKA writes AO-A35 data to the mail1 register
when a port-A write is selected by CSA, WiRA, and ENA and with MBA high. A low-to-high transition on ClKB
writes BO-B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and with MBB
high. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail
register are ignored while the mail flag is low.
When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port
mailbox select input is low and from the mail register when the port-mailbox select input is high. The mail1
register flag (MBF1) is set high by a low-to-high transition on ClKB when a port-B read is selected by CSB,
W/RB, and ENB and with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on
ClKA when a port-A read is selected by CSA, WiRA, and ENA and with MBA high. The data in a mail register
remains intact after it is read and changes only when new data is written to the register.

~TEXAS
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 SN74ACT3632
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

ClKA

--toI I.- th(RS)

ClKB
I I It
-.I ~ tsu(RS) I I ~ h(FS) I
_ _ _",,-,I I I tsu(FS) :---1[ [ I
RST1 \. I I .I I I
I [ I
FS1, FSO

~MI ~
IRA ~\\~\\~~ I I
I tpd(C-OR) ~
ORB~
tpd(R-F) ~
AEB\\\~~
tpd(R-F) ~
AFA~
tpd(R-F)~

Figure 1. FIF01 Reset Loading X1 and Y1 With a Preset Value of Eightt

t FIF02 is reset in the same manner to load X2 and Y2 with a preset value.

ClKA

FS1,FSO

IRA

ENA I/T/T///////////7///1 ~ ~ '<&8&' ~~"'~'"

AO-A35
AF~~set AE':x~t AFB(Y~~..t AE~,g~'" I Fir•• Word'o FIF01

ClKB
1 I 2
tpd(C-IR) ~r
IRB

t tsk1 is the minimum time between the rising ClKA edge and a rising ClKB edge for IRB to transition high in the next cycle. If the time between
the rising edge of ClKA and rising edge of ClKB is less than t sk1, IRB may transition high one cycle later than shown.
NOTE A: CSA = l, WiRA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values After Reset

~TEXAS
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SCAS224C-JUNE 1992 - REVISED SEPTEMBER 1995

I~ Ie ~I

~ Iw(ClKH) 1- Iw(ClKl) ...J

ClKA 1 '\ rI
\ y
I
I
\ ( '--
I
IRA
Isu(EN) I. ~I~~ Ih(EN)
I
I
I
~ ~!~e
CSA
I I
Isu(EN) ~ I
I
WiRA
?ZI?flI/Z/lZ{
Isu(EN) I~
IF
~I. ~ Ih(EN)
I
I
MBA I I

ENA

AO-A35
Isu(O) I. + ~ Ih(O)
iIIo Operalron i88888&$8
t Written to FIFOI
Figure 3. Port-A Write-Cycle Timing for FIF01

I~

~ Iw(ClKH) -+
Ie
tw(ClKl)
~I

...J
ClKB 1 '\ rI
\ y
I
I
\\""'--......1[(
I
'--
IRB
I I
I
Isu(EN) 14 ~I. ~ Ih(EN) I I
I I
eSB
Isu(EN) ~
~ I-
~I. ~ Ih(EN)
I
I
II
I I
WIRB
Z\\\\\\\\\\~ I- I I I??ZZ2ZZZ2
Isu(EN) ~ tj~ ~ Ih(EN) I
I
MBB
ISU(E:~
I
~ r Ih(EN) IsU(EN) ~ 1- Ih(EN)
ENB

BO-B35
2ZZZ7??lZlZi
Isu(O) I~ + I~
~ Ih(O)
%\\\\\M V'"'Z'"'Z'"'Z'"'i-:'"'Z'"'Z'"'Z'"'/-

'No Operation QM&$($Q(

t Written to FIF02
Figure 4. Port-B Write-Cycle Timing for FIF02

~TEXAS
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 SN74ACT3632
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CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

14 te -,
~ tw(ClKH) . . . tw(ClKl) -.I
Y { } ( '--
, \ \
"
ClKA
, ,
, , ,
ORA , , ,
, , ,
, , ,, I
CSA , ,
, , ,
, , ,, RllZ?lllZ
W/RA , ,
~ tsu(EN) ,
MBA

t Read from FIF02

Figure 5. Port·A Read·Cycle Timing for FIF02

'4 Ie -,
i+- tw(ClKH) ...I+- tw(ClKl) -.I
Y { }, '--
\ ( \
",
ClKB
, ,,
ORB
,
, ,,
, I ,1
1
~ ,1 I
CSB 1

I
,
1 1
1
1
W/RB
2222{ 1
I 1 ~
MBB
H tsu(EN)
1
,
1

1
I+- th(EN) tsu(EN) ,+--+I+:l th(EN) tsu(EN) I+---'....! th(EN)
ENB 1 1
tpd(M-OV) , 1 1 No
14

-~
-,
bta~ t Operation j...! tdls

*
ten 14 ta -.IX 1
BO-B35 W2t W3t j
WI
t Read from FIF01'
Figure 6. Port-B Read·Cycle Timing for FIF01

~TEXAS
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CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

ClKA

CSA ~lo~w~ ____ ~ ______ I _________________________________________________

~I

I I
WiRA High ~ !
tsu(EN) i -+' I.- th(EN)
MBA ~\\Li tl7"z-rzrZ:;;':27-:2"-:?/"-:/:'"'(':'"'/:""'%""'Z7%7%7%7%7"%7"2"7"%"7"Z:>"":2"-:V"-:/:'"'/:'"'/:""'7227%7%7%7"%"7"/:"7"%"7"%:>"":%"-:V"-:/:'"'/:'"'/:""'2""'27%7:<:727";
tSU(EN? /4-- th(EN)
ENA mzz;; i ""I..:~..,;:~..,;:~"T~~:\~--------------------
I I
IRA Hlghit-/ I
AO-A35
~ tw(ClKH) -, j+- I tw(ClKl)
ClKB 1 2 3
tpd(C-OR) 14-1~--~ ,..---I!:::::~
oRB ________~O~ld~D~a~m~ln~F~IF~O~1~O~u~tp~ut~R~~~I~st~e~r________~I-----' ~____________

CSB ~lo~w~________________________________~I--------_r-------------------
I
I
W/RB High I I
MBB low
I
I J I

7I
tsu7N~
..0-
I- th(EN)

BO-B35 _____________0~I~d~D~at~a~ln~F~IF~O~1~O~Ut~pu~t~R~e9=1~~=er__________~*----------~W~1~--------
t tsk1 is the minimum time between a rising ClKA edge and a rising ClKB edge for ORB to transition high and to clock the next word to the FIF01
output register in three ClKB cycles. If the time between the rising ClKA edge and rising ClKB edge is less than tsk1. the transition of ORB high
and load of the first word to the output register may occur one ClKB cycle later than shown.

Figure 7. ORB-Flag Timing and Flrst-Data-Word Fallthrough When FIF01 Is Empty

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SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

ClKB

CSB_l~O~W~____~I
I
______ ________________________________________________
~

WIRB low I
I

IRB High tsu(D) H I

I+- th(D)
BO-B35 W1
tsk1 t !4-----!1 1+----+1 te
tW(ClKH)"1 J4- I tw(ClKl)
ClKA

ENA m?ZZZ/!2ZZZ7/!?ZZ/ZZlZlfll/2ZC2ZC2
!.-ta - '
AO-A35----------~O~ld~Dm~a~l~n~F~IF~02~O~u~tP-u~t~Re-9~Is~te-r--------~--*----------~W~1----------

t tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition high and to clock the next word to the FIF02
output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tsk1. the transition of ORA high
and load of the first word to the output register may occur one CLKA cycle later than shown.

Figure 8. ORA-Flag Timing and First-Data-Word Fallthrough When FIF02 Is Empty

~TEXAS
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I.-- te - - - '
I. ~4 ~I
tw(CLKH)
CLKB I\.I
I
tw(CLKL)
,\-_--J1 ,\-_--J1 ,'----
CSB ~Lo~w~ _________I ___________________________________________________
I~

I
WIRB High I
MBB ~Lo~w~ ____ ~ ___I ___________________________________________________
I~

ENB
Isu(ENJ
I/ZZ/J14 I ':L
~I .. Ih(EN)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
''110.:>:.$.$~&

ORB High I
Next Word From FIFO!

jf- Iski t --.114-14_ _ te ----..I

tw(CLKH) joI ~ ~ tw(CLKL)
CLKA ~\-_--Jlr----.., )1 " 12 ',-_~' '~I...._-'r---
tpd(C-IR) I..
IRA _ _ _ _ _ _ _ _F...;,IF...;.O...;.i...;,F..;;U..;.II________________

CSA Low
.....I1~ I.
:
1
,"-------
tpd(C-IR)

~~---------------------------~I-----------
WiRA High 1

ENA

AO-A35
ToFIFOi

t tsk1 is the minimum time between a rising elKS edge and a rising elKA edge for IRA to transition high in the next elKA cycle. lithe time between
the rising elKS edge and rising elKA edge is less than tsk1. IRA may transition high one elKA cycle later than shown.

Figure 9. IRA-Flag Timing and First Available Write When FIF01 Is Full

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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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l.--- Ie _____

Iw(CLKH) I. .I. ~I Iw(CLKL)

I I 1
CLKA I \ 1
I \ / \ / \ / \
CSA Low
1
1
1
Low
W/RA 1
1
MBA Low 1
Isu(EN) I.. ~:.. ~(EN)
ENA
tI?l21 10s\$\
I
ORA High 1
I..- la--.!
I
Next Word From FIF02

jf- Isk1 t --.114-1'1-- Ie -....I

Iw(CLKH) J4 ~ ~ Iw(CLKL)
CLKB \.~_-.JI"'---'\
Ipd(C-IR) I.
11
~I
'l /2 \I...-_~I ''-_....Jr-
~I Ipd(C-IR)
IRB ______________F_I_FO_2_F_u_II____________________~1 :I.
\'------
CSB Low 1
~~---------------------------------------------------~I-------------------
W/RB ~Lo~w____________________________________~____~_+I~----------------
Isu(EN) ~ Ih(EN)
MBB ~$~$~$~$~$~$~$-:-~-:-:--..:~~~:--..:~$~$~$:""I::z::~$~$~$~$~$~0~$-:-$-:-~~\.:~\.:~$~$:""I:$~$~$~$~$~$~$~S1 1 ~--?2~2-72"7"2"7":;:.,.2.,.2~2~2:O-:V:O-::/..-.::/..-:
Isu(EN) ~~ Ih(EN)
ENB

BO-B35

t tsk1 is the minimum time between a rising ClKA edge and a rising ClKB edge lor IRB to transition high in the next CLKB cycle. lithe time between
the rising ClKA edge and rising ClKB edge is less than tsk1. IRB may transition high one ClKB cycle later than shown.

Figure 10. IRB-Flag Timing and First Available Write When FIF021s Full

-!II TEXAS
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CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
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ClKA

ENA

'--_ _; 2
ClKB
~ tpd(C-AE) "" tpd{C-AE) It ~
AEB Xl Words In FIFOl Y (Xl + 1) Words In FIFO~ '-
14- th(EN) tsu(EN) H
ENB ________________________________________"tZ~2~2~?~?~?J~ ~~

t tsk2 is the minimum time between a rising ClKA edge and a rising ClKB edge for AEB to transition high in the next ClKB cycle.lfthetime between
the rising ClKA edge and rising ClKB edge is less than tsk2. AEB may transttion high one ClKB cycle later than shown.
NOTE A: FIF01 write (CSA = l. WiRA = H. MBA = l). FIF01 read (CSB = l. W/RB = H. MBB = l). Data in the FIF01 output register has been
read from the FIFO.

Figure 11. Timing for AEB When FIF01 Is Almost Empty

ClKB

ENB

ClKA
-'t---~tj tpd(C-AE) !.. ~
AEA X2 Words In FIF02 Y (X2 + 1) Words In FIFO~ "-
tSU(EN)~ I4- t h(EN)
ENA ________________________________________~I/~?~?~~~?~A~~ ~
t tsk2 is the minimum time between a rising ClKB edge and a rising ClKA edge for AEA to transition high in the next ClKA cycle. lithe time between
the rising ClKB edge and rising ClKA edge is less than tsk2. AEA may transition high one ClKA cycle later than shown.
NOTE A: FIF02 write (CSB = L. W/RB = l. MBB = l). FIF02 read (CSA = L. WiRA = l. MBA = l). Data in the FIF02 output register has been
read from the FIFO.

Figure 12. Timing for AEA When FIF021s Almost Empty

~ThxAS
INSTRUMENTS
11-154 POST OFFice BOX 655303 • DALLAS. TeXAS 75265
 SN74ACT3632
512 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C-JUNE 1992-REVISEDSEPTEMBER 1995

~tsk2t ~
1
CLKA/ , ( ,
I 1 \ Y1 \ 12 \ I
taU(EN)~ I+- th(EN) 1 1
ENA 1lT~~ 1
1
1
1
tpd(C-AF) 14 I tpd(C-AF) I. ~
AFA [512 - (Vi + 1)) Words In FIF01 (512 - Vi) Words In FIF01

1-~\ ' ....__1

CLKB----1
' ....---11 \
tSU(EN)~ 14- th(EN)
I '---
ENB ____________________~~~~?~2~2~2~z~~ ~~~$.$.$~$~~~~\~__________________________
t tsk2ls the minimum time between a rising CLKA edge and a rising CLKB edge for AFA totransition high in the next CLKA cycle.lfthetime between
the rising CLKA edge and rising CLKB edge Is less than tsk2, AFA may transition high one CLKB cycle later than shown.
NOTE A: FIF01 write (CSA ~ L, W/RA =H, MBA - L), FIF01 read (CSB =L, W/RB =H, MBB =L). Data in the FIF01 output register has been
read from the FIFO.

Figure 13. Timing for AFA When FIF01 Is Almost Full

~tsk2t ~
CLKB / \
tau(EN)
(
~ I+- th(EN)
,'----1,,.--1-:""''-_--'y~1-...,\
1
12
:
' ....._...JI
ENB IT!l!fll~ 1 1
tpd(C-AF) 14 tpd(C-AF) ,.I.---tt-t
AFB [512 - (V2 + 1)) Words In FIF02 11-----
CLKA----1
''-_--II \
tsu(EN)
1 \
j....:::i 14- th(EN)
I ''-_--'I '---
ENA _ _ _ _ _ _ _ _ _....t~2~2~z~z~z~~~~ ~~$~~~$~$~~~~~~____________
t tsk2 isthe minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition high in the next CLKB cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tsk2, AFB may transition high one CLKA cycle later than shown.
NOTE A: FIF02 write (CSB - L, W/RB= L, MaB = L), FIF02 read (CSA =L, W/RA =L, MBA =L). Data in the FIF02 output register has been
read from the FIFO.

Figure 14. Timing for AFB When FIF02 Is Almost Full

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-155
SN74ACT3632
512x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C-JUNE 1992 - REVISED SEPTEMBER 1995

ClKA I , I ,I...-_--J/ 'I...__......J/

Isu(EN) ~ ~ Ih(EN)
------~~~I~--------------------
1 1
WiRA //ZZZZZZZI!I{ 1m
MBA

ENA
/?ZZZVZZZZ4 I. .
AO-A35
~ 1
ClKB I ''---.,.I-J/ 1 ,'-----
I Ipd(C-MF) ~ r tpd(C-MF) -.I
~
1 ' ' - - - -....

------~~-~\'--- _ _ _--~I_ _ _~)-------

1 I
\~------t"I------------------I~------J1
1- 1 1
W/RB VZZT4 1
I I
I ~\\\\§
I 1
MBB _ _ _-'-I_ _ _~/I 1
1 11 tSU(EN)~1.-..j th(EN) 1
ENB 1 11 uP!) ~1..:..S:"S:"~~~-i-1_ _ __
1.1
ten H
1 .1 tpd(M-OV)
j + - - - + - - - . I tpd(C-MR)
I
-~
-114--4
BO-B35
FIF01 Output Register

Figure 15. Timing for Mail1 Register and MBF1 Flag

~1EXAS
INSTRUMENTS
11-156 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3632
512x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST·OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

CLKB I , I ,\-__ I -J
''-__---II
~ :-- th(EN) tsu(EN)
-----~~~I--------------------------------
I I
W/RB
:sss\\~ : Pm
I I I
MBB
7!Z2ZZZ2?Z4 :W
ENB
/??ZZZ??I?Z?{ I. .
BO-B35
~ I
CLKA I ,"----rI-..J1
'F --I , ' - - - _...{r ,'-----
-+I tpd(C·MF) tpd(C-MF)

--------~----~\~----------+I------~/--------
I I -
\'------Tl-------------~:
I I I
___ -J1
I
W/RA ~S~S~s~s~::;o:-"'Si
I I (/""''/"'' /:"'' 2"'' 2"'' 2"'' 2.,.2.,./-:-·
I I
I
MBA ____~I---..J/I iI
I II lt~sU~(E~~~~~~~L~~t~h(~EN~) I
ENA I II IZZZi) ..S.;,.~;::,,),~__i-1______
t:1..::.:>:
ten
I
/4----tI
14: ~I tpd(M.OV)
;.---+.:..---.1 tpd(C-MR) tdls -t14_~"
i J
AO-A35 Wi (remains valid In mall2 r Ister after read)
FIF02 Output Register

Figure 16. Timing for Mail2 Register and MBF2 Flag

~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-157
SN74ACT3632
512x36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free·air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Vee) ............................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vecl ........................................... ±50 mA
Continuous output current, 10 (Vo = 0 to Vecl ............................................. ±50 mA
Continuous current through Vce or GND ................................................. ±400 mA
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
vee Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current -4 mA
IOL Low-level output current 8 mA
TA Operating free-air temperature 0 70 ·e

~1EXAS
INSTRUMENTS
11-158 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3632
512x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VOH VCC =4.5V, IOH =-4 mA 2.4 V
Val VCC=4.5V, IOl= 8mA 0.5 V
II VCC = 5.5 V, VI=VccorO ±5 ~
IOZ VCC=5.5 V, VO=VCcorO ±5 ~
ICC VCC=5.5V, VI=VCC-0.2VorO 400 ~
CSA=VIH AO-A35 0
CSB = VIH BO-B35 0
VCC= 5.5 V, One input at 3.4 V,
6.ICC:!: CSA=Vll AO-A35 1 mA
Other inputs at VCC or GND
CSB=Vll BO-B35 1
All other inputs 1
Ci VI=O, f = 1 MHz 4 pF
Co VO=O, f = 1 MHz 8 pF
t All tYPical values are at VCC = 5 V, TA = 25'C.
:!: This is the supply current when each input is at one of the specified TIL voltage levels rather than 0 V or VCC.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 16)
'ACT3632·15 'ACT3632·20 'ACT3632·30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency, ClKA or ClKB 66.7 50 33.4 MHz
tc Clock cycle time, ClKA or ClKB 15 20 30 ns
tw(ClKH) Pulse duration, ClKA and ClKB high 6 8 10 ns
tw(ClKl) Pulse duration, ClKA and ClKB low 6 8 10 ns
tsu(D) Setup time, AO-A35 before ClKAI and BO-B35 before ClKBI 4 5 6 ns
Setup time, CSA, W/RA, ENA, and MBA before ClKA1'; CSB,
tsu(EN) 4.5 5 6 ns
W/RB, ENB, and MBB before ClKBI
tsu(RS) Setup time, RST1 or RST2 low before ClKA1 or ClKBI§ 5 6 7 ns
tsu(FS) Setup time, FSO and FS1 before RST1 and RST2 high 7.5 8.5 9.5 ns
th(D) Hold time, AO-A35 aiter ClKAI and BO-B35 after ClKBI 1 1 1 ns
Hold time, CSA, W/RA, ENA, and MBA after ClKAI; CSB, W/RB,
th(EN) 1 1 1 ns
ENB, and MBB after ClKBI
th(RS) Hold time, RST1 or RST2 low aiter ClKA1 or ClKBI§ 4 4 5 ns
th(FS) Hold time, FSO and FS1 aiter RST1 and RST2 high 2 3 3 ns
Skew time between ClKA1 and ClKBI for ORA, ORB,
tsk1 ~ 7.5 9 11 ns
IRA,and IRB
Skew time between ClKA1 and ClKBI for AEA, AEB,
tsk2~ 12 16 20 ns
AFA, andAFB
§ Requirement to count the clock edge as one of at least four needed to reset a FIFO
~ Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and
ClKB cycle.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-159
SN74ACT3632
512x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 1 through 16)
'ACT3632·15 'ACT3632·20 'ACT3632·30
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
ta Access time, ClKAi to AO-A35 and ClKBi to BO-B35 3 11 3 13 3 15 ns
tpd(C·IR) Propagation delay time, ClKAi to IRA and ClKBi to IRB 2 8 2 10 2 12 ns
tpd(C·OR) Propagation delay time, ClKA i to ORA and ClKBi to ORB 1 8 1 10 1 12 ns
tpd(C-AE) Propagation delay time, ClKAi to AEA and ClKBi to AEB 1 8 1 10 1 12 ns
tpd(C-AF) Propagation delay time, ClKA i to AFA and ClKBi to AFB 1 8 1 10 1 12 ns
Propagation delay time, ClKA i to MBFl low or MBF2 high and
tpd(C-MF) 0 8 0 10 0 12 ns
ClKBi to MBF2 low or MBFl high
Propagation delay time, ClKAi to BO-B35t and ClKBi to
tpd(C-MR) 3 13.5 3 15 3 17 ns
AO-A35:t:
Propagation delay time, MBA to AO-A35 valid and MBB to
tpd(M-DV) 3 11 3 13 3 15 ns
BO-B35 valid
Propagation delay time, RSTI low to AEB low, AFA high, and
tpd(R-F) 1 15 1 20 1 30 ns
MBFl high, and RST2 low to AEA low, AFB high, and MBF2 high
Enable time, CSA and W/RA low to AO-A35 active and CSB low
ten 2 12 2 13 2 14 ns
and iN/RB high to BO-B35 active
Disable time, CSA or W/RA high to AO-A35 at high impedance
tdis 1 8 1 12 1 11 _ns
and CSB high or iN/RB low to BO-B35 at high impedance
t
..
Writing data to the maill register when the BO-B35 outputs are active and MBB is high
:t: Writing data to the mail2 register when the AO-A35 outputs are active and MBA is high

~TEXAS
INSTRUMENTS
11-160 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3632
512 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY

fdata =1/2 fclock

=
TA 7SoC
2S0 CL =0 pF -+--+--1---1---+-----,,£-1
~
I

~ 200 f--+--+---+---+--t7'=---:¥-~
a VCC=SV
>-
i 1S0f--+--+--+-~~~~-+-~
~
I
E 100f--+--~~rT~+--+--+-~

""
~f--~$L+--+--+--+--+-~

OL-_L-_L-_L-_+--_+--_L-~

o 10 20 30 40 SO 60 70
fclock - Clock Frequency - MHz

Figure 17

calculating power dissipation

The ICC(f) current for the graph in Figure 17 was taken while simultaneously reading and writing a FIFO on the
SN74ACT3632 with ClKA and ClKS set to fclock. All data inputs and data outputs change state during each
clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to
a zero-capacitance load. Once the capacitive load per data-output channel and the number of SN74ACT3632
inputs driven by TTL high levels are known, the power dissipation can be calculated with the equation below.
With ICC(f) taken from Figure 17, the maximum power dissipation (PT) of the SN74ACT3632 can be calculated
by:
PT =VCC x [ICC(f) + (N x ~Icc x dc)] + :L(CL x VCc2 x fo)
where:
N number of inputs driven by TTL levels
~Icc increase in power supply current for each input at a TTL high level
dc duty cycle of inputs at a TTL high level of 3.4 V
CL output capacitive load
fo switching frequency of an output
When no reads or writes are occurring on the SN74ACT3632, the power dissipated by a single clock (ClKA
or ClKS) input running at frequency fclock is calculated by:
PT = VCC x fclock x 0.184 mA IMHz

~TEXAS
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75266 11-161
SN74ACT3632
512x36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

5V

1.1 kO
From Output
Under Test ---41>-----....

6800 ;::~ 30pF

(see Note A)

LOAD CIRCUIT

L,.----
--..If~-;.~-
Timing 3V High-Level 3V
Input Ii 1.5 V Input ~
,.w, GND
_ _--J.Lj.. - - - - - GND
tsu~th I+- tw -+I
I I
Data, ~~::- 3V
~
I 3V
Enable --.T 1.5 V ~ Low-Level 1.5 V 1.5 V
Input GND Input _ _ _ _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

3V
Output L
Enable .-I: 1.5 V
GND
~ l~tPLZ
1

~3V
1 1 .----;-~
Low-Level
Output 1 I Input --1(1.5 V \ly5~-- 3V
_-+-'1 I VOL . GND
---+I I4-tPZH
~tpd
I VOH tpd~
High-Level
, In-Phase
--_1_- VOH
1 I
Output
1 I ~OV Output 11.5V 'L 1.5V
_ _--J. '\.::..: VOL
~ l~tpHZ

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 18. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
11-162 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

• Free-Running ClKA and ClKB Can Be • IRB, ORB, AEB, and AFB Flags
Asynchronous or Coincident Synchronized by ClKB
• Two Independent Clocked FIFOs Buffering • low-Power O.B-Micron Advanced CMOS
Data In Opposite Directions Technology
• Mailbox-Bypass Register for Each FIFO • Supports Clock Frequencies up to 67 MHz
• Programmable Almost-Full and • Fast Access Times of 11 ns
Almost-Empty Flags • Pln-to-Pin Compatible With the
• Microprocessor Interface Control logic SN74ACT3622 and SN74ACT3632
• IRA, ORA, AEA, and AFA Flags • Available in Space-Saving 120-Pin Thin
Synchronized by ClKA Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages

PCB PACKAGE
(TOP VIEW)

~~~~~~~E~~~~~~~~~~~§~~~~~~~~~~
A35 1 90 835 3:
A34 2 M 834 w
A33
A32
3
4
88
87
833
832 :>
w
Vee 5 M GND
A31 6 85 831 a:
A30
GND
7
8
84
83
830
829
a.
A29 9 82 828 I-
A28
A27
10
11
81
80
827
826
o
::l
A26
A25
12
13
79
78
Vee
825 o
A24
A23
14
15
77
76
824
GND
oa:
GND 823
A22
16
17
75
74 822 a.
Vee 18 73 821
A21 19 72 820
A20 20 71 819
A19 21 70 818
A18 69 GND
GND 68 817
A17 67 816
A16 66 Vee
A15 65 815
A14 64 814
A13 63 813
Vee 62 812
A12 61 GND

PRODUCT PREVIEW Information con...ns produC181n the lormatlve or Copyright © 1995, Texas Instruments Incorporated

~TEXAS
design phase 01 development. CharaCteristic data and other
speclflcatons are design goals. Texas Instruments reserves the right to
chenge or discontinue III... prodUC18 wllllout notlea.

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-163
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

PQPACKAGEt
(TOPVIEWj

NC NC
B35 NC
B34 A35
B33 A34
B32 A33
GND A32
B31 Vee
B30 A31
B29 A30
B28 GND
B27 A29
B26 A28
Vee A27
"'C B25 A26
XI B24 A25
0 GND
B23
A24
A23
C B22 GND
C B21 A22
0 B20 Vee
-I B19 A21
"'C B18 A20
XI GND A19
m B17
B16
A18
GND
S Vee A17
m B15 A16
:e B14
B13
B12
A15
A14
A13
GND Vee
NC A12
NC NC

Ne - No internal connection
t Uses Yamaichi socket le51-1324-828

~ThXAS
INSTRUMENTS
11-164 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A-JUNE 1994 - REVISED SEPTEMBER 1995

description
The SN74ACT3642 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock
frequencies up to 67 MHz with read access times as fast as 11 ns. The two independent 1024 x 36 dual-port
SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and
full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number
of words is stored in memory. Communication between each port can bypass the FIFO via two 36-bit mailbox
registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can
be used in parallel to create wider datapaths.
The SN74ACT3642 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the
port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag
of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the
almost-full and almost-empty flags of the FIFO can be programmed from port A.
The SN74ACT3642 is characterized for operation from O°C to 70°C. 3:
W
For more information on this device family, see the application report FIFO Mailbox-Bypass Registers: Using
Bypass Registers to Initialize DMA Control in the 1996 High-Performance FIFO Memories Designer's
Handbook, literature numberSCAA012A.
>
W
a:
Q.

t;
::l
C
oa:
Q.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-165
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS440A-JUNE 1994- REVISED SEPTEMBER 1995

functional block diagram

Ir------------------------------ MBFl

_ - - - - -.........1 MaUl
CLKA --r---~C:£:~~~====~:L-I~Re~g~IS~~!r--F=I::::==1
CSA - - Port·A 1--1----, f"1
WiRA - - Control 1--1----, .---
-...::.::------------=-.-~ .....--
ENA - - Logic t=
r- Li _ a; CD
~ ~I u ]
MBA - - .~... 1024x36 i'
I!
II
II:
'5
SRAM f+- ~:0
FIF01, "~~I!~ ~ t ~ 36
MaUl
Reset I~ ~~
Logic
I
I Write
Pointer
Ir Read
Pointer I11-4----tf--~
!

_ -+__~~~il
IRA...i 1
___~~t~~~t
Status-Flag II------l----~+-I-I-------- ORB
~ ~ 1 ~
." 36 IL_FIFOl
_ ____ ~. _____ _
::II
o
C ..........- - BO-B35
C
o-I
."
::II 36
m
S
m FIF02,
MaU2
Reset
Logic
==
:!=CLKB
-- Port·B .....-CSB
L-- - - Control
~W/RB
Logic __ ENB
MaU2
P' I Register L..__.............. MBB

MBF2------------------------------~1

-!/} 1ExAs
INSTRUMENTS
11-166 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3642
1024x36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME
AO-A35 I/O Port-A data. The 36-bit bidirectional data port for side A.
0 Port-A almost-em ply flag. Programmable flag synchronized to CLKA. AEA is low when the number of words in FIF02
AEA
(portA) is less than or equal to the value in the almost-empty A offset register, X2.
0 Port-B almost-empty flag. Programmable flag synchronized to ClKB. AEB is low when the number. of words in FIFOI
AEB
(port B) is less than or equal to the value in the almost-em ply B offset register, XI.
0 Port-A almost-full flag. Programmable flag synchronized to ClKA. AFA is low when the number of empty locations in
AFA
(portA) FIFOI is less than or equal to the value in the almost-full A offset register, Yl.
0 Port-B almost-full flag. Programmable flag synchronized to ClKB. AFB is low when the number of empty locations in
AFB
(port B) FIF02 is less than or equal to the value in the almost-full B offset register, Y2.
BO-B35 I/O Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
ClKA I
or coincident to ClKB. IRA, ORA, AFA, and AEA are all synchronized to the low-to-high transition of ClKA.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
ClKB I
or coincident to ClKA. IRB, ORB, AFB, and AEB are synchronized to the low-te-high transition of ClKB.
Port-A chip select. CSA must be low to enable a low-te-high transition of ClKA to read or write data on port A. The
CSA I
AO-A35 outputs are in the high-impedance state when CSA is high.

CSB I
Port-B chip select. CSB must be low to enable a low-te-high transition of elKB to read or write data on port B. The
BO-B35 outputs are in the high-impedance state when CSB is high. ==
w
ENA I Port-A enable. ENA must be high to enable a low-te-high transition of ClKA to read or write data on port A. 5>
ENB I Port-B enable. ENB must be high to enable a low-te-high transition of ClKB to read or write data on port B. w
Flag-offset selects. The low-te-high transition of a FIFO's reset input latches the values of FSO and FSI. If either FSO a:
FS1,FSO I
or FS 1 is high when a reset input goes high, one of three preset values is selected as the offset for the FIFO almost-full a..
and almost-empty flags. If both FIFOs are reset simultaneously and both FSO and FS1· are low when RSTI and RST2
I-
go high, the first four writes to FIFOI program the almost-full and almost-emply offsets for both FIFOs.
Input-ready flag. IRA is synchronized to the low-to-high transition of ClKA. When IRA is low, FIFOI is full and writes
o
IRA
0
to its array are disabled. IRA is set low when FIFOI is reset and is set high on the second low-te-high transition of ClKA ::J
(portA)
after reset. C
IRB
0
Input-ready flag. IRB is synchronized to the low-to-high transition of ClKB. When IRB is low, FIF02 is full and writes
to its array are disabled.IRB is set low when FIF02 is reset and is set high on the second low-te-high transition of ClKB
oa:
(port B)
after reset. a..
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
MBA I AO-A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects
FIF02 output-register data for output.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
MBB I BO-B35 outputs are active, a high level on MBB selects data from the mail 1 register for output and a low level selects
FIFOI output-register data for output.
Maill register flag. MBFl is set low by the low-to-high transition of ClKA that writes data to the mail 1 register. Writes
MBFl 0 tothe mail 1 register are inhibited while MBFl is low. MBFl is set high by a low-to-high transition of ClKB when a port-B
read is selected and MBB is high. MBFl is set high when FIFOI is reset.
Mail2 register flag. MBF2 is set low by the low-te-high transition of ClKB that writes data to the mail2 register. Writes
MBF2 0 to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of ClKA when a port-A
read is selected and MBA is high. MBF2 is also set high when FIF02 is reset.
Output-ready flag. ORA is synchronized to the low-te-high transition of ClKA. When ORA is low, FI F02 is empty and
0 reads from its memory are disabled. Ready data is present on the output register of FIF02 when ORA is high. ORA
ORA
(portA) is forced low when FI F02 is reset and goes high on the third low-to-high transition of ClKA after a word is loaded to
empty memory.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-167
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A-JUNE 1994-REVISEDSEPTEMBER 1995

Terminal Functions (Continued)

TERMINAL
110 DESCRIPTION
NAME
Output-ready flag. ORB is synchronized to the low-ta-high transition of ClKB. When ORB is low, FIF01 is empty and
0 reads from its memory are disabled. Ready data Is present on the output register of FIF01 when ORB is high. ORB
ORB
(port B) is forced low when FIF01 is reset and goes high on the third low-ta-high transition of ClKB after a word is loaded to
empty memory.
FIF01 reset. To reset FIF01, four low-to-high transitions of ClKA and four low-to-hlgh transnions of ClKB must occur
RSn I while RST1 is low. The low-to-high transition of RSTl latches the status of FSO and FSl for AFA and AEB offset
selection. FIFOl must be reset upon power up before data is written to its RAM.
FIF02 reset. To reset FIF02, four low-to-high transitions of CLKA and four low-ta-high transnions of ClKB must occur
RST2 I while RST2 is low. The low-to-high transition of RST2 latches the status of FSO and FS1 for AFB and AEA offset
selection. FIF02 must be reset upon power up before data is written to its RAM.
Port-A write/read select. A high on W/RA selects a wrne operation and a low selects a read operation on port A for a
WiRA I
low-ta-high transition of ClKA. The AO-A35 outputs are in the high-impedance state when W/RA is high.
Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a
WIRB I
low-to-high transition of ClKB. The BO-B35 outputs are in the high-impedance state when W/RB is low.

detailed description
"'C reset
::D
o The FIFO memories of the SN74ACT3642 are reset separately by taking their reset (RST1, RST2) inputs low
for at least four port-A clock (ClKA) and four port-B clock (ClKB) low-te-high transitions. The reset inputs can
C
C switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the
o-I input-ready flag (IRA, IRB) low, the output-ready flag (ORA, ORB) low, the almost-empty flag (AEA, AEB) low,
and the almost-full flag (AFA, AFB) high. Resetting a FIFO also forces the mailbox flag (MBF1, MBF2) of the
parallel mailbox register high. After a FIFO is reset, its input-ready flag is set high after two clock cycles to begin
"'C normal operation. A FIFO must be reset after power up before data is written to its memory.
::D
m A low-to-high transition on a FIFO reset (RST1, RST2) input latches the value of the flag-select (FSO, FS1)
inputs for choosing the almost-full and almost-empty offset programming method (see almost-empty and
S almost-full flag offset programming).
m
:e almost-empty flag and almost-full flag offset programming
Four registers in the SN74ACT3642 are used to hold the offset values forthe almost-empty and almost-full flags.
The port-B almost-empty flag (AEB) offset register is labeled X1 and the port-A almost-empty flag (AEA) offset
register is labeled X2. The port-A almost-full flag (AFA) offset register is labeled Y1 and the port-B almost-full
flag (AFB) offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The
offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from
port A (see Table 1).
Table 1. Flag Programming
FSl FSO RST1 RST2 Xl AND Yl REGISTERSt X2 AND Y2 REGISTER~
H H i x 64 X
H H X i X 64
H l i X 16 X
H l X i X 16
l H i X 8 X
l H X i X 8
l l i i Programmed from port A Programmed from port A
t Xl register holds the offset for AEB; Yl register holds the offset for AFA.
:I: X2 register holds the offset for AEA; Y2 register holds the offset for AFB.

~1ExAs
INSTRUMENTS
11-168 POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST·OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

almost-empty flag and almost-full flag offset programming (continued)

To load FIFO almost-empty flag and almost-full flag offset registers with one of the three preset values listed
in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset input.
For example, to load the preset value of 64 into X1 and Y1 , FSO and FS1 must be high when FIF01 reset (RST1)
returns high. Flag-offset registers associated with FIF02 are loaded with one of the preset values in the same
way with FIF02 reset (RST2). When using one of the preset values for the flag offsets, the FIFOs can be reset
simultaneously or at different times.
To program the X1, X2, Y1, and Y2 registers from port A, both FIFOs should be reset simultaneously with FSO
and FS 1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes
to FIF01 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. Each offset register
uses port-A inputs (A9-AO). The highest-numbered input is used as the most significant bit of the binary number
in each case. Valid programming values for the registers range from 1 to 1020. After all the offset registers are
programmed from port A, the port-8 input-ready flag (IR8) is set high and both FIFOs begin normal operation.
FIFO write/read operation
The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (GSA) and the port-A
write/read select (WiRA). The AO-A35 outputs are in the high-impedance state when either GSA or WiRA is
high. The AO-A35 outputs are active when both GSA and W/RA are low.
Data is loaded into FIF01 from the AO-A35 inputs on a low-to-high transition of GlKA when GSA is low, W/RA
is high, ENA is high, M8A is low, and IRA is high. Data is read from FIF02 to the AO-A35 outputs by a low-to-high
3:
w
transition of GLKA when GSA is low, W/RA is low, ENA is high, M8A is low, and ORA is high (see Table 2). FIFO :;
reads and writes on port A are independent of any concurrent port-8 operation.
w
Table 2. Port-A Enable Function Table a:
a.
CSA W/RA ENA MBA CLKA AO-A35 OUTPUTS PORT FUNCTION
t-
H X X X X In high-impedance state None
O
L H L X X In high-impedance state None ::l
L H H L t In high-impedance state FIF01 write C
L
L
H
L
H
L
H
L X
t In high-impedance state
Active, FIF02 output register
Mail1 write
None
oa:
L L H L t Active, FI F02 output register FIF02 read a.
L L L H X Active, mail2 register None
L L H H t Active, mail2 register Mail2 read (set MBF2 high)

The port-8 control signals are identical to those of port A with the exception that the port-8 writelread select
(W/R8) is the inverse of the port-A write/read select (W/RA). The state of the port-8 data (80-835) outputs is
controlled by the port-8 chip select (GS8) and the port-8 writelread select (W/R8). The 80-835 outputs are
in the high-impedance state when either GS8 is high or W/R8 is low. The 80-835 outputs are active when GS8
is low and W/R8 is high.
Data is loaded into FIF02 from the 80-835 inputs on a low-to-high transition of GlK8 when GS8 is low, W/R8
is low, EN8 is high, M88 is low, and IR8 is high. Data is read from FIF01 to the 80-835 outputs by a low-to-high
transition of GlK8 when GS8 is low, W/R8 is high, EN8 is high, M88 is low, and OR8 is high (see Table 3). FIFO
reads and writes on port 8 are independent of any concurrent port-A operation.

~TEXAS
INSTRUMENTS
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 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS440A-JUNE 1994 - REVISED SEPTEMBER 1995

FIFO write/read operation (continued)

Table 3. Port·B Enable Function Table

CSB W/RB ENB MBB ClKB BO-B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L L L X X In high-impedance state None
L L H L i In high-impedance state FIF02 write
L L H H i In high-impedance state Mail2write
L H L L X Active, FIF01 output register None
L H H L i Active, FIF01 output register FIF01 read
L H L H X Active, mail1 register None
L H H H i Active, mail1 register Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs, If a
port enable is low during a clock cycle, the port-chip select and write/read select may change states during the
setup- and hold-time window of the cycle,
"'C When a FIFO output-ready flag is low, the next data word is sent to the FIFO output register automatically by
:c
oc the low-to-high transition of the port clock that sets the output-ready flag high. When the output-ready flag is
high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the
port-chip select, write/read select, enable, and mailbox select.
c
o synchronized FIFO flags
-I Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve
"'C flag-signal reliability by reducing the probability of metastable events when ClKA and ClKB operate
asynchronously to one another (see the application report Metastability Performance of Clocked FIFOs in the
:c
m 1996 High-Performance FIFO Memories Data Book, literature number SCAD003C). ORA, AEA, IRA, and AFA
are synchronized to ClKA. ORB, AEB, IRB, and AFB are synchronized to ClKB. Tables 4 and 5 show the
~ relationship of each port flag to FIF01 and FIF02.
m
:e Table 4. FIF01 Flag Operation
SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS IN TOClKB TOClKA
FIF01t:l:
ORB AEB AFA IRA
0 L L H H
1 to X1 H L H H
(X1 + 1) to [1024 - (Y1 + 1)J H H H H
(1024 - Y1) to 1023 H H L H
1024 H H L L
t X1 IS the almost-empty offset for FIF01 used by AEB. Y1 IS the almost-full
offset for FIF01 used by AFA. Both X1 and Y1 are selected during a reset
of FIF01 or programmed from port A.
:j: When a word loaded to an empty FIFO is shifted to the output register, its
previous FIFO memory location is free.

~TEXAS
INSTRUMENTS
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 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

synchronized FIFO flags (continued)

Table 5. FIF02 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS IN TOCLKA TOCLKB
FIF02t*
ORA AEA AFB IRB
0 L L H H
1 to X2 H L H H
(X2 + 1) to 11024 - (Y2 + 1)] H H H H
(1024 - Y2) to 1023 H H L H
1024 H H L L
t X2 is the almost-empty offset for FIF02 used by AEA. Y2 is the almost-full
offset for FI F02 used by AFB. Both X2 and Y2 are selected during a reset
of FIF02 or programmed from port A.
* When a word loaded to an empty FIFO is shifted to the output register, its
previous FIFO memory location is free.

output-ready flags (ORA, ORS)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the
output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low, the ;:
previous data word is present in the FIFO output register and attempted FIFO reads are ignored. W
A FIFO read pOinter is incremented each time a new word is clocked to its output register. The state machine :;
that controls an output-ready flag monitors a write-pointer and read-pointer comparator that indicates when the w
FIFO SRAM status is empty, empty+ 1, or empty+2. From the time a word is written to a FIFO, it can be shifted a:
to the FI FO output register in a minimum of three cycles of the output-ready flag synchronizing clock; therefore, a..
an output-ready flag is low if a word in memory is the next data to be sent to the FIFO output register and three
I-
cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written.
The output-ready flag of the FIFO remains low until the third low-to-high transition of the synchronizing clock
o
occurs, simultaneously forcing the output-ready flag high and shifting the word to the FIFO output register. ::J
C
A low-to-high transition on an output-ready flag synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time tsk1' or greater, after the write. Otherwise, the subsequent clock cycle
oa:
can be the first synchronization cycle (see Figures 7 and 8).
a..
input-ready flags (IRA, IRS)
The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array. When the input-ready
flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when
the input-ready flag is low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an
input-ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status
is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be
written in a minimum of two cycles of the input-ready flag synchronizing clock; therefore, an input-ready flag is
low if less than two cycles of the input-ready flag synchronizing clock have elapsed since the next memory write
location has been read. The second low-to-high transition on the input-ready flag synchronizing clock after the
read sets the input-ready flag high.
A low-to-high transition on an input-ready flag synchronizing clock begins the first synchronization cycle of a
read if the clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 9 and 10).

~TEXAS
INSTRUMENTS
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 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS440A-JUNE 1994- REVISED SEPTEMBER 1995

almost-empty flags (AEA, AEB)

The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state
machine that controls an almost-empty flag monitors a write pOinter and read pointer comparator that indicates
when the FIFO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty state is
defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset
values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset
programming). An almost-empty flag is low when its FIFO contains X or less words and is high when its FIFO
contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory.
Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for its
almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1)
or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled
the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of its
synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an
almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater,
after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figures 11 and 12).
almost-full flags (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine
"'C that controls an almost-full flag monitors a write pointer and read pointer comparator that indicates when the
:c
oc FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the contents
of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FIFO reset
or programmed from port A (see almost-empty flag and almost-full flag offset programming). An almost-full flag
c is low when the number of words in its FIFO is greater than or equal to (1024 - Y) for the SN74ACT3622 or
o (1024 - Y) for the SN74ACT3642. An almost-full flag is high when the number of words in its FIFO is less than
-I orequal to [1024- (Y + 1)] forthe SN74ACT3622 or [1 024- (Y + 1)] forthe SN74ACT3642. A data word present
in the FIFO output register has been read from memory.
"'C
:c Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for its
m almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FI FO containing [1024 - (Y + 1)]
<
- or less words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced
m the number of words in memory to [1024 - (Y + 1)]. An almost-full flag is set high by the second low-to-high
transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to
~ [1024 - (Y + 1)]. A low-to-high transition of an almost-full flag synchronizing clock begins the first
synchronization cycle if it occurs at time tsk2, or greater, after the read that reduces the number of words in
memory to [1024 - (Y + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first
synchronization cycle (see Figures 13 and 14).
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port-data-transfer operation. A low-to-high transition on ClKA writes AO-A35 data to the mail1 register
when a port-A write is selected by CSA, W/RA, and ENA and with MBA high. A low-to-high transition on ClKB
writes BO-B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and with MBB
high. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail
register are ignored while the mail flag is low.
When data outputs of a port are active, the data on the bus comes from the FI FO output register when the port
mailbox select input is low and from the mail register when the port-mailbox select input is high. The mail1
register flag (MBF1) is set high by a low-to-high transition on ClKB when a port-B read is selected by CSB,
W/RB, and ENB and with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on
ClKA when a port-A read is selected by CSA, W/RA, and ENA and with MBA high. The data in a mail register
remains intact after it is read and changes only when new data is written to the register.

~TEXAS
INSTRUMENTS
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 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

ClKA
--tI Ie-- th(RS)
ClKB
1 I It
4 r tsu(RS) I I ~ h(FS) I
---~I I 1 tsu(FS) 1:---"'1 I 1
RST1 \ I 1 I I I

FS1, FSO

1 tpd(C-IR) I----+l 1 tpd(C-IR) ~

IRA ~~~~ I /,----
1 tpd(C-OR) ~
ORB~~~~
tpd(R-F) j4----tI
AEB~~~
tpd(R-F)~
AFA~

->w~
tpd(R-F)~

Figure 1. FIF01 Reset Loading X1 and Y1 With a Preset Value of Eightt

t FI F02 is reset in the same manner to load X2 and Y2 with a preset value.
a:
D.
ClKA 4 I-
~ tsu(FS) 1 1 1 I
o
:J
1 II I 1 1 I
C
FS1, FSO oa:
~ I
IRA _ _ _ _ _ _ _ _ _---J
tpd(C-IR) 1
ItSU(EN)j fI+-
1
Ih(EN) H tsk1t
D.
ENA
1/7////7///T//T/T///I pxxx, "&8?1 '<&8&' ~ """'~~"
AO-A35
AFA Offo.t AEB Offoet AFB Offset AEA Offset I First Word to FIF01
(Y1) (X1) (Y2) (X2)
ClKB

IRB

t tsk1 is the minimum time between the rising ClKA edge and a rising ClKB edge for IRB to transition high in the next cycle. If the time between
the rising edge of ClKA and rising edge of ClKB is less than tsk1, then IRB may transition high one cycle later than shown.
NOTE A: CSA = l, WiRA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values After Reset

~TEXAS
INSTRUMENTS
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 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

~ le------~~

Iw(ClKH) 14 -:- -I Iw(ClKl)

ClKA )t '\ r
1
\\..----'1:y \I..._ _-II( '--
IRA 1 1
ISU(EN)! 1+4----I_~14~' Ih(EN) 1

CSA ------~~~-~i~~~~----~l-------~I
Isu(EN) I- -I- ~ Ih(EN) 1
WiRA
?lllZ2ZlZZZZ{
Isu(EN) 14
iF
_1 4 ~ Ih(EN)
I1
MBA ~~~~~~~ 1 1

AO-A35
"tJ
::a t Written to FIF01
o Figure 3. Port·A Write·Cycle Timing for FIF01
C
C
o 14 Ie -I
-I 1 _I
"tJ
Iw(ClKH) 14 -~1 I Iw(ClKl)

::a
m
ClKB )t '\ r
1
\ y
1
I
\ ( '--
~ IRB
114
1
1
m Isu(EN) -1-,lh(EN) 1
:e CSB
~
1
1
1
I
Isu(EN) ~ -!4e
1
W/RB
\\\~\\\~
Isu(EN) ~
ifZ\
_1 4~ Ih(EN)
1
1
MBB 1 1
Isu(EN) Ih(EN) Isu(EN) 14- Ih(EN) Isu(EN) ~ 1- Ih(EN)
ENB 'lIZZZZ2ZZZij 1 ~ k%4Z\4Z\'\ bWfl?//
Isu(D) 14 -I- ~ Ih(D) .
BO-B35 No Operallon ~

t Written to FIF02
Figure 4. Port·B Write·Cycle Timing for FIF02

~TEXAS
INSTRUMENTS
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 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

~~------te------~~
Iw(ClKH) :.....------~.I~
.. ------~.: tw(ClKl)
)I..------.\....._ _~I \ ( \ Y
ClKB
I I I '---
I I I
ORB I I 1
1 1 1
~ - - " "~ I I I /, - - - - -
1
~ I I
1 I I :
WIRB WZZlI I I I \.\\\\\\\\)
I I 1
------+1-'"'\ ~ tsu(EN) I 1
MBB I). I "I I I
: I 1 -1 ~I+-_+:I~JEN) tsu(EN) I---I...! th(EN)
ENB VATjz/47/J I ~ I ~Y\\\'\ f/~/.""2;"'2""?""2"'2"'2'"
ope~~tlon I+.! Idls
BO-B35
tpd(M-OV)
ten
I
I" .:_!
I"

~
·1 :
Cta-l
wrt * w2f
:
I+-ta--'
* W3t
1

j
t Read from FIF01
Figure 5. Port-B Read-Cycle Timing for FIF01
->==W
w
a:
D..
tw(ClKH)
,"
I..
te
~ ..
·1
.1 Iw(ClKl) I-
ClKA
1
)I ~ r
I
\ (
I
\'---~YI '---
o
::l
C
I 1
ORA I
I
I
I
I
I
1
oa:
I I
CSA
} I 1/ D..
I I
I I I
I
I
WiRA
~~ I
I : lZlfllZ/fl
~ lau(EN)
MBA
j+-- th(EN) tsu(EN)

tRead Irom FIF02

Figure 6. Port-A Read-Cycle Timing for FIF02

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265 11-175
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS440A-JUNE 1994- REVISED SEPTEMBER 1995

ClKA
I
CSA ______I______ ________________________________________________
_
l
~
o
~
w
~
~
I
WiRA High I I

~ I.- th(EN)
tsu(EN)
MBA \\\A~\~_J (;(7"zrZ'""Z~Z:'-::V""'/.""'/.""'/.""'Z""7%"'7%"'7Z"'7'7."'7'Z"7"zr%rZ/.Z:>""':Z""'V""'/.""'/.""'?:""7Z"'7%"'7%"'7'%"'7'%"7"%7"%7":<:/.Z:>""':Z:>""':V""'/.""'/':""'/.""7Z""7Z"'7%"'7'%"'7'Z"7"%7";
tsU(EN) ~ I+- thIEf'&.

ENA IlZZZdt II \\:\O:~~~~~-T:'\:~:\~-------------------

I
IRA High I I

AO_A"~
~ tw(ClKH) , j4- I w(ClKl)
"'C ClKB 1 2 3
""1"'1 tpd(C-OR) "I~- - - t i ,..--l!==::::::~
O
rtAI ORB ----~
Old Data In FIF01
________ --~_~
Output Register
______ ~I _ _J ~--------

tJ CSB~lO~W~______________________________ *:________~__________________
Co W/RB High
I
~ I I
"'C MBB low I I
::II 1 tsu~Nll+=:l j+" th(EN)
m ENB //V/ZlZZZl/lZlll//lZ2Zl/lZ2Zl/l2/llZVl ~'\\\"
~ ~~~
m BO-B35 ____________~O~I~d~D~at~a~ln~F~IF~O~1~O~ut~pu~t~R~~~ls~te~r__________J*----------~W~1----------

:e t tsk1 is the minimum time between a rising elKA edge and a rising elKB edge for ORB to transition high and to clock the next word to the FIF01
output register in three elKB cycles. If the time between the rising elKA edge and rising elKB edge is less than tsk1. then the transition of ORB
high and load of the first word to the output register may occur one elKB cycle later than shown.

Figure 7. ORB-Flag Timing and Flrst-Oata-Word Fallthrough When FIF01 Is Empty

~TEXAS
INSTRUMENTS
11-176 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

elKB
I
eSB low I
W/RB~~ ____ ~~ ____ I _________________________________________________
~I

I
I.-- th(EN)

~
ORA Old Data In FIF02 Output Register W
:;
eSA low
w
WiRA low
a::
~~------------------------------~--------~------------------
D..
t-
O
::J
C
AO-A~ ____________~O~ld~D~a~m~l~n~F~IF~O~2~O~ut=p~ut~R~~~l~st~e~r__________J~__________~W~1__________ oa::
t tsk1 is the minimum time between a rising ClKB edge and a rising ClKA edge for ORA to transition high and to clock the next word to the FIF02 D..
output register in three ClKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tsk1 , then the transition of ORA
high and load of the first word to the output register may occur one CLKA cycle later than shown.

Figure 8. ORA-Flag Timing and Flrst-Data-Word Fallthrough When FIF02 Is Empty

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-177
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

~te ---'
I. ~.. ~I
'...._-
!w(CLKH) tw(CLKL)

CLKB I\'I 1
' ...._--J/ ' ...._--J/ ' ...._--J/
CSB ~Lo~w~ ________ ~1

I ____________________________________________________
1
W/RB High 1
1

MBB ~Lo~w~
____
Isu(EN) 14
~--~1 ~__------------------------------------------------
~14.1 Ih(EN)
ENB _ _&./"-?/'-'~:.J' i ~\,,;$:";0"...:l~....~~_________________
I
ORB High 1
I.-- la--.j
1
BO-B35 Previous Word In FIFO! Output Re Ister Next Word From FIF01

~ Iskl t ---'ioe-Iot- - Ie ---.I

." Iw(CLKH) 14 ~ , Iw(CLKL)
:D
o
CLKA ' -.... _---'I,...-~' j 1 " 12 '''--_...I!"f '. . ._...Jr--
C
C
IRA FIF01 Full
-----------------------------------~
I
tpd(C.IR) 14 ~I
I
14
1
1
,'-----
~ tpd(C.IR)

o-I CSA Low

-----------------------------------------------~I----------------
W/RA High I
."
:D
m
-<
m
ENA

:E AO-A35
ToFIF01

t tsk1 is the minimum time between a rising ClKS edge and a rising ClKA edge for IRA to transition high in the next CLKA cycle. lithe time between
the rising ClKS edge and rising ClKA edge is less than tskl. then IRA may transition high one CLKA cycle later than shown.

Figure 9. IRA-Flag Timing and First Available Write When FIF01 Is Full

~TEXAS
INSTRUMENTS
11-178 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

I.--Ie~
Iw(CLKH) 14 14 .: Iw(CLKL)

CLKA

CSA
I\.I
1
~Lo~w~________~I
,'-_--J/ ....._-
,'-_--J/
__________________________________________________ __
' ..._--J/ '
WffiA ~LO~W~ ________ 1 ____________________________________________________
~I

MBA -=Lo~w~ ____ ~~-rl~ __________________________________________________

1

Isu(EN) 1~.h.1t1(EN)
ENA _ _.oII/~'/.""/:,,,,'/.~1 1 ..$..$..~~~......____________________
~,,:>:

1
ORA High

AO-A35 Previous Word In FIF02 Output Re Ister Next Word From FIF02

jf- tsk1t --..114-14_ _ Ie ----I

~
~'-_--JI'--~'
Iw(CLKH) 14
) 'l
, Iw(CLKL)
''''_--J( '~. . ._--.Jr- 3:
CLKB

IRB FIF02 Full

1
Ipd(C.IR)
/2
14 ~
I
14
I
Ipd(C.IR)
----
\ .....
->w
-------------------~ 1 w
CSB Low 1 a:
~~-----------------~I-------
W/RB ~LO~W~___________________________________________+:~----------------
Q.

MBB
Isu(EN) j4---+~ Ih(EN)
~S~$~$~$"I:"'$"I:"'$"I:"'\\:~~~~l""'~l""'$~~~$~$~$~$~$~$"I:"'$"1:"'$~\\:~~~~~~l""'~~$~$~$~$~$~$~$"I:"'$"I:"':>:~$~S1
1 ~..,.2;.,.2oj-2'r0'r2,..2,..2,..?/,..~...,/:..,'/...,2.,.
b
::J
ISU(EN)~ Ih(EN) C
ENB
o
a:
BO-B35 Q.

t tsk1 is the minimum time between a rising ClKA edge and a rising ClKB edge for IRB to transition high in the next ClKB cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tsk1, then IRB may transition high one ClKB cycle later than shown.

Figure 10. IRS-Flag Timing and First Available Write When FIF021s Full

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 11-179
 SN74ACT3642
1024x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

ClKA / , ( ':-,,_--,/ _....1/

' .... ' ...._....1/ '",--..,/
ts~
ENA me r-th(EN)
___.....____________________
~ \\:\,;~$.0.0~$~:....:...;:~\

jt- tsk2t -tI

ClKB " /,.-~, } 1 ' ....._,.,12 ' ....._,.,/ , I '--
tpd(C-AE) -I~~---tl-I tpd(C-AE) It ~
AEB X1 Words In FIF01 V (X1 + 1) Words In FIF01 j '--
tsu(EN)b ~th(EN)
ENB _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~~2~z~~2~?~?~3~~ ~~
t tsk2 is the minimum time between a rising ClKA edge and a rising ClKB edge for AEB to transition high in the nextClKB cycle.lfthetlme between
the rising ClKA edge and rising ClKB edge is less than tsk2, then AEB may transition high one ClKB cycle later than shown.
NOTE A: FIFOI write (GSA =l, W/RA. H, MBA - l), FIFOI read (CSB _ l, W/RB - H, MBB - l). Data in the FIFOI output register has been
read from the FIFO.
Figure 11. Timing for AEB When FIF011s Almost Empty

""CJ
l:J
'...._-,.,/ , ......_..,/
o
C
c:
o-I ___'2-----,-,\
tpd(C-AE) """*~ ""'-I
I ,
tpd(C-AE)
(
ill
'--
tI
""CJ
AEA X2 Words In FIF02 V (X2 + 1) Words In FIF02 J \...
l:J tsu~ H tth(EN)
m
S t tsk2 is the minimum time between a rising ClKB edge and ariSing ClKA edge for AEA to transition high in the next ClKAcycle.lfthetime between
m the rising ClKB edge and rising ClKA edge is less than tsk2, then AEA may transition high one ClKA cycle later than shown.
NOTE A: FIF02 write (CSB =l, W/RB =l, MBB =l), FIF02 read (CSA =l, W/RA =l, MBA =l). Data in the FIF02 output register has been
=e read from the FIFO.

Figure 12. Timing for AEA When FIF02 Is Almost Empty

~1ExAs
INSTRUMENTS
11-180 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST·OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

~ Isk2t ~
ClKA / , t , I I
I \ Y1 \ 12 \ 1
Isu(EN) ~ I+- Ih(EN) I I
ENA RZZZ7~~ I
I
I
I
Ipd(C-AF) 14 I Ipd(C-AF) 14 ~
AFA [1024 - (Y1 + 1)] Words In FIF01 (1024 - Y1) Words In FIF01

I
ClKB---./ \ I \ ~~--~\ I ''-_----JI
~_....J ISU(EN)~ 1_lh(EN)
ENB ________________ ~t?~2~2~2~2~2J~ \;~S~S~~~S~S~~~_______________________
t tsk2 is the minimum time between a rising ClKA edge and a rising ClKB edge lor AFA to transition high in the next ClKA cycle. II the time between
the rising ClKA edge and rising ClKB edge is less than tsk2. then AFA may transition high one ClKB cycle later than shown.
NOTE A: FIF01 write (CSA = l. W/RA = H. MBA = l). FIF01 read (CSB = l. W/RB = H. MBB = l). Data in the FIF01 output register has been
read lrom the FIFO.

Figure 13. Timing for AFA When FIF011s Almost Full

~
ClKB / \
tsU(EN)!.....:!I
I
I+- Ih(EN)
~ tsk2t ~
,'-_----J/r--+i~\~_,.,y-:-1--'-"\\
I
12
I
,....---'1 ->w
W

ENB vWaJl~ I : a::

Ipd(C-AF) 14 14--...,,,
Ipd(C-AF) .. Il..
ir------
AFB [1024 - (Y2 + 1)] Words In FIF02
b
::J
ClKA---./
''-_-JI ,'-_----J/ C
ENA __________________~,e.2.z~2~2~2~2r ~0~S~S~S~~~~~L_ _______________________ oa::
t tsk2 is the minimum time between a riSing ClKB edge and a rising ClKA edge lor AFB to transition high in the next ClKB cycle. lithe time between Il..
the rising ClKB edge and rising ClKA edge is less than tsk2. then AFB may transition high one ClKA cycle later than shown.
NOTE A: FIF02 write (CSB = l. W/RB= l. MBB = l). FIF02 read (CSA = l. W/RA = l. MBA = l). Data in the FIF02 output register has been
read Irom the FIFO.

Figure 14. Timing for AFB When FIF021s Almost Full

~TEXAS
INSTRUMENTS
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 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

CLKA / , I '\-__ 1 '\-_ _...J1 '-

________~ts~ul~EN~l~ r-__ oJ
t_hl_EN_l______________________________________
CSA
~I
I I
WiRA
/@!///flIZ? :W
I I I
MBA
2Z?ZZI!Z2ZZ{ :W
ENA

AO-A35

CLKB /
MBFl

"'C
CSB
::D
0 W/RB
C I I I I
C
0
MBB
-------I~----~/I
I II tsuIENl~Y thlENl
I
I
-I ENB I II 41?2l ~~S~S.~~~__~I_______
"'C I ~ tpd(M-OV) I
::D ten H 14 1
j4---l----+I tpdlC-MRl tdls -+14-4-~.I
m BO-B35 Wl remains valid In maUl re Ister after readl

S FIFOl Output Register

m Figure 15. Timing for Mail1 Register and MBF1 Flag

~

~TEXAS
INSTRUMENTS
11-182 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

, I ' .....__..JI , _____..J/

-1 r-
CLKB /

tsu(EN) L. th(EN)
------~~~I-----------------
I I
W/RB
0ZZZZZZZ?Z-?1W
I I I
MBB
<?ZZZZVZZZ4 IW
ENB
/?ZZZZ?/?Z??{ I. .
BO-B35
~ I
CLKA / \-------1
, .....__~I__..JI '10.._______
IF --.! r tpd(C-MF)
-----------~----~,_____________~I~-----J)~------
tpd(C-MF) ....j

I I
\~
1- ___~I------------~I______-JI
I I I
3:
w
WiRA
VZZZ21I 1 lI ~~ 5>
w
I I
MBA ___--+____---'/1
II
I. _,
~r
a:
l tSU(EN)L. th(EN) 1
D..
ENA II IZ?Z!) ...s:""'"~..>a~__;-I_____
t:....,.<:::
I
AO-A35
ten i+---tI
~I tpd(M-OV)
:41j4-_-+ _ _.., tpd(C-MR)
1 _I
tdls -t14-4---.J. t>:::J
Wi (remains valid In mall2 re Ister after read)
C
FIF02 Output Register

Figure 16. Timing for Mail2 Register and MBF2 Flag

oa:
D..

-!llEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11-183
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A-JUNE 1994- REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI> Vecl ............................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Va > Vecl ........................................... ±50 mA
Continuous output current, la (Va = 0 to Vecl ............................................. ±50 mA
Continuous current through Vee or GND .......... ; ...................................... ±400 mA
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
"'C VIH High-level input voltage 2 V
:IJ Low-level input voltage 0.8 V
o VIL
IOH High-level output current -4 mA
C IOL Low-level output current 8 mA
C TA Operating free-air temperature 0 70 ·e
o
-I
"'C
:IJ
m
S
m
:e

~1ExAs
INSTRUMENTS
11-184 POST OFFICE sox 655303 • DALLAS. TEXAS 75265
 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPt MAX UNIT
VOH VCC=4.5 V, IOH =-4 mA 2.4 V
Val VCc=4.5 V, IOl= 8mA 0.5 V
II VCC=5.5 V, VI = VecorO ±5 !1A
IOZ Vce=5.5V, Vo=VccorO ±5 !1A
ICC VCC = 5.5 V, VI = Vec - 0.2 V or 0 400 !1A
CSA=VIH AO-A35 0
CSB=VIH BO-B35 0
Vce = 5.5 V, One input at 3.4 V,
LlICC:!: CSA= Vil AO-A35 1 mA
Other inputs at VCC or GND
CSB = Vil BO-B35 1
All other inputs 1
Ci VI = 0, f = 1 MHz 4 pF
Co VO=O, f= 1 MHz 8 pF
t All typical values are at VCC = 5 V, TA = 25°C.
:!: This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or Vee.

timing requirements over recommended ranges of supply voltage and operating free-air 3:
w
temperature (see Figures 1 through 16)
'ACT3642-15 'ACT3642-20 'ACT3642-30
-
>
MIN MAX MIN MAX MIN MAX
UNIT w
Clock frequency, ClKA or ClKB 66.7 33.4 MHz
a::
fclock
tc Clock cycle time, elKA or ClKB 15 20
50
30 ns
c..
tw(ClKH)
tw(ClKLl
Pulse duration, ClKA and ClKB high
Pulse duration, ClKA and ClKB low
6
6
8
8
10
10
ns
ns b
::l
tsu(D) Setup time, AO-A35 before ClKAi and BO-B35 before ClKBi 4 5 6 ns
C
tsu(EN)
Setup time, CSA, W/RA, ENA, and MBA before ClKAi; CSB,
VV/RB, ENB, and MBB before ClKBi
4 5 6 ns
oa::
tsu(RS) Setup time, RST1 or RST2 low before ClKA i or ClKBi§ 5 6 7 ns
tsu(FS) Setup time, FSO and FS 1 before RST1 and RST2 high 5 6 7 ns c..
th(D) Hold time, AO-A35 after ClKAi and BO-B35 after ClKBi 0 0 0 ns
Hold time, CSA, W/RA, ENA, and MBA after ClKAi; CSB, W/RB,
th(EN) 0 0 0 ns
ENB, and MBB after ClKBi
th(RS) Hold time, RST1 or RST2 low after ClKAi or ClKBi§ 4 4 5 ns
th(FS) Hold time, FSO and FS1 after RST1 and RST2 high 2 3 3 ns
Skew time between ClKAi and ClKBi for ORA, ORB, IRA, and
tsk1 ~ 6 8 10 ns
IRB
Skew time between ClKAi and ClKBi for AEA, AEB, AFA, and
tsk2~ 12 16 20 ns
AFB
§ ReqUirement to count the clock edge as one of at least four needed to reset a FIFO
~ Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and
ClKB cycle.

~TEXAS
INSTRUMENTS
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 SN74ACT3642
1024x36x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 1 through 16)
'ACT3642-15 'ACT3642-20 'ACT3642-30
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
ta Access time, CLKAi to AO-A35 and CLKBi to BO-B35 11 13 15 os
tpd(C-IR) Propagation delay time, CLKAi to IRA and CLKBi to IRB 11 13 15 ns
todlC-ORl Propagation delay time, CLKAi to ORA and CLKBi to ORB 11 13 15 ns
tpd(C-AE) Propagation delay time, CLKAito AEA and CLKBi to AEB 11 13 15 ns
todlC-AFl Propagation delay time, CLKAito AFA and CLKBi to AFB 11 13 15 ns
Propagation delay time, CLKAito MBFl low or MBF2 high and
tpd(C-MF) 11 13 15 ns
CLKBi to MBF2 low or MBFl high
Propagation delay time, CLKAito BO-B35t and CLKBi to
tpd{C-MR) 11 13 15 ns
AO-A35:J:
Propagation delay time, MBA to AO-A35 valid and MBB to
tpd{M-DV) 9 11 13 ns
BO-B35 valid
Propagation delay time, RSTl low to AEB low, AFA high, and
tpd{R-F) 15 20 30 ns
MBFl high, and RST2 low to AEA low, AFB high, and MBF2 high
Enable time, CSA and W/RA low to AO-A35 active and CSB low
10 12 14 ns
'"tJ ten and W/RB high to BO- B35 active
:D Disable time, CSA or W/RA high to AO-A35 at high impedance
oC tdis and CSB high or W/RB low to BO-B35 at high impedance
t Writing data to the maill register when the BO-B35 outputs are active and MBB is high
10 12 14 ns

C :J: Writing data to the mail2 register when the AO-A35 outputs are active and MBA is high

o
-I
'"tJ
:D
m
~
m
:e

~lExAs
INSTRUMENTS
11-186 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ACT3642
1024x36x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
300
f = 11/2 fCldck
=
TA 75°C
< 250 CL=OpF
E
I

~
::I
200
0
~
i-- DATA TO BE SUPPLIED
Co
Co
::I
150 r-----
AT PRODUCT RELEASE
-
I/)
I
IE 100
8
50

o
3:
w
o 10 20 30 40 50 60 70 80
:;:
fclock - Clock Frequency - MHz w
Figure 17 a:
a.
calculating power dissipation
With ICC(f) taken from Figure 17, the maximum power dissipation (Pr) of the SN74ACT3642 can be calculated
b
:::J
by: C
Pr = VCC x [ICC(f) + (N x t1ICC x dc)) + :E(CL x VCc 2 x fo) oa:
where:
a.
N = number of inputs driven by TTL levels
t1lcc = increase in power supply current for each input at a TTL high level
dc = duty cycle of inputs at a TTL high level of 3.4 V
CL = output capacitive load
fo = switching frequency of an output

~TEXAS
INSTRUMENTS
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 SN74ACT3642
1024 x 36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS440A- JUNE 1994 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

5V

1.1 kn
From Output
Under Test ----e----.
680 Q ;::::: 30 pF
(see Note A)

LOAD CIRCUIT

~
-3V
Timing 1. 3V High-Level 1.5 V 1.5 V
Input ---J4 ~ ~ ___ GND Input I I GND
"tJ tsu~th 14-- tw --+I
:D ~--:-::,- 3V
I I
o Data,
Enable ,J'1.5V ~ Low-Level ~ 1.5 V 1.5 V
I 3V

C Input GND Input _ _ _ _ GND

c
o VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
-f
"tJ Output L 3V
:D Enable ---I: 1.5 V
m I
~ i~tPLZ
GND

<
-
m
:e
Low-Level
Output
I I
I
--f-.JI
_----i-~
I
I
---+I ~tpZH
~3V

VOL
Input J(1.5V \~5-; --::0
I VOH
tpd --j4--+j ~ tpd
High-Level
I I In-Phase 1/---"" I - - VOH
Output
I I ~OV Output T 1.5 V
_ _--J.
\L'\:.:..:
1.5 V
VOL
--+i l~tpHZ

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES
NOTE A: Includes probe and jig capacitance

Figure 18. Load Circuit and. Voltage Waveforms

~ThxAs
INSTRUMENTS
11-188 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
12-1
 INTERNETWORKING 36-BIT CLOCKED FIFOS
Features Benefits

• 36-bit FIFO interface • Single-chip implementation for high levels

of integration
• Bidirectional option • Two dual-port SRAMs allow true
bidirectional capability
• Mailbox-register bypass • Quick access to priority information
• Microprocessor-control circuitry • Interface matches most processors and
DSP bus-cycle timing and
communications
• Separate programmable AF and AE flags • Easy alternatives for flag settings
as well as multiple default values for
separate AF and AE flags
• Byte swapping/bus matching • Allows for smooth interface between
multiple processors or buses
• Parity generation and check • Ensures valid data
• TI has established alternate source • 67% less board space than equivalent
o- options 132-pin PQFPs; over 66% less board
o(') space than four 9-bit, 32-pin PLCC
equivalents
s
Co
!!
o"
en

12-2
 SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING

• Free-Running ClKA and ClKB Can Be • Microprocessor Interface Control logic

Asynchronous or Coincident • FF and AF Flags Synchronized by ClKA
• 64 x 36 FIFO Buffering Data From Port A to • EF and AE Flags Synchronized by ClKB
Port B
• Passive Parity Checking on Each Port
• Mailbox Bypass Registers In Each
• Parity Generation Can Be Selected for Each
Direction
Port
• Dynamic Port-B Bus Sizing of 36 Bits (long
• low-Power Advanced BiCMOS Technology
Word), 18 Bits (Word), and 9 Bits (Byte)
• Supports Clock Frequencies up to 67 MHz
• Selection of Big- or little-Endian Format for
Word and Byte Bus Sizes • Fast Access Times of 10 ns
• Three Modes of Byte-Order Swapping on • Package Options Include Space-Saving
Port B 12o-Pln Thin Quad Flat (PCB) and 132-Pln
Quad Flat (PQ) Packages
• Programmable Almost-Full and
Almost-Empty Flags

description

The SN74ABT3613 is a high-speed, low-power BiCMOS clocked FI FO memory. It supports clock frequencies
up to 67 MHz and has read-access times as fast as 10 ns. A 64 x 36 dual-port SRAM FIFO in this device buffers
data from port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags
(almost full and almost empty) to indicate when a selected number of words is stored in memory. FIFO data on
port B can be output in 36-bit, 18-bit, and 9-bit formats with a choice of big- or little-end ian configurations. Three
modes of byte-order swapping are possible with any bus-size selection. Communication between each port can
bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has
been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can
be selected for data read from each port.
The SN74ABT3613 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
COincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses controlled by a synchronous interface.
The full flag and almost-full flag of a FIFO are two-stage synchronized to the port clock that writes data to its
array. The empty flag and almost-empty flag of a FI FO are two-stage synchronized to the port clock that reads
data from its array.
The SN74ABT3613 is characterized for operation from DOC to 7DoC.
For more information on this device family, see the application reports FIFO Mailbox-Bypass Registers; Using
Bypass Registers to Initialize DMA Control, Advanced Bus-MatchingIByte-$wapping Features for Internetwor-
king FIFO Applications, Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Ap-
plications, and Internetworking the SN74ABT3614 in the 1996 High-Performance FIFO Memories DeSigner's
Handbook, literature number SCAA012A.

Copyright © 1996, Texas Instruments Incorporated

=::SCT1!:'O:1: 8~O::C:~':.aI;;,::~!.:. :: ~~~:::~m':,~
standard warranty. Production processing does not necessarily Include
testing of all parameters. ~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-3
SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E-JULY 1992 - REVISED FEBRUARY 1996

PCB PACKAGE
(TOP VIEW)

~~~~~~~~~~~g~~~~~a~og~~~~~~~~m
A23 1
--------------------- 00
822
A22 2 89 821
A21 3 88 GND
GND 4 87 820
A20 5 86 819
A19 6 85 818
A18 7 84 817
A17 8 83 816
A16 9 82 B15
A15 10 81 B14
A14 11 80 B13
A13 12 79 B12
A12 13 78 B11
A11 14 77 B10
A10 15 76 GND
GND 16 75 B9
A9 17 74 B8
A8 18 73 B7
A7 19 72 Vee
Vee 20 71 B6
A6 21 70 B5
A5 22 69 B4
A4 23 68 B3
A3 24 67 GND
GND 25 66 B2
A2 26 65 B1
A1 27 64 BO
AO 28 63 EF
NC 29 62 AE
NC 30 61 NC
~~~~~~~~~~~~~~~~~~~~~~~~~~~~m~

Ne - No internal connection

~TEXAS
INSTRUMENTS
12-4 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E -JULY 1992 - REVISED FEBRUARY 1996

PQPACKAGEt
(TOP VIEW)

Iu..lu..len
Ie IN
uC u.: c u.. C _ I 1-
- 0 - 0 u.. C 1u.. m m u mm :.::: m m
...J I~ uc!) Wz m m en 1]l cit; z IW ~ ~ !:::!!:::! m z W C!) ul~ ...J z len u ()
C C :.:::
z CC
C C
cu..()W(»>~~C!)~~u..u..OlocC!)menenenen~C!)~~»()W()ZZ

GND GND
NC AE
NC EF
AO 80
A1 81
A2 82
GND GND
A3 83
A4 84
A5 85
A6 86
VCC VCC
A7 87
A8 88
A9 89
GND GND
A10 810
A11 811
VCC VCC
A12 812
A13 813
A14 814
GND GND
A15 815
A16 816
A17 817
A18 818
A19 819
A20 820
GND GND
A21 821
A22 822
A23 823

NC - No internal connection
t Uses Yamaichi socket IC51-1324-828

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265 12-5
SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUTMEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E -JULY 1992 - REVISED FEBRUARY 1996

functional block diagram

ClKA
CSA Port·A
WiRA Control r----------------------------MBFl
ENA logic
MBA

,.
I
4:+~~___..f-M~--l+'I....-tGen/Check a...-I-+-----,
I Malll I ~ L
Parity

.J -
I PEFB

C=I====~;~I~R~eg~ls~te~r~~~~==~~~~==~~______ PGB

. i
r-=:-----------~-~~,
..~
&~ 'C CD
~ S c ffi~ 0
I .!!! ~,g ",·a .~ I
I 5P L......;:~ .. ~ila... a:
i a:
La..
r""
64x36
SRAM r""" co c u;l I"'" _ II
- •+-HH~ "5 Il. CD OJ II) :I
.e-~
RST
0001
-
Device
Control
II -
.s
Co

~""'--
Cl ::ECD
g:~
.!.... -
8 I
I
36

EVEN

36 II ~
I Write
I Pointer
II Read
Pointer
I
I
I
I
I
Itt II
FF -.------++-+----ii-----I:
""""-
...i
Status-Flag EF
AF I I logic J------------- - -+'---+--+-1-+-+---- AE
FIFO
L------4-___________ J
FSO Programmable-Flag
FS1 Offset Register
AO-A35 BO-B35

PGA
L-----~----~--~~--IMM:a~II;2---,I~~----~
L&J Parlly (I
..._ _ _----:'""l...-..l
,:J~~~R~eg~l~st!er~JI~~----~j:jj~
PEFA _ ....----------------1 Gen/Check I '-4---- ClKB
r CSB
MBF2 ....- - - W/RB
Port·B ENS
....- - - BE
Control ....- - - SIZO
logic SIZl
....- - - SWO
L __ ,t1--- SWl

~TEXAS
INSTRUMENTS
12-6 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E- JULY 1992 - REVISED FEBRUARY 1996

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME
AO-A35 1/0 Port-A data. The 36-bit bidirectional data port for side A.
0 Almost-empty flag. Programmable almost-empty flag synchronized to ClKB. AE is low when the number of 36-bit words
AE
(port B) in the FIFO is less than or equal to the value in offset register X.
0 Almost-full flag. Programmable almost-full flag synchronized to ClKA. AF is low when the number of 36-bit empty
AF
(portA) locations in the FI Fa is less than or equal to the value in offset register X.
BO-B35 I/O Port-B data. The 36-bit bidirectional data port for side B.
Big-endian select. Selects the bytes on port B used during byte or word FIFO reads. A low on BE selects the most
BE I
significant bytes on BO-B35 for use, and a high selects the least significant bytes.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
ClKA I
or coincident to ClKB. FF and AF are synchronized to the low-te-high transition of ClKA.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
ClKB I or coincident to ClKA. Port-B byte swapping and data-port-sizing operations are also synchronous to the low-to-high
transition of ClKB. EF and AE are synchronized to the low-to-high transition of ClKB.
Port-A chip select. CSA must be low to enable a low-to-high transition of ClKA to read or write data on port A. The
CSA I
AO-A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of ClKB to read or write data on port B. The
CSB I
BO-B35 outputs are in the high-impedance state when CSB is high.
Empty flag. EF is synchronized to the low-to-high transition of ClKB. When EF is low, the FIFO is empty and reads from
a its memory are disabled. Data can be read from the FIFO to the output register when EF is high. EF is forced low when
EF
(port B) the device is reset and is set high by the second low-to-high transition of ClKB after data is loaded into empty FIFO
memory.
ENA I Port-A enable. ENA must be high to enable a low-to-high transition of ClKA to read or write data on port A.
ENB I Port-B enable. ENB must be high to enable a low-to-high transition of ClKB to read or write data on port B.
Full flag. FF is synchronized to the low-to-high transition of ClKA. When FF is low, the FIFO is full and writes to its
a
FF memory are disabled. FF is forced low when the device is reset and is set high by the second low-to-high transition of
(portA)
ClKA after reset.
Flag offset selects. The low-to-high transition of RST latches the values of FSO and FS1 , which selects one of four preset
FS1,FSO I
values for the almost-empty flag and almost-full flag offset.
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
MBA I
AO-A35 outputs are active, mail2 register data is output.
Mail1 register flag. MBF1 is set low by the low-to-high transition of ClKA that writes data to the mail1 register. Writes
MBF1 a to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of ClKB when a port-B
read is selected and both SIZ1 and SIZO are high. MBF1 is set high when the device is reset.
Mail2 register flag. MBF2 is set low by the low-to-high transition of ClKB that writes data to the mail2 register. Writes
MBF2 a to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of ClKA when a port-A
read is selected and MBA is high. MBF2 is set high when the device is reset.
Oddleven parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
0001
I ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
EVEN
for a read operation.
Port-A parity error flag. When any byte applied to terminals AO-A35 fails parity, PEFA is low. Bytes are organized as
AO-AB, A9-A 17, A1B-A26, and A27 -A35 with the most significant bit of each byte serving as the parity bit. The type
a of parity checked is determined by the state of ODD/EVEN.
PEFA
(portA) The parity trees used to check the AO-A35 inputs are shared by the mail2 register to generate parity if parity generation
is selected by PGA; therefore, if a mail2 read with parity generation is set up by having eSA low, ENA high, W/RA low,
MBA high, and PGA high, the PEFA flag is forced high regardless of the state of the AO-A35 inputs.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-7
SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST~OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E -JULY 1992 - REVISED FEBRUARY 1996

Terminal Functions (Continued)

TERMINAL
I/O DESCRIPTION
NAME
Port-B parity error flag. When any valid byte applied to terminals BO- B35 fails parity, PEFB is low, Bytes are organized
as BO-B8, B9-B17, B18-B26, and B27-835 with the most significant bit of each byte serving as the parity bit. A
byte is valid when it is used by the bus size selected for port B. The type of parity checkE!d is determined by the state
0
PEFB of ODDIEVEN.
(port B)
The parity trees used to check the BO-B35 inputs are shared by the maill register to generate parity If parity generation
is selected by PGB; therefore, if a maill resd with parity generation is set up by havlngCSB low, ENB high, WIRB low,
SIZl and SIZO high, and PGB high, the PEFB flag is forced high regardless of the state of the BO-B35 Inputs.
Port-A parity generation. Parity Is generated for data reads from the mall2 register when PGA is high. The type of parity
PGA I generated is selected by the state of ODDIEVEN. Bytes are organized asAO-AB, A9-A 17, A1B-A26, and A27 -A35.
The generated parity bits are output in the most significant bit of esch byte.
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated
PGB I is selected by the state of ODDIEVEN. Bytes are organized as BO-88, B9-B17, B1B-B26, and B27-B35. The
generated parity bits are output In the most significant bit of each byte.
Reset. To reset the device, four low-ta-hlgh transitions of CLKA and four low-ta-hlgh transitions of CLKB must occur
RST I while RST Is low. This sets the AF, MBF1, anc:l MBF2 flags high and the EF, AE, and FF flags low. The low-ta-high
transition of RST latches the status of the FS 1 and FSO inputs to select almost-full fiag and almost-empty flag offset.
Port-S bus size selects. The low-to-high transition of CLKB latches the states of SIZO, SIZ1, and BE, and the following
I
SIZO, SIZl low-ta-high transition of CLKB implements the latched states as a port-B bus size. Port-B bus sizes can be long word,
(port B)
word, or byte. A high on both SIZO and SIZl accesses the mailbox registers for a port-B 36-bit write or resd.
Port-B byte swap.selects. At the beginning of each long word FIFO read, one of four modes of byte-order swapping
I
SWO,SWl is selected by SWO and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order
(port B)
swapping Is possible with any bus-size selection.
Port-A writelresd select. W/RA high selects a write operation and a low selects a read operation on port A for a
WIRA I
low-ta-high transition of CLKA. The AO-A35 outputs are In the high-impedance state when WIRA Is high.
Port-B writelread select. WIRB high selects a write operation and a low selects a read operation on port B for a
WIRB I
low-ta-high transition of CLKB. The BO-B35 outputs are in the high-impedance state when WIRB Is high.

detailed description
reset
The SN74ABT3613 is reset by taking the reset (RST) input low for at least four port-A cl9Ck (ClKA) and four
port-B clock (ClKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of each FIFO and forces the full flag (FF) low, the empty flag
(EF) low, the almost-empty flag (AE) low, and the almost-full flag (AF) high. A reset also forces the mailbox flags
(MBF1, MBF2) high. After a reset, FF is set high after two low-to-high transitions of ClKA. The device must be
reset after power up before data is written to its memory.
A low-to-high transition on the RST input loads the almost-full and almost-empty offset register (X)with the value
selected by the flag-select (FSO, FS1) inputs. The values that can be loaded into the register are shown in
Table 1.

Table 1. Flag Programming

ALMOST-FULL AND
FS1 FSO RST ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H H i 16
H L i 12
L H i 8
L L i 4

~lExAs
INSTRUMENTS
12-8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E-JULY 1992 - REVISED FEBRUARY 1996

FIFO write/read operation

The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (GSA) and the port-A
write/read select (WiRA). The AO-A35 outputs are in the high-impedance state when either GSA or WiRA is
high. The AO-A35 outputs are active when both GSA and WiRA are low. Data is loaded into the FIFO from the
AO-A35 inputs on a low-to-high transition of GlKA when GSA is low, W/RA is high, ENA is high, MBA is low,
and FFA is high (see Table 2).

Table 2. Port-A Enable Function Table

CSA WIRA ENA MBA ClKA AO-A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
l H l X X In high-impedance state None
L H H L i In high-impedance state FIFO write
L H H H i In high-impedance state Maill write
L L L L X Active, mail2 register None
L L H L i Active, mail2 register None
L L L H X Active, mail2 register None
L L H H i Active, mail2 register Mail2 read (set MBF2 high)

The state of the port-B data (BO-B35) outputs is controlled by the port-B chip select (GSB) and the port-B
writeiread select (W/RB). The BO-B35 outputs are in the high-impedance state when either GSB or W/RB is
high. The BO-B35 outputs are active when both GSB and W/RB are low. Data is read from the FIFO to the
BO-B35 outputs by a low-to-high transition of GlKB when GSB is low, W/RB is low, ENB is high, EFB is high,
and either SIZO or SIZ1 is low (see Table 3).

Table 3. Port-B Enable Function Table

CSB W/RB ENB SIZ1,SIZO ClKB BO-B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H One, both low i In high-impedance state None
L H H Both high i In high-impedance state Mail2write
L L L One, both low X Active, FIFO output register None
L L H One, both low i Active, FIFO output register FIFO read
L L L Both high X Active, maill register None
L L H Both high i Active, maill register Maill read (set MBFl high)

The setup- and hold-time constraints to the port clocks for the port-chip selects (GSA, GSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select
can change states during the setup- and hold-time window of the cycle.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 12-9
SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E-JULY 1992- REVISED FEBRUARY 1996

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability
by reducing the probability of metastable events on the output when ClKA and ClKB operate asynchronously
to one another (see the application report Metastability Performance of Clocked FIFOs in the 1996
High-Performance FIFO Memories Data Book, literature number SCAD003C). FF and AF are synchronized to
ClKA. EF and AE are synchronized to ClKB. Table 4 shows the relationship of each port flag to the level of
FIFO fill.

Table 4. FIFO Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF 36-BIT TOCLKB TOCLKA
WORDS IN THE FIFOt
EF AE AF FF
0 L L H H
1 toX H L H H
(X+ 1)to[64-(X+ 1)] H H H H
(64-X) to 63 H H L H
64 H H L L
t xis the value in the almost-empty flag and almost-full flag offset register.
empty flag (EF)
The FIFO empty flag is synchronized to the port clock that reads data from its array (ClKB). When the empty
flag is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty
and attempted FIFO reads are ignored. When reading the FIFO with a byte or word size on port B, EF is set
low when the fourth byte or second word of the last long word is read.
The FIFO read pointer is incremented each time a new word is clocked to the output register. The state machine
that controls the empty flag monitors a write-pointer and a read-pointer comparator that indicates when the FIFO
SRAM status is empty, empty+ 1, or empty+2. A word written to the FIFO can be read to the FIFO output register
in a minimum of three port-B clock (ClKB) cycles. An empty flag is low if a word in memory is the next data to
be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not
elapsed since the time the word was written. The FI FO empty flag is set high by the second low-to-high transition
of ClKB and the new data word can be read to the FIFO output register in the following cycle.
A low-to-high transition on ClKB begins the first synchronization cycle of a write if the clock transition occurs
at time tsk1 , or greater, after the write. Otherwise, the subsequent clock cycle can be the first synchronization
cycle (see Figure 9).
full flag (FF)
The FIFO full flag is synchronized to the port clock that writes data to its array (ClKA). When the full flag is high,
a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is
low and attempted writes to the FIFO are ignored.
Each time a word is written to the FIFO, the write painter is incremented. The state machine that controls a full
flag monitors a write-painter and a read-pointer comparator that indicates when the FIFO SRAM status is full,
full-1, or full-2. From the time a word is read from the FIFO, the previous memory location is ready to be written
in a minimum of three CLKA cycles. A full flag is low if less than two ClKA cycles have elapsed since the next
memory-write location has been read. The second low-to-high transition on the full-flag synchronizing clock
after the read sets the full flag high and data can be written in the following clock cycle.
A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs
at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization
cycle (see Figure 10).

~TEXAS
INSTRUMENTS
12-10 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E - JULY 1992 - REVISED FEBRUARY 1996

almost-empty flag (AE)

The FIFO almost-empty flag is synchronized to the port clock that reads data from its array (ClKB). The state
machine that controls an almost-empty flag monitors a write-pointer and a read-pointer comparator that
indicates when the FIFO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty
state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with
one of four preset values during a device reset (see reset). An almost-empty flag is low when the FIFO contains
X or less long words in memory and is high when the FIFO contains (X + 1) or more long words.
Two low-to-high transitions of ClKB are required after a FIFO write for the almost-empty flag to reflect the new
level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1) or more long words remains low if two
ClKB cycles have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag
is set high by the second low-to-high transition of ClKB after the FIFO write that fills memory to the (X + 1) level.
A low-to-high transition of ClKB begins the first synchronization cycle if it occurs at time ts k2, or greater, after
the write that fills the FIFO to (X + 1) long words. Otherwise, the subsequent ClKB cycle can be the first
synchronization cycle (see Figure 11).
almost-full flag (AF)
The FIFO almost-full flag is synchronized to the port clock that writes data to its array (ClKA). The state machine
that controls an almost-full flag monitors a write-pointer and a read-pointer comparator that indicates when the
FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the value
of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values
during a device reset (see reset). An almost-full flag is low when the FIFO contains (64 - X) or more long words
in memory and is high when the FIFO contains [64 - (X + 1)] or less long words.
Two low-to-high transitions of ClKA are required after a FIFO read for the almost-full flag to reflect the new level
of fill; therefore, the almost-full flag of a FIFO containing [64 - (X + 1)] or less words remains low if two ClKA
cycles have not elapsed since the read that reduced the number of long words in memory to [64 - (X + 1)]. An
almost-full flag is set high by the second low-to-high transition of ClKA after the FIFO read that reduces the
number of long words in memory to [64 - (X + 1)]. A low-to-high transition of ClKA begins the first
synchronization cycle if it occurs at time tsk2, or greater, after the read that reduces the number of long words
in memory to [64 - (X + 1)]. Otherwise, the subsequent ClKA cycle can be the first synchronization cycle
(see Figure 12).
mailbox registers
Two 36-bit bypass registers (mail1, mail2) are on board the SN74ABT3613 to pass command and control
information between port A and port B without putting it in queue. A low-to-high transition on ClKA writes
AO-A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA, and MBA is high.
A low-to-high transition on ClKB writes BO-B35 data to the mail2 register when a port-B write is selected by
(CSB, WiRB, and ENB) and both SIZO and SIZ1 are high. Writing data to a mail register sets the corresponding
flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while the mail flag is low.
When the port-B data outputs (BO-B35) are active, the data on the bus comes from the FIFO output register
when either one or both SIZ1 and SIZO are low and from the mail1 register when both SIZ1 and SIZO are high.
The mail1 register flag (MBF1) is set high by a rising ClKB edge when a port-B read is selected by eSB, W/RB,
and ENB, and both SIZ1 and SIZO are high. The mail2 register flag (MBF2) is set high by a rising ClKA edge
when a port-A read is selected by CSA, W/RA, and ENA and MBA is high. The data in the mail register remains
intact after it is read and changes only when new data is written to the register.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 12-11
SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E -JULY 1992 -REVISED FEBRUARY 1996 .

dynamic bus sizing

The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from the
FI FO. Word- and byte-size bus selections can utilize the most significant bytes of the bus (big end ian) or least
significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and synchronous to
elKB to communicate with peripherals of various bus widths.
The levels applied to the port-B bus-size select (SIZO, SIZ1) inputs and the big-end ian select (BE) input are
stored on each elKB low-to-high transition. The stored port-B bus-size selection is implemented by the next
rising edge on elKB according to Figure 1.
Only 36-bit long-word data is written to or read from the FIFO memory on the SN74ABT3613. Bus-matching
operations are done after data is read from the FIFO RAM. Port-B bus sizing does not apply to mail-register
operations.
A35 A27 A26 A18 A17 A9 A8 AO

BYTE ORDER ON PORT A: 8 8 [J [J Write to FIFO

B35 B27 B26 B18 B17 B9 B8 BO

BE

X
SIZ1

L
SIZO

L
8 8 [J [J Read From FIFO

(a) LONG-WORD SIZE

B35 B27 B26 B18 B17 B9 B8 BO

BE

L
SIZ1

L
SIZO

H
8 8 ~ ~ 1st: Read From FIFO

B35 B27 B26 B18 B17 B9 B8 BO

[J [J ~ ~ 2nd: Read From FIFO

(b) WORD SIZE - BIG ENDIAN

B35 B27 B26 B18 B17 B9 B8 BO

BE

H
SIZ1

L
SIZO

H
~ ~ [J [J 1st: Read From FIFO

B35 B27 B26 B18 B17 B9 B8 BO

~ ~ 8 8 2nd: Read From FIFO

(e) WORD SIZE - LITTLE ENDIAN

Figure 1. Dynamic Bus Sizing

~TEXAS
INSTRUMENTS
12-12 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E- JULY 1992 - REVISED FEBRUARY 1996

dynamic bus sizing (continued)

BE

L
SIZ1

H
SIZO

L
o
B35 B27 B26

~
B18 B17

~
B9 B8

~
BO

1st:ReadFromFIFO

B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ ~ 2nd: Read From FIFO

B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ ~ 3rd: Read From FIFO

B35 B27 B26 B18 B17 B9 B8 BO

8 ~ ~ ~ 4th: Read From FIFO

(d) BYTE SIZE - BIG ENDIAN

B35 B27 B26 B18 B17 B9 B8 BO

BE

H
SIZ1

H
SIZO

L
~ ~ ~ 8 1st: Read From FIFO

B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ 8 2nd: Read From FIFO

B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ 0 3rd: Read From FIFO

B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ 0 4th: Read From FIFO

(e) BYTE SIZE - LITTLE ENDIAN

Figure 1. Dynamic Bus Sizing (Continued)

bus-matching FIFO reads

Data is read from the FIFO RAM in 36-bit long-word increments. If a long-word bus size is implemented, the
entire long word immediately shifts to the FIFO output register upon a read. If byte or word size is implemented
on port 8, only the first one or two bytes appear on the selected portion of the FIFO output register with the rest
of the long word stored in auxiliary registers. In this case, subsequent FIFO reads with the same bus-size
implementation output the rest of the long word to the FIFO output register in the order shown by Figure 1.
Each FI FO read with a new bus-size implementation automatically unloads data from the FIFO RAM to its output
register and auxiliary registers. Implementing a new port-8 bus size and performing a FIFO read before all bytes
or words stored in the auxiliary registers have been read results in a loss of the unread data in these registers.
When reading data from FIFO in byte or word format, the unused 80-835 outputs remain inactive but static,
with the unused FIFO output register bits holding the last data value to decrease power consumption.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-13
SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E-JULY 1992- REVISED FEBRUARY 1996

port-B mali-register access

In addition to selecting port-B bus sizes for FIFO reads, the port-B bus-size select (SIZO, SIZ1) inputs also
access the mail registers. When both SIZO and SIZ1 are high, the mail1 register is accessed for a port-B
long-word read and the mail2 register is accessed for a port-B long-word write. The mail register is accessed
immediately. Any bus-sizing operation that is underway is unaffected by the mail-register access. After the
mail-register access is complete, the previous FIFO access can resume in the next eLKB cycle. The logic
diagram in Figure 2 shows the previous bus-size selection is preserved when the mail registers are accessed
from port B. A port-B bus size is implemented on each rising eLKB edge according to the states of SIZO_Q,
SIZ1..:..Q, and BE_Q.

elKB

MUX
~ ~1
L-

~1
SIZO_Q
0 Q SIZ1_Q
SIZO BE_Q
SIZ1 "1
BE

Figure 2. Logic Diagram for SIZO, SIZ1, and BE Register

byte swapping
The byte-order arrangement of data read from the FIFO can be changed synchronous to the rising edge of
eLKB. Byte-order swapping is not available for mail-register data. Four modes of byte-order swapping
(including no swap) can be done with any data-part-size selection. The order of the bytes are rearranged within
the long word, but the bit order within the bytes remains constant.
Byte arrangement is chosen by the port-B swap-select (SWO, SW1) inputs on a eLKB rising edge that reads
a new long word from the FIFO. The byte order chosen on the first byte or first word of a new long-word read
from the FIFO is maintained until the entire long word is transferred, regardless of the SWO and SW1 states
during subsequent reads. Figure 3 is an example of the byte-order swapping available for long word reads.
Performing a byte swap and bus size simultaneously for a FIFO read rearranges the bytes as shown in Figure
3, then outputs the bytes as shown in Figure 1.

~1ExAs
INSTRUMENTS
12-14 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E-JULY 1992- REVISED FEBRUARY 1996

byte swapping (continued)

A35 A27 A26 A18 A17 A9 A8 AO

~~~~
~

B35 B27 B26 B18 B17 B9 B8 BO

(a) NO SWAP

A35 A27 A26 A18 A17 A9 A8 AO

ffi L H

B35 B27 B26 B18 B17 B9 B8 BO

(b) BYTE SWAP

A35 A27 A26 A18 A17 A9 A8 AO

~ H L

B35 B27 B26 B18 B17 89 88 80

(e) WORD SWAP

A35 A27 A26 A18 A17 A9 A8 AO

~
~

835 827 B26 816 817 89 86 80

(d) BYTE·WORD SWAP

Figure 3. Byte Swapping for FIFO Reads (Long-Word Size Example)

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-15
SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E - JULY 1992 - REVISED FEBRUARY 1996

parity checking
The port-A data inputs (AO-A35) and port-B data inputs (BO- B35) each have four parity trees to check the parity
of incoming (or outgoing) data. A parity failure on one or more bytes of the port-A data bus is reported by a low
level on the port-A parity error flag (PEFA). A parity failure on one or more bytes of the port-B data inputs that
are valid for the bus-size implementation is reported by a low level on the port-B parity-error flag (PEFB). Odd
or even parity checking can be selected and the parity-error flags can be ignored if this feature is not desired.
Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select
input. A parity error on one or more valid bytes of a port is reported by a low level on the corresponding
port-parity-error flag (PEFA, PEFB) output. Port-A bytes are arranged as AO-AB, A9-A 17, A 1B-A26, and
A27-A35. Port-B bytes are arranged as BO-BB, B9-B17, B1B-B26, and B27-B35, and its valid bytes are
those used in a port-B bus-size implementation. When odd/even parity is selected, a port-parity-error flag
(PEFA, PEFB) is low if any valid byte on the port has an odd/even number of low levels applied to the bits.
The four parity trees used to check the AO-A35 inputs are shared by the mail2 register when parity generation
is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is
selected with CSA low, ENA high, WiRA low, MBA high, and PGA high, the port-A parity-error flag (PEFA) is
held high regardless of the levels applied to the AO-A35 inputs. Likewise, the parity trees used to check
the BO-B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads
(PGB = high). When a port-B read from the mail1 register with parity generation is selected with CSB low, ENB
high, WiRB low, both SilO and SIl1 high, and PGB high, the port-B parity-error flag (PEFB) is held high
regardless of the levels applied to the BO-B35 inputs.
parity generation
A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the
SN7 4ABT3613 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged
as AO-AB, A9-A17, A1B-A26, and A27-A35, with the most significant bit of each byte used as the parity bit.
Port-B bytes are arranged as BO-BB, B9-B17, B1B-B26, and B27-B35 with the most significant bit of each
byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte
regardless of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity
generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on
the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the most
significant bits of each byte as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the
output register. The port-A parity-generate select (PGA) and odd/even parity select (ODD/EVEN) have setup-
and hold-time constraints to the port-A clock (ClKA) and the port-B parity-generate select (PGB) and
ODD/EVEN select have setup- and hold-time constraints to the port-B clock (ClKB). These timing constraints
only apply for a rising clock edge used to read a new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port-B bus (BO-B35) to check parity. The
circuit used to generate parity for the mail2 data is shared by the port-A bus (AO-A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in a mail register when the port-chip
select (CSA, CSB) is low, enable (ENA, ENB) is high, and write/read select (WiRA, W/RB) input is low, the mail
register is selected (MBA is high for port A; both SilO and SIl1 are high for port B), and port parity-generate
select (PGA, PGB) is high. Generating parity for mail-register data does not change the contents of the register.

~1EXAS
INSTRUMENTS
12-16 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS12BE -JULY 1992 - REVISED FEBRUARY 1996

ClKA
-tI '- th(RS)
ClKB
1

....! I- tsu(RS) tsu(FS) ~iHj th(FS)

RST - - -...~ 1 1 : ',......I - - - - - - I I f - - - - - - -
1 1 1 I 1 1
FS1,FSO

1 tpd(C-FF) j.---!--.I .. tpd(C-FF) ~

FF \§\\\~~ ,,----
1 1 ~ .1 tpd(C-EF)
EF &\\\S)\\\\~
1 1 Y tpd(C-AE)

AE \\\\\\~~\'\
1 I.----.! tpd(C-AF)
AF//llT~
__ tpd(R-F) i----.I

~':F~ /lZl/Tfl/'ZZ?
Figure 4. Device Reset Loading the X Register With the Value of Eight

~ ~ ~
\4- tw(ClKH) +Ie- tw(ClKl) -.I
II \I 1
Y,---......, ( , (
ClKA
1 I 1
'-
1 I 1
.......,.I.....~ th(EN)
High
I .. -
tsU(EN) .. 1 1
CSA - - - - -.....~
1 1
1 ~
1
I II
1

tsu(EN) I" .IUI th(EN) I 1

W/RA
V/I2IZZIl?I{ :F 1 : \~
tsu(EN) I" ~ .. ~ th(EN) 1 1
MBA ~~~~~~"' 1 1 1
tSU(E~lJ: ~ I4---ij
; - - th(EN) tsu(EN)
th(EN) r-
ENA ? /ll/ZllZlLd I~ ~~ l/""2""2"'2"'2""2"":;:~2~2

~~:::t'-±:~-~
AO-A35 .~Nr-oo'='OP""'e""'ra':':'tIO""n'"'l&OOO<X>O<~~~~

I 1

~~~ 2S)(: :
tpd(O-PE) ~ tpd(O-PE) ~
PEFA

t Written to the FIFO

Figure 5. FIFO·Wrlte-Cycle Timing

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-17
SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E -JULY 1992 - REVISED FEBRUARY 1996

ClKB ( '1...__( 'I..._-t ''-__..of'

1 1 1 i
EF High I 1 1 1
1 1 1
I 1 1 1
CSB ~1 ______~I------------~'------------~i1 __I1
1
1

W/RB ~~~ I i R""2~2""2""'/.""2"")

1 . ISU(EN~ ~4~ Isu(EN) I. ,14 ~t Ih(EN)

ENB ~ I~ .1 \\h\\\\\i JWZIZZ2

1 I' W 1 1 1I 1 No Operation 1

~~O..ll~~.:.:.:..~p~~~$~U~(S~). ',4 ~ : ~
B~u~ ::4 ~m;J~J"'-"""""" I · 1

SIZ\~u~~
SIZO ~
' (0,0)
~I
X
'I
~4 }:lh(SZ)
Not(1 '1 1)T X (0,0) X
!
Not(1, 1)T
~
~
1

6~~;~r: '~~
EVEN~rI+-- :~
I ,

BO-B35
len ~
~
la
Previous Dala

t SIZO = Hand SIZ1 = H selects the mail1 register for output on 80-835.
--.I
*:
--+I
I+-- la
W1¥ * W2¥
Idls ~
~

:I: Data read from the FIFO

DATA SWAP TABLE FOR FIFO lONG-WORD READS

FIFO-DATA WRITE SWAP MODE FIFO-DATA READ
A35-A27 A26-A18 A17-A9 A8-AO SW1 SWO B35-B27 B26-B18 B17-B9 B8-BO
A B C D L L A B C D
A B C D L H 0 C B A
A B C 0 H L C D A B
A B C D H H B A 0 C

Figure 6. FIFO Long-Word Read-Cycle Timing

~ThXAS
INSTRUMENTS
12-18 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBSI28E- JULY 1992- REVISED FEBRUARY 1996

elK8 _ _---' \ .....----II( \ ~ \ / '-

I I
EF High I I
I I
I I
I I rI

Little {
Endian* 80-817 --------t~~~!:§!!!:= ....._.....,.:=;..;.._ __

Endi:~¥{818-835------""'{C:j~~~~:J ---..L.::-:~~-- '--_"';';;=';;""_....J

t SIZO = Hand SIZI = H selects the maill register for output on BO-B35.
:j: Unused word BO-B17 or B18- B35 holds last FIFO-output-register data for word-size reads.

DATA SWAP TA8lE FOR FIFO-WORD READS

FIFO-DATA READ
FIFO-DATA WRITE SWAP MODE READ
81GENDIAN LITTLE END IAN
NO.
A35-A27 A26-A18 A17-A9 A8-AO SWI SWO 835-827 826-818 817-89 88-80
1 A B C 0
A B C 0 L L
2 C 0 A B
1 0 C B A
A B C 0 L H
2 B A 0 C
1 C 0 A B
A B C 0 H L
2 A B C 0
1 B A 0 C
A B C 0 H H
2 0 C B A

Figure 7. FIFO-Word Read-Cycle Timing

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 12-19
SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E -JULY 1992 - REVISED FEBRUARY 1996

CLKB

EF High I
I
I
CSB 'I
r I I 'I
W/RB S\\\\\\~:
I I I
I
I
I
I
I
I
wav I .
I tsu(EN) ~ th(EN) I I I .L
ENB VTfi/l2?A11
f""
: ~I
,.:_ .1_:
. I "<S88&' I ~ I \\\~
I
eW.2"""2"'V""2""2~;
No Operation I
tsu(SW) ~
.
SW1,SWO

,,~~
tsu(SZ) ~ th(SZ) I I I I :
SIZ1, SIZO . +t (1,1)1 )(>QQQQ<;
Not (1" 1)t I Not (1, 1)t I Not (1, 1)t I I I

PGB'~
ODD/EVEN
----,- I I I I

BO-B8
ten J+-.-.j

~ * R~ * R~d *
!+-:

.
ta

Pr~vlous Da~
-.J ~

i l l
ta

1
-.I :_

I
ta

2
-.I 1_ ta
Read 3
1
1
-.I
*
I
tdls

Read 4
~
ii
'J---
B27-B35 (* * *
14-- ta --.j

Previous Data
If- ta -.I
Read 1
1_ ta -.I
Read 2
~ ta
Read 3
-.I
X
tdls ~
Read 4 'J---
t SIZO = Hand SIZ1 = H selects the mail1 register for output on 80-835.
NOTE A: Unused bytes hold the last FIFO-output-register data for byte-size reads.

Figure 8. FIFO-Byte Read-Cycle Timing

~ThxAs
INSTRUMENTS
12-20 POST OFFICE BOX 655303 -DALLAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E-JULY 1992 - REVISED FEBRUARY 1996

DATA SWAP TABLE FOR FIFO-BYTE READS

FIFO-DATA READ
FIFO-DATA WRITE SWAP MODE READ BIG LITTLE
NO. ENDIAN ENDIAN
A35-A27 A26-A18 A17-A9 AS-AO SW1 SWO B35-B27 B8-BO
1 A D
2 B C
A B C D L L
3 C B
4 D A
1 D A
2 C B
A B C D L H
3 B C
4 A D
1 C B
2 D A
A B C D H L
3 A D
4 B C
1 B C
2 A D
A B C D H H
3 D A
4 C B

Figure 8. FIFO-Byte Read-Cycle Timing (Continued)

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-21
SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E - JULY 1992 - REVISED FEBRUARY 1996

ClKA
I
I I
CSA low I I
I i

FF High I I
tsu(O) 14--!'! 1_ I

AO-A35
Isklt 14 ~14 ---.I .
t W (ClKH)-1 M
te
Iw(ClKl)

ClKB 2

EF FIFO Empty

CSB low
I
wiRB low i
~~------------------------~I-----------------------
SIZ1. SIZO low I
Isu(EN) ~ I+- Ih(EN)
ENB ?/Z?ZZl2ZZ2Z//ZlZZZ/ZZ?ZZZZ7/!;h ~\\\\'\\'\\.~
14- la ---.j
BO-B35 ~----------~W~l---------
t tsk1 is the minimum time between a rising eLKA edge and a rising CLKS edge for EF to transition high in the next ClKS cycle. If the time between
the rising eLKA edge and rising elKS edge is less than tskl. the transition of EF high may occur one eLKS cycle later than shown.
NOTE A: Port-S size of long word is selected for the FIFO read by SIZl = L. SIZO = L. If port-S size is word or byte. EF is set low by the last word
or byte read from the FIFO. respectively.

Figure 9. EF-Flag Timing and First Data Read When the FIFO Is Empty

-!!J lExAs
INSTRUMENTS
12-22 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E-JULY 1992 - REVISED FEBRUARY 1996

i-tc~
~4 ~ tw(CLKL)

'..._-___
tw(CLKH) 14
CLKB I \. ~ \~_,.JI 1 ' ..._---1/
CSB -=LO~W~ _________1 I~ ________________________________________________
' ..._ - - J

W/RB _~LO~W~ _________ I~ ___________________________________________________

SIZ1. SIZO -=LO~W~_________ if-_____________________________________________

1

tsU(EN) I~ th(EN)
ENB _ _",II"",I"",11.J1J i t\.l\\"S...\.,;\\.~__________________
1
EF High

BO-B35 __ ~ __________ ~ __ -J,,-N_"_tW_o_~_Fr_~_th_'_FI_ro ___________________________________

14---tc~
~ ~ tw(CLKL)
CLKA ~\"._--,I '--_. . ~--'\ f2 ,\"._----:' ''''_---Ir-
tpd(C.FF) 14 ~r____+14==~~ tpd(C·FF)
FF ______________F_IF_O_FU_II____________________~l i \~ _________
1

CSA Low 1
~~----------------------------+I------------
1
W/RA High I
tsu(EN) ~ th(EN)
S. :.:....:$...$~$~~~~~~~$~$~$~$~$.....$.....$...$...$~$~$~~~:---:~~~$~$~0~$~$.....$.....$...$~$~$~~~~~:---::""':"i i
MBA .... (/...,z...,2""7'2""7'2"'7"z"'7"2'T'2~2:O-:?/,...,z...,z"7(
tsu(EN) ~ Ih(EN)
ENA ?Z?ZZZi/ZT/7/Z/!l/ZZZZ7~ i ~~~\'\\'0
\sueD) ~ th(D)
AO-A35
To FIFO
t tsk1 is the minimum timebetween a rising ClKB edge and a rising ClKA edge for FF to transition high in the next ClKA cycle. If the time between
the rising ClKB edge and rising ClKA edge is less than Isk1. FF may transition high one ClKA cycle later than shown.
NOTE A: Port·B size of long word is selected for the FIFO read by SIZ1 =l. SIZO = L. If port·B size is word or byte. tsk1 is referenced from the
rising ClKB edge that reads the first word or byte of the long word. respectively.

Figure 10. FF.Flag Timing and First Available Write When the FIFO Is Full

~ThXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 12-23
SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E -JULY 1992 -REViSED FEBRUARY 1996

CLKA

tsu(EN) i_ -:I ~ th(EN)

ENA WZT4 It:\;I~~~~~~~~~~'o,J"",,___________________
i+-- tSk2t ....j
CLKB

.1 tpd(C-AE) je-I---~
AE X Lon Words In the FIFO ir-------~~+-----~
(X + 1) Long Words In thelFIFO

tsu(EN) i+-::I !+- th(EN)

ENB _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _rL~2~2~2~Z~2g~ \s\'\S\'\
t tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tsk2. AE may transition high one CLKB cycle later than shown.
NOTES: A. FIFO write (CSA = L. W/RA =H. MBA =L). FIFO read (CSB =L. W/RB =L. MBB =L)
B. Port-B size of long word is selected for FIFO read by Sill = L. SilO = L.lf port-B size is word or byte. tsk2 is referenced to the first
word or byte read of the long word. respectively.

Figure 11. Timing for AE When the FIFO Is Almost Empty

CLKA I ',--_( ''-_...J/

J-
I'
tsk2t -tj

Y1
, 12
1
''-_...JI
tsu(EN) ~ j+- th(EN) 1 1
1 1
ENA RI/Tdiib'S\\
~ I I
~--~---------~------
1 ....
~
1
tpd(C-AF) I" .1 1 tpd(C-AF) I-
AF (64 - (X + 1)) Long Words In the FIFO\,"_(6_4_-_x)_Lo_n_g-l~I-0_rd_s_ln_th_e_FI_F_O_ _ _ __ _ _ _..Ji.....----
1
1
--I , I,---""''----J/
CLKB
''-__....J/
lsu(EN) ~ (4- th(EN)
'\._....J/ '---
ENB ___________.~~z~~2~2.2~2~~ ,,~~~~$~S.$~$~~~______________
t tsk2 is the minimum lime between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle.lfthetime between
the rising CLKA edge and rising CLKB edge is less than tsk2. AF may transition high one CLKB cycle later than shown.
NOTES: A. FIFO write (CSA =L. W/RA =H. MBA _ L). FIFO read (CSB. L. W/RB. L. MBB =L)
B. Port-B size of long word is selected for FIFO read by Sill = L. SilO = L. If port-B size is word or byte. tsk2 is referenced from the
first word or byte read of the long word. respectively.

Figure 12. Timing for AF When the FIFO Is Almost Full

~1ExAs
INSTRUMENTS
12-24 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E - JULY 1992 - REVISED FEBRUARY 1996

ClKA I ,---~( ,'---_/ ,'-----/ '--

~ ~ th(EN)

l I~I~-------------------------------
tsu(EN)

CSA
------i1'-----1-11 I
I I I
W/RA 0llll71ll2? i_
I I I
MBA 0'l71Zll272? i_
I I I

ClKB I

ENB

BO-B35

NOTE A: Port-B parity generation off (PGB = L)

Figure 13. Timing for Mall1 Register and MBF1 Flag

-!!11EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-25
SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E - JULY 1992 - REVISED FEBRUARY 1996

ClKB I '''----'If ' ....__--'1 ' ....__--'1

tsu(EN) ~ 14- th(EN)
CSB --------~~~................................................- -........- - - - - - - - - -.....

I_
I I I
WiRB vzzzzzv/d I_

SIZ1,SIZO VZZZl//?7A1--==1 r tsu(SZ) th(SZ)

I II
ENB Z7Z/07Z/J24t I 'W'
BO-B35 ~~
I
I ' . . --~l--~I , { ,~-------
r-
ClKA

~ tpd(C-MF) -.j tpd(C-MF) ~~

MBF2 ----------------~l--------\ I ,-------
I I
). I I !
I I I I
I I I I
WIRA ""Z""Z""Z""Z""Z""Z"'J.J, I I ~~$~::;~$~:S:~:'\:~$~:S:~S~)
I I I
I I I I
MBA I II I I

I
I I
I
I
tSU(E:.
IZZZ2I
I.

-
HI Ih(EN)
~ L
I
I
~,,"$.:..:S:.:..:S:..:\~-!-I_ _ _ _ __
ENA
I 1 I
ten 14---+1 14 ~I tpd(C-MR) !dIs J+---..I
AO-A35 _ W1 (remains valid In mall2 register after read) j
NOTE A: Port-A parity generation off (PGA = L)

Figure 14. Timing for Mall2 Register and MBF2 Flag

~TEXAS
INSTRUMENTS
12-26 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E-JULY 1992- REVISED FEBRUARY 1996

0001
EVEN \ I
WiRA
:I :I \ ________1
I I I I
MBA vzzzv7fllZ?llAlAfrflZZ2ZZ2ZZZZll
I I I
\sss\\\\\\\
I
PGA VZZZTJTftZZlZTmzd(zTaz;zzzzzzz? \%s\~
tpd(O-PE) ~ tpd(O-PE) t--------tI tpd(E-PE) ~, tpd(E-PE) I+-----tI
..JJ .IJ - ~
Valid X Valid X Valid \ Valid

NOTE A: eSA = Land ENA = H

Figure 15. ODD/EVEN, WiRA, MBA, and PGA to PEFA Timing

0001
EVEN
, I
I I
WiRB : : \ r ---- t
I I I'-----~I
SIZ1,
SIZO
mzm)zzzzzzzzzzzAz;zmzzzzzzz} ~
I I I I
PGB zmzzzhz;fllV?I2II7zz;fllI2?IV7l t>~

NOTE A: ess = L and ENS =H

Figure 16. ODD/EVEN, WiRB, SIZ1, SIZO, and PGB to PEFB Timing

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265 12-27
SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E - JULY 1992 - REVISED FEBRUARY 1996

0001
EVEN
\--------------------------
I
I
Low
I
I

~~----------------~I
I -------------------------
WiRA
I
MBA vzZ;zzzzar
I I
I
I
PGA I (~------------_+I-------------\
i I I r~--------------
1+ len ~ 14----- tpd(E.PB) 4 14----- tpd(O-PB) ----I J+-- tpd(E.PB) ---+j
A8,A17,
A26, A35 ~ Mall2 Data * Generated Parity * Generated Parity *~M=-al:'!"!:12~0=-at=-a

NOTE A: ENA = H

Figure 17. Parity-Generation Timing When Reading From the Mail2 Register

0001
EVEN \~--------------------------
I
Low
I
I
I

~~-----------------~i---------------------------
WiRB
I I
SIZ1,
SIZO ~ I
I I I
PGB ~2~~~2~?~22~?~2~21~-------------+1--------------)__________________
I I+-- tpd(E.PB) ---.J I I
1+ ten +I 1+ tpd(M.OV) -.J I J+-- tpd(E.PB) ---+I
14-- tpd(O-PB) --:
B8, B17,
B26,B35
------~-~G:-e-ne-r""'!at-ed':"::p:-a~rlt:-y-~X"--G=-e-ne-r""'!at-ed:"":P=-ar":"!lt-y-"'X~M~a":'!'1I1~0:-a~ta
Mall1
Data
NOTE A: ENS = H

Figure 18. Parity-Generation Timing When Reading From the Mail1 Register

~TEXAS
INSTRUMENTS
12-28 POST OFFice BOX 655303 • DALLAS, TeXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E-JULY 1992- REVISED FEBRUARY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Vee) ............................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ........................................... ±50 mA
Continuous output current, 10 (Vo = 0 to Vee) ............................................. ±50 mA
Continuous current through Vee or GND ................................................ ±500 mA
Operating free-air temperature range, TA ............................................... O·C to 70·C
Storage temperature range, Tstg .................................................. -65·C to 150·C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating condttions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current , -4 mA
IOL Low-level output current 8 mA
TA Operating free-air temperature 0 70 ·C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TY~ MAX UNIT
VOH VCC- 4.5V, IOH--4mA 2.4 V
VOL Vcc = 4.5 V, IOL-8mA 0.5 V
II Vcc =5.5 V, VI = VccorO ±50 IlA
IOZ VCC=5.5V, VO·VCc orO ±50 IlA
Outputs high 60
ICC Vee = 5.5 V, IO=OmA, VI = Vee or GND Outputs low 130 mA
Outputs disabled 60
ei VI=O, f= 1 MHz 4 pF
Co VO-O, f= 1 MHz 8 pF
:j: Ali typical values are at Vee = 5 V, TA = 25·e.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAl;. TEXAS 75265 12-29
SN74ABT3613
64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E-JULY 1992 - REVISED FEBRUARY 1996

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 4 through 18)
'ABT3613-15 'ABT3613-20 'ABT3613-30
UNIT
MIN MAX MIN MAX MIN MAX
Iclock Clock frequency, ClKA or ClKB 66.7 50 33.4 MHz
tc Clock cycle time, ClKA or ClKB 15 20 30 ns
tw(ClKH) Pulse duration, ClKA and ClKB high 6 8 12 ns
tw(ClKl) Pulse duration, ClKA and ClKB low 6 8 12 ns
tsu(D) Setup time, AO-A35 before ClKAi and BO-B35 before ClKBi 4 5 6 ns
Setup time, CSA, W/RA, ENA, and MBA before ClKAi; CSB,
tsu(EN) 5 5 6 ns
W/RB, and ENB before ClKBi
tsu(Sl) Setup time, SilO, Sill, and BE before ClKBi 4 5 6 ns
tsu(SW) Setup time, SWO and SWI before ClKBi 5 7 8 ns
tsu(PG) Setup time, ODD/EVEN and PGB before ClKBit 4 5 6 ns
tsu(RS) Setup time, RST low before ClKA i or ClKBi+ 5 6 7 ns
tsu(FS) Setup time, FSO and FSI before RST high 5 6 7 ns
th(D) Hold time, AO-A35 after ClKAi and BO-B35 afterClKBi 1 1 1 ns
Hold time, CSA, W/RA, EN A, and MBA after ClKAi; CSB, W/RB,
th(EN) 1 1 1 ns
and ENB after CLKBi
th(Sl) Hold time, SilO, Sill, and BE after ClKBi 2 2 2 ns
th(SW) Hold time, SWO and SWI after ClKBi 0 0 0 ns
thCPG) Hold time, ODD/EVEN and PGB after ClKBit 0 0 0 ns
th(RS) Hold time, RST low after ClKAi or ClKBi+ 5 6 7 ns
th(FS) Hold time, FSO and FSI after RST high 4 4 4 ns
tskl§ Skew time between ClKAi and ClKBi for EF and FF 8 8 10 ns
tsk2§ Skew time between ClKAi and ClKBi for AE and AF 9 16 20 ns
t Only applies for a clock edge that does a FIFO read
:j: Requirement to count the clock edge as one of at least four needed to reset a FIFO
§ Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and
ClKB cycle.

~TEXAS
INSTRUMENTS
12-30 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBSI28E-JULY 1992- REVISED FEBRUARY 1996

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 30 pF (see Figures 4 through 18)
'ABT3613-15 'ABT3613-20 'ABT3613-30
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
ta Access time, ClKAito AO-A35 and ClKBi to BO-B35 2 10 2 12 2 15 ns
tod(C-FFI Propagation delay time, ClKAi to FF 2 10 2 12 2 15 ns
tpdCC-EFI Propagation delay time, ClKBi to EF 2 10 2 12 2 15 ns
tod(C-AEI Propagation delay time, ClKBi to AE 2 10 2 12 2 15 ns
tpdCC-AFI Propagation delay time, ClKAi to AF 2 10 2 12 2 15 ns
Propagation delay time, ClKAi to MBFl low or MBF2 high and
tpd(C-MF) 1 9 1 12 1 15 ns
ClKBi to MBF2 low or MBFl high
Propagation delay time, ClKAi to BO- B35t and ClKBi to
tpd(C-MR) 3 11 3 12 3 15 ns
AD-A35:!:
tpdCC-PEI§ Propagation delay time, ClKBi to PEFB 2 11 2 12 2 13 ns
!Pd(M-DVl Propagation delay time, Sill, SilO to BO-B35 valid 1 11 1 11.5 1 12 ns
Propagation delay time, AD-A35 valid to PEFA valid; BO-B35
tpd(D-PE) 3 10 3 11 3 13 ns
valid to PEFB valid
tpdCO-PEI Propagation delay time, ODD/EVEN to PEFA and PEFB 3 11 3 12 3 14 ns
Propagation delay time, ODD/EVEN to parity bHs (AB, A17, A26,
tpd(O-PB)'11 2 12 2 13 2 15 ns
A35) and (BB,B17,B26,835)
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to
tpd(E-PE) 1 11 1 12 1 14 ns
PEFA; CSB, ENB, WiRB, Sill, SilO, or PGB to PEFB "'

Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to 1-

tpd(E-PB)'11 parity bits (AB, A17, A26, A35); CSB, ENB, WiRB, Sill, SilO, or 3 12 3 13 3 14 ns
PGB to parity bHs (BB, B17, B26, B35)
Propagation delay time, RSf to AE, EF low and AF, MBF1,
tpd(R-F) 1 15 1 20 1 25 ns
MBF2high
Enable time, CSA and W/RA low to AD-A35 active and CSB low
ten 2 10 2 12 2 14 ns
and W/RB high to BO-B35 active
Disable time, GSA or W/RA high to AO-A35 at high impedance .1
ldis B 1 9 1 11 ns
and CSB high or WiRB low to BO- 835 at high impedance
.. data to the malll
t Writing register when the BO-835 outputs are active and Sill and SilO are high
:!: Writing data to the mail2 register when the AO-A35 outputs are active and MBA is high
§ Only applies when a new port-B bus size is implemented by the rising ClKB edge
'II Only applies when reading data from a mail register

:II 1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-31
SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E - JULY 1992 - REVISED FEBRUARY 1996

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400 I I I I _I
'data = 1/2 'clock VCC=5.5V /
350 -TA=25°C
ct CL=OpF V
E
I 300
/ /
'E VCC=5( V
~
::I 250
/ / ./
/ ~ V~
0
~
c. 200
c.
::I
II)
I
150
V; 0 V VCC =4.5V
S
0
0
100 k% ~
50

o
,~ V

o 10 20 30 40 50 60 70 80
'clock - Clock Frequency - MHz

Figure 19

calculating power dissipation

The ICC(!) current for the graph in Figure 19 was taken while simultaneously reading and writing the FIFO on
the SN74ACT3613 with ClKA and ClKB set to fclock. All data inputs and data outputs change state during each
clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to
a zero-capacitance load. Once the capacitive load per data-output channel is known, the power dissipation can
be calculated with the equation below.
With ICC(!) taken from Figure 19, the maximum power dissipation (PT) of the SN7 4ABT3613 can be calculated
by:
PT = VCC x ICC(f) + :E[CL x (VOH - VOLl2 x fol
where:
CL = output capacitive load
fo = switching frequency of an output
VOH = high-level output voltage
VOL = low-level output voltage
When no reads or writes are occurring on the SN74ABT3613, the power dissipated by a single clock (ClKA
or ClKB) input running at frequency fclock is calculated by:
PT = VCC x fclock x 0.29 mA/MHz

~TEXAS
INSTRUMENTS
12-32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3613
64 x 36 CLOCKED FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128E- JULY 1992- REVISED FEBRUARY 1996

PARAMETER MEASUREMENT INFORMATION

SV

1.1 k.Q

From Output
Under Test - - e - - - -____

680n 30pF
(see Note A)

LOAD CIRCUIT

Timing
Input
i 1.S V
3V High-Level
Input --If~-;-.~
,.". ~ - 3V
GND
-----'.q. - - - - - GND
tsu~th 14-
I
tw --+I
I
~ -:-" -:- -
~ 1.S V ~
Data, 3V
Enable J"" 1.S V ~ Low-Level 3V
Input GND Input ~ _:.. -:..:: _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

~~:~~ Jf1.SV \~;V--- ::0

~ I+- tPZL
Low-Level IIi+- tPLZ ......:
._----;-..,.1---- ~3V

Input
Output --I-.JI :
VOL
~ ~tpZH
I VOH
High-Level
Output I I In-Phase
=OV
~
Output
:+-tPHZ

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 20. Load Circuit and Voltage Waveforms

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 12-33
12-34
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F- JUNE 1992 - REVISED FEBRUARY 1996

• Free-Running ClKA and ClKB Can Be • EFA, FFA, AEA, and AFA Flags
Asynchronous or Coincident Synchronized by ClKA
• Two Independent 64 x 36 Clocked FIFOs • EFB, FFB, AEB, and AFB Flags
Buffering Data In Opposite Directions Synchronized by ClKB
• Mailbox Bypass Register for Each FIFO • Passive Parity Checking on Each Port
• Dynamic Port-B Bus Sizing of 36 Bits (long • Parity Generation Can Be Selected for Each
Word), 18 Bits (Word), and 9 Bits (Byte) Port
• Selection of Blg- or little-Endian Format for • low-Power Advanced BiCMOS Technology
Word and Byte Bus Sizes • Supports Clock Frequencies up to 67 MHz
• Three Modes of Byte-Order Swapping on • Fast Access Times of 10 ns
Port B
• Package Options Include Space-Saving
• Programmable Almost-Full and 12Q.Pln Thin Quad Flat (PCB) and 132-Pin
Almost·Empty Flags Quad Flat (PQ) Packages
• Microprocessor Interface Control logic

description
The SN74ABT36i4 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock
frequencies up to 67 MHz and has read-access times as fast as 10 ns. Two independent 64 x 36 dual-port SRAM
FI FOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags (almost full and almost empty) to indicate when a selected number of words is
stored in memory. FIFO data on port B can be input and output in 36-bit, is-bit, and 9-bit formats with a choice
of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size
selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port
and can be ignored if not desired. Parity generation can be selected for data read from each port.
The SN74ABT36i4 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
cOincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses controlled by a synchronous interface.
The full flag and almost-full flag of a FIFO are two-stage synchronized to the port clock that writes data to its
array. The empty flag and almost-empty flag of a FIFO are two-stage synchronized to the port clock that reads
data from its array.
The SN74ABT36i4 is characterized for operation from O°C to 70°C.
For more information on this device family, see the application reports FIFO Mailbox-Bypass Registers: Using
Bypass Registers to Initialize DMA Control, Advanced Bus-Matching/Byte-Swapping Features for
Internetworking FIFO Applications, Parity-Generate and Parity-Check Features for High-Bandwidth-
Computing FIFO Applications, and Internetworking the SN74ABT3614 in the 1996 High-Performance FIFO
Memories Designer's Handbook, literature number SCAAOi2A.

Copyright © 1996, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-35
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
seBS' 26F - JUNE' 992 - REVISED FEBRUARY' 996

PCB PACKAGE
(TOP VIEW)

~~~~~~~~~~~~~~~~~~~o8m~~~~~~~m
A23 1 --------------------- 00 B22
A22 2 89 B21
A21 3 88 GND
GND 4 87 B20
A20 5 86 B19
A19 6 85 B18
A18 7 84 B17
A17 8 83 B16
A16 9 82 B15
A15 10 81 B14
A14 11 80 B13
A13 12 79 B12
A12 13 78 B11
A11 14 77 B10
A10 15 76 GND
GND 16 75 B9
A9 17 74 B8
A8 18 73 87
A7 19 72 Vee
Vee 20 71 B6
A6 21 70 B5
A5 22 69 B4
A4 23 68 B3
A3 24 67 GND
GND 25 66 B2
A2 26 65 B1
Al 27 64 BO
AD 28 63 EFB
EFA 29 62 AEB
AEA 30 61 AFB
M~~~~~~~~~~~~~~~~~~~~~~~~~~~~g

~1ExAs
INSTRUMENTS
12-36 POST OffiCE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

PQPACKAGEt
(TOP VIEW)

GND GND
AEA AE8
EFA EF8
AO 80
Al 81
A2 82
GND GND
A3 83
A4 84
A5 85
A6 86
VCC VCC
A7 87
A8 88
A9 89
GND GND
Al0 810
All 811
VCC VCC
A12 812
A13 813
A14 814
GND GND
A15 815
A16 816
A17 817
A18 818
A19 819
A20 820
GND GND
A21 821
A22 822
A23 823

NC - No internal connection
t Uses Yamaichi socket IC51-1324-828

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-37
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

functional block diagram

ClKA
CSA Port·A
WiRA Control
.-------------------------------- MBF1
ENA logic
1 r-:pa-r~lty--~I----------------PEFB
MBA
.,.;.-t-+.....I-t-_ _ _+-tIr--~M~a~II-1 --,r:t----..JGeniCheck,hI-+----""
c=l====~:IL-_R~e~g~ls~te~r__~~~==~==~~===t~-----PGB
r-~----------~-~l~~
~~
1 .- ,.,,:;::5 ir IR\
1 CIa. CI
I &]I. 64x36 • 'E" ~ • ~ Ii ~ t}, 1
i II': SRAM ~ c () ~,.... - I
.....++---HI-II+-f 1 t1 i': j H---,
RST-
Device
0001 __ Control
I1 .5
i.- ,i.--
gj~
.!.... -
a I
I
36

EVEN

I1 I Write
Pointer
I Read
Pointer
I
I
1
1
1 t t l
FFA --4------+-+-++-+--+,1-----1 Status.Flag 1
AFA I logic 1
FIF01
36 L _ _ _ _ _ _~-----------~

FSO---------+~-rr-------; Programmable-Flag
FS1---------+~-rr-------; Offset Register
AO-A3S--4-...---t BO-B35
r- -----.-- -,
I FIF02
EFA --4-----++-+-+-I--~!f----------f Status-Flag
I !
,I----------I!---I-+-++-II------ FFB
AEA ! logic I ! AFB
I + + I
!1 I
I
Read
Pointer
I Write
Pointer
I
I
II 36

I I
I~ ~ "i: - 1
~i 5 ~i ~~
I ~j f4 fl f4 ~R~!: f+~! + i
t
I
~a
a. :E '5 ~.i-+++-I-+o"
~~ I ~1Il
G)

I 0 ! 1

PGA
~~ L~-1F-------=.=--~-J
Mall2
Parity
L-_ _ _ 4.r
.....'-I WI-4-L,..!R~eg~ls~te~r__j-4---_::t:ttt:tt~
ClKB
PEFA ----------011------1 Gen/Check
1 - + - - CSB
MBF2---------~I-------------~ WiRB
Port·B ENB
H--BE
Control
SIZO
logic SIZ1
H--SWO
L_-.J-+----- SW1

~1ExAs
INSTRUMENTS
12-38 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F -JUNE 1992 - REVISED FEBRUARY 1996

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME
AO-A35 1/0 Port-A data. The 36-bit bidirectional data port for side A.
0 Port-A almost-empty flag. Programmable flag synchronized to ClKA. AEA is low when the number of 36-bit words
AEA
(portA) in FIF02 is less than or equal to the value in offset register X.
0 Port-B almost-empty flag. Programmable lIag synchronized to ClKB. AEB is low when the number of 36-bit words
AEB
(port B) in FIFOI is less than or equal to the value in offset register X.
0 Port-A almost-full lIag. Programmable lIag synchronized to ClKA. AFA is low when the number of 36-bit empty
AFA
(portA) locations in FIFOI is less than or equal to the value in offset register X.
0 Port-B almost-full lIag. Programmable lIag synchronized to ClKB. AFB is low when the number of 36-bit empty
AFB
(port B) locations in FIF02 is less t~an or equal to the value In offset register X.
BO-B35 I/O Port-B data. The 36-bit bidirectional data port for side B.
Big-endian select. Selects the bytes on port B used during byte or word data transfer. A low on BE selects the most
BE I
significant bytes on BO - 835 for use, and a high selects the least significant bytes.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
ClKA I
or coincident to ClKB. EFA, FFA, AFA, and AEA are synchronized to the low-te-high transition of ClKA.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
ClKB I or coincident to ClKA. Port-B byte swapping and data-port-sizing operations are also synchronous to the low-te-high
transHion of ClKB. EFB, FFB. AFB, and AEB are synchronized to the low-te-high transition of ClKB.
Port-A chip select. CSA must be low to enable a low-to-hlgh transition of ClKA to read or write data on port A. The
CSA I
AO-A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-te-high transHion of ClKB to read or wrHe data on port B. The
CSB I
80- 835 outputs are in the high-impedance state when CSB is high.
Port-A empty lIag. EFA is synchronized to the low-te-high transition of ClKA. When EFA is low, FIF02 is empty and
0 reads from Hs memory are disabled. Data can be read from FI F02 to the output register when EFA is high. EFA is forced
EFA
(portA) low when the device is reset and is set high by the second low-to-high transition of ClKA after data is 10adedJnto empty
FIF02 memory.
Port-B empty lIag. EFB is synchronized to the low-te-high transition of ClKB. When EFB is low, FIFOI is empty and
0 reads from its memory are disabled. Data can be read from FIFOI to the output register when EFB is high. EFB is
EFB
(port B) forced low when the device Is reset and is set high by the second low-te-high transition of ClKB after data is loaded
into empty FIF01 memory.
ENA I Port-A enable. ENA must be high to enable a low-te-high transition of ClKA to read or write data on port A.
ENB I Port-B enable. ENB must be high to enable a low-te-high transition of ClKB to read or write data on port B.

0
Port-A lull flag. mis synchronized to the low-te-high transition of ClKA. When FFA is low, FIFOI is full and writes
FFA to its memory are disabled. FFA is forced low when the device is reset and is set high by the second low-te-high
(portA)
transition of ClKA after reset.
Port-Bfull flag. FFB is synchronized to the low-te-high transition of ClKB. When FFB is low, FIF02 is full and writes
0
FFB to its memory are disabled. FFB is forced low when the device is reset and is set high by the second low-te-high
(port B)
transHion of ClKB after reset.
Flag offset selects. The low-te-high transHion of RST latches the values 01 FSO and FS1, which selects one of four
FS1, FSO I
preset values for the almost-empty lIag and aimost-fuliliag offset.
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
MBA I AO- A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects
FIF02 output register data for output.
Maill register flag. MBFl is set low by the low-to-high transition of ClKA that writes data to the mail1 register. Writes
MBF1 0 to the mail 1 register are inhibited while MBF1 is low. MBFl is set high by a low-te-high transition 01 ClKB when a port-B
read Is selected and both SIZI and SIZO are high. MBFl is set high when the device is reset.
Mail2 register flag. MBF2 is set low by the low-te-high transition of ClKB that writes data to the mail2 register. Writes
MBF2 0 to the mail2 register are inhibHed while MBF2 is low. MBF2 is set high by a low-to-high transition of ClKA when a port-A
read is selected and MBA is high. MBF2 is set high when the device is reset.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 12-39
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

Terminal Functions (Continued)

TERMINAL
I/O DESCRIPTION
NAME
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/
I ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
EVEN
for a read operation.
Port-A parity-error flag. When any byte applied to terminals AO-A35 fails parity. PEFA is low. Bytes are organized as
AO-AS. A9-A17. A1S-A26. and A27-A35. with the most significant bit of each byte serving as the parity bit. The
PEFA
a type of parity checked is determined by the state of the ODD/EVEN input.
(portA) The parity trees used tochecktheAO-A35 inputs are shared by the mail2 register to generate parity if parity generation
is selected by PGA; therefore. if a mail2 read with parity generation is setup by having W/RA low. MBA high. and PGA
high. the PEFA flag is forced high regardless of the state of the AO-A35 inputs.
Port-B parity-error flag. When any valid byte applied to terminals BO- B35 fails parity, PEFB is low. Bytes are organized
as BO-BS, B9-B17, B18-B26. and B27-B35, with the most significant bit of each byte serving as the parity bit. A
byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by the state
PEFB
a of the ODD/EVEN input.
(port B)
The parity trees used to check the BO- B35 inputs are shared by the mail1 register to generate parity if parity generation
is selected by PGB; therefore, if a mail1 read with parity generation is set up by having W/RB low, SIZ1 and SIZO high,
and PGB high, the PEFB flag is forced high regardless of the state of the BO-B35 inputs.
Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity generated
PGA I is selected by the state of the ODD/EVEN input. Bytes are organized as AO-AB, A9-A17, A18-A26, and A27 -A35.
The generated parity bits are output in the most significant bit of each byte.
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated
PGB I is selected by the state of the ODD/EVEN input. Bytes are organized as BO-B8, B9-B17, B18-B26, and B27-B35.
The generated parity bits are output in the most significant bit of each byte.
Reset. To reset the device, four low-to-high transitions of ClKA and four low-to-high transitions of ClKB must occur
while RST is low. This sets the AFA, AFB, MBF1, and MBF2 flags high and the EFA, EFB, AEA, AEB, FFA, and FFB
RST I
flags low. The low-to-high transition of RST latches the status of the FS1 and FSO inputs to select almost-full flag and
almost-empty flag offset.
Port-B bus-size selects. The low-to-high transition of ClKB latches the states of SIZO, SIZ1, and BE, and the following
I
SIZO,SIZl low-to-high transition of ClKB implements the latched states as a port-B bus size. Port-B bus sizes can be long word,
(port B)
word, or byte. A high on both SIZO and SIZ1 accesses the mailbox registers for a port-B 36-bit write or read.
Port-B byte-swap selects. At the beginning of each long word transfer, one of four modes of byte-order swapping is
I
SWO,SW1 selected by SWO and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order
(port B)
swapping is possible with any bus-size selection.
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
W/RA I
low-to-high transition of ClKA. The AO-A35 outputs are in the high-impedance state when W/RA is high.
Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
W/RB I
low-to-high transition of ClKB. The BO-B35 outputs are in the high-impedance state when W/RB is high.

detailed description
reset
The SN74ABT3614 is reset by taking the reset (RST) input low for at least four port-A clock (ClKA) and four
port-B clock (ClKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the
empty flags (EFA, EFB) low, the almost-empty flags (AEA, AEB) low, and the almost-full flags (AFA, AFB) high.
A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high
transitions of ClKA and FFB is set high after two low-to-high transitions of ClKB. The device must be reset after
power up before data is written to its memory.
A low-to-high transition on HST loads the almost-full and almost-empty offset register (X) with the value selected
by the flag-select (FSO, FS1) inputs. The values that can be loaded into the register are shown in Table 1.

-!I1lExAs
INSTRUMENTS
12-40 POST OFFICE eox 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

reset (continued)

Table 1. Flag Programming

ALMOST· FULL ~ND
FS1 FSO RST ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H H i 16
H L i 12
L H i 8
L L i 4

FIFO write/read operation

The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (WiRA). The AO-A35 outputs are in the high-impedance state when either CSA or WiRA is
high. The AO-A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIF01 from the
AO-A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low,
and FFA is high. Data is read from FIF02 to the AO-A35 outputs by a low-to-high transition of CLKA when CSA
is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2).

Table 2. Port-A Enable Function Table

CSA W/RA ENA, MBA CLKA AO-A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L i In high-impedance state FIF01 write
L H H H i In high-impedance state Maill write
,L L L L X Active, FIF02 output register None
L L H L i Active, FIF02 output register FIF02 read
L L L H X Active, mail2 register None
L L H H i Active, mail2 register Mail2 read (set MBF2 high)

The state of the port-B data (BO-B35) outputs is controlled by the port-B chip select (CSB) and the port-B
write/read select (W/RB). The BO-B35 outputs are in the high-impedance state when either CSB or W/RB is
high. The BO-B35 outputs are active when both CSB and W/RB are low. Data is loaded into FIF02 from the
BO-B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, FFB is high,
and either SIZO or SIZ1 is low. Data is read from FIF01 to the BO-B35 outputs by a low-to-high transition of
CLKB when CSB is low, W/RB is low, ENB is high, EFB is high, and either SIZO or SIZ1 is low (see Table 3).
The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select
can change states during the setup- and hold-time window of the cycle.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75266 12-41
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

FIFO writer/read operation (continued)

Table 3. Port-B Enable Function Table

CSB W/RB ENB SIZ1, SIZO ClKB BO-B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H One, both low l' In high-impedance state FIF02 write
L H H Both high l' In high-impedance state Mail2write
L L L One, both low X Active, FIFOI output register None
L L H One, both low l' Active, FI Fat output register FIFOI read
L L L Both high X Active, maill register None
L L H Both high l' Active, mail 1 register Maill read (set MBFl high)

synchronized FIFO flags

Each FI FO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability
by reducing the probability of metastable events on the output when ClKA and ClKB operate asynchronously
to one another (see the application report Metastability Performance of Clocked FIFOs in the 1996
High-Performance FIFO Memories Data Book, literature number SCAD003C). EFA, AEA, FFA, and AFA are
synchronized to ClKA. EFB, AEB, FFB, and AFB are synchronized to ClKB. Tables 4 and 5 show the
relationship of each port flag to FIF01 and FIF02.

Table 4. FIF01 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF 36·BIT TOClKB TOClKA
WORDS IN FIFOlt
EFB AEB AFA FFA
0 L L H H
1 toX H L H H
(X + 1) to [64 - (X + 1)] H H H H
(64-X) to 63 H H L H
64 H H L L
t X IS the value In the almost-empty flag and almost-full flag offset register.

Table 5. FIF02 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF 36-BIT TOClKA TOClKB
WORDS IN FIF02t
EFA AEA AFB FFB
0 L L H H
1 to X H L H H
(X+ l)to[64-(X+ 1)] H H H H
(64 -X) to 63 H H L H
64 H H L L
t X is the value in the almost-empty flag and almost-full flag offset register.

~lEXAS
INSTRUMENTS
12-42 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

empty flags (EFA, EFB)

The FIFO empty flag is synchronized to the port clock that reads data from its array. When the empty flag is high,
new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and attempted
FIFO reads are ignored. When reading FIF01 with a byte or word size on port S, EFS is set low when the fourth
byte or second word of the last long word is read.
The FIFO read pointer is incremented each time a new word is clocked to the output register. The state machine
that controls an empty flag monitors a write-pointer and read-pointer comparator that indicates when the FI FO
SRAM status is empty, empty+ 1, or empty+2. A word written to a FIFO can be read to the FIFO output register
in a minimum of three cycles of the empty flag synchronizing clock; therefore, an empty flag is low if a word in
memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data
from the FIFO have not elapsed since the time the word was written. The FIFO empty flag is set high by the
second low-to-high transition of the synchronizing clock and the new data word can be read to the FIFO output
register in the following cycle.
A low-to-high transition on an empty-flag synchronizing clock begins the first synchronization cycle of a write
if the clock transition occurs at time tsk1 ' or greater, after the write. Otherwise, the subsequent clock cycle can
be the first synchronization cycle (see Figures 13 and 14).
futl flags (FFA, FFB)
The FIFO full flag is synchronized to the port clock that writes data to its array. When the full flag is high, a
memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is
low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a full
flag monitors a write-painter and read-pointer comparator that indicates when the FIFO SRAM status is full,
full-1, or full-2. From the time a word is read from a FIFO, the previous memory location is ready to be written
in a minimum of three cycles of the full-flag synchronizing clock. A full flag is low if less than two cycles of the
full-flag synchronizing clock have elapsed since the next memory write location has been read. The second
low-to-high transition on the full-flag synchronizing clock after the read sets the full flag high and data can be
written in the following clock cycle.
A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the
clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the
first synchronization cycle (see Figures 15 and 16).
almost-empty flags (AEA, AEB)
The FIFO almost-empty flag is synchronized to the port clock that reads data from its array. The state machine
that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that indicates when
the FIFO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty state is defined
by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset
values during a device reset (see reset). An almost-empty flag is low when the FIFO contains X or.less long
words in memory and is high when the FIFO contains (X + 1) or more long words.
Two low-to-high transitions of the almost-empty-flag synchronizing clock are required after a FIFO write for the
almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1)
or more long words remains low if two cycles of the synchronizing clock have not elapsed since the write that
filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of
the synchronizing clock after the FI FO write that fills memory to the (X + 1) level. A low-to-high transition of an
almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater,
after the write that fills the FIFO to (X + 1) long words. Otherwise, the subsequent synchronizing clock cycle can
be the first synchronization cycle (see Figures 17 and 18).

-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 12-43
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

almost-full flags (AFA, AFB)

The FIFO almost-full flag is synchronized to the port clock that writes data to its array. The state machine that
controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO
SRAM status is almost full, almost full-1 , or almost full-2. The almost-full state is defined by the value of the
almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a
device reset (see reset). An almost-full flag is low when the FIFO contains (64 - X) or more long words in
memory and is high when the FIFO contains [64 - (X + 1)] or less long words.
Two low-to-high transitions of the almost-full-flag synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [64 - (X + 1)]
or less words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced
the number of long words in memory to [64 - (X + 1)]. An almost-full flag is set high by the second low-to-high
transition of the synchronizing clock after the FIFO read that reduces the number of long words in memory to
[64 - (X + 1)]. A low-to-high transition of an almost-full-flag synchronizing clock begins the first synchronization
cycle if it occurs at time tsk2, or greater, after the read that reduces the number of long words in memory to
[64 - (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see
Figures 19 and 20).
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port data transfer operation. A low-to-high transition on ClKA writes AO-A35 data to the mail1 register
when a port-A write is selected by CSA, WiRA, and ENA, and MBA is high. A low-to-high transition on ClKB
writes BO-B35 data to the mail2 register when a port-B write is selected by CSB, WiRB, and ENB and both SIZO
and SIZ1 are high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted
writes to a mail register are ignored while the mail flag is low.
When the port-A data outputs (AO-A35) are active, the data on the bus comes from the FIF02 output register
when MBA is low and from the mail2 register when MBA is high. When the port-B data outputs (BO-B35) are
active, the data on the bus comes from the FIF01 output register when either one or both SIZ1 and SIZO are
low and from the mail2 register when both SIZ1 and SIZO are high. The mail1 register flag (MBF1) is set high
by a rising ClKB edge when a port-B read is selected by CSB, W/RB, and ENB and both SIZ1 and SIZO are
high. The mail2 register flag (MBF2) is set high by a rising ClKA edge when a port-A read is selected by CSA,
W/RA, and ENA and MBA is high. The data in the mail register remains intact after it is read and changes only
when new data is written to the register.
dynamic bus sizing
The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FI F01
or written to FIF02. Word- and byte-size bus selections can utilize the most significant bytes of the bus (big
endian) or least significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and
synchronous to ClKB to communicate with peripherals of various bus widths.
The levels applied to the port-B bus-size select (SIZO, SIZ1) inputs and the big-endian select (BE) input are
stored on each ClKB low-to-high transition. The stored port-B bus-size selection is implemented by the next
rising edge on ClKB according to Figure 1.
Only 36-bit long-word data is written to or read from the two FIFO memories on the SN74ABT3614.
Bus-matching operations are done after data is read from the FIF01 RAM and before data is written to the FIF02
RAM. Port-B bus sizing does not apply to mail-register operations.

-!I1TEXAS
INSTRUMENTS
12-44 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F -JUNE 1992 - REVISED FEBRUARY 1996

dynamic bus sizing (continued)

c:::J 0
A35 A27 A26 A18 A17 A9 A8 AO

BYTE ORDER ON PORT A: ~ ~ Write to FIF01/Read From FIF02

B35 B27 B26 B18 B17 B9 B8 BO

BE

X
SIZ1

L
SIZO

L
c:::J 0 ~ ~ Read From FIF01IWrite to FIF02

(a) LONG WORD SIZE

B35 B27 B26 B18 B17 B9 B8 BO

BE

L
SIZ1

L
SIZO

H
Q 0 ~ ~ 1st: Read From FIF01/Write to FIF02

B35 B27 B26 B18 B17 B9 B8 BO

~ G ~ ~ 2nd: Read From FIF01IWrite to FIF02

(b) WORD SIZE - BIG ENDIAN

B35 B27 B26 B18 B17 B9 B8 BO

BE

H
SIZ1 SIZO
~ ~ ~ ~ 1st:ReadFromFIF01/WrltetoFIF02
L H

0 0
B35 B27 B26 B18 B17 B9 B8 BO

~ ~ 2nd: Read From FIF01IWrite to FIF02

(e) WORD SIZE - LITTLE ENDIAN

B35 B27 B26 B18 B17 B9 B8 BO

BE
L
SIZ1

H
SIZO Q ~ ~ ~ 1st:ReadFromFIF01lWrltetoFIF02
L

8
B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ 2nd: Read From FIF01IWrite to FIF02

B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ ~ 3rd: Read From FIF01IWrite to FIF02

o
B35 B27 B26

~
B18 B17

~
(d) BYTE SIZE - BIG ENDIAN
B9 B8

~
BO

4th: Read From FIF01IWrite to FIF02

Figure 1. Dynamic Bus Sizing

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-45
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

dynamic bus sizing (continued)

B35 827 826 818 817 89 88 80

BE

H
SIZ1

H
SIZO

L
~ ~ ~ 8 1st: Read From FIF01lWrlte to FIF02

835 827 828 818 817 89 88 80

~ ~ ~ 8 2nd: Read From FIF01lWrlte to FIF02

835 827 826 818 817 89 88 80

~ ~ ~ 0 3rd: Read From FIF01/Writeto FIF02

0
835 827 826 818 B17 89 88 80

~ ~ ~ 4th: Read From FIF01IWriteto FIF02

(e) 8YTE SIZE - LlnLE ENDIAN

Figure 1. Dynamic Bus Sizing (continued)

bus-matching FIF01 reads

Data is read from the FIF01 RAM in 36-bit long-word increments. If a long-word bus size is implemented, the
entire long word immediately shifts to the FIF01 output register. If byte or word size is implemented on port B,
only the first one or two bytes appear on the selected portion of the FIF01 output register with the rest of the
long word stored in auxiliary registers. In this case, subsequent FIF01 reads with the same bus-size
implementation output the rest of the long word to the FIF01 output register in the order shown by Figure 1.
Each FIF01 read with a new bus-size implementation automatically unloads data from the FIF01 RAM to its
output register and auxiliary registers. Therefore, implementing a new port-B bus size and performing a FIF01
read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread
long-word data.
When reading data from FIF01 in byte or word format, the unused BO-B35 outputs remain inactive but static
with the unused FIF01 output register bits holding the last data value to decrease power consumption.
bus-matching FIF02 writes
Data is written to the FIF02 RAM in 36-bit long-word increments. FIF02 writes with a long-word bus size
immediately store each long word in FIF02 RAM. Data written to FIF02 with a byte or word b.us size stores the
initial bytes or words in auxiliary registers. The elKB rising edge that writes the fourth byte or the second word
of long word to FIF02 also stores the entire long word in FIF02 RAM. The bytes are arranged in the manner
shown in Figure 1.
Each FIF02 write with a new bus-size implementation resets the state machine that controls the data flow from
the auxiliary registers to the FIF02 RAM. Therefore, implementing a new bus size and performing a FIF02 write
before bytes or words stored in the auxiliary registers have been loaded to FIF02 RAM results in a loss of data.

~TEXAS
INSTRUMENTS
12-46 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F -JUNE 1992 - REVISED FEBRUARY 1996

part-S mali-register access

In addition to selecting port-B bus sizes for FIFO reads and writes, the port-B bus size select (SilO, Sill) inputs
also access the mail registers. When both SilO and Sill are high, the maill register is accessed for a port-B
long-word read and the mail2 register is accessed for a port-B long-word write. The mail register is accessed
immediately. Any bus-sizing operation that is underway is unaffected by the mail-register access. After the
mail-register access is complete, the previous FIFO access can resume in the next elKB cycle. The logic
diagram in Figure 2 shows that the previous bus-size selection is preserved when the mail registers are
accessed from port B. A port-B bus size is implemented on each rising elKB edge according to the states of
SllO_Q, SllCQ, and BE_Q.

elKB

-v '--
~1
MUX

-1
SIZO_Q
0 Q SIZ1_Q
SIZO BE_Q
SIZ1 "1
BE

Figure 2. Logic Diagram for SIZO, SIZ1, and BE Register

byte swapping
The byte-order arrangement of data read from FIFOl or data written to FIF02 can be changed synchronous
to the rising edge of elKB. Byte-order swapping is not available for mail-register data. Four modes of byte-order
swapping (including no swap) can be done with any data-part-size selection. The order of the bytes are
rearranged within the long word, but the bit order within the bytes remains constant.
Byte arrangement is chosen by the port-B swap select (SWO, SW1) inputs on a elKB rising edge that reads
a new long word from FIFOl or writes a new long word to FIF02. The byte order chosen on the first byte or first
word of a new long-word read from FIFOl or written to FIF02 is maintained until the entire long word is
transferred, regardless of the SWO and SWl states during subsequent writes or reads. Figure 3 is an example
of the byte-order swapping available for long words. Performing a byte swap and bus size simultaneously for
a FIFOl read first rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 1.
Simultaneous bus-sizing and byte-swapping operations for FIF02 writes load the data according to Figure 1,
then swap the bytes as shown in Figure 3 when the long word is loaded to FIF02 RAM.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-47
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

byte swapping (continued)

A35 A27 A26 A18 A17 A9 A8 AO

~
~

6666
B35 B27 B26
Ca) NO SWAP
B18 B17 B9 B8 BO

A35 A27 A26 A18 A17 A9 A8 AO

ffi L H

B35 B27 B26 B18 B17 B9 B8 BO

(e) WORD SWAP

A35 A27 A26 A18 A17 A9 A8 AO

~
~

B35 B27 B26 B18 B17 B9 B8 BO

Cd) BYTE-WORD SWAP

Figure 3_ Byte Swapping (Long-Word Size Example)

~lEXAS
INSTRUMENTS
12-48 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F- JUNE 1992 - REVISED FEBRUARY 1996

parity checking
The port-A data inputs (AO-A35) and port-B data inputs (BO- B35) each have four parity trees to check the parity
of incoming (or outgoing) data. A parity failure on one or more bytes of the port-A data bus is reported by a low
level on the port-A parity error flag (PEFA). A parity failure on one or more bytes of the port-B data inputs that
are valid for the bus-size implementation is reported by a low level on the port-B parity-error flag (PEFB). Odd-
or even-parity checking can be selected, and the parity-error flags can be ignored if this feature is not desired.
Parity status is checked on each input bus according to the level of the oddfeven parity (ODDfEVEN) select
input. A parity error on one or more valid bytes of a port is reported by a low level on the corresponding
port-parity-error flag (PEFA, PEFB) output. Port-A bytes are arranged as AD-AS, A9-A 17, A 18-A26, and
A27-A35. Port-B bytes are arranged as BO-B8, B9-B17, B18-B26, and B27-B35, and its valid bytes are
those used in a port-B bus-size implementation. When oddfeven parity is selected, a port-parity-error flag
(PEFA, PEFB) is low if any valid byte on the port has an oddfeven number of low levels applied to the bits.
The four parity trees used to check the AO-A35 inputs are shared by the mail2 register when parity generation
is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is
selected with CSA low, ENA high, WiRA low, MBA high, and PGA high, the port-A parity-error flag (PEFA) is
held high regardless of the levels applied to the AO-A35 inputs. Likewise, the parity trees used to check
the BO-B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads
(PGB = high). When a port-B read from the mail1 register with parity generation is selected with CSB low, ENB
high, and WiRB low, both SIZO and SIZ1 high, and PGB high, the port-B parity-error flag (PEFB) is held high
regardless of the levels applied to the BO-B35 inputs.
parity generation
A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the
SN7 4ABT3614 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged
as AO-A8, A9-A 17, A 18-A26, and A27 -A35, with the most significant bit of each byte used as the parity bit.
Port-B bytes are arranged as BO-B8, B9-B17, B18-B26, and B27 -B35, with the most significant bit of each
byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte
regardless of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity
generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on
the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the most
significant bits of each byte as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the
output register. The port-A parity-generate select (PGA) and oddfeven parity select (ODDfEVEN) have setup-
and hold-time constraints to the port-A clock (ClKA) and the port-B parity generate select (PGB)' and
ODDfEVEN have setup and hold-time constraints to the port-B clock (ClKB). These timing constraints only
apply for a rising clock edge used to read a new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port-B bus (BO-B35) to check parity. The
circuit used to generate parity for the mail2 data is shared by the port-A bus (AO-A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in a mail register when the port chip
select (CSA, CSB) is low, enable (ENA, ENB) is high, writefread select (WiRA, WiRB) input is low, the mail
register is selected (MBA is high for port A; both SIZO and SIZ1 are high for port B), and port parity-generate
select (PGA, PGB) is high. Generating parity for mail register data does not change the contents of the register.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-49
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

ClKA
--.I I.- th(RS)
ClKB
I
....I I- tsu(RS) I : tsu(FS) ~ th(FS) I i
RST----~ I I : II i I
I i I I I I I
FS1,FSO

I tpd(C-FF) ~ tpd(C-FF) ~
FFA S\\\\\\y~" I 1'----
I tpd(C-EF) ~ H I
EFA S\\\\\\~ I
~ I I I
I tpd(C-FF) '+----+iI tpd(C-FF) ~
FFB S\\'>~~ y--
I tpd(C-EF) ~ ~
EFB~~
_ tpd(R-F) ~ I I I
~':F~ /lZZZZZ/lZZ/? :: :
tpd(C-AE) 14 I ~

AEA~~~~
tpd(C-AF) 14 I tI
AFA c/l22Z?Zll?/ZZZZZi,vzl)
tpd(C-AE) 14 ~

AEB~~\\$
tpd(C-AF) 14 ~

Figure 4. Device Reset Loading the X Register With the Value of Eight

~lExAs
INSTRUMENTS
12-50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F -JUNE 1992- REVISED FEBRUARY 1996

14 tc ~I

:.- tw(ClKH) t tw(ClKl) -+i

ClKA )t ~ ~ \ ( \ ( '----
I I I
FFA High
I I I
tsu(EN) 14 ,01 th(EN) I I
I I
CSA
tsU(EN)
~14 :~
~14 -I th(EN)
I
I
1/
I
I I
I
WiRA
Wllll/Zlll{ I~ I : \\\\\§\\S
tsu(EN) 14 _lUI
th(EN) I I
MBA I I I
tsu(EN} J.: ~ r th(EN) tsu(EN) ~ ~ th(EN)
ENA VZ?J22?Z22d I ~ ~\\\\\\\\\\ V""'Z""'/j""'Z""'Z""'/j""'Z""':;:""'Z""
tsU(D) 14 -101 th(D)
AO-A35 flo §Perallon >88&$8888
I I
=~:
tpd(D-PE) ~ tpd(D-PE) ~
:. ~
PEFA

tWritten to FIF01

Figure 5. Port-A Write-Cycle Timing for FIF01

-!II TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 12-51
SN74ABT3614
64·x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

ClKB ( \ ( \ ...._ _..,,/ \'-_ _--",

FFB High !
I
: tsU(EN)~
!
I
CSB tsU(EN)~-""';-:----------------+!J'--
I
WiRB /lZV$@flfll2'1

t SIZO =Hand SIZl =H writes data to the mail2 register.

DATA SWAP TABLE FOR lONG-WORD WRITES TO FIF02
SWAP MODE DATA WRITTEN TO FIF02 DATA READ FROM FIF02
SW1 SWO B35-B27 B26-B18 B17-B9 B8-BO A35-A27 A26-A18 A17-A9 A8-AO
L L A B C D A B C D
L H D C B A A B C D
H L C D A B A B C D
H H B A D C A B C D

Figure 6. Port-B Long-Word Write-Cycle Timing for FIF02

~1ExAs
INSTRUMENTS
12-52 POST OFFICE BOX 665303 • DAlLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

elKB ~'-_ _ _( , ( ,'-_ _ _(

1 1 1
1 1 1
High 1 1 1
1 1 1
I tsu(EN) 1+--+1 I~ th(EN)

WiRB ~I LJ--I!r--------+: tsu(EN) ....J)

'7"'l'7"?'7"?'7"?:'7"?'7"?'7"?~'7"?'7"?'7"?'7"?'7"?:'7"2'7"<.'7"?'7"?'7"?'7":dt+---+i ----------'JI-----
~~ ~ ~I th(EN)
ENB
vzzzzz¥mvmar ~ \\\\\\'0 tsu(EN) j4

1
-14

tsu(SZ) i4----iT---+l::th(SZ)
BE ;XXXX YX
tsu(SZ) _:I+----i~~ th(SZ) tsu(SZ) 1+1 -~-tI:i th(SZ)
SIZ1,SIZO ~ (0 II (0 1 Not (1 lIT
L
tsu(D) !+I -~-tI th(D)

little
Endlan
{
BO-B17 ;.;l ~~~:z8lS~~:z8lS~~t:=~jz~~~~C==:x;~~~Z~
tsu(D) ~ ~t ~~ ~
End~~~ {
B18-B35 ~'--~rr-'~ !'X~
ODD/EVEN ~ _ _ _ _ _ _ _ _ _ _ _~ _ _ _ _ _ _ _ _ _ _ _ _ _ _

I
--~-~:
PEFB .----:":'Va"":'!'lId-.--~

t SIZO = Hand SIZI = H writes data to the mail2 register.

NOTE A: PEFB indicates parity error for the following bytes: B35-B27 and B26-B18 for big-endian bus, and B17-B9 and B8-BO for little-
endian bus.

DATA SWAP TABLE FOR WORD WRITES TO FIF02

DATA WRITTEN TO FIF02
SWAP MODE WRITE DATA READ FROM FIF02
BIGENDIAN LITTLE ENDIAN
NO.
SWI SWO B35-B27 B26-B18 B17-B9 B8-BO A35-A27 A26-A18 A17-A9 A8-AO
1 A B C D
L L A B C D
2 C D A B
1 D C B A
L H A B C D
2 B A D C

H L
1 C D A B
A B C D
2 A B C D
H
1 B A D C
H A B C D
2 D C B A

Figure 7. Port-B Word Write-Cycle Timing for FIF02

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 12-53
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

ClKB
I I
I I
High I I
I I
Isu(EN) ~ Ih(EN) It-.!
I
I I'~+I 1_
I ________________________~.J' 1

I Isu(EN) H :
W/RB /7/7/"(7///4 I I
I ISU(EN)~~ ~ .r~
ENB~ I ~
I Isu(SW) ~ Ih(EN)
~~
S W 1 , S W O .
ISU~I I

BE ~
ISU I Ih(SZ) I I I
I Isu(SZ)· th(SZ)
SIZ1, SIZO (1,0) (1,0) (1,0) (1,0)
I
t::. ~ .. Not (1, l)t
Llttle{ BO-B8 _ _ _ _
Endian I
Bi9{
Endian B27-B35 _
::: ~ll
_ _
~l
_
I I I

ODD/EVEN ~ : : :.:~
tpd(C-PE) 14'+1 tpd(O-PE) H tpd(O-PE) H tpd(O-PE) H
PEFB
Valid
t SIZO = Hand SIZl
= H writes data to the mail2 register.
NOTE A: PEF8 indicates parity error for the following bytes: 835-827 for big-end ian bus and 817-89 for little-endian bus.

Figure 8. Port-B Byte Write-Cycle Timing for FIF02

~TEXAS
INSTRUMENTS
12-54 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F -JUNE 1992 - REVISED FEBRUARY 1996

DATA SWAP TABLE FOR BYTE WRITES TO FIF02

DATA WRITTEN
TOFIF02
SWAP MODE WRITE DATA READ FROM FIF02
BIG LITTLE
NO.
ENDIAN END IAN
SW1 SWO B35-B27 B8-BO A35-A27 A26-A18 A17-A9 AS-AD
1 A D
2 B C
L L A B C D
3 C B
4 D A
1 D A
2 C B
L H A B C D
3 B C
4 A D
1 C B
2 D A
H L A B C D
3 A D
4 B C
1 B C
2 A D
H H A B C D
3 D A
4 C B

Figure 8. Port-B Byte Write-Cycle Timing for FIF02 (Continued)

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-55
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

elKB \ ( \ \. . .-_...J!I '-

I I
I I
EFB High
I I
I I
___~------~-----~i---I
I
I I I
I
i bvA?

ten ~ I+-- ta --.I I+-- ta --tI tdls ~

BO-B35------------~~----t~:JP~~~V~IO~us~D~a~mL:jX------~W~1*~~---*------W-2~*-----)__
t SIZO = Hand SIZ1 = H selects the mail1 register for output on BO-B35.
:j: Data read from FIFOI

DATA SWAP TABLE FOR lONG·WORD READS FROM FIF01

DATA WRITTEN TO FIF01 SWAP MODE DATA READ FROM FIF01
A35-A27 A26-A18 A17-A9 A8-AO SW1 SWO B35-B27 B26-B18 B17-B9 B8-BO
A B C D L L A B C D
A B C D L H D C B A
A B C D H L C D A B
A B C D H H B A D C

Figure 9. Port-B Long-Word Read-Cycle Timing for FIF01

~1ExAs
INSTRUMENTS
12-56 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

''---~I
elKB _ __
''----'IfI ,\--_-1/ '--
EFB High I
I
I
----~I~----------~------------~II
bzzzz%

lltUe{ BO-B17
Endlan+ --------t~~§J~!!!:= ....._-.,.~;.;;..;. _ _- J '--_-.;..=;.;;.,.,_----'

[ tdlS~
Endl:~¥~B18-B35 ------~{C:j~§J~!!!:::J \-__.....;.;=~_ _.J Read 2 }.-

t SIZO = Hand SIZ1 = H selects the mail1 register for output on 80-835.
:I: Unused word 80-817 or 818-835 holds the last FIF01-output-register data for word-size reads.

DATA SWAP TABLE FOR WORD READS FROM FIF01

DATA READ FROM FIF01
DATA WRITTEN TO FIF01 SWAP MODE READ
BIG ENDIAN liTTLE ENDIAN
NO.
A35-A27 A26-A18 A17-A9 AB-AO SW1 SWO B35-B27 B26-B18 B17-B9 B8-BO
1 A 8 C D
A 8 C D L L
2 C D A 8
1 D C 8 A
A 8 C D L H
2 8 A D C
1 C D A 8
A 8 C D H L
2 A 8 C D
1 8 A D C
A 8 C D H H
2 D C 8 A

Figure 10. Port·B Word Read·Cycle Timing for FIF01

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 12-57
SN74ABT3614
84 x 38 x 2 CLOCKED BiDiRECiiONAL FiRSi·iN, FiRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F-JUNE 1992- REVISED FEBRUARY 1996

elKS

High
1
1
1
) , 1
1 1 1 1

W'-RS~~
1 ,I
1 1
1
:
1
1
1
WVZ;
~
ENS
1 Isu(EN}

77!ZTfl/44 : ~ : '<88&3 : ~ : \\\~ No

Ih(EN} 1 1 1

qzzza 1

SW1,SWO

SEls

Isu(SZ} ~ Ih(SZ} I I I 1 :

SIZ1, SIZO +1 (I, l}f >I(>QO<><Z

Not(1,,1}t , Nol(I,I}t I Nol(I,I}t 1 1 1

PGS,

* R~t * !- * ~ead *
ODD/EVEN~~~~~~~~.

len !+---.I '-: la - ' la -.I Ie -.I 1- la -..! Idls h

SD-S8 t.
Pr~vlous Dal~ I
1
1
R,ead 2
I 1
1
3
1
Read 1I 'J--
I+- la ---+I I+-- la -.I I+- la -.I I- la -..! ~
S27 -S35 --------«:::==J* Previous Dala
Read 1 * Read 2 * Read 3 X
Idls
Read 4 'J---
t SIZO = Hand SIZI = H selects the maill register for output on 90-935.
NOTE A: Unused bytes hold the last FIF01-output-register data for byte-size reads.

Figure 11. Port-B Byte Read-Cycle Timing for FIF01

~1ExAs
INSTRUMENTS
12-58 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

DATA SWAP TABLE FOR BYTE READS FROM FIF01

DATA READ
FROM FIF01
DATA WRITTEN TO FIF01 SWAP MODE READ
BIG LITTLE
NO.
ENDIAN ENDIAN
A35-A27 A26-A18 A17-A9 A8-AO SW1 SWO B35-B27 B8-BO
1 A D
2 B C
A B C D L L
3 C B
4 D A
1 D A
2 C B
A B C D L H
3 B C
4 A D
1 C B
2 D A
A B C D H L
3 A D
4 B C
1 B C
2 A D
A B C D H H
3 D A
4 C B

Figure 11. Port·B Byte Read·Cycle Timing for FIF01 (continued)

~ ~ ~
I... tw(CLKH) * tw(CLKL) -.I
CLKA )I { }--~\ (----\ y
I ~---- ~----~I
I I I
High I I I
I I I
I I II

MBA

AO-A35 _ _ _ _---I

PGA,
ODD/EVEN ~~~~~=QI '-_--oJ ~==~~ '--_-' v.~~~~~~~~=~~~~

t Read from FIF02

Figure 12. Port·A Read·Cycle Timing for FIF02

~TEXAS
INSTRUMENTS
POST OFFICE sox 655303 • DALLAS. TEXAS 75265 12-59
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

ClKA
/
/
CSA low /
I
WiRA High /
tsu(EN) r-=:l /4- th(E~)
MBA ~ 5;0n'77-7'70727"27"2:>'"'::2""'V'7/,:'72"72727:(7"27"2:>'"'::2""'V"'/,:'72"72727'27"27"')::>"":2""'V""'/,:'7/,:'72"7'):7':(7'2727')::>""::("'V"'/.'72"7/j~?
ENA ;~ ~,",_-,t"",h
(E~N)~ ... ........._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
/ I
FFA High / /
tsu(D) ~ 1_ I

AO-A35
tsk1t ,.. -/.. tc --.I
tw(ClKH) bl+---j tw(ClKl)
ClKB 1 2

EFB FIF01 Empty

CSB low
/
/
wiRB low /
~--------------------------~/----------------------
SIZ1, SIZO low /

tS~NL~ !+- th(EN)

~~~
ENB?l2VZ/ZZZ2ZZZZZfI
'-ta-'
BO-B~ ~~----~W~1-----

t tsk1 is the minimum time between a rising ClKA edge and a rising ClKB edge for EFB to transition high in the next ClKB cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tsk1, the transition of EFB high may occur one ClKB cycle later than shown.
NOTE A: Port-B size of the long word is selected for FIF01 read by SIZ1 = l, SIZO = L. If port-B size is word or byte, EFB is set low by the last
word or byte read from FIF01, respectively.

Figure 13. EFB-Flag Timing and First Data Read When FIF011s Empty

~TEXAS
INSTRUMENTS
12--60 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F -JUNE 1992 - REVISED FEBRUARY 1996

ClKB
I
CSB Low I
I
I
wiRB High I
Isu(EN) j+--!I
I ~ t+- Ih(EN)
SIZ1, SIZO ':""'''''~S:'''''OS:'''''OS:'''''i:S:'''''i:S'''':L1 (/"'2-72~2'72"7'2"7'2"?"2"?"2r2r2~2~V"":/""i':"'2"'2"'2'"7'2"7'2"7'2"?"2"?"2r2r2~2~2""V"":/"':/"'2"'2'"7'2'"7'2"7'2"7'2"?"2"?"2r?:r2~2~2""V"""';
ISU(EN):=:: t it1(EN)
ENB tWA I ~",..
~..S~~..~~\_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
I I
FFB High i I
Isu(D) i+--J I
I~ I+- Ih(D)
BO-B35

I tl. ' - Ie ~
skI ~ ~ Iw(ClKl)
Iw(ClKH) ~ I
CLKA

EFA ________ FI_F_02_E_m~p~ty~______tP_d_(~_E_~__~~_-_-_-_-~)__~r~~~~~IP-d(-~-E-F-)-----------------

I
CSA low I
--~------------------------------+I---------------------------
WiRA low I
I
I
MBA low I
I I+- Ih(EN)
ISU(EN)~
ENA 7/llllllZ7//ZZZl~ ~~
I+-- la -I
AO-A35 ~'------~W:":"I-----

t tsk1 is the minimum time between a rising ClKB edge and a rising ClKA edge for EFA to transition high in the next ClKA cycle. lithe time between
the rising ClKB edge and rising ClKA edge is less than tskl, the transition of EFA high may occur one ClKA cycle later than shown.
NOTE A: Port-B size of the long word is selected for FIF02 write by SIZ1 = l. SIZO = L. If port-B size is word or byte. tsk1 is referenced to the
rising ClKB edge that writes the last word or byte of the long word, respectively.

Figure 14. EFA-Flag Timing and First Data Read When FIF021s Empty

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-61
SN74ABT3614
64 x 36 x 2 CLOCKED BiDiRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F -JUNE 1992- REVISED FEBRUARY 1996

l.-- te-.l
1 1
tw(CLKH) 14 ~4 ~ tw(CLKL)
CLKB
CSB
I
~Lo~w~
,
________
I
1
~1

1
' ...._--11 'I..._~I 'I..._~I
_________________________________________________ __
'---
1
WffiB ~Lo~w~ ________ ~I~---------------------------------------------------
SIZ1, SIZO -=Lo:.:w::....________ 1
~1 ___________________________________________________
tsu(EN) I~ th(EN)
ENB ____.... £../"""2/'-'171 ~...,:'\:
....$
....$"""'.......
:\ __________________
1
High

BO-B35 Previous Word In FIF01 Output Register Next Word From FIF01

i 4 - - - te -----.,
~ ~ tw(CLKL)
CLKA ~'- _ _ .JI '--_...J .-:---" f2 ',-_~'
~
,'-_--Ir-
14----.r"" t d(e- F)
FIFOl Full
t
pd(e-FF) 14 }
..
: X,-P__F_ __
1
CSA Low 1

-----------------------------------------~I----------------
1
WiRA

ENA
?/ZZZZI!lZZl/Zll/Z2ZZZl/ZlZZZ2lZZZZZ2Z : ~
tsu(O) ~ th(O)
AO-A35
ToFIFOl

t tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition high in the next ClKA cycle. lithe time between
the rising ClKB edge and rising ClKA edge is less than tsk1, FFA may transition high one ClKA cycle later than shown.
NOTE A: Port-B size of the long word is selected for the FIF01 read by SIZ1 =l, SIZO =L. II port-B size is word or byte, tsk1 is referenced from
the rising ClKB edge that reads the first word or byte of the long word, respectively.

Figure 15. FFA·Flag Timing and First Available Write When FIF01 Is Full

~TEXAS
INSTRUMENTS
12-62 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

tw(CLKH)
CLKA

CSA
I
I . - tc ---.I.
I-
_~Low~
,- ~
\\.._---J{
1
tw(CLKL)
\. . .__/ __ __
\ .....

________-TI__________________________________________________
/ \..... / _-
\ ....

1
W/RA ~~~ ______-+I__________________________________________________
- Low 1

MBA ~Low~ ________ ~I

1__________________________________________________

~ th(EN)
ENA
t 8u (EN)
Il//7J i ~.$~$1o..;~1o..l:\.0lI0
. . _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
1
High

Next Word From F1F02

~ t8k1t -tI~~_ _ tc ~
tw(CLKH) I- ~ -I tw(CLKL)
CLKB ~\.._--,Ir-~\ )1 " f2 \""_---'!I \ r-
FFB _________F_IF_O_2_FU_II_ _ _ _ _ _ _ _ _- - J
tpd(CoFF) I-
i~ ..._~I~-==~~
: \""tpd(CoFF)
_____
I
CSB . Low I
I
1
WiRB

SIZ1,SIZO

ENB

BO-B35
ToFIF02

t tskl is the minimum time between a rising CLKA edge and a rising CLKB edge lor FFB to transition high in the nextCLKB cycle. lIthe time between
the rising CLKA edge and rising CLKB edge Is less than tskl. FFB may transition high one CLKB cycle later than shown.
NOTE A:. Port-B size 01 the long word is selected lor FIF02 write by SIZl • L. SIZO =L. II port-B size is word or byte, FFB is set low by the last
word or byte write 01 the long word, respectively.

Figure 16. FFB-Flag Timing and First Available Write When FIF02 Is Full

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265 12-63
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRSi-OUi MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F-JUNE 1992 - REVISED FEBRUARY 1996

ClKA

ENA vzzzzJ "1lI~'I1o..S

J4-
Isu(EN) 14 Ih(EN)
...S...S;".;S;".;\:o..;~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
I+- ISk2t --.j
ClKB

AEB X long Words In FIF01

Ipd(C-AE) ~ Ipd(C.AE) r l
ex + 1) long Words In FIF01
Isu(EN) H 14- Ih(EN)
ENB ________________________________________t~?~?~?~2~2~~ ~

t tsk2 is the minimum time between a rising ClKA edge and a rising ClKB edge for AEB to transition high in the next ClKB cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tsk2, AEB may transition high one ClKB cycle later than shown.
NOTES: A. FIF01 write (CSA =l, WiRA =H, MBA =l), FIF01 read (CSB =l, WiRB =l, MBB =l)
B. Port-B size of the long word is selected for FIF01 read by SIZ1 = l, SIZO = L. If port-B size is word or byte, AEB is set low by the
first word or byte read of the long word, respectively.

Figure 17. Timing for AEB When FIF011s Almost Empty

ClKB

ENB mzm tsu(EN) 14 -:: /f- Ih(EN)

1%\\\\\
, ~~~~---------------------------------------
jf- Isk2t -tI
ClKA
, 1
Ipd(C-AE) 14'J4---~-1 Ipd(C.AE) ~ -,
AEA X long Words In FIF02 j ex + 1) long Words In FIF02 "--

ENA
I.--.::l
Isu(EN)1.
j4- Ih(EN)
1.
______________________ t~2~?~0.??~21 ~\\

t tsk2 is the minimum time between a rising ClKB edge and a rising ClKA edge for AEA to transition high in the next ClKA cycle.lfthetimebetween
the rising ClKB edge and rising ClKA edge is less than tsk2, AEA may transition high one ClKA cycle later than shown.
NOTES: A. FIF02 write (CSB = l, WiRB =H, MBB =l), FIF02 read (CSA = l, WiRA = l, MBA = l)
B. Port-B size of the long word is selected for FIF02 write by SIZ1 = l, SIZO = L. If port-B size is word or byte, tsk2 is referenced from
the rising ClKB edge that writes the last word or byte of the long word, respectively.

Figure 18. Timing for AEA When FIF021s Almost Empty

~1EXAS
INSTRUMENTS
12-64 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING

,R , ,
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

14- lsk2t ~
CLKA I { 1 I, Y1 12
1
, 1
lsu(EN) 14- th(EN) I 1

WA4~\\
I 1
ENA
I
tpd(C-AF) I" ~I
I
I
I
I
tpd(C.AF) 14
1
AFA [64 - (X + 1)] Long Words In FIF01 (64 - Xl Long Words In FIF01

I
CLKB
1 , I
f~--~'~ __-JI ''''____.,1 '----
-:I
''''____..J
tsu(EN) 14 J4- th(EN)
ENB ____________________.Jv.~z~z~~2~2~2~j, ~~$~~~~~~$~$.~~___________________________

t tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition high in the next CLKA cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tsk2, AFA may transition high one CLKB cycle later than shown.
NOTES: A. FIFOt write (CSA - L, W/RA - H, MBA = l), FIF01 read (CSB = l, W/RB = l, MBB = l)
B. Port-B size of the long word is selected for FIF01 read by SIZl =l, SIZO - L. If port-B size is word or byte, tsk2 is referenced from
the first word or byte read of the long word, respectively.

Figure 19. Timing for AFA When FIF01 Is Almost Full

'\.._...,,1

tpd(C-AF) 14 ~: I tpd(C.AF)1 14-4--~~:

AFB [64 - (X + 1)] Long Words In FIF02 \\,.(_64__
-_Xl_L_O_ng_w-IIi-°r_d_s_ln_F_IF_O_2__________________ ..."t-----
I
CLKA ---1 , 1 , I
''"-__--'I ''''____.,1 '----
~ tsu(EN) l-th(EN)
ENA 1?/?222? ~~~~~~~~~~~~,~_______________________
t lsk2 is the minimum time between a rising ClKB edge and a rising ClKA edge for AFB to transition high in the next ClKB cycle. If the time between
the rising ClKB edge and riSing ClKA edge is less than tsk2, AFB may transition high one ClKA cycle later than shown.
NOTES: A. FIF02 write (CSB =l, W/RB= H, MBB = l), FIF02 read (GSA = l, W/'RA = l, MBA _ L)
B. Port-B size of the long word is selected for FIF02 write by SIZl _ l, SIZO _ L. If port-B size is word or byte, AFB is set low by the
last word or byte write of the long word, respectively.

Figure 20. Timing for AFB When FIF02 Is Almost Full

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 12-65
SN74ABT3614
64 x 36 x :2 CLOCKED BiDiRECTiONAL FiRST·iN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F -JUNE 1992 - REVISED FEBRUARY 1996

ClKA I ,\-__--J/ ,\-__-oJ/

ClKB I
,'------

SIZ1, SIZO

ENB

BO-B35 W1 (remains valid In mall1 re Isler after read)

FIF01 Output Register
NOTE A: Port-B parity generation off (PGB = l)

Figure 21. Timing for Mail1 Register and MBF1 Flag

~TEXAS
INSTRUMENTS
12-66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F-JUNE 1992 - REVISED FEBRUARY 1996

ClKB /
'-----'If ' ...__-"1 ' ...._ _- . J I
tsu(EN) ~ 14-- th(EN)
CSB --------~~~~----------------------------------------
I I 1
W/RB varazzzz} W' I
I~ r tsu(SZ) th(SZ)
SIZI, SIZO Vlfl;Tazz}j I W'
I 1 1

ENB 2l712llZ22'4 I W
BO-B35 ~~
1
''------,1--...,1 \ 1 ,'--------
r-
ClKA /

\4- tpd(C-MF) -.\ tpd(C-MF) ~~

MBF2 ----------------~I--------~ I 1--------
1 1

)~-----+I------------------~:--------(
I I I 1

W/RA I?Z22'Zd I
I
1
I
1
~~$>S
I
I 1
MBA
II II
I I
I II tsU(EN)!-----+!~ th(EN)

ENA 1
I.!.
I 1
~I: tpd(M-OV/
l!27a \:_S:lo,.;I:SS:""""\~+I_ _ __
I
len ~ I. ~ tpd(C-MR) tdls ~
Ii I I
AO-A35 l ><><><XX»< WI (remains valid In mall2 register after read)
1
)
FIF02 Output Register
NOTE A: Port-A parity generation off (PGA = L)

Figure 22. Timing for Mail2 Register and MBF2 Flag

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-67
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
. WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

0001
EVEN \ I
I I
WiRA II II ).
I~------------~I
,,-----
MBA 0lZlflZz;zzzmzzrAwvz;fi7?IIJ
I I I
bss\'W
I
PGA
0Z??2/4ZVVZZ22Tdz;vzzzzzzzzzd ~
tpd(O·PE) !f------tI tpd(O-PE) I4----t/ tpd(E·PE) ~ tpd(E·PE) ~
Valid )I{ Valid )I{ Valid! \ Valid

Figure 23. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing

0001
EVEN \ I
I I
WiRB

SIZ1,
SIZO
I I I I
PGB
vzzzz»,zv~ ~
tpd(O-PE) ~ tpd(O·PE) ~ tpd(E.PE) ~ tpd(E.PE) ~
Valid )I{ Valid )I{ Valid! \ Valid

Figure 24. ODD/EVEN, W/RB, SIZ1, SIZO, and PGB to PEFB Timing

~1EXAS
INSTRUMENTS
12-68 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

0001
EVEN
\~-----------------------
I
Low
I
I
I

~~--------------~I~-----------------------
WiRA
I I
MBA V!zZZZZZ;Zf I
I I I
PGA ?ZZ(zzzmz? I )------
I J4-- tpd(E-PB) --.j I I
I+- ten -to! 1+ tpd(M-OV) ~ I 14-- tpd(o-PB) ~ j4-- tpd(E-PB) ~
A8, A17,
A26,A35 -----t~ Generated Parity *: Generated Parity *:"""'M"""'all""'2""'Oa""'ta
Mall2
~ata

Figure 25. Parity-Generation Timing When Reading From the Mall2 Register

0001
EVEN
\~-----------------------
I
Low
I
I
I

~------------------+I--------------------------
WiRB
I I
SIZ1,
SIZO zd?zzT1V4'
I I
I
I
PGB ~2/.~2+2~2/.~2~2~2%~J~-------+I--------~)~_____
I J4-- tpd(E-PB) --.j I I
I+- ten -to! 1+ tpd(M-OV) -to! I 14-- tpd(o-PB) -1 j4-- tpd(E-PB) --+I
B8, B17,
B26,B35
----~~..-""!:G:-e-ne-ra"!"te-:d":p-ar:":"lty-""""'X"--""!:G:-e-ne-ra~te"':'d":'pa-:rl~tY-""\i"'M~a':':'1I1~0:-a~ta
Mall1
Data

Figure 26. Parity-Generation Timing When Reading From the Mail1 Register

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 12-{l9
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F-JUNE 1992- REVISED FEBRUARY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Vee> ............................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee> ........................................... ±50 mA
Continuous output current, 10 (Vo = 0 to Vee> ............................................. ±50 mA
Continuous current through Vee or GND ................................................. ±500 mA
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
lunctional operation 01 the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions lor extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
10H High-level output current -4 mA
10L Low-level output current 8 mA
TA Operating Iree-air temperature 0 70 ·C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
VOH VCC = 4.5 V, 10H =-4mA 2.4 V
VOL Vcc = 4.5 V, 10L= 8 mA 0.5 V
II VCC=5.5V, VI = VccorO ±50 I!A
10Z VCC=5.5V, VO=Vcc orO ±50 I!A
Outputs high 30
ICC Vcc= 5.5 V, 10=0 mA, VI = VCC or GND Outputs low 130 mA
Outputs disabled 30
Ci VI=O, 1=1 MHz 4 pF
Co VO=O, 1=1 MHz 8 pF
:I: All tYPical values are at VCC = 5 V, TA = 25·C.

~TEXAS
INSTRUMENTS
12-70 POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBSI26F - JUNE 1992 - REVISED FEBRUARY 1996

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 4 through 26)
'ABT3614-15 'ABT3614-20 'ABT3614-30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency, ClKA or CLKB 66.7 50 33.4 MHz
Ie Clock cycle time, ClKA or ClKB 15 20 30 ns
tw(ClKH) Pulse duration, ClKA and ClKB high 6 8 12 ns
tw(ClKll Pulse duration, ClKA and ClKB low 6 8 12 ns
tsu(D) Setup time, AO-A35 before CLKAr and BO-B35 before ClKBr 4 5 6 ns
Setup tlme.~, W/RA. ENA, and MBA before ClKAr; CSB.
tsu(EN) 5 5 6 ns
WiRB. and ENB before ClKBr
tsu(SZ) Setup time, SIZO. SIZ1. and BE before ClKBr 4 5 6 ns
tsu(SWl Setup time. SWO and SW1 before ClKBr 5 7 8 ns
Setup time. ODD/EVEN and PGA before ClKA1"; ODD/EVEN and
tsu(PG) 4 5 6 ns
PGB before ClKBtt
tsulRS} Setup time. RST low before ClKAr or ClKB11 5 6 7 ns
tsu(FSI Setup time, FSa and FS1 before RS'f high 5 6 7 ns
th(D) Hold time, AO-A35 alter CLKAr and 80-835 alter ClKBr 1 1 1 ns
Hold time, CSA, W/RA, ENA, and MBA alter ClKAr; CSB. WIRB.
th(EN) 1 1 1 ns
and ENB alter ClKBr
th(SZI Hold time, SIZO. SIZ1. and BE alter ClKBr 2 2 2 ns
!h(SW) Hold time, swa and SW1 alter ClKBr 0 0 0 ns
Hold time, ODD/MN and PGA alter CLKAr; ODD/EVEN and
!h(PG) 0 0 0 ns
PGB alter ClKBrt
!heRS) Hold time. RS'f low alter CLKAr or ClKBr; 5 6 7 ns
!h(FSI Hold time. FSa and FS1 alter RSf high 4 4 4 ns
Skew time betwean ClKArand ClKBr for m. ~. FFA. and
tsk1§
m 8 8 10 ns

Skew time between ClKAr and ClKBr for AEA. AEB. AFA. and
tsk2§ 9 16 20 ns
AFB
t Only applies for a clock edge that does a FIFO read
; Requirement to count the clock edge as one 01 at leest four needed to reset a FIFO
§ Skew time is not a timing constraint lor proper device operation and is only included to illustrate the timing relationship between ClKA cycle and
ClKBcycle.

:'IlEXAS
INSTRUMENTS
POST OFFICE BOX 65630S • DALLAS. TEXAS 75265 12-71
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F -JUNE 1992- REVISED FEBRUARY 1996

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 4 through 26)
'ABT3614-15 'ABT3614-20 'ABT3614-30
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
ta Access time, ClKA! to AD-A35 and ClKB! to BO-B35 2 10 2 12 2 15 ns
tpd(C-FF) Propagation delay time, ClKA! to FFA and ClKB! to FFB 2 10 2 12 2 15 ns
tod(C-EF) Propagation delay time, ClKA! to EFA and ClKB! to EFB 2 10 2 12 2 15 ns
tpd(C-AE) Propagation delay time, ClKA! to AEA and ClKB! to AEB 2 10 2 12 2 15 ns
tod(C-AF) Propagation delay time, ClKA! to AFA and ClKB! to AFB 2 10 2 12 2 15 ns
Propagation delay time, ClKA! to MBF1 low or MBF2 high and
tpd(C-MF) 1 9 1 12 1 15 ns
ClKB! to MBF2 low or MBF1 high
Propagation delay time, ClKA! to BO-B35t and ClKB! to
tpd(C-MR) 3 11 3 13 3 15 ns
AD-A3S:!:
tod(C-PE)§ Propagation delay time, ClKB! to PEFB 2 11 '2 12 2 13 ns
Propagation delay time, MBA to AD-A35 valid and SIZ1, SIZO to
tpd(M-DV) 1 11 1 11.5 1 12 ns
BO-B3S valid
Propagation delay time, AD-A35 valid to PEFA valid; BO-B35
tpd(D-PE) 3 10 3 11 3 13 ns
valid to PEFB valid

tpd(O-PE) Propagation delay time, ODD/EVEN to PEFA and PEFB 3 11 3 12 3 14 ns

Propagation delay time, ODD/EVEN to parity bits (A8, A 17, A26,
tpd(O_PB)1f 2 11 2 12 2 14 ns
A35)and(B8,B17,B26,B35)
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to
tpd(E-PE) 1 11 1 12 1 14 ns
PEFA; CSB, ENB, WiRB, SIZ1, SIZO, or PGB to PEFB
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to
tpd(E_PB)1f parity bits (A8, A 17, A26, A35); CSB, ENB, WiRB, SIZ1, SIZO, or 3 12 3 13 3 14 ns
PGB to parity bits (B8, B17, B26, B35)

tod(R-F) Propagation delay time, RST to (MBF1, MBF2) high 1 15 1 20 1 30 ns

Enable time, CSA and W/RA low to AD-A35 active and CSB low
ten 2 10 2 12 2 14 ns
and WiRB high to BO-B35 active
Disable time, CSA or W/RA high to AD-A35 at high impedance
tdis 1 8 1 9 1 11 ns
and CSB high or WiRB low to BO-B35 at high impedance
t Writing data to the mail1 register when the BO-B35 outputs are active and SIZ1, SIZO are high
:j: Writing data to the mail2 register when the AO-A35 outputs are active and MBA is high
§ Only applies when a new port-B bus size is implemented by the rising ClKB edge
II Only applies when reading data from a mail register

~TEXAS
INSTRUMENTS
12-72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F-JUNE 1992- REVISED FEBRUARY 1996

TYPICAL CHARACTERISTICS

SUPPLY CURRENT
vs
CLOCK FREQUENCY
400 I.!. I I _I.
fdata = 1/2 fclo k VCC = 5.5 V /
350 -TA=25°C
00( CL=OpF V
E
I 300
/ ./
C V
~
::I 250
VCC=5Z
/ / ./
/ ~ V~
()
~
a. 200
a.
~ ~ /VCC=4.5V
::I
In
I
150
5:
J~ 100 ,
~ '/'
50 , #
o
o 10 20 30 40 50 60 70 80

fclock - Clock Frequency - MHz

Figure 27

calculating power dissipation

The ICC(f) current for the graph in Figure 27 was taken while simultaneously reading and writing the FIFO on
the SN74ACT3614 with ClKA and ClKB set to fclock. All data inputs and data outputs change state during each
clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to
a zero-capacitance load. Once the capacitive load per data-output channel is known, the power dissipation can
be calculated using the equation below.
With ICC(f) taken from Figure 27, the maximum power dissipation (PT) of the SN74ABT3614 can be calculated
by:
PT = VCC x ICC(f) + L(CL x VOH 2 x fa)
where:
CL = output capacitive load
fa = switching frequency of an output
VOH = high-level output voltage
When no reads or writes are occurring on the SN74ABT3614, the power dissipated by a single clock (ClKA
or ClKB) input running at frequency fclock is calculated by:
PT = VCC x fclock x 0.29 mA/MHz

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265 12-73
SN74ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996

PARAMETER MEASUREMENT INFORMATION

5V

1.1 k.Q
From Output
Under Test --+---~

6800 ;:::;; 30 pF
(see Note A)

LOAD CIRCUIT

Timing
Input
j,.----
1.5 V
3V High-Level ~
1.5 V 1.5 V
--3V

--~.q.----- GND Input I I GND

I~
tsu .14 ., th ~tw~
I I
Data, ~ -;..-:; - 3 V
~
I 3V
Enable ~1.5V ~ Low-Level 1.5 V 1.5 V
Input GND Input _ _ _ _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

3V
Output
Enable --'iL 1.5 V GND
-+\ i4-tPLZ
=3V
Low-Level
Output
:'

--f-iI
~---~
Input -4 1•5 V \1.5~ - - ::0

tpd ~ I4--+L- tpd

High-Level
Output I I In-Phase II----..J - - VOH
, I =OV Output _ _--'/1.5 V '\::.V VOL
-+i l4-tPHZ
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 28. Load Circuit and Voltage Waveforms

~1ExAs
INSTRUMENTS
12-74 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
13-1
 HIGH-BANDWIDTH COMPUTING 36-BIT CLOCKED FIFOS
Features Benefits

• 36-bit FI FO interface • Single-chip implementation for high levels

of integration
• Bidirectional option • Two dual-port SRAMS allow true
bidirectional capability
• Mailbox-register bypass • Quick access to priority information
• Microprocessor-control circuitry • Interface matches most processors and
DSP bus-cycle timing and
communications
• Multiple default values for separate AF • Easy alternatives for flag settings
and AE flags
• Parity generation and check • Ensures valid data
• EIAJ standard 120-pin thin quad • 67% less board space than equivalent
flat packs (TQFP) 132-pin PQFPs; over 66% less board
space than four 9-bit 32-pin PLCC
equivalents
• TI has established an alternate source • Standardization that comes from a
common second source
(')
0"
(")

~
Co
!!
."
o
tJ)

13-2
 SN74ABT3611
64x36
FIRST·OUT MEMORY

• Free-Running ClKA and ClKB Can Be • Empty Flag (EF) and Almost-Empty
Asynchronous or Coincident Flag (AE) Synchronized by ClKB
• 64 x 36 Clocked FIFO Buffering Data From • Passive Parity Checking on Each Port
Port A to Port B • Parity Generation Can Be Selected for Each
• Mailbox-Bypass Register In Each Direction Port
• Programmable Almost-Full and • low-Power Advanced BiCMOS Technology
Almost-Empty Flags • Supports Clock Frequencies up to 67 MHz
• Microprocessor Interface Control logic • Fast Access Times of 10 ns
• Full Flag (FF) and Almost-Full Flag (AF) • Available in Space-Saving 120-Pin Thin
Synchronized by ClKA Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages

description
The SN74ABT3611 is a high-speed, low-power BiCMOS clocked FI FO memory. It supports clock frequencies
up to 67 MHz and has read access times as fast as 10 ns. A 64 x 36 dual-port SRAM FIFO buffers data from
port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words are stored in memory. Communication
between each port can take place through two 36-bit mailbox registers. Each mailbox register has a flag to signal
when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired.
Parity generation can be selected for data read from each port. Two or more devices can be used in parallel
to create wider datapaths.
The SN74ABT3611 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The full flag (FF) and almost-full flag (AF) of the FIFO are two-stage synchronized to the port clock that writes
data to its array (ClKA). The empty flag (EF) and almost-empty (AE) flag of the FIFO are two-stage
synchronized to the port clock that reads data from array (ClKB).
The SN74ABT3611 is characterized for operation from O°C to 70°C.
For more information on this device family, see the application reports FIFO Mailbox-Bypass Registers: Using
Bypass Registers to Initialize DMA Control and Parity-Generate and Parity-Check Features for
High-Bandwidth-Computing FIFO Applications in the 1996 High-Performance FIFO Memories DeSigner's
Handbook, literature number SCAA012A.

Copyright © t 995, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13-3
SN74ABT3611
64x36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

PCB PACKAGE
(TOP VIEW)

omW~~~~M~~om~~W~~M~~Om~~W~~MN~
~~~~~~~~~~~~~~~~~~~~~mmmmmmmmm
A23 90 822
A22 89 821
A21 88 GND
GND 4 87 820
A20 5 86 819
A19 6 85 818
A18 7 84 817
A17 8 83 816
A16 9 82 815
A15 10 81 814
A14 11 80 813
A13 12 79 812
A12 13 78 811
A11 14 77 810
A10 15 76 GND
GND 16 75 89
A9 17 74 88
A8 18 73 87
A7 19 72 Vee
Vee 20 71 86
A6 21 70 85
A5 22 69 84
A4 23 68 83
A3 24 67 GND
GND 25 66 82
A2 26 65 81
A1 27 64 80
AO 28 63 EF8
NC 29 62 AE8
NC 30 61 NC

Ne - No internal connection

~1ExA.s
INSTRUMENTS
13-4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3611
64x36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCBS127D- JULY 1992 - REVISED SEPTEMBER 1995

PQPACKAGEt
(TOP VIEW)

GND GND
NC AEB
NC EFB
AO BO
A1 B1
A2 B2
GND GND
A3 B3
A4 B4
A5 B5
A6 B6
VCC VCC
A7 B7
A8 B8
A9 B9
GND GND
A10 B10
A11 B11
VCC VCC
A12 B12
A13 B13
A14 B14
GND GND
A15 B15
A16 B16
A17 B17
A18 B18
A19 B19
A20 B20
GND GND
A21 B21
A22 B22
A23 B23

NC - No internal connection
t Uses Yamaichi socket IC51-1324-828

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-5
SN74ABT3611
64x36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

functional block diagram

Port-A
Control
logic

36
36

AO-A35--.......... ...........-BO-B35

Programmable-
FSO--------_1~~----------_1 Flag
FS1--------_1~~----------_1
Offset Register

PGA ----tt~====~~~±:,+_f~~~tl-..------,
~~~~R~~!I~st~e~r
.r l-Ll
........___
----:l..-J ~I.-----~t:t1j:~
Parity
Mall2
__
I

PEFA Gen/Check I I ....

ClKB
MBF2 --------------<t------------------' Port-B CSB
Control WiRB
logic
.... ENB
MBB

~TEXAS
INSTRUMENTS
13-6 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3611
64x36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCBSI27D - JULY 1992 - REVISED SEPTEMBER 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME
AO-A35 I/O Port-A data. The 36-bit bidirectional data port for side A.
Almost-empty flag. Programmable flag synchronized to ClKB. AE is low when the number of words in the FIFO is less
AE 0
than or equal to the value in the offset register, X.
Almost-full flag. Programmable flag synchronized to ClKA. AF is low when the number of empty locations in the FIFO
AF 0
is less than or equal to the value in the offset register, X.
BO-B35 I/O Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
ClKA I
or coincident to ClKB. FF and AF are synchronized to the low-te-high transition of ClKA.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
ClKB I
or coincident to ClKA. EF and AE are synchronized to the low-to-high transition of ClKB.
Port-A chip select. CSA must be low to enable a low-to-high transition of ClKA to read or write data on port A. The
CSA I
AO-A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of ClKB to read or write data on port B. The
CSB I
BO-B35 outputs are in the high-impedance state when CSB is high.
Empty flag. EF is synchronized to the low-to-high transition of ClKB. When EF is low, the FIFO is empty and reads from
its memory are disabled. Data can be read from the FIFO to its output register when EF is high. EF is forced low when
EF 0
the device is reset and is set high by the second low-te-high transition of ClKB aiter data is loaded into empty FIFO
memory.
ENA I Port-A enable. ENA must be high to enable a low-to-high transition of ClKA to read or write data on port A.
ENB I Port-B enable. ENB must be high to enable a low-to-high transition of ClKB to read or write data on port B.
Full flag. FF is synchronized to the low-to-high transition of ClKA. When FF is low, the FIFO is full and writes to its
FF 0 memory are disabled. FF is forced low when the device is reset and is set high by the second low-te-high transition of
ClKA after reset.
Flag-offset selects. The low-to-high transition of RST latches the values of FSO and FSI , which loads one offour preset
FS1, FSO I
values into the almost-full and almost-empty offset register, X.
MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
MBB I BO-B35 outputs are active. a high level on MBB selects data from the maill register for output and alow level selects
the FIFO output register data for output.
Maill register flag. MBFl is set low by the low-to-high transition of ClKA that writes data to the mail1 register. Writes
MBFl 0 to the mail 1 register are inhibited while MBFl is low. MBFl is set high by a low-lo-high transition of ClKB when a port-B
read is selected and MBB is high. MBFl is set high when the device is reset.
Mail2 register flag. MBF2 is set low by the low-to-high transition of ClKB that writes data to the mail2 register. Writes
MBF2 0 to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-te-high transition of ClKA when a port-A
read is selected and MBA is high. MBF2 is set high when the device is reset.
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/
I ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
EVEN
for a read operation.
Port-A parity error flag. When any byte applied to AO-A35 fails parity, PEFA is low. Bytes are organized as AO-AB.
A9 -A17. A18-A26. and A27 -A35, with the most significant bit of each byte serving as the parity bit. The type of parity
0 checked is determined by the state of ODD/EVEN.
PEFA
(portA) The parity trees used to check the AO-A35 inputs are shared by the mail2 register to generate parity if parity generation
is selected by PGA. Therefore. if a mail2 read with parity generation is set up by having CSA low. ENA high. WiRA low.
MBA high. and PGA high, PEFA is forced high regardless of the state of the AO -A35 inputs.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-7
SN74ABT3611
64x36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

Terminal Functions (Continued)

TERMINAL
I/O DESCRIPTION
NAME
Port-B parity error flag. When any byte applied to terminals BO-B35 fails parity. PEFB is low. Bytes are organized as
BO-B8. B9-B17. B18-826. and 927 -B35. with the most significant bit of each byte serving as the parity bit. The type
0 of parHy checked is detennined by the state of ODD/EVEN.
PEFB
(port B) The parity trees used to check the BO- B35 inputs are shared by the maill register to generate parity if parHy generation
is selected by PGB. Therefore. if a maill read wHh parity generation is set up by having CSB low. ENB high. WiRB
low. MBB high. and PGB high. ~ is forced high regardless of the state of the 90-935 inputs.
Port-A parity generation. Parity is generated for mail2 register reads from port A when PGA is high. The type of parity
PGA I generated is selected by the state of ODD/EVEN. Bytes are organized as AO-A8. A9-A 17. A18-A26. and A27 -A35.
The generated parity bHs are output in the most signlflcan1 bit of each byte.
Port-B parity generation. Parity Is generated for data reads from port B when PGB is high. The type of parity generated
PGB I is selected by the state of ODD/EVEN. Bytes are organized as BO-B8. B9-B17. B18-B26. and 927-B35. The
generated parity bits are output in the most significant bit of each byte.
Reset. To reset the device. four low-to-high transitions of ClKA and four low-to-high transitions of ClKB must occur
RST I while RST is low. This setsAF. MBF1. and MBF2 high and EF. AE. and FF low. The low-to-high transition of RST latches
the status of FSl and FSO to select AF and AE flag offset.
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
W/RA I
low-to-hlgh transition of ClKA. The AO-A35 outputs are in the high-impedance state when W/RA is high.
Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
W/RB I
low-to-high transition of ClKB. The BO-B35 outputs are in the high-impedance state when W/RB is high.

detailed description
reset
The SN74ABT3611 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. RST can switch asynchronously to the clocks. A device reset
initializes the internal read and write pointers'of the FIFO and forces the full flag (FF) low, the empty flag (EF)
low, the almost-empty flag (AE) low, and the almost-full flag (AF) high. A reset also forces the mailbox flags
(MBF1, MBF2) high. After a reset, FF is set high after two low-to-high transitions of CLKA. The device must be
reset after power up before data is written to its memory.
A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected
by the flag-select (FSO. FS1) inputs. The values that can be loaded into the register are shown in Table 1.

Table 1. Flag Programming

ALMOST-FULL AND
FS1 FSO RST ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H H i 16
H l i 12
l H i 8
l l i 4

FIFO write/read operation

The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The AO-A35 outputs are in the hiQ!:!-impedance state when either CSA or W/RA is
high. The AO-A35 outputs are active when both CSA and W/RA are low. Data is loaded into the FIFO from the
AO-A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high. ENA is high, MBA is low,
and FF is high (see Table 2).

~1ExAs
INSTRUMENTS
13-8 POST OFFICE BOX 655303 • OALLAS. TEXAS 75285
 SN74ABT3611
64x36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

FIFO write/read operation (continued)

Table 2. Port·A Enable Function Table

CSA W/RA ENA MBA ClKA AO-A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H l X X In high-impedance state None
L H H L t In high-impedance state FIFO write
L H H H t In high-impedance state Mail1 write
L L l L X Active, mail2 register None
l L H L t Active, mail2 register None
L L L H X Active, mail2 register None
L L H H t Active, mail2 register Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A. The state of the port-B data (BO-B35) outputs is
controlled by the port-B chip select (GSB) and the £ort-B write/read select (W/RB). The BO-B35 outputs are
in the high-impedance state when either GSB or W/RB is high. The BO- B35 outputs are active when both GSB
and W/RB are low. Data is read from the FIFO to the BO-B35 outputs by a low-to-high transition of GlKB when
GSB is low, W/RB is low, ENB is high, MBB is high, and EF is high (see Table 3).

Table 3. Port·B Enable Function Table

CSB W/RB ENB MBB ClKB BO-B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
l H l X X In high-impedance state None
L H H L t In high-impedance state None
L H H H t In high-impedance state Mail2 write
L L l L X Active, FI FO output register None
L L H L t Active, FIFO output register FIFO read
l l L H X Active, mail1 register None
L L H H t Active, mail1 register Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-chip selects (GSA, GSB) and write/read
selects (WIRA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select
.
can change states during the setup- and hold-time window of the cycle .

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13-9
SN74ABT3611
64x36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127D.;. JULY 1992 - REVISED SEPTEMBER 1995

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability
by reducing the probability of metastable events on their outputs when CLKA and CLKS operate
asynchronously to one another (see the application report Metastability Performance of Clocked FIFOs in the
1996 High-Performance FIFO Memories Data Book, literature number SCAD003C). FF and AF are
synchronized to CLKA. EF and AE are synchronized to CLKS. Table 4 shows the relationship of the flags to the
FIFO.

Table 4. FIFO Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS TOCLKB TOCLKA
INTHEFIFO
EF AE AF FF
0 L L H H
1 toX H L H H
(X+ 1)to[64-(X+1)] H H H H
(64-X)to 63 H H L H
64 H H L L
t xIs the value In the almost-emply flag and almost-full flag offset register.
empty flag (EF)
The FIFO empty flag is synchronized to the port clock that reads data from its array (CLKS). When EF is high,
new data can be read to the FI FO output register. When EF is low, the FI FO is empty and attempted FI FO reads
are ignored.
The FIFO read pOinter is incremented each time a new word is clocked to its output register. The state machine
that controls EF monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM
status is empty, empty+ 1, or empty+2. A word written to the FIFO can be read to the FIFO output register in a
minimum of three port-B clock (CLKB) cycles; therefore, EF is low if a word in memory is the next data to be
sent to the FIFO output register and two CLKB cycles have not elapsed since the time the word was written.
The empty flag of the FIFO is set high by the second low-to-high transition of CLKS, and the new data word can
be read to the FIFO output register in the following cycle.
A low-to-high transition on CLKS begins the first synchronization cycle of a write if the clock transition occurs
at time tsk1, or greater, after the write. Otherwise, the subsequent CLKS cycle can be the first synchronization
cycle (see Figure 4).
full flag (FF)
The FIFO full flag is synchronized to the port clock that writes data to its array (CLKA). When FF is high, an
SRAM location is free to receive new data. No memory locations are free when FF is low and attempted writes
to the FIFO are ignored.
Each time a word is written to the FIFO, its write pOinter is incremented. The state machine that controls FF
monitors a write-pointer and read-pointer comparator that indicates when the FI FO SRAM status is full, full-1 ,
or full-2. From the time a word is read from the FIFO, its previous memory location is ready to be written in a
minimum of three port-A clock cycles. FF is low if less than two CLKA cycles have elapsed since the next
memory write location has been read. The second low-to-high transition on CLKA after the read sets FF high
and data can be written in the following clock cycle.
A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs
at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization
cycle (see Figure 5).

~1ExAs
INSTRUMENTS
13-'-10 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3611
64x36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

almost-empty flag (AE)

The FIFO almost-empty flag is synchronized to the port clock that reads data from its array (ClKB). The state
machine that controls AE monitors a write-pointer and read-pointer comparator that indicates when the FIFO
SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty state is defined by the
value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values
during a device reset (see rese~. AE is low when the FIFO contains X or less words in memory and is high when
the FIFO contains (X + 1) or more words.
Two low-to-high transitions on the port-B clock (ClKB) are required after a FI FO write for the almost-empty flag
to reflect the new level of fill. The almost-empty flag (AE) of a FIFO containing (X + 1) or more words remains
low if two ClKB cycles have not elapsed since the write that filled the memory to the (X + 1) level. AE is set high
by the second ClKB low-to-high transition after the FI FO write that fills memory to the (X + 1) level. A low-to-high
transition on ClKB begins the first synchronization cycle if it occurs at time ts k2, or greater, after the write that
fills the FIFO to (X + 1) words. Otherwise, the subsequent ClKB cycle can be the first synchronization cycle
(see Figure 6).
almost-fuJI flag (AF)
The FIFO almost-full flag is synchronized to the port clock that writes data to its array (ClKA). The state machine
that controls AF monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the value of the almost-full
and almost-~ty offset register (X). This register is loaded with one of four preset values during a device reset
(see rese~. AF is low when the FIFO contains (64 - X) or more words in memory and is high when the FIFO
contains [64 - (X + 1)] or less words.
Two low-to-high transitions on the port-A clock (ClKA) are required after a FIFO read for AF to reflect the new
level of fill. The almost-full flag of a FI FO containing [64 - (X + 1)] or less words remains low if two ClKA cycles
have not elapsed since the read that reduced the number of words in memory to [64 - (X + 1)]. AF is set high
by the second ClKA low-to-high transition after the FIFO read that reduces the number of words in memory
to [64 - (X + 1)]. A low-lo-high transition on ClKA begins the first synchronization cycle if it occurs at time ts k2,
or greater, after the read that reduces the number of words in memory to [64 - (X + 1)]. Otherwise, the
subsequent ClKA cycle can be the first synchronization cycle (see Figure 7).
mailbox registers
Two 36-bit bypass registers are on the SN74ABT3611 to pass command and control information between port
A and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a
port-data-transfer operation. A low-to-high transition on ClKA writes AO-A35 data to the mail1 register when
a port-A write is selected by(CSA, WiRA, and ENA) with MBA high. A low-to-high transition on ClKB writes
BO-B35 data to the mail2 register when a port-B write is selected by (CSB, W/RB, and ENB) with MBB high.
Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register
are ignored while its mail flag is low.
When the port-B data (BO-B35) outputs are active, the data on the bus comes from the FIFO output register
when MBB is low and from themail1registerwhenMBBishigh.Mail2 data is always present on AO-A35 outputs
when they are active. The mail1 register flag (MBF1) is set high by a low-to-high transition on ClKB when a
port-B read is selected by CSB, W/RB, and ENB with MBB high. The mail2 register flag (MBF2) is set high by
a low-to-high transition on ClKA when a port-A read is selected by CSA, W/RA, and ENA with MBA high. The
data in a mail register remains intact after it is read and changes only when new data is written to the register.
parity checking
The port-A (AO-A35) inputs and port-B (BO-B35) inputs each have four parity trees to check the parity of
incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a low level on
the port-parity-error flag (PEFA, PEFB). Odd or even parity checking can be selected and the parity-error flags
can be ignored if this feature is not desired.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-11
SN74ABT3611
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SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

parity checking (continued)

Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select
input. A parity error on one or more bytes of a port is reported by a low level on the corresponding port parity
error flag (PEFA, PEFB) output. Port-A bytes are arranged as AO-AS, A9-A 17, A1S-A26, and A27 -A35, and
port-B bytes are arranged as BO-88, B9-B17, B1S-B26, and B27-B35. When odd/even parity is selected,
PEFA, PEFB is low if any byte on the port has an odd/even number of low levels applied to its bits.
The four parity trees used to check the AO-A35 inputs are shared by the mall2 register when parity generation
is selected for po,;-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is
selected with CS low, ENA high, WiRA low, MBA high, and PGA high, PEFA is held high regardless ofthe levels
applied to the AO-A35 inputs. Likewise, the parity trees used to check the BO-B35 Inputs are shared by the
mail1 register when parity generation is selected for port-B reads (PGB = h!gh). When a port-B read from the
mail1 register with parity generation is selected with CSB low, ENB high, W/RB low, MBB high, and PGB hi~h,
PEFB is held high regardless of the levels applied to the BO-B35 inputs.
parity generation
A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the
SN74ABT3611 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged
as AO-AS, A9-A17, A1S-A26, and A27-A35, with the most significant bit of each byte used as the parity bit.
Port-B bytes are arranged as BO-BS, B9-B17, B1S-B26, and B27-B35, with the most significant bit of each
byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all 36 inputs regardless
of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity generation
selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the
ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the most
significant bits of each byte as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the
output register. Therefore, the port-B parity generate select (PGB) and ODD/EVEN have setup- and hold-time
constraints to the port-B clock (ClKB) for a rising edge of ClKB used to read a new word to the FIFO output
register.
The Circuit used to generate parity for the mail1 data is shared by the port-B bus (BO-B35) to check parity and
the circuit used to generate parity for the mail2 data is shared by the port-A bus (AO-A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in a mail register when WiRA, wiRB
is low, MBA, MBB is high, CSA, CSB is low, ENA, ENB is high, and PGA, PGB is high. Generating parity for
mail-register data does not change the contents of the register.

~1ExAs
INSTRUMENTS
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 SN74ABT3611
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CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCBS127D- JULY 1992 - REVISED SEPTEMBER 1995

CLKA
--,j I.- th(RS)
CLKB
I
--tI j4- tsu(RS) I : tsu(FS) ~ th(FS) I
R S T - - -....~ I I ill :
I : I I I I
FS1, FSO

I· tpd(CoFF) H---! tpd(CoFF) ~

FF~~ 1,----
I tpd(Co~F) ~ ~
EF&'\~~\
I I Y tpd(CoAE)

AE~~~
I j+-----! tpd(CoAF)
AF !l7/TJZ{VWflVZ/Z?
__ tpd(R-F) ~

~:F~ //2//lh71/);
Figure 1. Device Reset Loading the X Register With the Value of Eight

~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-13
SN74ABT3611
64x36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

I. Ie _I

CLKA
I+-tW(CLKH)

)I
1-
'l
tw(CLKL) --I
Y
I
\ , I
\ (
I
'---
I I
FF High
tsu(EN1) II. -I., th(EN1)
I
I
I
1
I
I
CSA
tau(EN1)
~I. Ith(EN1)
-1°1 - I
I
II
r
WiRA
?ZlZZlWZl/{ IF I
I I~~~
I
MBA
tsu(EN3) I. -I.~ th(EN3)
I -114- th(EN2) I

tSU(EN21 'I'~ 1 tau(EN~H 14- th(EN2)

ENA WLZZ?VVz. ._ ~~:\ Jv/l2Z2?l2
tau(O) I. +_1 th(O)
AO-A35 No 8perillron jX8888888
1 1
=~.;: ~
tpd(O.PE) H tpd(D-PE) j+---.t
PEFA

Figure 2. FIF01-Wrlte-Cycle Timing

~1ExAS .
INSTRUMENTS.
13-14 POST OFFICE BOX 665303 • DAllAS, TEXAS 75265
 SN74ABT3611
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SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

I_ tc .1
~ tw(ClKH) . . . tw(ClKl) -.I
ClKB Y {. } \ ( \ '-
1 1
1 1
EF High 1 1
1 1

--------~--------------~------------+J/
1 1
CSB
1 1
1 1
1 1
1
1
MBB ). 1

BO-B35 - - - - _

PGB,

Figure 3. FIFO-Read-Cycle Timing

~TEXAS
INSTRUMENTS
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SN74ABT3611
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SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

CLKA

CSA ~Lo~w~
I _________________________________________________
____________-+I

1
I

EF ________E_m_p~
__F_IF_O______________ _ J i
i
__________________________________
cSB~Lo~w -+I_____________________________
i
wiRB Low i
----------------------------------+1--------------------------
MBB Low ii
tsu(EN2) I ~ j4- th(EN2)
ENB vmvzz;/ZZZZZl/ZW/ifl/ZTJ1 ~
if- ts -.j
BO-B35 ~.....----------::W~1:-------

t tsk1 is the minimum time between a rising ClKA edge and a rising ClKB edge for EF to transition high in the next ClKB cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tsk1, the transition of EF high may occur one ClKB cycle later than shown.

Figure 4. EF·Flag Timing and First Data Read When the FIFO Is Empty

~1ExAs .
INSTRUMENTS
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 SN74ABT3611
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CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

r-
I'"
tc
~'"
---1~I
,'-----
tw(CLKH) tw(CLKL)

CLKB I " ~ ' ...._--11 ' ...._--11

CSB ~Lo~w~ ________ ~I
1_______________________________________________________
I
WiRB Low 1
1
1
MBB ~Lo~w~ ______ ~~I~ _____________________________________________________
tsu(EN2) 1+=f+iJ.. th(EN2)
ENB I?2ZI 1 '~0~~~~~~~ ___________________
I
High

BO-B35 ~~~~ ____~~~~J,~N~e~xt~W~or~d~Fr_o~m_FI_Fo

_____________________________________

: - tSk1t --.I"i'"- - tc ~
tw(CLKH) i'" ~ ~ tw(CLKL)
I
'~=~/===='~"t;;;~r--
CLKA ~,-_____
, 11 ~ '4. /2 ~I
tpd(C-FF) J.4
FF ______________F_ul_IF_IF_O________________________ 1 :I" _______ \~
tpd(C-FF)

CSA __
Lo_w
______________________________________________ ~I I___________________
I
WiRA

AO-A35
To FIFO

t tsk1 is the minimum time between a rising ClKB edge and a rising ClKA edge for FF to transition high in the next ClKA cycle. If the time between
the rising ClKB edge and rising ClKA edge is less tsk1, FF may transition high one ClKA cycle later than shown.

Figure 5. FF-Flag Timing and First Available Write When the FIFO Is Full

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-17
SN74ABT3611
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBSI27D-JULY 1992- REVISED SEPTEMBER 1995

ClKA

ENA

ClKB
~---tl'i tpd(C-AE) 14 'i
AE X Words In FIFO Y(X + 1) Words In FIFO j '--
tsu(EN2) H 14- th(EN2)
ENB __________________________--------------------~~~z~~2~2.2~2.u4f ~
t tsk2 is the minimum time between a rising ClKA edge and arising ClKB edge for AE to transition high in the next ClKB cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tsk2, AE may transition high one ClKB cycle later than shown.
NOTE A: FIFO write (CSA = l, W/RA = H, MBA _ l), FIFO read (CSB = l, W/RB _ l, MBB - l).

Figure 6. Timing for AE When the FIFO Is Almost Empty

k- .ts k2* -t!

ClKA / \ t \ /r--+:""'\,------,1'''':"'1-""'\ Y2 \ . . . --'1
t SU (EN21--11: th(EN2) I I
ENA M?2//I I \.~\\\\\\ I :
I I
tpd(C-AF)If-I·--~·i tpd(C-AF)II+.--",,~
[64 - (X + 1)] Words In FIFO
I
(64 - X) Words In FIFO 11------
I
ClKB~ \. . -_/ \
tsu(EN2)
J......--~\
~ ·1:-th(EN2)
/ \ ....- _ /
ENB _ _ _ _ _ _ _ _-'t_z_2_2_z_2~<r ~~~~~~~~~~~~:"-~ ____________
:I: tsk2 is the minimum time between a rising ClKA edge and a rising ClKB edge for AF to transition high in the next ClKA cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tsk2, AF may transition high one ClKB cycle later than shown.
NOTE A: FIFO write (CSA = l, W/RA =H, MBA =l), FIFO read (CSB =l, W/RB =l, MBB =l).

Figure 7. Timing for AF When the FIFO Is Almost Full

~TEXAS
INSTRUMENTS
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 SN74ABT3611
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CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

I , I ' .....__...,,/ ''-__---II

ClKA

CSA
tsu(ENi) H r- th(EN1)
----------~~~I--------------------------------------------
I I
W/RA ZlZZW/IlZZ? :M
I II
MBA ZlZZW/IlZZ? :M
I II
ENA ?ZZZZZZZlfl/{ I i<88?I
AO-A35 ~ .

I
ClKB I I ---1/
''---i- ',-_ _ _{ ''-_ __
IF tpd(C.MF) 1 r tpd(C-MF) -.!
MBFi --------------~------~,~____________
I -
+I--------JI--------
I
\L----~I-----------_rl
1- I I ____-J1I
W/RB ~$~S~s~s~s~Si 1 : ~"'2"7"2"?'2,,?,;:"'2"'6"'V"'/~
I I I I
MBB -----!-'I ______ /1
..J
II tsu(EN2) ~y th(EN2)
I
I
ENB : II1 1?2?J7 t~~~S~'~~1 _______
I 14 .1 tpd(M.OVJ !. _I
ten r - - I j4-'--+-----.! tpd(C.MR) tdls ~
BO-B35 Wi remains valid In malli re Ister after read)
FIFO Output Register

NOTE A: Port-B parity generation off (PGB = L)

Figure 8. Timing for Mail1 Register and MBF1 Flag

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS, TeXAS 75265 13-19
SN74ABT3611
64x36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

ClKB / \ I \ ....__--J/ \ ...._____/ '--

__............~IS~U(~E~N1~)~ r-....t_h(_EN_1_1........__............................................__........____
~I
1 1
WiRB
7lZZZlZlZZZ/{ l~
1 11
MBB
7lZZZlZlZZZ/{ l~
ENB

BO-B35

ClKA /

WiRA

1 I 1 1
MBA _ _--+-1_ _---'/1 L ., 1
1 1 Isu(EN21 I.-------+i--! Ih(EN2) 1
ENA 1
I
1
1
fZ%T<1 ~~$~~~'~___~I__________
- 1
len H '-- Ipd(C.MRI --to! Idls 1----..1
AO-A35 W1 (remains valid In mall2 re Isler after read)

NOTE A: Port·A parity generation off (PGA = L)

Figure 9. Timing for Mail2 Register and MBF2 Flag

~1ExAs
INSTRUMENTS
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 SN74ABT3611
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

0001 - - - - - . . \ J
EVEN . fI
I I
WIRA I I \ 1
: : I~--------~I

MBA /Zlfl/?/{?zZZZ2Vl7flZzv/IV//flAl ~\\M

I I I I
PGA (;?ZlZz/4ZZV22?fl22Zzzzzzzzzzz t\»\\\\\~
tpd(O-PE) ~ tpd(O-PE) ~ tpd(E-PE) I----+j tpd(E-PE) It----1
Valid }I( Valid }I( Valid' \ Valid

NOTE A: CSA = Land ENA = H

Figure 10. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing

OO~
EVEN \ l ~------------------------------------
I I
W/RB : : \ ________ 1
I I I I
MBB vz;zz/ATITI2ZZZ2?A;mzwfl?l22d t\~
I I I I
paB vzzzzzt;zzzzzzzfll?7lllll2Z4 ~
tpd(O-PE) \t------.j tpd(O-PE) \t------.j tpd(E-PE) ~ tpd(E-PE) Y
PEFB Valid }I( Valid }I( Valid I \ Valid

NOTE A: CSB = Land ENB = H

Figure 11. ODD/EVEN, WIRB, MBB, and PGB to PEFB Timing

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13-21
SN74ABT3611
64 x36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCBS127D- JULY 1992 - REVISED SEPTEMBER 1995

OD~--------------------------~\
EVEN I~-----------------------------------
I
CSA ~L~OW~________________________~I-------------------------------- ___
I
WiRA ~,------------~i----------------
I I
MBA vz>zzzzzzz?
I 1
i
1
PGA vz/zzzzz;;d i )--------
A8,A17,
ten
I
'-I
1

II
1
I+--- tpd(E-PB) --I >II
I
~ tpd(o-PB) --+I >II
i-- tpd(E-PB) --+I
A26, A35 \, Mall2 Data A Generated Parity A Generated Parity )I{~M~al~12~D~at:-a

NOTE A: ENA = H

Figure 12. Parity-Generation Timing When Reading From the Mall2 Register

ODD/--------------------------~\
EVEN I~-----------------------------------
I
CSB~L~ow~________________________~I~---------------------------------
I
WffiB~'___ _ _ _ _ _ _ _ _ _ _ _~i------------------------
I I
MBB 2Z'?7!//!4 :
I I I
PGB vJ(?fll/Z{ i )------
I ~ tpd(E.PB) --.j I
B8,B17,
ten ~I
~
j+ tpd(M-DV) -.j I ~ tpd(o-PB) 1
I

>II
i-- tpd(E-PB) - :
B26, B35 ~ Generated Parity A Generated Parity )I{~M:-al::-:11-::D:-at:-a
Mall1
Data
NOTE A: ENS = H

Figure 13. Parity-Generation Timing When Reading From the Mail1 Register

~TEXAS
INSTRUMENTS
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 SN74ABT3611
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127D- JULY 1992 - REVISED SEPTEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Veel ............................................... ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Veel ........................................... ± 50 mA
Continuous output current, 10 (Vo = 0 to Veel ............................................. ± 50 mA
Continuous current through Vee or GND ................................................. ± 500 mA
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage O.S V
10H High-level output current -4 mA
10L Low-level output current S mA
TA Operating free-air temperature 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
VOH Vcc= 4.5 V, 10H =-4 mA 2.4 V
VOL VCC=4.5V, 10L= SmA 0.5 V
II VCC=5.5V, VI = VCC orO ±50 IJA
10Z VCC=5.5V, VO=Vcc orO ±50 IJA
Outputs high 60
ICC VCC=5.5V, 10=OmA, VI = VCC or GND Outputs low 130 mA
Outputs disabled 60
Ci VI =0, f= 1 MHz 4 pF
Co VO=O, f= 1 MHz 8 pF
:j: All tYPical values are at VCC = 5 V, TA = 25°C.

~TEXAS
INSTRUMENTS
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SN74ABT3611
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CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCBSI27D-JULY 1992-REVISED SEPTEMBER 1995

timing requirements over recommended ranges of supply voltage and operating free·air
temperature (see Figures 1 through 13)
'ABT3611-15 'ABT3611-20 'ABT3611-30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency, ClKA or ClKB 66.7 50 33.4 MHz
tc Clock cycle time, ClKA or ClKB 15 20 30 MHz
tw(ClKH) Pulse duration, ClKA and ClKB high 6 8 12 ns
tw(ClKl) Pulse duration, ClKA and ClKB low 6 8 12 ns
tsu(D1 Setup time, AO-A35 before ClKA i and BO-B35 before ClKBi 4 5 6 ns
Setup time, CSA, W/RA before ClKAi; CSB, W/RB,
tsu(EN1) 6 6 7 ns
before ClKBi

tsu(EN2) Setup time, ENA before ClKAi; ENB before ClKBi 4 5 6 ns

tsu(EN3) Setup time, MBA before ClKAi; ENB before ClKBi 4 5 6 ns
tsu(PG) Setup time, ODD/EVEN and PGB before ClKBit 4 5 6 ns
tsu(RS) Setup time, RST low before ClKAi or ClKBf:!: 5 6 7 ns
tsu(FS) Setup time, FSO and FS1 before RST high 5 6 7 ns
th(D) Hold time, AO-A35 after ClKAi and BO-B35 after ClKBi 1 1 1 ns
th(EN1) Hold time, CSA, W/RA after ClKAi; CSB, W/RB after ClKBi 1 1 1 ns
th(EN2) Hold time, ENA after ClKAi; ENB after ClKBi 1 1 1 ns
th(EN3) Hold time, MBA after ClKAi; MBB after ClKBi 1 1 1 ns
th(PG) Hold time, ODD/EVEN and PGB after ClKBit 0 0 0 ns
th(RS) Hold time, RST low after CLKA i or ClKBf:!: 6 6 7 ns
th(FS) Hold time, FSO and FS1 after RST high 4 4 4 ns
Skew time between ClKA i and ClKBi for EFA, EFB,
I sk1§ 8 8 10 ns
FFA, and FFB
Skew time. between ClKA i and ClKBi for AEA, AEB,
tsk2§ 9 16 20 ns
AFA, and AFB
t
..
Only applies for a rising edge of ClKB that does a FIFO read
:j: Requirement to count the clock edge as one of at least four needed to reset a FI FO
§ Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and
ClKB cycle.

~TEXAS
INSTRUMENTS
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 SN74ABT3611
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SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 1 through 13)
'ABT3611-15 'ABT3611-20 'ABT3611-30
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
ta Access time, CLKBi to BO-B35 2 10 2 12 2 15 ns
tpd(C-FF) Propagation delay time, CLKAi to FF 2 10 2 12 2 15 ns
tpd(C-EF) Propagation delay time, CLKBi to EF 2 10 2 12 2 15 ns
tpd(C-AE) Propagation delay time, CLKBi to AE 2 10 2 12 2 15 ns
tpd(C-AF) Propagation delay time, CLKAi to AF 2 10 2 12 2 15 ns
Propagation delay time, CLKAi to MBF1 low or MBF2 high and
tpd(C-MF) 1 9 1 12 1 15 ns
CLKBi to MBF2 low or MBF1 high
Propagation delay time, CLKAi to BO-B35t and CLKBi to
tpd(C-MR) 3 12 3 14 3 16 ns
AO-A35:1:

tpd(M-DV) Propagation delay time, MBB to BO-B35 valid 1 11 1 11.5 1 12 ns

Propagation delay time, AO-A35 valid to PEFA valid; BO-B35
tpd(D-PE) 3 12 3 13 3 14 ns
valid to PEFB valid

tpd(O-PE) Propagation delay time, ODD/EVEN to PEFA and PEFB 3 11 3 12 3 14 ns

Propagation delay time, ODD/EVEN to parity bits (A8, A 17, A26,
tpd(O-PB)§ 2 12 2 13 2 15 ns
A35) and (B8,B17,B26,B35)
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to
tpd(E-PE) 1 12 1 13 1 15 ns
PEFA; CSB, ENB, W/RB, MBB, or PGB to PEFB
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to
tpd(E-PB)§ parity bits (A8, A17, A26, A35); CSB, ENB, W/RB, MBB, or PGB 3 14 3 15 3 16 ns
to parity bits (B8, B17, B26, B35)
Propagation delay time, RST to AE low and (AF, MBF1, MBF2)
tpd(R-F) 1 15 1 20 1 30 ns
high
Enable time, CSA and W/RA low to AO-A35 active and CSB low
ten 2 10 2 12 2 14 ns
and W/RB high to BO-B35 active
Disable time, CSA or W/RA high to AO-A35 at high impedance
tdis 1 9 1 10 1 11 ns
and CSB high or W/RB low to BO-B35 at high impedance
..
t Wrltmg data to the mal11 register when the BO-B35 outputs are active and MBB IS high .
:I: Writing data to the mail2 register when the AO-A35 outputs are active and MBA is high.
§ Only applies when reading data from a mail register

~1ExA.s
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-25
SN74ABT3611
64x36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127D -JULY 1992- REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400 I .!. I I I
fd~ta = 112 fCIO~k VCC=S.SV /
3S0 -TA=2SoC
ct CL=OpF V
E /
C
I

~::J
300
VCC = Sz,
/
V
""/ . / ""
2S0

~V
~
(.)
:..
C.
a. 200
/
~ ~ V VCC =4.SV
::J
II)
I
1S0

~~
,
£(.)
(.)
100

SO , ~
o
o 10 20 30 40 SO 60 70 80

fclock - Clock Frequency - MHz

Figure 14

calculating power dissipation

The iCC(!) data for the graph was taken while simultaneously reading and writing the FIFO on the SN74ACT3611
with ClKA and ClKB operating at frequency fclock' All data inputs and data outputs change state during each
clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to
a zero-capacitance load. Once the capacitive load per data-output channel is known, the power dissipation can
be calculated with the equation below.
With iCC(!) taken from Figure 14, the maximum power dissipation (PT) of the SN74ABT3611 can be calculated
by:
PT = Vcc x ICC(!) + :E(CL x (VOH - Vod 2 x fo)
where:
CL = output capacitive load
fo switching frequency of an output
VOH = high-level output voltage
VOL = low-level output voltage
When no reads or writes are occurring on the SN74ABT3611, the power dissipated by a single clock (ClKA or
ClKB) input running at frequency fclock is calculated by:
PT = Vcc x fclock x 0.29 rnA/MHz

~1ExAS
INSTRUMENTS
13-26 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3611
64x36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SCBS127D- JULY 1992 - REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

5V

1.1 kn
From Output
Under Test - - - . - - - - .

680n -: ~ 30 pF
;;;;" (see Note A)

LOAD CIRCUIT

Timing
Input
j...-----
1.5 V
3V High-Level ~
1.5 V ~.~ -
3V

--~,q.----- GND Input I I GND

tsu~th *-
I
tw --.I
I
~-:-::-
~ 1.5 V ~
Data, 3V
Enable J ' 1.5 V ~ Low-Level 3V
Input GND Input ~ .::.~~ _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

~~:~~ ~1.5V \1.;;--- ::0

--+i 1.-1 tpLZ ---.: i+-- tpZL
, 1 _ _----r~~--- =3V
\I~'~--
Low-Level 1
Output _ ......~ : VOL Input --1(1.5 V
,
3V
GND
-+I ~tPZH
VOH tpd~ i+--+I- tpd
High-Level ,, _ _~I_- VOH
Output In-Phase
, I =OV Output
_ _--J.
j1.5V 'S..1.5V VOL
'\..::..
-+j ,.-tPHZ
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 15. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-27
13-28
 SN74ABT3612
64x36 x 2
CLOCKED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
SCBS129F -JULY 1992 - REVISED FEBRUARY 1996

• Free-Running ClKA and ClKB Can Be • EFB, FFB, AEB, and AFB Flags
Asynchronous or Coincident Synchronized by ClKB
• Two Independent 64 x 36 Clocked FIFOs • Passive Parity Checking on Each Port
Buffering Data in Opposite Directions • Parity Generation Can Be Selected for Each
• Mailbox-Bypass Register for Each FIFO Port
• Programmable Almost-Full and • low-Power Advanced BiCMOS Technology
Almost-Empty Flags • Supports Clock Frequencies up to 67 MHz
• Microprocessor Interface Control logic • Fast Access Times of 10 ns
• EFA, FFA, AEA, and AFA Flags • Package Options Include Space-Saving
Synchronized by ClKA 12Q-Pin Thin Quad Flat (PCB) and 132-Pin
Plastic Quad Flat (PQ) Packages

description
The SN74ABT3612 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock
frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64 x 36 dual-port SRAM
FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is
stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each
port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or
more devices can be used in parallel to create wider datapaths.
The SN74ABT3612 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The full flag (FFA, FFB) and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock
that writes data to its array. The empty flag (EFA, EFB) and almost-empty (AEA, AEB) flag of a FIFO are
two-stage synchronized to the port clock that reads data from its array.
The SN74ABT3612 is characterized for operation from O°C to 70°C.
For more information on this device family, see the application reports FIFO Mailbox-Bypass Registers; Using
Bypass Registers to Initialize DMA Control, and Parity-Generate and Parity-Check Features for
High-Bandwidth-Computing FIFO Applications in the 1996 High-Performance FIFO Memories Designer's
Handbook, literature number SCAA012A.

Copyright © 1996, Texas Instruments Incorporated

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-29
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F -JULY 1992 - REVISED FEBRUARY 1996

PCB PACKAGE
(TOP VIEW)

A23 822
A22 821
A21 GND
GND 820
A20 86 819
A19 85 818
A18 84 817
A17 83 816
A16 82 815
A15 81 814
A14 80 813
A13 79 812
A12 78 811
All 77 810
Al0 76 GND
GND 75 89
A9 74 88
A8 73 87
A7 72 Vee
Vee 71 86
A6 70 85
A5 69 84
A4 68 83
A3 67 GND
GND 66 82
A2 65 81
Al 64 80
AO 63 EF8
EFA 62 AE8
AEA 61 AF8

NC - No internal connection

~TEXAS
INSTRUMENTS
13-30 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

PQPACKAGEt
(fOP VIEW)

GND GND
AEA AE8
EFA EF8
AO 80
A1 81
A2 82
GND GND
A3 83
A4 84
A5 85
A6 86
VCC Vce
A7 87
A8 B8
A9 B9
GND GND
A10 810
A11 B11
Vce Vce
A12 B12
A13 B13
A14 814
GND GND
A15 B15
A16 B16
A17 B17
A18 818
A19 819
A20 820
GND GND
A21 821
A22 822
A23 823

8~~~~~re~8g~<~~~~~~~~~~~Mg8~re~~~~~8
>«<~«<>« ~<~<~mmm~mmm>mmm~mmm>

NC - No internal connection
t Uses Yamaichi socket IC51-1324-828

~TEXAS
INSTRUMENTS
POST OFFICE BOX 665303 • DALlAS. TEXAS 75265 13--31
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

functional block diagram

ClKA----~
CSA----~ Port-A
W i R A - - - - - i Control
E N A - - - - - i logic
PEFB
MBA ----~ Parity I
~~~~_ _ _....rIMMa~IIi11--l+'ir:tGen/CheckM"'----'"
I I Register ~~'=i==~:!======+-I--- PGB
r-~---------~-~'~~
l l i~
. i~ c
.2
0
._,
, ~.. 64x36 ... :E'~ .... 1 I
i II: SRAM I"'" ~ fii I"'" S I
• ++-+-1+..... ~
RST-
0001 _
Device
Control
,
,- 0 ,
i
! 104 .5
~-,
CI
Do
S:-- 36

EVEN
,
I
Write
Pointer
I Read
Pointer
,
I
, .t J ,
, Status-Flag I--------i'----If--t-++-+--- EFB
, FIF01 logic , AEB
L _ _ _ _ _ _ _ _~---------~
36

FSO-----+~~I----------~ Programmable-Flag
FS1---------+~f--t-~--------~ Offset Register
BO-B35
AO-A35--4-+---~

rFiFO;-- -i'
Status-Flag
-,
II--------t-----t~t-t-+---- FFB
logic AFB

I, .. I
+
Read I+ Write I
I,
I I Pointer Pointer I 36

, I
'r--;:- - - ,
~,.~ 5 ~~,
, ~ 4f ~ ~R~: f40 •1 ,
I~~ IT! ~~ I :
~~L~_~ _________ ~J
PGA
Mall2
W Parity WI-4-l..,~R~eg~l~st!!er:""JI-4_ _ _"'Jttijtj-,
PEFA ----------':.------....
- f---------. ~-I Gen/Check I ......- - ClKB
MBF2------------~I----------------~ Port-B ..........- - CSB
Control ....., . . - - - WiRB
logic ENB
......- - MBB
'----~

~TEXAS
INSTRUMENTS
13-32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

Terminal Functions
PIN NAME 1/0 DESCRIPTION
AO-A35 110 Port-A data. The 36-bit bidirectional data port for side A.
0 Port-A almost-empty flag. Programmable flag synchronized to ClKA. AEA Is low when the number of words in FIF02
AEA
(portA) is less than or equal to the value in offset register X.
0 Port-B almost-empty flag. Programmable flag synchronized to ClKB. AEB is low when the number of words in FIF01
AEB
(port B) is less than or equal to the value in offset register X.
0 Port-A almost-full flag. Programmable flag synchronized to ClKA. AFA is low when the number of empty locations in
AFA
(portA) FIFOl is less than or equal to the value In offset register X.
0 Port-B almost-full flag. Programmable flag synchronized to ClKB. AFB is low when the number of empty locations in
AFB
(port B) FIF02 is less than or equal to the value in offset register X.
BO-B35 110 Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
ClKA I
or coincident to ClKB. EFA. FFA. AFA. and AEA are synchronized to the low-te-high transition of ClKA.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
ClKB I
or coincident to ClKA. EFB. FFB. AFB. and AEB are synchronized to the low-to-high transition of ClKB.
Port-A chip select. GSA must be low to enable a low-te-high transition of CLKA to read or write data on port A. The
CSA I
AO-A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-te-high transition of ClKB to read or write data on port B. The
CSB I
BO-B35 outputs are in the high-impedance state when CSB is high.
Port-A empty flag. EFA is synchronized to the low-te-high transition of ClKA. When EFA is low. FIF02 is empty and
0 reads from its memory are disabled. Data can be read from FIF02 to the output register when EFA is high. EFA is forced
EFA
(portA) low when the device is reset and is set high by the second low-te-high transition of ClKA after data is loaded into empty
FIF02 memory.
Port-B empty flag. EFB is synchronized to the low-te-high transition of ClKB. When EFB is low. FIFOl is empty and
0 reads from its memory are disabled. Data can be read from FI FOl to the output register when EFB is high. EFB is forced
EFB
(port B) low when the device is reset and is set high by the second low-te-high transition of ClKB after data is loaded into empty
FIFOl memory.
ENA I Port-A enable. ENA must be high to enable a low-te-high transition of ctKA to read or write data on port A.
ENB I Port-B enable. ENB must be high to enable a low-te-high transition of ClKB to read or write data on port B.
Port-A full flag. FFA is synchronized to the low-te-high transition of ClKA. When FFA is low. FIFOl is full and writes to
.0
FFA its memory are disabled. FFA is forced low when the device is reset and is set high by the second low-to-high transition
(portA)
of ClKA after reset.
Port-B full flag. FFB is synchronized to the low-to-high transition of ClKB. When FFB is low. FIF02 is full and writes to
0
FFB its memory are disabled. FFB is forced low when the device is reset and is set high by the second low-to-high transition
(port B)
of ClKB after reset.
Flag-offset selects. The low-te-high transition of RST latches the values of FSO and FS 1. which selects one offour preset
FS1.FSO I
values for the almost~mpty flag and almost-full flag offset.
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
MBA I AO- A35 outputs are active. a high level on MBA selects data from the mail2 register for output and a low level selects
FIF02 output register data for output.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
MBB I BO-B35 outputs are active. a high level on MBB selects data from the maill register for output and a low level selects
FIFOl output register data for output.
. MaUl register flag. MBFl is set low by the low-to-high transition of ClKA that writes data to the maill register. Writes
MBFl 0 to the maUl register are inhibited while MBFl Is low. MBFl is set high by a low-to-high transition of ClKB when a port-B
read is selected and MBB is high. MBFl is set high when the device is reset.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 13-33
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

Terminal Functions (Continued)

PIN NAME I/O DESCRIPTION
Mail2 register flag. MBF2 is set low by the low-te-high transition of ClKB that writes data to the mail2 register. Writes
MBF2 0 to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-te-high transition of ClKA when a port-A
read is selected and MBA is high. MBF2 is set high when the device is reset.
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/
I ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
EVEN
for a read operation.
Port-A parity error flag. When any byte applied to AO-A35 fails parity, PEFA is low. Bytes are organized as AD-AS,
A9 - A17, A1S - A26, and A27 - A35, with the most significant bit of each byte serving as the parity M. The type of parity
0 checked is determined by the state of ODD/EVEN.
PEFA
(portA) The parity trees used to check the AO- A35 inputs are shared by the mail2 register to generate parity if parity generation
is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having W/RA low, MBA high, and PGA
high, PEFA is forced high regardless of the state of the AO-A35 inputs.
Port-B parity error flag. When any byte applied to terminals BO-B35 fails parity, PEFB is low. Bytes are organized as
BO-B8, B9-B17, B18-B26, and B27 -B35, with the most significant bit of each byte serving as the parity bit. The
0 type of parity checked is determined by the state of ODD/EVEN.
PEFB
(port B) The parity trees used to check the BO - B35 inputs are shared by the mail1 register to generate parity if parity generation
is selected by PGB. Therefore, if a mail 1 read with parity generation is set up by having W/RB low, MBB high, and PGB
high, PEFB is forced high regardless of the state of the BO-B35 inputs.
Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity generated
PGA I is selected by the state of ODD/EVEN. Bytes are organized as AD-AS, A9-A17, A18-A26, and A27-A35. The
generated parity bits are output in the most significant bit of each byte.
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated
PGB I is selected by the state of ODD/EVEN. Bytes are organized as BO-BS, B9-B17, B18-B26, and B27-B35. The
generated parity bits are output in the most significant bit of each byte.
Reset. To reset the device, four low-te-high transitions of ClKA and four low-te-high transitions of ClKB must occur
RST I while RST is low. This sets AFA, AFB, MBF1, and MBF2 high and EFA, EFB, AEA, AEB, FFA, and FFB low. The
low-te-high transition of RST latches the status of FS1 and FSO to select almost-full flag and almost-empty flag offset.
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
W/RA I
low-te-high transition of ClKA. The AO-A35 outputs are in the high-impedance state when W/RA is high.
Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
W/RB I
low-te-high transition of ClKB. The BO-B35 outputs are in the high-impedance state when W/RB is high.

detailed description
reset
The SN74ABT3612 is reset by taking the reset (RST) input low for at least four port-A clock (ClKA) and four
port-B clock (ClKB) low-to-high transitions. RST can switch asynchronously to the clocks. A device reset
initializes the internal read and write painters of each FIFO and forces the full flags (FFA, FFB) low, the empty
flags (EFA, EFB) low, the almost-empty flags (AEA, AEB) low, and the almost-full flags (AFA, AFB) high. A reset
also forces the mailbox flags (MBF1 , MBF2) high. After a reset, FFA is set high after two low-to-high transitions
of ClKA and FFB is set high after two low-to-high transitions of ClKB. The device must be reset after power
up before data is written to its memory.
A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected
by the flag-select (FSQ, FS1) inputs. The values that can be loaded into the register are shown in Table 1.

~1ExAs
INSTRUMENTS
13-34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

reset (continued)

Table 1. Flag Programming

ALMOST-FUll AND
FS1 FSO RST ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H H l' 16
H l l' 12
L H l' 8
L L l' 4

FIFO write/read operation

The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (WiRA). The AO-A35 outputs are in the high-impedance state when either CSA or WiRA is
high. The AO-A35 outputs are active when both CSA and WiRA are low. Data is loaded into FIF01 from the
AO-A35 inputs on a low-to-high transition of CLKA when CSA is low, WiRA is high, ENA is high, MBA is low,
and FFA is high. Data is read from FIF02 to the AO-A35 outputs by a low-to-high transition of CLKA when CSA
is low, WiRA is low, ENA is high, MBA is low, and EFA is high (see Table 2).

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA elKA AO-A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L l' In high-impedance state FIF01 write
L H H H l' In high-impedance state Mail1 write
L L L L X Active, FIF02 output register None
L L H L l' Active, FI F02 output register FIF02read
L L L H X Active, mail2 register None
L L H H l' Active, mail2 register Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A. The state of the port-B data (BO-B35) outputs is
controlled by the port-B chip select (CSB) and the port-B write/read select (WiRB). The BO-B35 outputs are
in the high-impedance state when either CSB or W/RB is high. The BO-B35 outputs are active when both CSB
and W/RB are low.
Data is loaded into FIF02 from the BO-B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB
is high, ENB is high, MBB is low, and FFB is high. Data is read from FIF01 to the BO-B35 outputs by a
low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, MBB is high, and EFB is high (see
Table 3).
The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select
can change states during the setup- and hold-time window of the cycle.

~ThxAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 13-35
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

CSB W/RB ENB MBB ClKB BO-B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L l' In high-impedance state FIF02write
L H H H i In high-impedance state Mail2write
L L L L X Active, FIFOI output register None
L L H L l' Active, FIFOI output register FIFOI read
L L L H X Active, maill register None
L L H H l' Active, maill register Maill read (set MBFl high)

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability
by reducing the probability of metastable events on the output when ClKA and ClKB operate asynchronously
to one another (see the application report Metastability Performance of Clocked FIFOs in the 1996
High-Performance FIFO Memories Data Book, literature number SCAD003C). EFA, AEA, FFA, and AFA are
synchronized to ClKA. EFB, AEB, FFB, and AFB are synchronized to ClKS. Tables 4 and 5 show the
relationship of each port flag to FIF01 and FIF02.

Table 4. FIF01 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS TOClKB TOClKA
IN FIF01t
EFB AEB AFA FFA
0 L L H H
1 toX H L H H
(X +1) to [64 - (X +1)] H H H H
(64 -X) to 63 H H L H
64 H H L L
t X is the value in the almost-empty flag and almost-full flag offset register.

Table 5. FIF02 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS TOCLKA TOCLKB
IN FIF02t
EFA AEA AFB FFB
0 L L H H
1 toX H L H H
(X +1) to [64 - (X +1)] H H H H
(64 -X) to 63 H H L H
64 H H L L
t X is the value in the almost-empty flag and almost-full flag offset register.

~TEXAS
INSTRUMENTS
13-36 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F -JULY 1992- REVISED FEBRUARY 1996

empty flags (EFA, EFB)

The empty flags of a FIFO is synchronized to the port clock that reads data from its array. When the empty flag
is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and
attempted FIFO reads are ignored.
The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state
machine that controls an empty flag monitors a write-painter and read-pointer comparator that indicates when
the FIFO SRAM status is empty, empty+ 1, or empty+2. A word written to a FIFO can be read to the FIFO output
register in a minimum of three cycles of the empty flag synchronizing clock; therefore, an empty flag is low if
a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that
reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is
set high by the second low-to-high transition of the synchronizing clock and the new data word can be read to
the FIFO output register in the following cycle.
A low-to-high transition on an empty flag synchronizing clock begins the first synchronization cycle of a write
if the clock transition occurs at time tsk1' or greater, after the write. Otherwise, the subsequent clock cycle can
be the first synchronization cycle (see Figures 6 and 7).
full flags (FFA, FFB)
The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is high,
a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is
lowand attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls the full
flag monitors a write-painter and read-painter comparator that indicates when the FIFO SRAM status is full,
full-1, or full-2. From the time a word is read from a FIFO, the previous memory location is ready to be written
in a minimum of three cycles of the full flag synchronizing clock; therefore, a full flag is low if less than two cycles
of the full-flag synchronizing clock have elapsed since the next memory write location has been read. The
second low-to-high transition on the full-flag synchronizing clock after the read sets the full flag high and data
can be written in the following clock cycle.
A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the
clock tranSition occurs at time t5k1, or greater, after the read. Otherwise, the subsequent clock cycle can be the
first synchronization cycle (see Figures 8 and 9).
almost-empty flags (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state
machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty state is
defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of
four preset values during a device reset (see reset). An almost-empty flag is low when the FIFO contains X or
less words in memory and is high when the FIFO contains (X + 1) or more words.
Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for the
almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1)
or more words remains low if two cycles of the synchronizing clock have not elapsed since the write that filled
the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of the
synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an
almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t5k2' or greater,
after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figures 11 and 12).

-!!1lEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-37
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

almost-full flags (AFA, AFB)

The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine
that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the value of
the almost-full and almost-empty offset register (X). This register is loaded with one'of four preset values during
a device reset (see rese~. An almost-full flag is low when the FIFO contains (64 - X) or more words in memory
and is high when the FIFO contains [64 - (X + 1)] or less words.
Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill; therefore. the almost-full flag of a FIFO containing [64 - (X + 1)]
or less words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced
the number of words in memory to [64 - (X + 1)]. An almost-full flag is set high by the second low-to-high
transition of the synchronizing clock after the FIFO read that reduces the number of words in memory to
[64 - (X + 1)]. A low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization
cycle if it occurs at time tsk2, or greater, after the read that reduces the number of words in memory to
[64 - (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see
Figures 13 and 14).
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port-data-transfer operation. A low-to-high transition on ClKA writes AO-A35 data to the mail1 register
when a port-A write is selected by CSA, W/RA, and ENA and MBA is high. A low-to-high transition on ClKB
writes BO-B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and MBB
is high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted writes to a
mail register are ignored while the mail flag is low.
When a port's data outputs are active, the data on the bus comes from the FIFO output register when the port
mailbox-select input (MBA, MBB) is low and from the mail register when MBAIMBB is high. The mail1 register
flag (MBF1) is set high by a low-to-high transition on ClKB when a port-B read is selected by CSB, W/RB, and
ENB and MBB is high. The mail2 register flag (MBF2) is set high by a low-to-high transition on ClKA when a
port-A read is selected by CSA, W/RA, and ENA and MBA is high. The data in a mail register remains intact
after it is read and changes only when new data is written to the register.
parity checking
The port-A inputs (AO-A35) and port-B inputs (BO-B35) each have four parity trees to check the parity of
incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a low level on
the port-parity-error flag (PEFA, PEFB). Odd- or even-parity checking can be selected and the parity-error flags
can be ignored if this feature is not desired.
Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select
input. A parity error on one or more bytes of a port is reported by a low level on the corresponding PEFA, PEFB.
Port-A bytes are arranged as AO-AS, A9-A 17, A18-A26, and A27 -A35, with the most significant bit of each
byte used as the parity bit. Port-B bytes are arranged as BO-B8, B9-B17, B18-B26, and B27 -B35, with the
most significant bit of each byte used as the parity bit. When odd/even parity is selected, PEFA, PEFB is low
if any byte on the port has an odd/even number of low levels applied to the bits.
The four parity trees used to check the AO-A35 inputs are shared by the mail2 register when parity generation
is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is
selected with W/RA low, CSA low, ENA high, MBA high, and PGA high, PEFA is held high regardless ofthe levels
applied to the AO-A35 inputs. Likewise, the parity trees used to check the BO-B35 inputs are shared by the
mail1 register when parity generation is selected for port-B reads (PGB = high). When a port-B read from the
mail1 register with parity generation is selected with W/RB low, CSB low, ENB high, MBB high, and PGB high,
PEFB is held high regardless of the levels applied to the BO-B35 inputs.

~TEXAS
INSTRUMENTS
13-38 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

parity generation
A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the
SN7 4ABT3612 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged
as AO-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte used as the parity bit.
Port-B bytes are arranged as BO-B8, B9-B17, B18-B26, and B27 -B35, with the most significant bit of each
byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all 36 inputs regardless
ofthe state ofthe parity-generate select (PGA, PGB) inputs. When data is read from a port with parity generation
selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the
ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the most
significant bits of each byte as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the
output register. Therefore, the port-A parity generate select (PGA) and odd/even parity select (ODD/EVEN)
have setup- and hold-time constraints to the port-A clock (ClKA) and the port-B parity generate select (PGB)
and ODD/EVEN have setup- and hold-time constraints to the port-B clock (ClKB). These timing constraints only
apply for a rising clock edge used to read a new word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port-B bus (BO-B35) to check parity and
the circuit used to generate parity for the mail2 data is shared by the port-A bus (AO-A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in a mail register when W/RA, W/RB
is low; MBA, MBB is high; CSA, CSB is low; ENA, ENB is high; and PGA, PGB is high. Generating parity for
mail-register data does not change the contents of the register.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-39
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

ClKA
--tI ~ th(RS)
ClKB
I
-.I I- tsu(RS) I : tsu(FS) ~Hj th(FS) I :
R S T - - -....~ I I III : I
I : I I I I I
FS1,FSO

I tpd(C-FFJ ~ tpd(C-FFJi-+---tj
FFAS\~~~ i I
I tpd(C-EF) L I
EFA S\\\\\\~ I
~ I I I
I tpd(C-FF) ~I tpd(C-FF)~
FFB SS\\\\'r~~ y--
I tpd(CjF) ~
EFBS\\~~~
I 101 I ~ tpd(C-AE)
AEA~~
I ~
AFA VZZ;ZZZZZZZZZZZ 72?7A
~tPd(C-AF) ?
_ tpd(R-F) ~ I I I
~B:F~ ?Z2lZZZlZZZl :
I- .! Ipd(C-AE)
AEB SS\\\\\~~
; ;IPd(C-AF)

Figure 1. Device Reset Loading the X Register With the Value of Eight

~TEXAS
INSTRUMENTS
13-40 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F -JULY 1992- REVISED FEBRUARY 1996

14 Ie ~I

:... Iw(CLKH) t Iw(CLKL) 1

CLKA } '\ Y \ y
I
\ ( 'L-
i I
I I
FFA High I I
Isu(EN1)
I
14 ~14 .: Ih(EN1) I I
I I
CSA
Isu(EN1)
~14 :W&
.1 4~ Ih(EN1)
I
I
1/
I
I
1
WiRA
?ZlZ2Zll?Z/Z{ I
I~ 1 : \\\\\\\\\~
Isu(EN3) 14 ~IUI Ih(EN3) I I
MBA

ENA m?ZZllZZ?/.f
tSU(EN2~
I

1
~
_
I
r Ih(EN)
~4\\\
I
Isu(EN2)~ !+- Ih(EN2)
Jrzzzz:z?m
Isu(O) 14 ~ul Ih(O)
AO-A35 No Operation j88888888
I 1

=~:: ~
Ipd(O-PE) j4----tI Ipd(O-PE) j4----tI
PEFA

tWritten to FIF01
Figure 2. Port-A Write-Cycle Timing for FIF01

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS. TeXAS 75265 13-41
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992- REVISED FEBRUARY 1996

14
~ tw(ClKH) +
te

tw(ClKl) 1
~I

ClKB
I " rI
I
\ y
I
I
\ (
I
I
'-
FFB High I
tsu(EN1)
I
I- ~I- ~ th(EN1) I I
I I
CSB
tsu(EN1)
~I- i~
~IUI th(EN1)
I
I
II
I
I I
WiRB 0?7!Z1Z222{ I~ I I \S\\\\\\\'
tsu(EN3) I- ~I ul th(EN3) I I
MBB

?/?ZI//ZZZIC
tSU(EN~
I
aa f
I _\\§§\~«
I
th(EN2)
I
tsu(EN2)~ j+- th(EN2)
. V/!ZZZZZZ/
ENB

BO-B35
tsu(D) I- +.! th(D)
((10 Operation i8888&$8;
I I
=~ I I ~
tpd(D-PE) ~ tpd(D-PE) ~
PEFB

t Written to FIF02
Figure 3. Port·B Write-Cycle Timing for FIF02

-!!1 TEXAS
INSTRUMENTS
13-42 POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
 SN74ABT3612
64 x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

~ ~ ~
i+ tw(ClKH) - - tw(ClKl) ..I
ClKB )I { },---"",,\ (,---"""\'-_ _--':y,..--~'_
I I
High
I I
I I
I I
~I'L.----------t-______________
I I
~--------------~-J/
- I
I I I
WiRB .......$....$....$....~
'-\ I I
..,. I I
_ _+I~ I I
MBB I). I I I
I I tsu(EN2) , tsu(EN2) I tsu(EN2) I
I ~ ~ "'----I
I .J. I -I I+- th(EN2) I --tj I+- th(EN2) I --tj i4- th(EN2)
ENB mz/4V2221 i WO<XXXXXXYI I ~ tz;mzzz;
tpd(M-DV) .I
ten-
~ ·11 ~ ta -'I
I
i _,
j+"ta-.:
ope':tlon HI tdls

BO-B35 -----~ pr§us Dataf

t (PG) I ~
*
~ th(PGk (PG) I.
Word 1&
-.
"
~ th(PG)
Word 2t j

~;~i~~~~_
EVEN

t Read from FIF01

Figure 4. Port·B Read·Cycle Timing for FIF01

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13-43
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992- REVISED FEBRUARY 1996

~ ~ ~
:.... tw(CLKH) ..I+- tw(CLKL) ..I
CLKA I \. },---""'\\ ( \ yr---~,-
I I I
I I I
High I I I
I I I
} : I : I
I I I
W/RA ~S~S:~0~~~~: : 1!/IlflZl/
1 I I
MBA ---If--"",,\ I I
I I tSU(EN2)i tsu(EN2)1 tSU (EN2)1
I 1 ~ ~ r.:::=;I
I 1 1 -I i+- th(EN2) 1 -I I+- th(EN2) 1 ~ I+- th(EN2)
ENA //?ZZ?ZTfllJ :~ I t\\\S\-~~~ (zmzlfo
I _I I I
t dIM OV)
H 14
I :.- ta -+I ~ ta
No
~ tdls
AO-A35

PGA,
p - ten

tsu(PG) ~ .~~
~ preVI~US Oatat * Word 1& *
-.j Operation

Word 2t j

0001 ~'-_--I~""_""""-'I""""-'I""""""_'-._ - - I ~~...u...u'-ll.lilo.li.OL4L4.i1.L..ii.ii...A.iIi~""

EVEN

t Read from FIF02

Figure 5. Port-A Read-Cycle Timing for FIF02

-!!1
TEXAS
INSTRUMENTS
13-44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
SCBS129F-JULY 1992 - REVISED FEBRUARY 1996

ClKA
I
I I
CSA Low I I
I I
WiRA High ~ I
i ~ I.- th(E~3)
tsu(EN3)
MBA ~~ ~"'0""'?/:~0~0~0-r0-r0'r'0'r'0~0~'//."'-::/:"'-::(:~/:""'?0""'?0""0""0~2-r2-r2'r'2r2~~~2"'-::'//."""(:~'/""'?2""2""0~2~2-r2-r2""2'r'2r2~2~V
,. -: /:,. . ,/:~'/" '?
t (EN2)?
SU ~ lhjgN2}
ENA Il/I/d I S...$~~...:'»____________________
\;:Q.$...
I I
-FFA High t ... _I
I I
AO-A35

tw(ClKH) ~ I tw(CLKL)
ClKB 1 2

EFB _________F_IF_O_1_Em~p~~~______________~

t tsk1 is the minimum time between a rising ClKA edge and a rising ClKS edge for EFS to transition high in the next ClKS cycle. lithe time between
the rising ClKA edge and rising ClKS edge is less than tsk1. the transition of EFS high may occur one ClKS cycle later than shown.

Figure 6. EFB-Flag Timing and First Data Read When FIF01 Is Empty

-!/} TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-45
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

ClKB
I
CSB ~lo~w~ ____ ~I
I______ ~ ________________________________________________
I
WiRB High ~ I
tsu(EN3) i --.I *- th(EN3) .
MBB S\\\\~ k?'V(/ZZZZ/Z2ZZ//IZlZZZ2ZZZ2?ZZZ
ENB
tSU(ENZ?
t'//~ i ~:~~~
~~_.S.S.~~S.\~ __________________________________________
I I
I .
FFB High tsu(O) H I
BO-B35

~k1t ~ ~-I Iew(ClKl)

tw(ClKH) ~ -
ClKA 1 2

EFA _________
F_IF_02_E_m~p~ty~_______________ _ J
i
I
CSA low I
~~----------------------------~I~------------------------
I
WiRA low I
~------------------------------------------~I-----------------------------------
MBA low I
tS~EN2~ j4- th(EN2)

t tsk1 is the minimum time between a rising ClKS edge and a rising ClKA edge for EFA to transition high in the next ClKA cycle. If the time between
the rising ClKS edge and rising ClKA edge is less than tsk1. the transition of EFA high may occur one ClKA cycle later than shown.

Figure 7. EFA·Flag Timing and First Data Read When FIF02 Is Empty

~TEXAS
INSTRUMENTS
13-46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
SCBSt29F - JULY 1992 - REVISED FEBRUARY 1996

I.-- tc ----tI
~I
' _-
tw(CLKH) :.. ,.. tw(CLKL)

I \, " ,'-_---1/ '''--___I ,'-_---1/

eLKB .....
CSB ~Low~ ________ -+I__________________________________________________
wffiB ~LOW~ ________ ~I I __________________________________________________
MBB ~Lo~w~ ____ ~ __ I
+I~ ________________________________________________
taU(EN2) 1~~h(EN2)
~~-~~~~~$~\~-----------------------------------------
ENB
II??A' I
High I
BO-835 Previous Word In FIF01 Oul ul R 18I8r Nexl Word From FIF01

!+" tak1 t -.lit-it- - tc ---.I

CLKA ~""'_---II"'-""'"
tw(CLKH)
)1
~ t\4
'l
,
{2
tpd(Q-FF) I..
tw(CLKL)
',--_~I
-I I..
,~ tpd(Q-FF)
~

FFA F1F01 Full

-------------------------------~
I I
I ,'------
C~ Low I
--~----------------------------------~I-------------
WiRA High I

ENA

AO-A35
ToFIF01

t tskl is the minimum time between a rising ClKBedge and a rising ClKA edge for FFA to transition high in the next ClKA cycle. lithe time between
the rising ClKB edge and rising ClKA edge is less than tskl, m may transition high one ClKA cycle later than shown.

Figure 8. FFA-Flag Timing and First Available Write When FIF01 Is Full

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265 13-47
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F -JULY 1992 - REVISED FEBRUARY 1996

I.--- te -----tI
tw(CLKH) ~ 14 ~ tw(CLKL)
CLKA

CSA
I \ . II '\.-_JI
~Lo~w~_________i~
1
_________________________________________________
' ...._ - - - . 1 ' ...._---'1 ,----
W/RA ___________1
~LO~W '~ _________________________________________________

MBA -=Lo~w~ _________1 I~ _________________________________________________

tsu(EN21 ~""tt,(EN2)
~~~~$~$~~~-------------------------------------
ENA

1
High

AO-A35 Previous Word In FIF02 Output Re Isler Next Word From FIF02

t+- tsk1 t --.1"14_ _ te ----.I

~
CLKB ,,'-_--..1 1, . -.......,
tw(CLKH) 14
) 1 "
tpd(C-FF)
, tw(CLKL)
b
14
,'-_---:(
_I 14
,. . .___r -
-I tpd(C-FF)
FFB
--------~~----------~
FIF02 Full I I
1
,"'------
CSB Low 1

~~-----------------------~I----------------
W/RB High 1

ENB

BO-B35

t tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition high in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tsk1, FFB may transition high one CLKB cycle later than shown.

Figure 9. FFB-Flag Timing and First Available Write When FIF02 Is Full

~1ExAs
INSTRUMENTS
13-48 POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F -JULY 1992- REVISED FEBRUARY 1996

ClKA
tsu(EN2) ~ : - th(EN2)
ENA
~~ I~~S~S~~~S~S~~~ _______________________________________
I'- tsk2t -t/
ClKB
!4---~tf tpd(C-AE) 14 ~
AEB X Words In FIF01 Y(X + 1) Words In FIF01 J \...
tsu(EN2) H 14- th(EN2)
ENB ________________________________________e~~2~2~2~2~2g~ ~~
t tsk2 is the minimum time between a rising ClKA edge and a rising ClKB edge for AEB to transition high in the next ClKB cycle. lithe time between
the rising ClKA edge and rising ClKB edge is less than tsk2, AEB may transition high one ClKB cycle later than shown.
NOTE A: FIF01 write (CSA = l, WiRA = H, MBA = l), FIF01 read (CSB = l, WiRB = l, MBB = l).

Figure 10. Timing for AEB When FIF01 Is Almost Empty

ClKB
:~([N:-}M
ENB ~~67
:-- th(EN2)
1~~$.S.S.S.0.~~ _____________________________________
If- tsk2t -t/
ClKA
~
! 4 - - -....... tpd(C-AE) 1.._--.......
AEA X Words In FIF02 y(X + 1) Words In FIF02
tsu(EN2)
J
H r-
'- th(EN2)
ENA ______________________________________~4V~.2.?2./.?4~ \S>s\$SS\
t tsk2 is the minimum time between a rising ClKB edge and a rising ClKA edge for AEA to transition high in the next ClKA cycle. If the time between
the rising ClKB edge and rising ClKA edge is less than tsk2, AEA may transition high one ClKA cycle later than shown.
NOTE A: FIF02 write (CSB = l, WiRB = H, MBB = l), FIF02 read (CSA = l, WiRA = l, MBA = l).

Figure 11. Timing for AEA When FIF021s Almost Empty

-!II TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-49
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

14- tsk2t ----I

ClKA I \ ( \
/"'-+1""\ Y-1- ....\ 12 \ ;-
ENA
tsu(EN2) i+---==. th(EN2)t 1
//~~~~0~$~$~$~$~$\~______~1__________________~_____________
1
1
1
tpd(C-AF) I.~ I tpd(C-AF) I. ~
-----------.[1 (64 _ X) Words In FIF01
AFA [64 - (X + 1)] Words In FIF01 '-----r---------------'
1

ClKB--t
\'--~I "'~i 1~....t--t-h("'\E~~2j-~/ \ ....._--oJ/ '--
ENB ________________ ~/~2/.~~~7~_~2~~~~0.$.S.S.~.$~\~_____________________
t tsk2 is the minimum time between a rising ClKA edge and a rising ClKB edge lor AFA totransition high in the next ClKA cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tsk2. AFA may transition high one ClKB cycle later than shown.
NOTE A: FIF01 write (CSA = l. WiRA = H. MBA = l). FIF01 read (CSB = l. WiRB = l. MBB = l).

Figure 12. Timing for AFA When FIF011s Almost Full

14-- tsk2t ~
ClKB I \ ( \~_--oJI"'-+1"'\\....._~y-1- ....\ 12 \~_..J;-
tsu(EN2) i+---==. t th(EN2) 1 1
ENB IlZlI7fll ~'\\\\\'\ 1 1
tpd(C-AF) 14 tpd(C-AF) II+.--~~
Ir----
AFB [64 - (X + 1)] Words In FIF02

I
J.....--~\ I \'--~/
ClKA--t \1-_""/
th(EN2)
\
ISU(EN2>-~
ENA ________________~t/.~/~/~/~/~/lu~ '~0.$.$.$.$.~~
r- ______________________
'--
t tsk2 is the minimum time between a rising ClKB edge and a rising ClKA edge for AFB to transition high in the next ClKB cycle. Ifthe time between
the rising ClKB edge and rising ClKA edge is less than I sk2. AFB may transition high one ClKA cycle later than shown.
NOTE A: FIF02 write (CSB = L. W/RB= H, MBB = L). FIF02 read (CSA = l. W/RA = L. MBA = L).

Figure 13. Timing for AFB When FIF021s Almost Full

~1ExAs
INSTRUMENTS
13-50 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
SCBS129F -JULY 1992 - REVISED FEBRUARY 1996

ClKA I , I ' ....__ I .J ''-_ _--II

~ ~ th(EN1)
tsu(EN1)
-----~~~I-------------------------------
I I
W/RA
<?llZZ/21A4 : m
MBA

I II
ENA ????/?????2?{ I... .

AO-A35
~ I
I ,....--~I--~I ' ....----1 '. . _______
ClKB

------~r---~\
t tpd(C-MF) -.j
. . __________
r --I
tpd(C-MF)
_+I-------J)--------
I I
~'----~1----------~:----J1
W/RB ~s~s~s~S\~"~i: : ?/.,""z-"z.,.z'"?'z'"?'zrz.,..z'-;
I I I I
MBB _ _ _~II_ _ _~/I I ~LI·' th(EN2) I
tsu(EN2) I+~----+lp~

b0227 ~~S~S.&~-TI-----
ENB

ten
I
I
H 1II41i4----+--~ tdls
I
i-----.!
BO-B35
FIF01 Output Register

NOTE A: Port-B parity generation off (PGB = L)

Figure 14. Timing for Mail1 Register and MBF1 Flag

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13-51
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F - JULY 1992 - REVISED FEBRUARY 1996

ClKB / , I ''-__....J/ ,'__ _--J/

tsu(EN1) ~ :--- th(EN1)
------~~~I----------------------------------
I I
WiRB
?llZ/flVfl1 I m
1_
I I I
MBB
7ZZZZI7ZZ2'Z4 1m
ENB 7//7///7//71
BO-B35
~ I
ClKA /
IF --I
''-----1r
',---~I--~/
-.I
,'-_______
tpd(C-MF) tpd(C-MF)
-------~---~\'-_ _ _ _ _~I--_ _ _) - - - - - - -
I I
~'-------~I-------- ----------~I______-J{ __
WiRA
TI/?i'4 I I }\\\\~
MBA ______~I______~/: I I
I II tsu(EN2) ~I.--.j th(EN2) i
ENA I II I?Z/Zl \:,-$~$~S'~_.;..I______
I 141 ~I tpd(M-OV) I
ten H i4----+---.I tpd(C-MR) tdls i-------.!
AO-A35 W1 (remains valid In mall2 re Ister after read)
FIF02 Output Register

NOTE A: Port-A parity generation off (PGA = L)

Figure 15. Timing for Mail2 Register and MBF2 Flag

~1EXAS
INSTRUMENTS
13-52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
SCBS129F -JULY 1992 - REVISED FEBRUARY 1996

0001
EVEN ). t
1 1
WIRA 1 1 \ _ _ _ _ _...... 1
I I 1 1
MBA VZl7ATfl/fl2Z/Z/l/Z(2ZZZA ~~
1 1 1 1
PGA 22ZZlTJTflTflZ?flV?7~ $\~~
tpd(o-PE)
Valid

NOTE A: CSA = L, ENA = H

i---I
* tpd(O.PE) ~
Valid * tpd(E·PE) ~
Valid "1
tpd(E·PE) 1---..1
{ Valid

Figure 16. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing

0001
EVEN ). t
1 1
W/RB : : \ t,-----
1 1 I~--------~I

MBB V2V7!/1fiZ?ZlZlPZ)ZZZZWfl/2/Z;f ~~
I 1 1 1
PGB vzzzzz;?zzzzzzmA;vw~ ~\\~'\0

NOTE A: CSB
tpd(O.PE)

Valid

= L. ENB = H
~
* tpd(O·PE)

Valid *
It------fI tpd(E.PE)

Valid
~
"1
tpd(E·PE) ~
\ Valid

Figure 17. ODD/EVEN, W/RB, MBB, and PGB to PEFB Timing

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13-53
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F -JULY 1992 - REVISED FEBRUARY 1996

\ .................................................................--
0001
EVEN
1
1
Low 1
1

~------------------~:--------------------------
WiRA
1 1
MBA
vzZ;vzzzzf :
1 1 1
PGA
W{?JZZZZ4 : )------
I+-- tpd(E-PB) ---.j
A8,A17,
1
I+- ten -tI I+- tpd(M-OV)--ti 1
1
~ tpd(o-PB) -1 : . - tpd(E-PB) --+I
A26, A35 ------'""'~ Generated Parity X Generated Parity )I("':'M~a"::':1I2:-:0~a~ta
Mall2
Data

NOTE A: ENA = H

Figure 18. Parity-Generation Timing When Reading From the Mail2 Register

0001
EVEN
\------------------------------------
1
1
Low
1
1

WiRB
~----------~------~:--------------------------
1 1
MBB
v)azzmz,f :
1 1 1
PGB
v/44V/4I+-- : )------
1
I+- ten +1 I+-
tpd(E-PB) ---.j
tpd(M-OV) -tI 1
1
~ tpd(o-PB) -1'" : . - tpd(E-PB) -1
B8,B17,
B26, B35 -----fC~ ~ Generated Parity A Generated Parity Xr:M~a"::'1I1:-:0~a~ta
Mall1
Data

NOTE A: ENB = H

Figure 19. Parity-Generation Timing When Reading From the Mail1 Register

-!I11ExAs
INSTRUMENTS
13-54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
SCBS129F -JULY 1992 - REVISED FEBRUARY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Vee) ............................................... ±20 rnA
Output clamp current, 10K (Vo < 0 or Vo > Vee) ........................................... ±50 rnA
Continuous output current, 10 (VO = 0 to Vee) ............................................. ±50 rnA
Continuous current through Vee or GND ................................................. ±500 rnA
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions lor extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
10H High-level output current -4 rnA
10L Low-level output current 8 rnA
TA Operating Iree-air temperature 0 70 'C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP:j: MAX UNIT
VOH VCC = 4.5 v, IOH=-4mA 2.4 V
VOL Vcc = 4.5 V, 10L = 8 rnA 0.5 V
II VCC=5.5V, VI =VCC orO ±50 IlA
10Z Vcc = 5.5 V, VO=Vcc orO ±50 IlA
Outputs high 60 rnA
ICC VCC=5.5V, 10=OmA, VI = VCC or GND Outputs low 130 rnA
Outputs disabled 60 rnA
Ci VI=O, 1=1 MHz 4 pF
Co VO=O, 1=1 MHz 8 pF
:j: All tYPical values are at VCC = 5 V, TA = 25'C.

~T~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13-55
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
SCBS129F -JULY 1992- REVISED FEBRUARY 1996

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 19)
'ABT3612·15 'ABT3612·20 'ABT3612·30
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency, ClKA or ClKS 66.7 50 33.4 MHz
tc Clock cycle time, ClKA or ClKS , 15 20 30 ns
twlClKHl Pulse duration, ClKA and ClKS high 6 8 12 ns
tw(ClKl) Pulse duration, ClKA and ClKS low 6 8 12 ns
tsulD) Setup time, AO-A35 before ClKAt and SO-835 before ClKSt 4 5 6 ns
Setup time, CSA, W/RA before ClKAt; CSS, W/RS before
tsu(EN1) 6 6 7 ns
ClKSt
tsu(EN2) Setup time, ENA before ClKAt; ENS before ClKSt 4 5 6 ns
tsu(EN3) Setup time, MSAbefore ClKAt; MSS before ClKSt 4 5 6 ns
Setup time, ODD/EVEN and PGA before ClKAt; ODD/EVEN and
tsu(PG) 4 5 6 ns
PGS before ClKStt
tsulRSl Setup time, RST low before ClKAt or ClKBt:!: 5 6 7 ns
tsu(FS) Setup time, FSO and FSl before RS'f high 5 6 7 ns
thlD) Hold time, AO-A35 after ClKAt and SO-S35 after ClKSt 2.5 2.5 2.5 ns
th(EN1) Hold time, CSA, W/RA aiter ClKAt; CSS, W/RS after ClKSt 2 2 2 ns
tll(!:N2~ Hold time, ENA after ClKAt; ENS after ClKSt 2.5 2.5 2.5 ns
th(EN3) Hold time, MBA aiter ClKAt; MSS aiter ClKSt 1 1 1 ns
Hold time, ODD/EVEN and PGA aiter ClKAt; ODD/EVEN and
th(PG) 1 1 1 ns
PGS aiter ClKStt
thIRSt Hold time, RST low aiter ClKAt or ClKSt:!: 5 6 7 ns
th(FS) Hold time, FSO and FSl after RST high 4 4 4 ns
Skew time between ClKAt and ClKSi for EFA, EFS,
tskl§ 8 8 10 ns
FFA, and FFS
Skew time between ClKAi and ClKSi for AEA, AES,
tsk2§ 9 16 20 ns
AFA,andAFS
t Only applies for a clock edge that does a FIFO read
:!: Requirement to count the clock edge as one of at least four needed to reset a FIFO
§ Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and
ClKS cycle.

~~
INSTRUMENTS
13-56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 · SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
SCBS129F -JULY 1992 - REVISED FEBRUARY 1996

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 30 pF (see Figures 1 through 19)
'ABT3612-15 ' ABT3612-20 ' ABT3612-30
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
ta Access time, CLKAito AO-A35 and CLKBito BO-B35 2 10 2 12 2 15 ns
todlC-FFl Propagation delay time, CLKAi to FFA and CLKBi to FFB 2 10 2 12 2 15 ns
tpd(G-EFI Propagation delay time, CLKAi to EFA and CLKBi to EFB 2 10 2 12 2 15 ns
tpd(C-AE) Propagation delay time, CLKAi to AEA and CLKBi to AEB 2 10 2 12 2 15 ns
tpd(C-AFI Propagation delay time, CLKAi to AFA and CLKBi to AFB 2 10 2 12 2 15 ns
Propagation delay time, CLKAi to MBFl low or MBF2 high and
tpd(C-MF) 1 9 1 12 1 15 ns
CLKBi to MBF2 low or MBFl high
Propagation delay time, CLKAi to BO-B35t and CLKBi to
tpd(G-MR) 3 11 3 13 3 15 ns
AO-A35;
Propagation delay time, MBA to AD-A35 valid and MBB to
tpd(M-DV) 1 11 1 11.5 1 12 ns
BO-B35 valid
Propagation delay time, AO-A35 valid to PEFA valid; BO-B35
tpd(D-PE) 3 10 3 11 3 13 ns
valid to PEFB valid
tpd(O-PEI Propagation delay time, ODD/EVEN to PEFA and PEFB 3 11 3 12 3 14 ns
Propagation delay time, ODD/EVEN to parity bits (A8, AI?, A26,
tpd(O-PB)§ 2 11 2 12 2 14 ns
A35) and (B8,BI7,B26,B35)
Propagation delay time, W/RA, CSA, ENA, MBA, or PGA to
tpd(E-PE) 1 11 1 12 1 14 ns
PEFA; W/RB, CSB, ENB, MBB, or PGB to PEFB
Propagation delay time, W/RA, CSA, ENA, MBA, or PGA to
tpd(E-PB)§ parity bits (A8, AU, A26, A35); W/RB, CSB, ENB, MBB, or PGB 3 12 3 13 3 14 ns
to parity bits (B8, B17, B26, B35)
Propagation delay time, RST to (AEA, AEB) low and (AFA, AFB,
tpd(R-F) 1 15 1 20 1 30 ns
MBF1, MBF2) high.
Enable time, CSA and W/RA low to AD-A35 active and CSB low
ten 2 10 2 12 2 14 ns
and Vii/RB high to BO-B35 active
Disable time, CSA or W/RA high to AO-A35 at high impedance
tdis 1 8 1 9 1 11 ns
and CSB high or Vii/RB low to BO-B35 at high impedance
..
t Writing data to the mall 1 register when the BO-B35 outputs are active and MBB IS high
; Writing data to the mail2 register when the AD-A35 outputs are active and MBA is high
§ Only applies when reading data from a mail register

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265 13-57
SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F -JULY 1992- REVISED FEBRUARY 1996

TYPICAL CHARACTERISTICS

SUPPLY CURRENT
vs
CLOCK FREQUENCY
400 I _I
fdata = 1/2 fclock VCC=5.5V /
350 - TA = 25°C
c( CL=OpF V
E
I 300
/ /
'E V
~
:I 250
VCC=5(
/ ./ /
/ ~ V~
0
~
Co
Co 200

~ ~ /VCC=4.5V
:I
I/)
I
150
e:
0
0
100 ,
~~
50

o
, ~
o 10 20 30 40 50 60 70 80

fclock - Clock Frequency - MHz

Figure 20

calculating power dissipation

The ICC(/) current for the graph in Figure 20 was taken while simultaneously reading and writing the FIFO on
the SN7 4ACT3612 with ClKA and ClKB set to fclock. All data inputs and data outputs change state during each
clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to
a zero-capacitance load. Once the capacitive load per data-output channel is known, the power dissipation can
be calculated with the equation below.
With ICC(I) taken from Figure 20, the maximum dynamic power dissipation (Po) of the SN74ABT3612 can be
calculated by:
Po = Vce x ICC(/) + I(CL x Vce x (VOH - VoLl x fo)
where:
CL = output capacitive load
fo switching frequency of an output
VOH = high-level output voltage
VOL = low-level output voltage
When no reads or writes are occurring on the SN74ABT3612, the power dissipated by a single clock (ClKA
or ClKB) input running at frequency fclock is calculated by:
PT = Vce x fclock x 0.29 mA/MHz

-!111ExAs
INSTRUMENTS
13-58 POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
 SN74ABT3612
64x36x2
CLOCKED BIDIRECTIONAL FIRST·IN FIRST·OUT MEMORY
SCBS129F -JULY 1992 - REVISED FEBRUARY 1996

PARAMETER MEASUREMENT INFORMATION

5V

1.1 kn
From Output
Under Test ----.>------e

680 n ;::r: 30 pF
(see Note A)

LOAD CIRCUIT

----If~~.;-V-
Timing 1 3V High-Level 3V
Input _ _ _.....J.~ ~ ~ __ _ Input ~ I." Y GND
-r GND
tsu~th I+- tw -+I
I I
Data, ~ -:-.:: - 3V
Enable .J"" 1.5 V ~ Low-Level ~ 1.5 V ~ 3V
Input GND Input ~ ~":" _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

~~!~~~ ~1.5V \1.;V--- ::D

--+i II+- tPLZ

I I _----i-~l----
-.1 i4- tpZL
=3V
Low-Level
Output I I Input
L 1.5 V \7.5-; - - 3V
_-+..JI 1 VOL --.Ij I ' GND
-'1 !+-tPZH
VOH tpd~ ~tpd
High-Level
I I In-Phase 1/ - - VOH
Output
I I =OV Output T 1.5V 'S.. 1.5V
~ l+-tPHZ ----I. \.:.:.: VOL

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 21. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 13-59
13-60
14-1
 MILITARY FIFOS
Features Benefits

• Frequencies up to 40 MHz • Multiple frequencies for greater

system-performance flexibility .
• 3-state outputs • Disable output from the data path
• Depths available from 16 to 64 words • Shallow depths for elastic store
• Package options include SOIC, PLCC, • Multiple package options for high-volume
and DIP production requirements

-s::s:_.
~
-"
o"
..
en

14-2
INTRODUCTION
TI continues its commitment to make the latest technology available to its military customers by offering the FIFO
memories included in this section. These military FIFOs cover a wide portion of the commercial product
spectrum.
TI Military Products has been qualified per MIL-PRF-38535 (QML) since 1992. Our integrated circuits have the
quality and reliability levels associated with this performance-based qualified manufacturer's line (QML)
specification. This QML qualification is overseen by the Defense Electronics Supply Center (DESC).
Several of these military FIFOs are QML qualified in plastic packages, allowing the military designer to have
a device tested through the military temperature range (-55°C to 125°C) with the small-outline configuration
of the commercial plastic package. QML plastic and standard ceramic packaging options offer TI's customers
flexibility and performance.
Based on the customer's interest, TI Military Products can offer additional FIFO functions currently available
qnly as commercial devices. For more information on military FIFO products, please contact your local TI
military-products field sales representative or authorized TI military-products distributor.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-3
14-4
 SN54ABT7819
512 x 18 x 2
FIRST·OUT MEMORY

• Member of the Texas Instruments • Microprocessor Interface Control logic

Wldebus ™ Family • Programmable Almost·FuIl/Almost·Empty
• Free-Running ClKA and ClKB Can Be Flags
Asynchronous or Coincident • Fast Access Times of 9 ns With a 50-pF
• Read and Write Operations Synchronized load and Slmultaneous·Swltching Data
to Independent System Clocks Outputs
• Two Separate 512 x 18 Clocked FIFOs • Advanced BICMOS Technology
Buffering Data In Opposite Directions • Released as DESC SMD (Standard
• IRA and ORA Synchronized to ClKA Microcircuit Drawing) 5962-9470401QXA
• IRB and ORB Synchronized to ClKB • Available in 84·Pin Ceramic Pin Grid Array
(GB) Package

GBPACKAGE
(TOP VIEW)

2 3 4 5 6 7 8 9 10 11

A @@@@@@@@@@@
B @@@@@@@@@@@
C @@. @@@ @@
D @@ @@

D
E @@@ @@@
F @@@ @@@
G @@@ @@@
H @@ @@
J @@ @@@ @@
K @@@@@@@@@@@
L @@@@@@@@@@@

description
A FIFO memory is a storage device that allows data to be read from its array in the same order it is written. The
SN54ABT7819 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. Two independent
512 x 18 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to
indicate empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag.
The SN54ABT7819 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.

Widebus is a trademark of Texas Instruments Incorporated.

Copyright © 1995, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-5
SN54ABT7819
512x18x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS306B - AUGUST 1994 - REVISED DECEMBER 1995

description (continued)
The state of the AO-A 17 outputs is controlled by eSA and W/RA. When both eSA and W/RA are low, the outputs
are active. The AO-A 17 outputs are in the high-impedance state when either eSA or W/RA is high. Data is
written to FIFOA-B from port A on the low-to-high transition of CLKA when eSA is low, W/RA Is high, WENA
is high, and the IRA flag is high. Data is read from FIFOB-A to the AO-A 17 outputs on the low-to-high transition
of eLKA when eSA is low, W/RA is low, RENA is high, and the ORA flag is high.
The state of the BO-B17 outputs is controlled by eSB and W/RB. When both eSB and W/RB are low, the outputs
are active. The BO-B17 outputs are in the high-impedance state when either eSB or W/RB is high. Data is
written to FIFOB-A from port B on the low-to-high transition of eLKB when eSB is low, W/RB is high, WENB
is high, and the IRB flag is high. Data is read from FIFOA-B to the BO-B17 outputs on the low-to-high transition
of eLKB when eSB is low, W/RB is low, RENB is high, and the ORB flag is high.
The setup- and hold"time constraints for the chip selects (eSA, eSB) and writelread selects (W/RA, W/RB)
enable and read operations on memory and are not related to the high-impedance control of the data outputs.
If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock cycle, the
chip select and writelread select can switch at any time during the cycle to change the state of the data outputs.
The input-ready and output-ready flags of a FIFO are two-stage synchronized to the port clocks for use as
reliable control signals. eLKA synchronizes the status of the input-ready flag of FIFOA-B (IRA) and the
output-ready flag of FIFOB-A (ORA). eLKB synchronizes the status ofthe input-ready flag of FIFOB-A (lRB)
and the output-ready flag of FI FOA-B (ORB). When the input-ready flag of a port is low, the FI FO receiving input
from the port is full and writes are disabled to its array. When the output-ready flag of a port is low, the FIFO that
outputs data to the port is empty and reads from its memory are disabled. The first word loaded to an empty
memory is sent to the FIFO output register at the same time its output-ready flag is asserted (high). When the
memory is read empty and the output-ready flag is forced low, the last valid data remains on the FIFO outputs
until the output-ready flag is asserted (high) again. In this way, a high on the output-ready flag indicates new
data is present on the FIFO outputs.
The SN54ABT7819 is characterized for operation from -55°e to 125°e.

~1ExAs
INSTRUMENTS
14-6 POST OFfiCE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305B - AUGUST 1994 - REVISED DECEMBER 1995

Terminal Assignments
TERMINAL NAME TERMINAL NAME TERMINAL NAME TERMINAL NAME
Al PENA Bll IRB F9 NC K2 All
A2 CSA Cl GNO FlO B6 K3 GNO
A3 W/RA C2 HFA Fl1 GNO K4 VCC
A4 WENA C5 CLKA Gl A5 K5 GNO
A5 ORA C6 NC G2 GNO K6 A17
A6 VCC C7 VCC G3 A4 K7 GND
A7 ORB Cl0 HFB G9 B4 K8 VCC
A8 WENB Cll GND Gl0 GND K9 GND
A9 W/RB Dl Al Gl1 B5 Kl0 Bl0
Al0 CSB D2 AO Hl A7 Kll B9
All AF/AEB 010 BO H2 GND L1 Al0
Bl IRA Dll Bl Hl0 GND L2 A12
B2 AF/AEA El A3 Hll B7 L3 A13
B3 RSTA E2 A2 Jl A8 L4 A14
B4 GND E3 VCC J2 VCC L5 A16
B5 RENA E9 VCC J5 A15 L6 B15
B6 CLKB El0 B2 J6 NC L7 B16
B7 RENB Ell B3 J7 B17 L8 B14
B8 GNO Fl A6 Jl0 VCC L9 B13
B9 RSTB F2 GND Jll B8 Ll0 B12
Bl0 PENB F3 NC Kl A9 L11 Bl1

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-7
SN54ABT7819
512.>< 18x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS306B- AUC3UST 1994 - REVISED DECEMBER 1996

logic symbolt
C5 ~ B6
CLKA CLOCK A FIFO 512 x 18x2 CLOCKB CLKB

A2 '"& SN54ABT7819
-a l/1 A10
CSA
A3
" OE1 OE2 A9
CSB
W/RA " WiRB

::::;:: :;:::
~ & WRITE WRITE & ~
ENABLE ENABLE
A4 FIFOA~ FIFOB-A A8
WENA

L....b
:::;;:. -
~
~
WENB

& READ READ &

Vi
" ENABLE ENABLE

---
B5 FIFOA~
B7
RENA FIFOB-A RENB
""'"-
B3 B9
RSTA
" RESET FIFOA~ RESET FIFOB-A l/1 RSTB
A1 B10
PROGRAM ENABLE l/1
PENA
" PROGRAM ENABLE
FIFOA~ FIFOB-A
PENB

B1 B11
IRA INPUT·READY INPUT·READY IRB
PORTA PORTB
A5 A7
ORA OUTPUT·READY OUTPUT·READY ORB
C2 PORTA PORTB C10
HFA HALF·FULL HALF·FULL HFB
FIFOA~ FIFOB-A
B2 A11
AF/AEA ALMOST·FULUEMPTY ALMOST·FULUEMPTY AF/AEB
~FOA~ FIFOB1-

D2 010
AO 0 0 BO
01 011
A1 B1
E2 E10
A2 B2
E1 E11
A3 B3
G3 G9
A4 B4
G1 G11
A5 B5
F1 F10
A6 B6
H1 H11
A7 B7
J1 1V 2V J11
A8 Be

~ ~
K1 K11
A9 B9
L1 K10
A10 B10
K2 L11
A11 B11
L2 L10
A12 B12
L3 L9
A13 B13
L4 L6
A14 B14
J5 La
A15 B15
L5 L7
A16 B16
K6 J7
A17 17 17 B17

t This symbol is in accordance wHh ANSI/IEEE Sid 91-1984 and lEe Publication 617-12.

-!!11ExAs
INSTRUMENTS
14-8 POST OFFICE BOX 665303 • DALLAS. TEXAS 75285
 SN54ABT7819
512x 18x2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS306B-AUGUST 1994- REVISED DECEMBER 1995

functional block diagram

J5E'NJ:
RENA
WENA Port-A
~ Control
+
wIllA
elKA
FifiA
logic
I
I
Read
Pointer
I
t
~ Register I
I
18
512x18
Dual-Port SRAM
FlFOB-A H Reglater:

18
+ 18
i+-+-I Pointer
WrIte I
I

Flag IRB
ORA logic AF/AEB
FlFOB-A HFB
8
AO-A17 ~
8 ~ 8O-B17

IRA Flag
AF/AEA logic
HFA ORB
FlFOA-B

I Write
I Pointer
I
t
512x 18
18
I Raglster J-.- Dual-Port SRAM
FlFOA-B
Raglater ! .......
t
I Read I
Pointer I Mi'B
.QlKB
Port-B c:st
Control WiRB
logic WENB
RENB
15ENii

~1ExAs
INSTRUMENI'S
POST OFFICE BOX 86B303 • DALlAS, 'IECAS 75286 14-9
SN54ABT7819
512x18x2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SGBS306B - AUGUST 1994 - REVISED DECEMBER 1995

enable logic diagram (positive logic)

CSA - - - -......-<:r.......
W/RA t - - - - - - - - - WENFIFOA-B
WENA ---~+_-~_J

t---+------- Output Enable (AO-A17)

L...--CL--.J

t----- REN FIFOB-A

RENA -----------~

'-~r-'----- CSB
WEN FIFOB-A - - - - - - - - { 1---+__._--- W/RB
"'-------'--t-~--- WENB

Output Enable (BO-B17) -----~.--{

REN FIFOA-B - - . , .
~---------- RENB

FUNCTION TABLES
SELECT INPUTS
AO-A17 A·PORT OPERATION
ClKA CSA W/RA WENA RENA
X H X X X HighZ None
f l H H X HighZ Wrtte AO-A 17 to FIFOA-B
f l L X H Active Read FIFOB-A to AO-A 17

SELECT INPUTS
BO-B17 B· PORT OPERATION
ClKB CSB W/RB WENB RENB
X H X X X HighZ None
f L H H X HlghZ Write BO -B17 to FIFOB-A
f L L X H Active Read FIFOA-B to BO-B17

-!!11ExAs
INSTRUMENTS
14-10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT7819
512 x 18x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305B - AUGUST 1994 - REVISED DECEMBER 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME
AO-A17 1/0 Port-A data. The 18-bit bidirectional data port for side A.
FIFOA-B aimost-full/almost-empty flag. Depth offsets can be programmed for AF/AEA, or the default value of 128 can
AF/AEA 0 be used for both the almost-empty offset (X) and the almost-full offset (V). AF/AEA is high when X or less words or
(512 - Y) or more words are stored in FIFOA-B. AF/AEA is forced high when FIFOA-B is reset.
FIFOB-A aimost-full/almost-empty flag. Depth offsets can be programmed for AF/AEB, or the default value of 128 can
AF/AEB 0 be used for both the almost-empty offset (X) and the almost-full offset (V). AF/AEB is high when X or less words or
(512 - y) or more words are stored in FIFOB -A. AF/AEB is forced high when FIFOB -A is reset.
BO-B17 I/O Port-B data. The 18-bit bidirectional data port for side B.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A to its low-ta-high transition
ClKA I
and can be asynchronous or coincident to ClKB.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B to its low-to-high transition
ClKB I
and can be asynchronous or coincident to ClKA.
Port-A chip select. CSA must be low to enable a low-ta-high transition of ClKA to either write data from AO-A 17 to
CSA I FIFOA-B or read data from FIFOB-A to AO-A 17. The AO-A 17 outputs are in the high-impedance state when CSA is
high.
Port-B chip select. CSB must be low to enable a low-ta-high transition of ClKB to either write data from BO-B17 to
CSB I FIFOB-A or read data from FIFOA-B to BO-B17. The BO-B 17 outputs are in the high-impedance state when CSB is
high.
FIFOA-B half-full flag. HFA is high when FIFOA-B contains 256 or more words and is low when FIFOA-B contains
HFA 0
255 or less words. HFA is set low after FIFOA-B is reset.
FIFOB -A half-full flag. HFB is high when FIFOB-A contains 256 or more words and is low when FIFOB-A contains
HFB 0
255 or less words. HFB is set low after FIFO~ -A is reset.
Port-A input-ready flag. IRA is synchronized to the low-ta-high transition of ClKA. When IRA is low, FIFOA-B is full and
IRA 0 writes to its array are disabled. IRA is set low during a FIFOA- B reset and is set high on the second low-ta-high transition
of ClKA after reset.
Port-B input-ready flag. IRB is synchronized to the low-ta-high transition of ClKB. When IRB is low, FIFOB-A is full and
IRB 0 writes to its array are disabled. IRB is set low during a FIFOB -A reset and is set high on the second low-ta-high transition
of ClKB after reset.
Port-A output-ready flag. ORA is synchronized to the low-ta-high transition of ClKA. When ORA is low, FIFOB-A is
empty and reads from its array are disabled. The last valid word remains on the FIFOB-A outputs when ORA is low.
ORA 0
Ready data is present for the AO-A 17 outputs when ORA is high. ORA is set low during a FIFOB-A reset and goes high
on the third low-to-high transition of ClKA after the first word is loaded to an empty FIFOB -A.
Port-B output-ready flag. ORB is synchronized to the low-ta-high transition of ClKB. When ORB is low, FIFOA-B is
empty and reads from its array are disabled. The last valid word remains on the FIFOA-B outputs when ORB is low.
ORB 0
Ready data is present for the BO-B17 outputs when ORB is high. ORB is set low during a FIFOA-B reset and goes high
on the third low-to-high transition of ClKB after the first word is loaded to an empty FIFOA-B.
AF/AEA program enable. After FIFOA-B is reset and before a word is written to its array, the binary value on AO-A7
PENA I
is latched as an AF/AEA offset when PENA is low and ClKA is high.
AF/AEB program enable. After FIFOB -A is reset and before a word is written to its array, the binary value on BO-B7
PENB I
is latched as an AF/AEB offset when PENB is low and ClKB is high.
Port-A read enable. A high level on RENA enables data to be read from FIFOB-A on the low-ta-hlgh transition of ClKA
RENA I
when CSA is low, WiRA is low, and ORA is high.
Port-B read enable. A high level on RENB enables data to be read from FIFOA- B on the low-ta-high transition of ClKB
RENB I
when CSB is low, WiRB is low, and ORB is high.
FIFOA-B reset. To reset FIFOA-B, four low-to-high transitions of ClKA and four low-ta-high transitions of ClKB must
RSTA I
occur while RSTA is low. This sets HFA low, IRA low, ORB low, and AF/AEA high.
FIFOB -A reset. To reset FIFOB -A, four low-ta-high transitions of ClKA and four low-ta-high transitions of ClKB must
RSTB I
occur while RSTB is low. This sets HFB low, IRB low, ORA low, and AF/AEB high.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14--11
SN54ABT7819
512 x 18x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305B - AUGUST 1994 - REVISED DECEMBER 1995

Terminal Functions (Continued)

TERMINAL
110 DESCRIPTION
NAME
Port-A write enable. A high level on WENA enables data on AO-A17 to be written into FIFOA-B on the low-to-high
WENA I
transition of CLKA when WIRA is high, CSA is low, and IRA is high.
Port-S wrHe enable. A high level on WENB enables data on BO-B17 to be written into FIFOB -A on the low-to-high
WENS I
transition of ClKB when WIRB is high, ~ Is low, and IRB is high.
Port-A wme/read select. A high on W/RA enables AO-A 17 data to be written to FIFOA-B on a low-to-high transHion of
ClKA when WENA is high, CSA Is low, and IRA Is high. A low on W/RA enables data to be read from FIFOB-A on a
W/RA I
10W-lo-high transHlon of CLKA when RENA is high, CSA Is low, and ORA is high. The AO-A17 outputs are in the
high-impedance state when W/RA is high.
Port-B write/read select. A high on W/RS enables BO-B17 data to be written to FIFOB-A on a low-to-high transition of
ClKB when WENB is high, ~ is low, and IRB Is high. A low on W/RB enables data to be read from FIFOA-B on a
WIRS I
low-to-high transHion of ClKS when RENB is high, CSB is low, and ORB is high. The BO-B17 outputs are in the
high-impedance state when W/RB is high.

ClKA

ClKB
I
I
RSTA\ I I
I
IRA~ II
ORB

HFA~

AF/AEA "W01
Figure 1. Reset Cycle for FIFOA-Bt
t FIFOB -A is reset in the same manner.

~1ExAs
INSTRUMENTS
14-12 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305B - AUGUST 1994 - REVISED DECEMBER 1995

ClKA

IRA
I i 1
1 1 1
o
1 1 1

I II
\ 1---+1----1-'1.
\ _-1--_---+'1.I;r-
'1-..

1 1

W/RA ®SSW' I I~ !~
I I 1 1

WENA~~I~~~
1 1 1 1
~.......I..,I 1 I I
AO-A17 ~ Word it ~ Word 2t ~ word3t)@(Word4t ~
t Written to FIFOA-B
Figure 2. Write Timing - Port A

ClKB
I I
, I
IRB I I
I I 0

CSB \~--~----~I \~~.I, ____~11;r-

..
I I

WiRB ®SSW' ~iI i~

I
WENB~I~I~~~
I I I I
...-_1 1 1 I
BO-B17 ~ Word it ~ Word 2t ~ Word3t ~ Word4t ~
t Written to FIFOB-A
Figure 3. Write Timing - Port B

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-13
SN54ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SGBS305B-AUGUST 1994- REVISED DECEMBER 1995

ClKA
I
I
CSA I o
I
I
WiRA I
I 0

WENA ~ ~~
. . . .~________________________________________

-+I 14- tau

AO-A17

ClKB
I I
I I
ORB
: ~1":r- ~~-----
F tpd tpd --.!
CSB ~~____________________________________ -+:_________ _______________________________
~:

I I
wffiB ~~____________________________________ -+:_________~:_______________________________
I I
RENB ~
I
14---- tpd --Io! I
BO-B17 ---~~~---------------------
~ Wi FromFIFOA-B

Figure 4. ORB-Flag Timing and First-Data-Word Fallthrough When FIFOA-B Is Emptyt

t Operation of FIFOB-A is identical to that of FIFOA-B.

~1ExAs
INSTRUMENTS
14-14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305B - AUGUST 1994 - REVISED DECEMBER 1995

ClKB
I
I
CSB I o
I
I 1
WiRB I o
I
RENB £W I
~\)",~~ __________________
I
BO-B17 _ _ _ _ _ --IX'-________ F_ro_m_F_IF_O_A_-B_ _ _ _ _ _ _ _ _ _ _ __

ClKA
I
I

-------------------:~-J1 }~-----------------
IRA

-il~. -~~I tpd

I --M~I-
i.
4.-i tpd
CSA I 1
-------------------~I----------------------O
I
WENA
W////////////// ~
I
I
WiRA
o

AO-A17

Figure 5. Write-Cycle and IRA-Flag Timing When FIFOA-B Is Fullt

t Operation of FIFOB-A is identical to that of FIFOA-B.

~ThXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-15
SN54ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SGBS305B - AUGUST 1994 - REVISED DECEMBER 1995

ClKA

ORA
I o
I
I

~I II
I
t I
~~~I
W/RA·~ I
.
. ~
~
I I I
RENA~ ~ '@88W '@88W ~
len 14 ~ 14- tpd --.I ---.: i4-- tdls

AO-A17 ----"""'*'\~ Word1t ~

1'\ Word2t X
.. Word3t X
.. Word4t ~
,~------

t Read from FIFOB-A

Figure 6. Read Timing - Port A

ClKB

ORB
---------+-------------------------1 0

RENB~ ~ '@88W '@88W ~

ten j4 ~ I+- tpd --.I -+j i4--ldls

BO-B17 ------I,~ Word 1t ~

1\ Word 2t X Word 3t X Word 4t ~
,*"-- - - - -
t Read from FIFOA-B

Figure 7. Read Timing - Port B

~1ExAs
INSTRUMENTS
14-16 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 CU<A Lf1Jl{1JLf\JL.fl~~~JlSL
WENA J I I : I I'-_______-_________
I I I I
I I I I I ,,'J--------------
C{

IRA I I I - I ~S

"-'17~~ @-O~@-t§.:.,.4.~."._~~ I I I
I I I
~
n~Jl.JtLJl.J1L~~[LfLJYL
o
o
eLKB g
I!" I I I I I I -
I I I I I :
1
I ~

;~r
RENB I c
I I I I I I I m
\( 1 I __ L _ I , I I 6
II
~~ """ 1\
r '
I I I
\r-IN::-:\r.::I $ Ii
I
$
m
~
A::;~.... ~
I I I 1 1
oz
i "-B17~1 I
W1
: II
II
! II
II
I I:
II r---
! (/)l>
Iilr-

-------.1
I I : !!l"'l1
Iil-
ID::U
AF/AEA !
I I I i 'en
1'Cil_
cz
:-:-1

HFA
- ------- ----------I !!l-
-"'11
!8-
.... ::u
len
--------~ ~----- ~-:-I
CiiO en
NOTES: A. GSA, CSB = 0, WiRA = 1, WIRB = 0 ~C:Ulz
o ........ UI
B. X is the almost-empty offset and Y is the almost-full offset for AF/AEA. m 3: I\:) .t:oo
C. HFB and AF/AEB function in the same manner for FIFO B - A. ;::~mx l>
m
m3: ........
Figure 8. FIFOA - B (HFA, AF/AEA) Asynchronous Flag Timing :DOC» .......
!
-.J
~::uX ~
'" -< I\:) co
SN54ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305B-AUGUST 1994- REVISED DECEMBER 1995

offset values for AF/AE

The aimost-fuil/aimost-empty flag of each FIFO has two programmable limits: the almost-empty offset value (X)
and the almost-full offset value (Y). They can be programmed from the input of the FIFO after it is reset and
before a word is written to its memory. An AF/AE flag is high when its FIFO contains X or less words or (512 - Y)
or more words.
To program the offset values for AF/AEA, PENAcan be brought low after FIFOA-B is reset and only when ClKA
is low. On the following low-to-high transition of ClKA, the binary value on AO-A7 is stored as the almost-empty
offset value (X) and the almost-full offset value (Y). Holding PENA low for another low-to-high transition of ClKA
reprograms Y to the binary value on AO-A7 at the time of the second ClKA low-to-high transition.
During the first two ClKA cycles used for offset programming, PENA can be brought high only when ClKA is
low. PENA can be brought high at any time after the second ClKA pulse used for offset programming returns
low. A maximum value of 255 can be programmed for either X or Y (see Figure 9). To use the default values
of X = Y = 128, PENA must be tied high. No data is stored in FIFOA-B while the AF/AEA offsets are
programmed. The AF/AEB flag is programmed in the same manner with PENB enabling ClKB to program the
offset values taken from BO-B7.

___....II
CLKA

IRA ______-.JI

WiRA~

WENA

AO-A7 ~ XandY X\.__Y_-,~

Figure 9. Programing X and Y Separately for AF/AEA

~lEXAS
INSTRUMENTS
14-18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305B- AUGUST 1994 - REVISED DECEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Voltage range applied to any output in the high state or power-off state, Vo ............. -0.5 V to 5.5 V
Current into any output in the low state, 10 ................................................. 48 rnA
Input clamp current, 11K (VI < 0) .......................................................... -18 rnA
Output clamp current, 10K (Vo < 0) ....................................................... -50 rnA
Operating free-air temperature range, TA .......................................... -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VI Input voltage 0 VCC V
IOH High-level output current -12 mA
IOL Low-level output current 24 mA
l!.t/l!.v Input transition rise or fall rate 5 ns/V
TA Operating free-air temperature -55 125 °C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP:I: MAX UNIT
VIK VCC s 4.5V, 11=-18mA -1.2 V
VCC=4.5V, IOH=-3mA 2.5
VOH VCC = 5 V, IOH=-3mA 3 V
VCC = 4.5 V, IOH=-12mA 2
VOL VCC =4.5 V, IOL = 24 mA 0.5 0.55 V
II VCC = 5.5 V, VI = VCC or GND ±1 ~
IOZH§ VCC-5.5V, Vo = 2.7 V 50 ~
10ZL§ VCC = 5.5 V, Va = 0.5 V -50 ~
loll VCC-5.5V, Va = 2.5 V -40 -100 -180 mA
Outputs high 15
ICC VCC=5.5V, 10=0, VI =VCC or GND Outputs low 95 mA
Outputs disabled 15
Ci Control inputs VI = 2.5 V or 0.5 V 6 pF
Co Flags Vo - 2.5 V or 0.5 V 4 pF
Cio A or B ports Vo =2.5 V or 0.5 V 8 pF
:I: All typical values are at VCC - 5 V, TA = 25°C.
§ The parameters 10ZH and 10ZL include the input leakage current.
II Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

~TEXAS
IN5»TRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-19
SN54ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305B-AUGUST 1994- REVISED DECEMBER 1995

timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 8)
MIN MAX UNIT

fclock Clock frequency 50 MHz

tw Pulse duration, CLKA, CLKB high or low 8 ns
AO-A17 before CLKAt and BO-B17 before CLKBt 5
CSA before CLKAt and CSB before CLKBt 7.5
W/RA before CLKAt and W/RB before CLKBt 7.5
tsu Setup time WENA before CLKAt and WENB before CLKBt 5 ns
RENA before CLKAt and RENB before CLKBt 5
PENA before CLKAt and PENB before CLKBt 5
RSTA or RSTB low before first CLKAt and CLKBt t 5
AO-A17 after CLKAt and BO-B17 after CLKBt 0
CSA after CLKAt and CSB after CLKBi 0
W/RA after CLKAi and W/RB after CLKBt 0
th Hold time WENA after CLKAi and WENB after CLKBt 0 ns
RENA after CLKAi and RENB after CLKBi 0
PENA after CLKA low and PENB after CLKB low 3
RSTA or RSTB low after fourth CLKAi and CLKBi t 4
t To permit the clock pulse to be utilized for reset purposes

~1ExAs
INSTRUMENTS
14-20 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SGBS305B -AUGUST 1994 - REVISED DECEMBER 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) {see Figures 10 and 11}
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
'max CLKAor CLKB 50 MHz
CLKAi AO-A17 3 12
Ipd ns
CLKBi BO-B17 3 12
CLKAi IRA 3 12
Ipd ns
CLKBi IRB 3 12
CLKAi ORA 2.5 12
\Pd ns
CLKBi ORB 2.5 12
CLKAi 7 18
Ipd AF/AEA ns
CLKBi 7 18
tpLH RSTA AF/AEA 3 15 ns
CLKAi 7 18
\Pd AF/AEB ns
CLKBi 7 18
RSTB AF/AEB 3 15
tpLH ns
CLKAi HFA 7 18
CLKBi 7 18
tpHL HFA ns
RSTA 3 15
tpHL CLKAi HFB 7 18 ns
tpLH CLKBi 7 18
HFB ns
tpHL RSTB 3 15
CSA 1.5 10
len AO-A17 ns
W/RA 1.5 10
CSB 1.5 10
len BO-B17 ns
W/RB 1.5 10
CSA 1.5 10
!dis AO-A17 ns
W/RA 1.5 10
CSB 1.5 10
tdis BO-B17 ns
W/RB 1.5 10

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-21
SN54ABT7819
512 x 18 x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305B-AUGUST 1994- REVISED DECEMBER 1995

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME SUPPLY CURRENT
vs vs
LOAD CAPACITANCE CLOCK FREQUENCY
160
VCC~5V I II
typ+6 f-TA=25 D C
TA=75DC
CL=OpF VCC = 5.5 V . /V
!
RL =500n
/ 140
V , /V
c(
l/
~
I
/ E 120
V
VCC=5V -
t>V ,/
I
typ+4
V V V
1=
./ ~ ~ /'
f
c ./
V 0
~
:::I 100
'"
V ,/ /'
V
typ+2
..v 80

1
a.
V"
~ /- V /.VCC=4.5V
:::I
III
I
./
1/ IE 60

%~V
Q. 0
I
typ 0

-
'Q
a. / 40

typ-2 "
o 50 100 150 200 250 300
20
10 15 20 25 30 35 40 45 50 55 60 65 70
CL - Load Capacitance - pF 'clock - Clock Frequency - MHz

Figure 10 Figure 11

calculating power dissipation

With ICC(!} taken from Figure 11 , the maximum power dissipation (PT) based on all outputs changing states on
each read may be calculated by:
PT = Vcc x ICC(!} + l:(CL x VOH 2 x fo)
where:
ICC(!) = maximum Icc per clock frequency
CL = output capacitive load
fo data output frequency
VOH = typical output high level

~1ExAs
INSTRUMENTS
14-22 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT7819
512 x 18x 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305B - AUGUST 1994 - REVISED DECEMBER 1995

PARAMETER MEASUREMENT INFORMATION

-------- 3V

7V
Input ~1'5V \1.5 V

I I ov
b.
S1

R1
Rl= R1 = R2

Output
tpZl-+1
I
I
r- ~
I
I
~tpLZ
I -3.5V

r-c:G~~
I I
From Output Test I
Under Test Point I I

' "I'..,
I I
VOL
Cl R2 I
I
tpHZ~ J4- t

~c:c:~~5=
-+i tPZH ~
VOH

-= Output -OV

lOAD CIRCUIT VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PARAMETER R1. R2 clt S1

I tpZH Open
ten 5000 50pF
tPZL Closed
I tpHZ Open
letis 5000 50pF
tpLZ Closed
\pd 5000 50pF Open
t Includes probe and test-flldure capacitance

Figure 12. Load Circuit and Voltage Waveforms

-!!11EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-23
14-24
 SN54ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
1994 - REVISED FEBRUARY 1996

• Member of the Texas Instruments • Programmable Almost-Full/Almost-Empty

Wldebus ™ Family Flags
• Independent Asynchronous Inputs and • Empty, Full, and Half-Full Flags
Outputs • Fast Access Times of 12 ns With a 5Q-pF
• Produced In Advanced BICMOS Load and Simultaneous Switching Data
Technology Outputs
• Two Separate 512 x 18 FIFOs Buffering • Available In 84-Pln Ceramic Pin
Data In Opposite Directions Grid Array (GB)
GBPACKAGE
(TOP VIEW)

2 3 4 5 6 7 8 9 10 11

A @@@@@@@@@@@
B @@@@@@@@@@@
C @@. @@@ @@
0 @@ @@

D
E @@@ @@@
F @@@ @@@
G @@@ @@@
H @@ @@
J @@ @@@ @@
K @@@@@@@@@@@
L @@@@@@@@@@@

description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN54ABT7820 is arranged as two 512 x 18-bit FIFOs for high speed and fast access times.
It processes data at rates from 0 to 67 MHz with access times of 12 ns in a bit-parallel format.
The SN54ABT7820 consists of bus transceiver circuits, two 512 x 18 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs
GAB and GBA control the transceiver functions. The SAB and SBA control inputs select whether real-time or
stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight
fundamental bus-management functions that can be performed with the SN54ABT7820.
The SN54ABT7820 is characterized for operation from -55°C to 125°C.

Widebus is a trademark of Texas Instruments Incorporated.

Copyright © 1996, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-25
SN54ABT7820
512x18x2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS303B - AUGUST 1994 - REVISED FEBRUARY 1996

Terminal Assignments
TERMINAL NAME TERMINAL NAME TERMINAL NAME TERMINAL NAME
A1 PENA B11 FULLB F9 NC K2 A11
A2 GBA C1 GNO F10 B6 K3 GNO
A3 SBA C2 HFA F11 GNO K4 VCC
A4 LOCKA C5 UNCKB G1 A5 K5 GNO
A5 VCC C6 NC G2 GNO K6 A17
A6 VCC C7 VCC G3 A4 K7 GNO
A7 VCC C10 HFB G9 B4 K8 VCC
A8 LOCKB C11 GNO G10 GNO K9 GNO
A9 SAB 01 A1 G11 B5 K10 B10
A10 GAB 02 AO H1 A7 K11 B9
A11 AF/AEB 010 BO H2 GNO L1 A10
B1 FULLA 011 B1 H10 GNO L2 A12
B2 AF/AEA E1 A3 H11 B7 L3 A13
B3 RSTA E2 A2 J1 A8 L4 A14
B4 GNO E3 VCC J2 VCC L5 A16
B5 EMPTYB E9 VCC J5 A15 L6 B15
B6 UNCKA E10 B2 J6 NC L7 B16
B7 EMPTYA E11 B3 J7 B17 L8 B14
B8 GNO F1 A6 J10 VCC L9 B13
B9 RSTB F2 GNO J11 B8 L10 B12
B10 PENB F3 NC K1 A9 L11 B11

~1ExAs
INSTRUMENTS
14-26 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT7820
512x 18x2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS303B - AUGUST 1994 - REVISED FEBRUARY 1996

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME
AO-A17 I/O Port-A data. The 18-bit bidirectional data port for side A.
FIFO A almost-full/almost-empty flag. Depth offset values can be programmed for AF/AEA, or the default value of 128
AF/AEA 0 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is high when FIFO A contains
X or less words or (512 - Y) or more words. AF/AEA is set high after FIFO A is reset.
FIFO B almost-full/almost-empty flag. Depth offset values can be programmed for AF/AEB, or the default value of 128
AF/AEB 0 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is high when FIFO B contains
X or less words or (512 - Y) or more words. AF/AEB is set high after FIFO B is reset.
BO-B17 I/O Port-B data. The 18-bit bidirectional data port for side B.
FIFO A empty flag. EMPTYA is low when FIFO A is empty and is high when FIFO A is not empty. EMPTYA is set low
EMPTYA 0
after FIFO A is reset.
FIFO B empty flag. EMPTYB is low when FIFO B is empty and is high when FIFO B is not empty. EMPTYB is set low
EMPTYB 0
after FIFO B is reset.
FIFO A full flag. FULLA is low when FIFO A is full and is high when FIFO A is not full. FULLA is set high after FIFO A
FULLA 0
is reset.
FIFO B full flag. FULLB is low when FIFO B is full and is high when FIFO B is not full. FULLB is set high after FIFO B
FULLB 0
is reset.
Port-B output enable. BO-B17 outputs are active when GAB is high and are in the high-impedance state when GAB is
GAB I
low.
Port-A output enable. AO-A17 outputs are active when GBA is high and are in the high-impedance state when GBA is
GBA I
low.
FIFO A half-full flag. HFA is high when FIFO A contains 256 or more words and is low when FIFO A contains 255 or fewer
HFA 0
words. HFA is set low after FIFO A is reset.
FIFO B half-full flag. HFB is high when FIFO B contains 256 or more words and is low when FIFO B contains 255 or fewer
HFB 0
words. HFB is set low after FIFO B is reset.
FIFO A load clock. Data is written into FIFO A on a low-to-high transition of LOCKA when FULLA is high. The first word
LOCKA I
written into an empty FIFO A is sent directly to the FIFO A data outputs.
FIFO B load clock. Data is written into FIFO B on a low-ta-high transition of LDCKB when FULLB is high. The first word
LDCKB I
written into an empty FIFO B is sent directly to the FIFO B data outputs.
FIFO A program enable. After reset and before a word is written into FIFO A, the binary value on AO-A7 is latched as
PENA I
an AF/AEA offset value when PENA is low and LOCKA is high.
FIFO B program enable. After reset and before a word is written into FIFO B, the binary value on BO-B7 is latched as
PENB I
an AF/AEB offset value when PENB is low and LDCKB is high.
RSTA I FIFO A reset. A low level on RSTA resets FIFO A forcing EMPTYA low, HFA low, FULLA high, and AF/AEA high.
RSTB I FIFO B reset. A low level on RSTB resets FIFO B forcing EMPTYB low, HFB low, FULLB high, and AF/AEB high.
Port-B read select. SAB selects the source of BO-B17 read data. A low level selects real-time data from AO-A 17. A high
SAB I
level selects the FIFO A output.
Port-A read select. SBA selects the source of AO-A17 read data. A low level selects real-time data from BO - B17. A
SBA I
high level selects the FIFO B output.
UNCKA I FIFO A unload clock. Data is read from FIFO A on a low-to-high transition of UNCKA when EMPTYA is high.
UNCKB I FIFO B unload clock. Data is read from FIFO B on a low-to-high transition of UNCKB when EMPTYB is high.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-27
SN54ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SGBS303B-AUGUST 1994- REVISED FEBRUARY 1996

logic symbolt

<ll
FIFO
A9 512x 18x2
SAB
A3 SN54ABT7820
SBA :}MOOE
A10
GAB EN1
A2
GBA EN2
B3 "- A B9
RSTA RESET B RSTB
A1 r-, B10
PENA PROG ENA PROGENB /1 PENB
A4 A8
LOCKA LOCKA LOCKB LOCKB
B6 C5
UNCKA UNCKA UNCKB UNCKB
B1 B11
FULLA FULLA FULLB FULLB
B7 B5
EMPTYA EMPTYA EMPTYB EMPTYB
B2 ALMOST·FULU ALMOST-FULU A11
AF/AEA AF/AEB
ALMOST-EMPTY A ALMOST·EMPTY B
HFA
C2

.,
HALF-FULL A HALF·FULLB
r
C10
HFB

02 010
AO 0 0 BO
01 011
A1 B1
E2 E10
A2 B2
E1 E11
A3 B3
G3 G9
A4 B4
G1 G11
A5 B5
F1 F10
A6 B6
H1 H11
A7 B7
J1 J11
A8 B8

~ ~
K1 K11
A9 B9
L1 K10
A10 B10
K2 L11
A11 B11
L2 L10
A12 B12
L3 L9
A13 B13
L4 L8
A14 B14
J5 L6
A15 B15
L5 L7
A16 B16
K6 J7
A17 17 17 B17

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

~1ExAs
INSTRUMENTS
14-28 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT7820
512x18x2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS303B - AUGUST 1994 - REVISED FEBRUARY 1996

logic diagram (positive logic)

SAB

SBA
I r--.... n ......J

HFB
t .~
- ell
FIFOB RSTB
512 x 18
AF/AEB PENB

EMPTYB FULLB
UNCKB
r----------.,
I i
, r
LOCKB

Q [1] D BO
GBA ! I I
[2]
I~
1 __ !I [3]
I
IL. _ _ _ _ _ _ _ _ _ _ ..1
r----r
:
[4]
••
I 1 of 18 Channels I [15]
[16]
To Other Channels
[17]
[16]

GAB

ell I
RSTA FIFO A HFA
512 x 18
PENA AF/AEA
FULLA EMPTYA
LDCKA
, r r----------.,
UNCKA

~
AO D [1] Q
[2)
[3]

. I I

L=__
[4]
I I I
[15] 2..~!.C~~~J
[16]
To Other Channels
[17]
[18]

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-29
SN54ABT7820
512x18x2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS303B-AUGUST 1994- REVISED FEBRUARY 1996

BusA BusB BusA BusB

SAB SBA GAB GBA SAB SBA GAB GBA

L X H L x x L L

BusA BusB BusA BusB

SAB SBA GAB GBA SAB SBA GAB GBA

X L L H H L H H

BusA BusB BusA BusB

SAB SBA GAB GBA SAB SBA GAB GBA

H X H L L H H H

BusA BusB
BusA BusB

SAB SBA GAB GBA SAB SBA GAB GBA

X H L H H H H H

Figure 1. Bus-Management Functions

~TEXAS
INSTRUMENTS
14-30 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS303B-AUGUST 1994- REVISED FEBRUARY 1996

SELECT-MODE CONTROL TABLE

CONTROL OPERATION
SBA SAB A BUS B BUS
L L Real-time B to A bus Real-time A to B bus
H L FIFO B to A bus Real-time A to B bus
L H Real-time B to A bus FIFO A to B bus
H H FIFO B to A bus FIFO A to B bus

OUTPUT-ENABLE CONTROL TABLE

CONTROL OPERATION
GBA GAB A BUS BBUS
L L Isolation/input to A bus Isolation/input to B bus
H L A bus enabled Isolation/input to B bus
L H Isolation/input to A bus B bus enabled
H H A bus enabled B bus enabled

Figure 1. BUS-Management Functions (Continued)

-!II TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-31
 [3 (I) en (I)
timing diagram for FIFO At
~
Ol .......... Z
gJ:O I\) en
BOX ~
~OJ""'»
I'ISTA ~ l> m Q) OJ
cOX"'"
Gl ......
~I------------------------------------------------~----- ~ OJ I\) Q)
PENA
o I
I :!6 ~
~:a

~~~~~----­
LOCKA 'm
ill 0
::; .....
"'-
mO
AO-A17
$TI$l"'~~ 18§§8iS@&X~i*~ ~z
Ill»
~.­
l>-n
I I I I I I :n-
~:o
UNCKA 1IIIII nnnnn ",(I)
~ I I . I I I I ~H i Yr-;
L...;~ y~ l . - :§:-;-I
!il_~ I I I I I I I I I I I _z
~~~ .odvol, I WO~d1 j : ~~ _~w_~~ _~~ -n
:a
~-J QO-Q17
~ ~ 257 258

~~~
, . 129 130
(I)

I I I I I I II -;-I

~rnG; EMPTYA JJ I
I!
I I
I
I
I
I I
o
c:
.....
s:::
;~
I I I I I
m
II - I I I
~-----+I----~I----~----~
WI I
s:::
FULLA I I I o
~ ~
HFA
I
II
I
II
I
I
I
I
I
I
I
~----~----~---
I I I
AF/AEA

I
iI II
I
I
~-----~----~

I I
I I
Set x =Y = 128 Empty + X Half-Full Full - Y Full Full - Y Half-Full Empty+X Empty

t SAB = GAB = H, GBA= L

Operation of FIFO B is identical to that of FIFO A.
 SN54ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS303B - AUGUST 1994 - REVISED FEBRUARY 1996

offset values for AF/AE

The aimost-full/aimost-empty (AF/AE) flag of each FIFO has two programmable limits: the almost-empty offset
value (X) and the almost-full offset value (Y). The offsets of a flag can be programmed from the input of its FIFO
after it is reset and before any data is written to its memory. An AF/AE flag is high when its FIFO contains X or
fewer words or (512 - Y) or more words.
To program the offset values for AF/AEA, PENA can be brought low after FIFO A is reset and only when LOCKA
is low. On the following low-to-high transition of LOCKA, the binary value on AO-A7 is stored as the
almost-empty offset value (X) and the almost-full offset value (Y). Holding PENA low for another low-to-high
transition of LOCKA reprograms Y to the binary value on AO-A7 at the time of the second LOCKA low-to-high
transition.
PENA can be brought back high only when LOCKA is low during the first two LOCKA cycles. PENA can be
brought high at any time after the second LOCKA pulse returns low. A maximum value of 255 can be
programmed for either X or Y (see Figure 2). To use the default values of X =Y =128 for AF/AEA, PENA must
be tied high. No data is stored in the FIFO when its AF/AE offsets are programmed.
The AF/AEB flag is programmed in the same manner. PENB enables LOCKB to program the AF/AEB offset
values taken from BO-B7.

RSTA ~ /
\.,--,- - "

LOCKA

AO-A17 ~ XandY X"-__ .JX. . ___

Y
__ w_or_d_1_ __

EMPTYA~ /
Figure 2. Programming X and Y Separately for AF/AEA

~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265 14-33
SN54ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
SGBS303B - AUGUST 1994 - REVISED FEBRUARY 1996

absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Voltage range applied to any output in the high state or power-off state, Vo ............. -0.5 V to 5.5 V
Current into any output in the low state, 10 ................................................. 48 rnA
Input clamp current, 11K (VI < 0) .......................................................... -18 rnA
Output clamp current, 10K (Vo < 0) ....................................................... -50 rnA
Operating free-air temperature range, TA .......................................... -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under"absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

recommended operating conditions

MIN NOM MAX UNIT
Vee Supply voltage 4.5 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
Input voltage V
VI
IOH High-level output current ° Vee
-12 mA
IOL Low-level output current 24 mA
At/Av Input transition rise or fall rate 5 ns/V
TA Operating free-air temperature -55 125 ·e

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP:t MAX UNIT
VIK Vee=4.5V, 11--lamA -1.2 V
Vee- 4.5V, IOH--3mA 2.5
VOH Vee = 5 V, IOH=-3mA 3 V
Vee = 4.5 V, IOH=-12 rnA 2
VOL Vee- 4.5V, ioL-24 mA 0.55 V
II Vee =5.5 V, VI = Vee or GND ±5 IlA
IOZH§ Vee- 5.5V, Vo =2.7 V 50 IlA
IOZL§ Vee- 5.5V, VO·O.5V -50 IlA
lOll Vee =5.5 V, Vo - 2.5 V -40 -100 -180 mA
Outputs high 15
ICC Vee = 5.5 V, 10- 0, VI =Vee or GND Outputs low 95 mA
Outputs disabled 15
ei Control inputs VI - 2.5 V or 0.5 V 6 pF
Co Flags Va =2.5 V or 0.5 V 4 pF
eio Aor B ports Vo = 2.5 V or 0.5 V a pF
:tAli typical values are at Vee - 5 V, TA = 25·e.
§ The parameters IOZH and 10ZL include the input leakage current.
II Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

~TEXAS
INSTRUMENTS
14-34 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT7820
512x18x2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS303B - AUGUST 1994 - REVISED FEBRUARY 1996

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
MIN MAX UNIT
fclock Clock frequency 40 MHz
LOCKA, LOCKB high 9
LOCKA, LOCKB low 9
tw Pulse duration UNCKA, UNCKB high 9 ns
UNCKA, UNCKB low 9
RSTA, RSTB low 10
AO-A17 before LOCKAi and BO-B17 before LOCKBi 4
PENA before LOCKAi and PENB before LOCKBi 6
tsu Setup time ns
LOCKA inactive before RSTA high and LOCKB inactive before RSTB
4
high
AO-A17 after LOCKAi and BO-B17 after LDCKBi 0
th Hold time PENA after LOCKA low and PENB after LDCKB low 3 ns
LDCKA inactive after RSTA high and LOCKB inactive after RSTB high 4

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-35
SN54ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS303B - AUGUST 1994 - REVISED FEBRUARY 1996

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 50 pF (unless otherwise noted) (see Figure 5)
PARAMETER FROM PNPUT) TO (OUTPUT) MIN MAX UNIT
fmax LOCK,UNCK 40 MHz
LOCKAi, LOCKBi 3 18
tpd B/A ns
UNCKAi, UNCKBi 3 15
tpLH LOCKAT, LOCKBT 3 17
EMPTYA, EMP"I'YB ns
tpHL UNCKAT, UNCKBi 3 16
tpHL RSTA low, RSTB low Eii.1Pi"iiA",EMPTYB 5 18 ns
tpHL LOCKAi, LOCKBi FULLA,FULLB 5 16 ns
UNCKAT, UNCKBi 5 17
tPLH RSTAlow, FULLA,FULLB ns
7 22
RSTBlow
LOCKAi, LOCKBT 7 18
tpd AF/AEA, AF/AEB ns
UNCKAi, UNCKBT 7 18
tPLH RSTA low, RSTB low AF/AEA, AF/AEB 1 16 ns
tpLH LOCKAi, LOCKBi HFA, HFB 6 17 ns
UNCKA, UNCKB 7 17
tPHL HFA, HFB ns
RSTA low, RSTB low 1 16
SAB/SBA; 1 12
tpd B/A ns
NB 1 11
ten GBNGAB NB 1 10 ns
tdis GBNGAB AlB 1 13 ns
t All typIcal values are at 5 V, TA = 25°C.
:j: These parameters are measured with the internal output state of the storage register opposite that of the bus input.

~1ExAs
INSTRUMENTS
14-36 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT7820
512 x 18 x 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS303B - AUGUST 1994 - REVISED FEBRUARY 1996

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME SUPPLY CURRENT
vs vs
LOAD CAPACITANCE CLOCK FREQUENCY
160
VCC~5V
1
TA=75°C _I 1 J V
typ+ 6 I- TA = 25°C CL=OpF VCC=5.5~

!II
RL=500Q
/ «
140
/ V
./
V/'VV
C

..E
I
typ+ 4
/ E
I
120
VCC=,5V /'
V
i=
>- ./
V ~ ~ ,,/
100
:::I
V
/ V /' ,,/V
-m
c
c ./
V 0
~
0 typ+2 80
iCI V Co
:::I
/- /'
V
~
C/)
... I
/ ,,/ VCC = 4.5 V
Co
e / S 60

~ :::;V
a.. typ 0
I E
-'8.
/
/ 40

typ-2 20
o 50 100 150 200 250 300 10 15 20 25 30 35 40 45 50 55 60 65 70
CL - Load Capacitance - pF fclock - Clock Frequency - MHz

Figure 3 Figure 4

calculating power dissipation

With ICC(f) taken from Figure 4, the maximum power dissipation (PT) based on all outputs changing states on
each read can be calculated by:
PT = VCC x ICC(f) + :E(CL x VCc 2 x fo)
where:
ICC(f) = maximum Icc per clock frequency
CL = output capacitive load
fo = data output frequency

~TEXAS
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS, TeXAS 75265 14-37
SN54ABT7820
512x18x2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS303B - AUGUST 1994 - REVISED FEBRUARY 1996

PARAMETER MEASUREMENT INFORMATION

7V

Sl!> Rl =R1 =R2 Input 1 1•5 V \l.~V---- 3V

R1
~ 4- ov
tpZl~ I+- 1
From Output _...-_+-_-.- Test 1 I tpLZ -+j I+-
Under Test Point Output --';"1\r-I ---T~t-- =3.5 V
1 1.5V 1 ..
R2 1 I-'L
1 - . - - - VOL
1 ~HZ -.j 14- L 0.3 V
tpZH -+! 1 1 _*- __ _

Output - - - ' - =OV

lOAD CIRCUIT VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES

PARAMETER R1, R2 Clt Sl

tpZH Open
ten ~ 5000 50pF
tpZL Closed
Open
tdis ..!ft!L 5000 50pF
tpLZ Closed
tpd 5000 50pF Open
t Includes probe and test-fixture capacitance

Figure 5. Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
14-38 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN54ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGASOOI B - FEBRUARY 1995 - REVISED MARCH 1996

• Member of the Texas Instruments • Input-Ready, Output-Ready, and Half-Full

W/debus™ Family Flags
• Independent Asynchronous Inputs and • Cascadable In Word Width and/or Word
Outputs Depth
• 1024 Words x 18 Bits • Fast Access Times of 20 ns With a 5O-pF
• Read and Write Operations Can Be Load
Synchronized to Independent System • High Output Drive for Direct Bus Interface
Clocks • Package Options Include S8-Pin Ceramic
• Programmable Almost-FuIl/Almost-Empty PGA (GB) or Space-Saving S8-Pin Ceramic
Flag Quad Flatpack (HV)t

description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN54ACT7811 is a 1024 x 18-bit FIFO for high speed and fast access times. It processes data
at rates up to 28.5 MHz and access times of 20 ns in a bit-parallel format. Data outputs are noninverting with
respect to the data inputs. Expansion is easily accomplished in both word width and word depth.
The SN54ACT7811 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry
adds the ability to synchronize independent read and write (interrupts, requests) to their respective system
clock.
The SN54ACT7811 is characterized for operation from -55°C to 125°C.

GBPACKAGE
(TOP VIEW)

234 5 6 7 8 9

A @] @ @ @ @ @ @ @ @
B @ @ @ @ @ @ @ @ @
C @ @ @ @ @ @ @ @
o @ @ @ @ @ @
E @ @ @ @
F @ @ @ @ @ @
G @ @ @ @ @ @ @ @
H @ @ @ @ @ @ @ @ @
J @ @ @ @ @ @ @ @ @

t The SN54ACT7811 HV is not production released.

Widebus is a trademark of Texas Instruments Incorporated.

Copyright © 1996, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-39
SN54ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGASOOI B - FEBRUARY 1995 - REVISED MARCH 1996

GB-Package Terminal Assignments

TERMINAL NAME TERMINAL NAME TERMINAL NAME TERMINAL NAME
A1 Q15 97 Q5 F2 017 H8 DO
A2 Q13 98 Q4 F8 WRTEN2 H9 OAF
A3 Q12 99 Q1 F9 AF/AE Jl 011
A4 Q11 C1 RESET G1 016 J2 010
A5 Q10 C2 Q16 G2 015 J3 08
A6 Q8 C8 Q2 G8 WRTCLK J4 NC
A7 Q7 C9 QO G9 WRTEN1 J5 . 07
A8 Q6 01 OE HI 014 J6 06
A9 Q3 09 HF H2 013 J7 05
91 OR E1 ROEN1 H3 012 J8 03
92 Q17 E2 ROEN2 H4 09 J9 02
93 Q14 E9 IR H6 04
95 Q9 F1 ROCLK H7 01
VCC = 94, C6, C7, 02, 07, E8, G3, G4, G6 GNO = 96, C3, C4, 03, 08, F3, F7, G7, H5
NC = No internal connection

HVPACKAGEt
(TOP VIEW)

~ ~ N
o(3ZZ I~ 00 0
~ ~ ~ Z 0 ~ ~ LU ffl Oz a: O~ ~ Z ~
ooo~a:a:a:oa:>~o~oo~o
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 60 VCC
11 59 Q14
012 12 58 Q13
011 13 57 GNO
14 56 Q12
09 15 55 Q11
VCC 16 54 VCC
08 17 53 Q10
GNO 18 52 Q9
07 19 51 GNO
06 20 50 Q8
05 21 49 Q7
04 22 48 VCC
03 23 47 Q6
02 24 46 Q5
01 25 45 GNO
26 44 Q4
27 28 29.30 31 32 33 34 35 36 37 38 39 40 41 42 43

t The SN54ACT7811 HV is not production released.

~1ExAs
INSTRUMENTS
14-40 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGAS001 B - FEBRUARY 1995 - REVISED MARCH 1996

logic symbolt

<I>
FIFO 1024 x 18

C1 .J'.,
RESET RESET
G8
WRTCLK WRTCLK E9
G9
[~JWRTEN
IR
WRTEN1 09
F8 HALFINFULL
ROY
HF
WRTEN2 F9
F1 ROCLK ALMOST FULUEMPTY AF/AE
ROCLK B1
E1 I-- OUT ROY OR
ROEN1 &
01
OE EN1 ROEN
E2
ROEN2
I--
OAF
H9

H8
I"-

., OEF ALMOST FULL

r
C9
00 0 0 QO
H7 B9
01 Q1
J9 C8
02 Q2
J8 A9
03 Q3
H6 B8
04 Q4
J7 B7
05 Q5
J6 A8
06 Q6
J5 A7
07 Q7
J3 A6
08
09
H4 [§) [§)1':7 B5
Q8
Q9
J2 AS
010 Q10
J1 A4
011 Q11
H3 A3
012 Q12
H2 A2
013 Q13
H1 B3
014 Q14
G2 A1
015 Q15
G1 C2
016 Q16
F2 B2
017 17 17 Q17

tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
Pin numbers shown are for the GB package.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-41
SN54ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGAS001 B - FEBRUARY 1995 - REVISED MARCH 1996

functional block diagram

OE

~J
00-017

L Location 1
ROCLK
ROEN1
Synchronous
Read
Control
I Read
Pointer
I
/
Location 2

ROEN2

I 1024 x 18 RAM

WRTCLK
WRTEN1
WRTEN2
Synchronous
Write
Control t- r-
i Write
Pointer
I
I Location 1023
Location 1024
I
11
~ I
Reset Register QO-Q17
Logic
RESET
Status-
Flag OR
Logic IR
HF
AF/AE

~TEXAS
INSTRUMENTS
14-42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGASOO1 B - FEBRUARY 1995 - REVISED MARCH 1996

Terminal Functions
TERMINALt
1/0 DESCRIPTION
NAME NO.
AF/AE boundary is defined by the AF/AE offset value (X). This value can be programmed during
reset, orthe default value of 256 can be used. The AF/AE flag is high when the FIFO contains (X + 1)
or fewer words or (1025 - X) or more words. The AF/AE flag is low when the FI FO contains between
(X + 2) and (1024 - X) words.
Programming procedure for AF/AE - The AF/AE flag is programmed during each reset cycle. The
AF/AE offset value (X) is either a user-defined value or the default of X =256. Instructions to program
AF/AE using both methods are as follows:
User-defined X
AF/AE F9 0
Step 1: Take DAF from high to low.
Step 2: If the reset (RESET) input is not already low, take RESET low.
Step 3: With DAF held low, take RESET high. This defines the AF/AE flag using X.
Step 4: To retain the current offset for the next reset, keep DAF low.
DllIlwI!..X
To redefine the AF/AE flag using the default value of X =256, hold DAF high during the reset
cycle.
Define almost full. The high-to-Iow transition of DAF stores the binary value of data inputs as the
DAF H9 I AF/AE offset value (X). With DAF held low. a low pulse on the reset (RESET) input defines the AF/AE
flag using X.
F2, G1,G2,
Data inputs for 18-bit-wide data to be stored in the memory. Data lines DO-DS also carry the AF/AE
DO-D17 H1-H4, H6-HS, I
offset value (X) on a high-to-Iow transition of the DAF input.
J1-J3, J5-J9
Half-full flag. HF is high when the FIFO contains 513 or more words and is low when it contains 512
HF D9 0
or fewer words.
Input-readyflag.IR is high when the FIFO is notfull and low when the device is full. During reset, IR
is driven low on the rising edge of the second write clock (WRTCLK) pulse. IR is then driven high on
IR E9 0
the riSing edge of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR
is driven low, IR Is driven high on the second WRTCLK pulse after the first valid read.
Output enable. The data-out (QO-Q17) outputs are in the high-impedance state when OE is low. OE
OE D1 I
must be high before the rising edge of read clock (RDCLK) to read a word from memory.
Output ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset, OR
is set low on the rising edge of the third read clock (RDCLK) pulse. OR is set high on the rising edge
OR 81 0
of the third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the
rising edge of the first RDCLK pulse after the last word is read.
Data outputs. The first data word to be loaded into the FIFO is moved to the data-out (QO-Q17)
A1-A9, 82, 83,
register on the riSing edge of the third read clock (RDCLK) pulse to occur alter the first valid write.
QO-Q17 85,87-89, C2, 0
The read-enable (RDEN1, RDEN2) inputs do not affect this operation. Thefollowing data is unloaded
CS,C9
on the rising edge of RDCLK when RDEN1, RDEN2, OE, and OR are high.
Read clock. Data is read out of memory on a low-to-high transition at RDCLK if the OR output and
the OE, RDEN1, and RDEN2 control inputs are high. RDCLK is a free-running clock and functions
RDCLK F1 I
as the synchronizing clock for all data transfers out of the FIFO. OR is also driven synchronously with
respect to RDCLK.
RDEN1, E1 Read enable. RDEN1 and RDEN2 must be high before a riSing edge on RDCLK to read a word out
I
RDEN2 E2 of memory. The read enables are not used to read the first word stored in memory.
Reset. A reset is aocomplished by taking RESET low and generating a minimum of four RDCLK and
WRTCLK cycles. This ensures that the internal read and write pointers are reset and that OR, HF,
and IR are low and AF/AE is high. The FIFO must be reset upon power up. With DAF input at a low
RESET C1 I
level, a low pulse on RESET defines AF/AE using the AF/AE offset value (X), where X is the value
previously stored. With DAF at a high level, a low-level pulse on RESET defines AF/AE using the
default value of X = 256.
t Terminals listed are for the G8 package.

-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265 14-43
SN54ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS001 B- FEBRUARY 1995 - REVISED MARCH 1996

Terminal Functions (Continued)

TERMINALt
I/O DESCRIPTION
NAME NO.
Write clock. Data is written into memory on a low-ta-high transition of WRTCLK if the IR output and
the WRTEN1 and WRTEN2 control inputs are high. WRTCLK is a free-running clock and functions
WRTCLK G8 I
as the synchronizing clock for all data transfers into the FIFO. IR output is also driven synchronously
with respect to the WRTCLK signal.
WRTEN1, G9 Write enables. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word
I
WRTEN2 F8 to be written into memory. The write enables do not affect the storage of the AF/AE offset value (X).
t Terminals listed are for the GB package.

WRTCLK

WRTEN1

WRTEN2

00-017

RDCLK

RDEN1

RDEN2

OE
o
QO-Q17
I I i

AF/AE I
I
I
I
I
I
I
Store the Value of 00-08 as X
I Define the AF/AE Flag
Using the Value of X
t X is the binary value of 00-08 only.
Figure 1. Reset Cycle: Define AF/AE Using the Value of X

~1ExAs
INSTRUMENTS
14-44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGASOOl B - FEBRUARY 1995 - REVISED MARCH 1996

RES~ I~ __________________ ~

OAF ~9.~~·!?,ar!'~
I
WRTCLK I

WRTEN1

WRTEN2

DO-D17

RDCLK

RDEN1

RDEN2

--------~------~--~--------+_------~----------
OE
o1
QO-Q17 Invalid
i i i

AF/AE ?{l!Or'!~.i£8~ I
HF Rfg~t:§r;:sa I
IR ggggg~cir'!§8(im
Define the AF/AE Flag
=
Using the Value of X 256

Figure 2. Reset Cycle: Define AF/AE Using the Default Value

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-45
SN54ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGAS001B- FEBRUARY 1995- REVISED MARCH 1996

1
o

WRTCLK
~~~r-fl
I I I I
I I . I I
WRTEN1 o
I I I I
I I I I
I I I I
WRTEN2

00-017

ROCLK

1
ROEN1
o
I I i I I
ROEN2
I I I I I
I I I I I
I I I I I
OE II II I
I
I
I
I
I
1
o
I I I I I
QO-Q17 _______I_nV_al_ld______~><~------~------W~:1------~:_______:~_
I
OR

AF/AE

HF

IR
L
Figure 3. Write Cycle

-!111ExAs
INSTRUMENTS
14--46 POST OFFICE BOX 655303 • DALLAS, TEXAS 76265
 SN54ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS001 B - FEBRUARY 1995 - REVISED MARCH 1996

WRTCLK

I I
WRTEN1 ~ I
WRTEN2 --n
I

I
I
I
I
00-017) Wl:025

I I
ROCLK I I ~r-fl--,~r--rL-fL-
I I I I I I
ROEN1JI I I I I
I I I I I
I I I I I
I I I I I
ROEN2 I I I I
I I I I I
I I I I I
OEil I I i
IH I I
QO-Q17 I I +~
I
OR I
I
I
I
AF/AE I
I
I
HF I
I
I
IR 1 . . _____--.1

Figure 4. Read Cycle

~1EXAS
INSTRUMENTS
POST OFFICE BOX 555303 • DALLAS. TEXAS 75255 14-47
SN54ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST·OUT MEMORY
SGAS001 B - FEBRUARY 1995 - REVISED MARCH 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage, VI ............................................................................. 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range, TA ............................................ -55°C to 125°C
Storage temperature range, Tstg .................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
lunctional operation 01 the device at these or any other conditions beyond those indicated under "recommended operating condHions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliabilHy.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL LOW-level input voltage 0.8 V
10H High-level output current -8 mA
10L Low-level output current 16 mA
TA Operating Iree-air temperature -55 125 ·e

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP:j: MAX UNIT
VOH Vee = 4.5 V, IOH=-8mA 2.4 V
VOL Vee = 4.5 V, 10L= 16mA 0.5 V
II Vee=5.5V, VI =VeeorOV ±5 j.tA
102 Vee =5.5 V, Vo = VeeorOV ±5 j.tA
VI =Vee - 0.2 V or 0 V 400 j.tA
lee§
One input at 3.4 V, Other inputs at Vee or GND 1 mA
ei VI=OV, 1=1 MHz 4 pF
Co VO=OV, 1=1 MHz 8 pF
:j: All tYPical values are at Vee = 5 V, TA = 25°C.
§ ICC tested with outputs open

~1EXAS
INSTRUMENTS
14-48 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGAS001B - FEBRUARY 1995 - REVISED MARCH 1996

timing requirements (see Figures 1 through 8)

MIN MAX UNIT
fclock Clock frequency 28.5 MHz
Data in (00-017) high or low 14
WRTCLKhigh 10
WRTCLKlow 14
RDCLKhigh 10
Iw Pulse duration ns
RDCLKlow 14
OAF high 10
WRTEN1, WRTEN2 high or low 10
OE, RDEN1, RDEN2 high or low 10
Data in (00-017) before WRTCLKi 5
WRTEN1, WRTEN2 high before WRTCLKi 5
OE, RDEN1, RDEN2 high before RDCLKi 5
lsu Setup time Reset: RESET low before first WRTCLK and RDCLKit 7 ns
Define AF/AE: 00-08 before DAFt 5
Define AF/AE: DAFt before RESETi 7
Define AF/AE (default): OAF high before RESETi 5
Data in (00-017) afterWRTCLKi 1
WRTEN1, WRTEN2 high after WRTCLKi 1
OE, RDEN1, RDEN2 high after RDCLKi 1
th Hold time Reset: RESET low after fourth WRTCLK and RDCLKit 0 ns
Define AF/AE: 00-08 after DAFt 1
Define AF/AE: OAF low after RESEfi 0
Define AF/AE (default): OAF high after RESETi 1
..
t To permit the clock pulse to be utilized for reset purposes

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-49
SN54ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGAS001 B - FEBRUARY 1995 - REVISED MARCH 1996

switching characteristics over recommended operating free-air temperature range (see Figures 9
and 10)
VCC = 4.5 V to 5.5 V,
CL=50pF,
FROM TO
PARAMETER RL = 5000, UNIT
(INPUT) (OUTPUT)
TA = -55°C to 125°C
MIN MAX
fmax WRTCLK or RDCLK 28.5 MHz
tpd 3 20
RDCLKT AnyQ ns
tpdt
tpg WRTCLKI IR 1 14 ns
tpd RDCLKI OR 1 14 ns
WRTCLKI 5 24
tpd AF/AE ns
RDCLKI 5 24
tpLH WRTCLKI 5 23
HF ns
tpHL RDCLKI 5 23
tpLH AF/AE 2 23
RESET! ns
tpHL HF 3 25
len 1 11
OE AnyQ ns
tdis 1 14
t This parameter IS measured with CL = 30 pF (see Figure 5).

operating characteristics, Vee =5 V, TA =25°C

PARAMETER TEST CONDITIONS
Power dissipation capacitance per 1K bits CL =50 pF, f = 5 MHz

~TEXAS
INSTRUMENTS
14-50 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS001 B - FEBRUARY 1995 - REVISED MARCH 1996

TYPICAL CHARACTERISTICS

TYPICAL PROPAGATION DELAY TIME TYPICAL POWER DISSIPATION CAPACITANCE

vs vs
lOAD CAPACITANCE SUPPLY VOLTAGE
18
68
VCC~5V
17 _ TA=25°C
II.
0. M~Z
f l 15
I
III RL = 500 (l
67
TA = 25°C ./
C
,/ 8c CL=50pF
I
16
~ V
. /V
G)
E ...co /
j:: 0. 66
>-
co
iii
15

/
", ~
C Y
c
c
0
14 ."
0
:;0. 65 ./
;;Cl / .~ V
co 13 i5 V
0.
E!
D..
I 12
I I
64
V
'C
_0.
11
/
D..

'C
I
63
V
0.
V
10
I 62
o 50 100 150 200 250 300 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5

C L - Load Capacitance - pF VCC - Supply Voltage - V

Figure 5 Figure 6

calculating power dissipation

The maximum power dissipation (PT) of the SN54ACT7811 can be calculated by:
PT = Vee x [lee + (N x ~Iee x dc)] + E (Cpd x Vee 2 x fi) + E (Cl x Vee2 x fa)
Where:
lee power-down lee maximum
N number of inputs driven by a TTL device
~ lee increase in supply current
dc duty cycle of inputs at a TTL high level of 3.4 V
Cpd power dissipation capacitance
Cl output capacitive load
fi data input frequency
fa data output frequency

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-51
SN54ACT7811
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS001 B - FEBRUARY 1995 - REVISED MARCH 1996

APPLICATION INFORMATION
expanding the SN54ACT7811
The SN54ACT7811 is expandable in width and depth. Expanding in word depth offers special timing
considerations:
- After the first data word is loaded into the FIFO, the word is unloaded, and the OR output goes high after
(N x 3) RDCLK cycles, where N is the number of devices used in depth expansion.
- After the FIFO is filled, the IR output goes low, the first word is unloaded, and the IR is driven high after(N
x 2) write clock cycles, where N is the number of devices used in depth expansion.

CLOCK

WRTCLK
WRTEN1
SN54ACT7811
WRTCLK
WRTEN1
ROCLK
OR
1 SN54ACT7811
WRTCLK
WRTEN1
ROCLK
ROEN1
ROCLK
ROEN1
L
WRTEN2
IR
WRTEN2
IR
ROEN1
ROEN2 n WRTEN2
IR
ROEN2
OR
ROEN2
OR
OE 1--5V OE OE

00-017 00-017 QO-Q17 00-017 QO-Q17 QO-Q17

Figure 7. Word-Depth Expansion: 2048 Words x 18 Bits, N = 2

SN54ACT7811
WRTCLK WRTCLK ROCLK ROCLK
WRTEN WRTEN1 ROEN1 ROEN
WRTEN2 ROEN2

~
IR OR
OE OE

018 - 035 00-017 QO-Q17 Q18-Q35

.---.
IR

- I
SN54ACT7811
' - - - WRTCLK
0-
- OR

ROCLK
WRTEN1 ROEN1 - -
WRTEN2 ROEN2
IR OR
OE -
00-017 ) 00-017 QO-Q17 QO-Q17

Figure 8. Word-Width Expansion: 1024 Words x 36 Bits

~TEXAS
INSTRUMENTS
14-52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ACT7811
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGAS001B - FEBRUARY 1995 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

From Output
Input J. I
\1.5V - - - - 3V

UnderTe~ ~ I I ov
RL=5000 1 T CL=50pF
Output
14- tpd ~

)tl"-";"'--"'~
14- tpd ---+I
::
"':" -=-
LOAD CIRCUIT TOTEM·POLE OUTPUTS

Figure 9. Standard CMOS Outputs

7V
Input 1 5v 1• \.- 1.5~---3V
~ RL= R1 = R2
---11 ~ ov
S1
R1
-+l i+t
tPZL PLZ -.: l+-
I I I I
From Output _ ......_ ......_~_ Test ---+-'1 i 1~"'3.5V
Under Test Point Output I ,1.5V : f--*
. - . - VOL
R2 I tpHZ -.I 1+ L 0.3 V
tpZH -+I 14- I ~
I -- VOH
Output '1.5 V f' ;'3~
\-
. ~".OV
LOAD CIRCUIT
VOLTAGE WAVEFORMS

PARAMETER R1, R2 CLf S1

I tPZH Open
ten 5000 50pF
tpZL Closed
I tpHZ Open
lcIis 5000 50pF
tPLZ Closed
ted 5000 50pF Open
t Includes probe and test fixture capacitance
Figure 10•. 3-State Outputs (Any Q)

~ThxAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-53
14-54
 SN54ACT7881
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY

• Member of the Texas Instruments • Cascadable In Word Width and/or Word

Wldebus™ Family Depth
• Independent Asynchronous Inputs and • Fast Access Times of 13 ns With a 50-pF
Outputs Load
• Read and Write Operations Can Be • High Output Drive for Direct Bus Interface
Synchronized to Independent System • Released as DESC SMD (Standard
Clocks Microcircuit Drawing) 5962-9562701NXD
• Programmable Almost-Full/Almost-Empty • Qualified as a Military Plastic Device Per
Flag MIL-PRF-38535 (QML)
• Pln-to-Pln Compatible With SN74ACT7882, • Available In a Space-Saving 80-Pin Shrink
SN74ACT7884, and SN74ACT7811 Quad Flat (PN) Package
• Input-Ready, Output-Ready, and Half-Full
Flags
PNPACKAGEt
(TOP VIEW}

NC 60 Vee
GNO 59 Vee
GNO 58 NC
016 4 57 03
017 5 56 02
Vee 6 55 GNO
OR 54 01
GNO 53 00
Vee 52 Vee
RESET 51 HF
OE 50 IR
ROEN2 49 GNO
ROEN1 48 GNO
ROCLK 47 AF/AE
GNO 46 Vee
017 45 WRTEN2
016 44 WRTEN1
015 43 WRTCLK
NC 42 GNO
NC 41 NC
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
O~MN~omO~O~~~~MN~O~O
z~~~~~OOOZOOOOOOOO z
00000 > (!)

Nc - No internal connection
t For packaging options other than the PN package, please contact your nearest TI field sales office or the factory.

Widebus is a trademark of Texas Instruments Incorporated.

Copyright © t 995, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-55
SN54ACT7881
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGAS004 - AUGUST 1995

description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN54ACT7881 is organized as 1024 x 18 bits. The SN54ACT7881 processes data at rates up
to 50 MHz and access times of 13 ns in a bit-parallel format. Data outputs are noninverting with respect to the
data inputs. Expansion is easily accomplished in both word width and word depth.
The SN54ACT7881 has normal input-bus to output-bus asynchronous operation. The special enable circuitry
adds the ability to synchronize independent reads and writes to their respective system clocks.
The SN54ACT7881 is characterized for operation from -55°C to 125°C.

~TEXAS
INSTRUMENTS
14-56 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ACT7881
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS004 - AUGUST 1995

logic symbolt

<l!
FIFO
1024x 18

1
RESET "- RESET
29
WRTCLK WRTCLK
30 35
WRTEN1
WRTEN2
31 ~WRTEN IN ROY
HALF FULL
36
IR
HF
5 33
ROCLK ROCLK ALMOST FULUEMPTY AF/AE
4 66
ROEN1 ~ OUT ROY OR
2
OE EN1 ROEN
3
ROEN2
OAF
27

26
"-
.,~ ALMOST FULL
r
38
00 0 0 QO
25 39
01 Q1
24 41
02 Q2
23 42
03 Q3
22 44
04 Q4
21 46
05 Q5
20 47
06 Q6
19 49
07 Q7
17 50
08
15 ~~1V 52
Q8
09 Q9
14 53
010 Q10
13 55
011 Q11
12 56
012 Q12
11 58
013 Q13
10 59
014 Q14
9 61
015 Q15
8 63
016 Q16
7 64
017 17 17 Q17

t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-67
SN54ACT7881
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS004 - AUGUST 1995

functional block diagram

OE

00-017

L ~J
Location 1
RDCLK Synchronous
RDEN1
RDEN2
Read
Control t
I Read
Pointer
I
I
Location 2

I RAM
1024 x 18

WRTCLK Synchronous
WRTEN1
WRTEN2
Write
Control r- I-- I
I Write
Pointer
I
..
I
tJ
~ Reset Logic r Register 00-017

OR
Status-
Flag iR
Logic HF
AFIAE

~1ExAs
INSTRUMENTS
14-58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ACT7881
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS004 - AUGUST 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME NO.
Aimost-fuil/almost-emptyflag. The AF/AE boundary is defined by the almost-fuIValmost-empty offset
value (X). This value can be programmed during reset or the default value of 256 can be used. AF/AE
is high when the FIFO contains (X + 1) or less words or (1025-X) or more words. AF/AE is low when
the FIFO contains between (X + 2) and (1024 - X) words.
Programming procedure for AF/AE - The aimost-fuil/almost-empty flag is programmed during each
reset cycle. The aimost-fuil/almost-empty offset value (X) is either a user-defined value orthe default
of X = 256. Instructions to program AF/AE using both methods are as follows:
AF/AE 47 0 User-defjned X
Step 1: Take DAF from high to low.
Step 2: If RESET is not already low, take RESET low.
Step 3: With DAF held low, take RESET high. This defines the AF/AE using X.
Step 4: To retain the current offset for the next reset, keep DAF low.
!&Ia.uJ1.X
To redefine AF/AE using the default value of X =256, hold DAF high during the reset cycle.
Define-almost-full. The high-te-Iow transition of DAF stores the binary value of data inputs as the
DAF 39 I almost-fuIValmost-empty offset value (X). With DAF held low, a low pulse on RESET defines the
almost-fuIValmost-empty (AF/AE) flag using X.
18-16,27-22, Data inputs for 18-bit-wide data to be stored in the memory. A high-to-Iow transition of DAF captures
DO-D17 I
29,38-31 data for the almost-empty/almost-full offset (X) from D8-DO.
Half-full flag. HF is high when the FIFO contains 512 or more words and is low when the number of
HF 51 0
words in memory is less than half the depth of the FIFO.
Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset,lR
is driven low on the rising edge olthe second WRTCLK pulse. IR is then driven high on the rising edge
IR 50 0
of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low,
IR is driven high on the second WRTCLK pulse after the first valid read.
Output enable. The 00-017 outputs are in the high-impedance state when OE is low. OE must be
OE 11 I
high before the rising edge of RDCLK to read a word from memory.
Output-ready flag. OR is high when the FIFO is not empty and low when the FIFO is empty. During
reset, OR is set low on the rising edge of the third RDCLK pulse. OR is set high on the rising edge
OR 7 0
01 the third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the
rising edge of the first RDCLK pulse after the last word is read.
4, 5, 53, 54, 56, Data outputs. The first data word to be loaded into the FIFO is moved to 00-017 on the rising edge
57, 61, 64, 65, of the third RDCLK pulse to occur after the first valid write. RDEN1 and RDEN2 do not affect this
00-017 0
67, 68, 70, 71, 73, operation. Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2, OE, and
74,77,78,80, OR are high.
Read clock. Data is read out of memory on the low-te-high transition of RDCLK if OR, OE, RDEN1,
RDCLK 14 I and RDEN2 are high. RDCLK is a free-running clock and functions as the synchronizing clock for
all data transfers out of the FIFO. OR is also driven synchronously with respect to RDCLK.
RDEN1, 13 Read enable. RDEN 1 and RDEN2 must be high before a rising edge on RDCLK to read a word out
I
RDEN2 12 of memory. RDEN 1 and RDEN2 are not used to read the first word stored in memory.
Reset. A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and
WRTCLK cycles. This ensures that the internal read and write pointers are reset and that OR, HF,
and IR are low, and AF/AE is high. The FIFO must be reset upon power up. With DAF at a low level,
RESET 10 I
a low pulse on RESET defines AF/AE using the aimost-fuil/almost-empty offset value (X), where X
is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines the
AF/AE flag using the default value of X =256.

~TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS. TEXAS 75265 14-59
SN54ACT7881
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS004 ~ AUGUST 1995

Terminal Functions (Continued)

TERMINAL
I/O DESCRIPTION
NAME NO.
WrHe clock. Data is written into memory on a low-to-high transHion of WRTCLK if IR, WRTEN1, and
WRTCLK 29 I WRTEN2 are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all
data transfers into the FIFO. IR is also driven synchronously wHh respect to WRTCLK
WrHe enable. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word to
WRTEN1, 30
I be written into memory. WRTEN1 and WRTEN2 do not affect the storege of the almost-fuIVaimost-
WRTEN2 31
empty offset value (Xl.

WRTCLK

WRTEN1

WRTEN2

DO-D17

RDCLK

RDEN1

RDEN2

OE

AF/AE &;%iIAf~ I
HF S&/t1A8J!i%8 I
IR 888S&fu*M~
Store the Value of Data as X Define the AF/AE Flag Using the
Programmed Value of X
t X is the binary value on 08-00.

Figure 1. Reset Cycle: Define AF/AE Flag Using a Programmed Value of X

~1EXAS
INSTRUMENTS
POST OFFICE BOX 865303 • DALlAS. TEXAS 75265
 SN54ACT7881
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGAS004 - AUGUST 1995

OAF Don't Cars

--------~~------------------~
WRTCLK

WRTEN1

RDCLK

RDEN1

AF/AE

HF
~QQ~~~------4-------------~------~-----------
IR

Figure 2, Reset Cycle: Define AF/AE Flag Using the Default Value of X = 256

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-61
SN54ACT7881
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS004 - AUGUST 1995

WRTCLK

WRTEN1 i j j i
i i i i
i i i i
WRTEN2 I T j j j
---J i i i I

00-017 _ 1 1 1 ......1_w3......
......W_t...........W_2..... 1 ----'I~~~~$
1 .......1_w4.......
RDCLK

I
-...,~$"l-,~$L
I I I I
RDEN1 I I I I I
I I I I I
I I I I j
RDEN2 I I I I I
I I I I I
OE
I I I I I
I I I I I

QO-Q17 E888888Kili*OC(~""'___----r: ---"T": W_1_ _ ~:r-- __. ,.:__

OR _ _ _ _ _ _ _ _ _ _.... 1 i
i
AF/AE

HF _______________________________ ~

I
I
IR
L
DATA WORD NUMBERS
FOR FLAG TRANSITIONS
TRANSITION WORD
A B C
W513 W(1025-X) W1025

Figure 3. Write Cycle

~lEXAS
INSTRUMENTS
14-62 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ACT7881
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS004 - AUGUST 1995

WRTCLK
WRTEN1 ~~
I ____________ +-_________________________________________
WRTEN2 i1~ _____.....;____________________
00-017 ~3~r~~~~~~~~~~~~~~~~~~~~~~~~~~~~
RDCLK I

RDEN1 .J 1

RDEN2 - -...
1 ---' I
OE ~~~---~---+---~---~------+I---
OO~7 ~
OR L-
AF/AE

HF I
I
IR -'~_ _ _ _ _- - I

DATA WORD NUMBERS FOR FLAG TRANSITIONS

TRANSITION WORD
A B C 0 E F
W513 W514 W(1024-X) W(1025-X) W1024 W1025

Figure 4. Read Cycle

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-63
SN54ACT7881
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGASOO4 - AUGUST 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .. ; ....................................................... -0.5 V to 7 V
Input voltage, VI ............................................................................. 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range, TA ............................................ -55°e to 125°e
Storage temperature range, Tstg .................................................... -65°e to 1500 e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage O.S V
10H High-level output current -S mA
10L LOW-level output current 16 mA
TA Operating free-air temperature -55 125 °e

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
VOH Vee = 4.5 V, 10H--SmA 2.4 V
VOL Vee = 4.5 V, IOL-16mA 0.5 V
II Vee=5.5V, VI = Vee orO ±5 !IA
laz Vee = 5.5 V, Vo-Vee orO ±5 !IA
VI a Vee-0.2 VorO 400 !IA
lee§
One input at 3.4 V, Other inputs at Vee or GND 1.2 mA
ei VI-O, f-l MHz 4 pF
Co "0=0, f.l MHz S pF
* All typical values are at Vee = 5 V, TA =25°C.
§ ICC tested with outputs open

~1ExAs
INSTRUMENTS
1<Hl4 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 SN54ACT7881
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGAS004 - AUGUST 1995

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 4)
MIN MAX UNIT
fclock Clock frequency 50 MHz
WRTCLKhigh 7
WRTCLKlow 7
tw Pulse duration RDCLKhigh 7 ns
RDCLKlow 7
DAF high 7
DO-D17 before WRTCLKi 5
WRTEN1, WRTEN2 high before WRTCLKi 5
OE, RDEN1, RDEN2 high before RDCLKi 5
tsu Setup time Reset: RESET low before first WRTCLKi and RDCLKit 6' ns
Define AF/AE: DO-D8 before DAFt 5
Define AF/AE: DAFt before RESETi 6
Define AF/AE (default): DAF high before RESETi 5
DO-D17 after WRTCLKi 0
WRTEN1, WRTEN2 high after WRTCLKi 0
OE, RDEN1, RDEN2 high after RDCLKi 0
th Hold time Reset: RESET low after fourth WRTCLKi and RDCLKit 0' ns
Define AF/AE: DO-D8 after DAFt 1
Define AF/AE: DAF low after RESETi 0
Define AF/AE (default): DAF high after RESETi 0
, These parameters are not production tested on product compliant to MIL-PRF-38535.
t To permit the clock pulse to be utilized for reset purposes

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 50 pF (unless otherwise noted) (see Figures 7 and 8)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
f max WRTCLK or RDCLK 50 MHz
tod 3 13
RDCLKi AnyQ ns
tpd:!:
tod WRTCLKi IR 2 9.5
ns
tpd RDCLKi OR 2 9.5
WRTCLKi 6 19
tpd AF/AE ns
RDCLKi 6 19
tpLH WRTCLKi 6 17
HF ns
tPHL RDCLKi 6 17
tpLH AF/AE 3 17
RESETt ns
tpHL HF 3 19
ten 2 11
OE AnyQ ns
tdis 2 14
:!:Thls parameter IS measured with CL = 30 pF (see Figure 5).

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-65
SN54ACT7881
1024 x 18
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGAS004 - AUGUST 1995

operating characteristics, Vee =5 V, TA =25°C

PARAMETER TEST CONDITIONS
Cpd Power dissipation capacitance per 1K bits CL= 50 pF, f =5 MHz

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
18
VCC~5V
17 _ RL=5OOQ
In . TA=25°C
c ,/"
I 16
CD
E
1= ./
V
15

Ic
0
14 ,r
/
"".

:;CII
8. 13 /!
Ii!
0.
I 12
I
J. 11 I
10
I
o 50 100 150 200 250 300

CL - Load Capacitance - pF

FigureS

~1ExAs
INSTRUMENTS
14-66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ACT7881
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS004 - AUGUST 1995

TYPICAL CHARACTERISTICS
POWER DISSIPATION CAPACITANCE
vs
SUPPLY VOLTAGE
68
u. fl =15 M~z
Q.
TA = 25'C
I
67 CL=50pF
/
8c
~ /'
V
Q. 66
8
c
/'
V
i 65
Q.
/'
~ 64 V
I
a.
I V
V
'C 63
8" V
62
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5

VCC - Supply Voltage - V

Figure 6

calculating power dissipation

The maximum power dissipation (PT) of the SN54ACT7881 can be calculated by:
PT 0= Vcc x [Icc + (N x ~Icc x dc)] + L(Cpd x Vcc 2 x ti) + L(CL x Vcc 2 x foJ
where:
Icc power-down Icc maximum
N number of inputs driven by a TIL device
~Icc increase in supply current
dc duty cycle of inputs at a TIL high level of 3.4 V
Cpd power dissipation capacitance
CL output capacitive load
fi data input frequency
fa data output frequency

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-67
SN54ACT7881
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS004 - AUGUST 1995

PARAMETER MEASUREMENT INFORMATION

'"' -1 y~----- ::
~ tpd~ !.-tpd ~

VLoad
Output Output )t,.-----~ ::H
Under Test

T TOTEM·POLE OUTPUTS

LOAD CIRCUIT

Figure 7. Standard CMOS Outputs

" .. ~.. v \ , .• :---::

-+l it -.l 14-
tPZL PLZ

_--;1'""\1 11
VLoad
Output
Under Test
Output : \1.5 v : p-
- - I - VOL
"'3.5 V

T tPZH ~
1
o

1+
tPHZ
•

-.I 1+
1 j
L 0.3 V

~
--VOH

Output 1.5 V - {" ;3~

LOAD CIRCUIT "'OV

VOLTAGE WAVEFORMS

CLt
PARAMETER IOL IOH VLoad (typical)
tpZH 8mA 8mA OV 20pF
tpZL 8mA 8mA 3.5V 20pF
tpHZ 8mA 8mA 1.5V 20pF
tpLZ 8mA 8mA 1.5V 20 pF
tpo l6mA 8mA 1.5V 20pF
t Includes probe and test·fixture capacitance
Figure 8. 3·State Outputs (Any Q)

~TEXAS
INSTRUMENTS
14-68 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ACT7881
1024 x 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS004- AUGUST 1995

APPLICATION INFORMATION

expanding the SN54ACT7881

The SN54ACT7881 is expandable in both word width and word depth. Word-clepth expansion is accomplished
by connecting the devices in series such that data flows through each device in the chain. Figure 9 shows two
SN54ACT7881 devices configured for word-clepth expansion. The common clock between the devices can be
tied to either the write clock (WRTCll<) of the first device or the read clock (RDCll<) of the last device. The
output-ready flag (OR) of the previous device and the input-ready flag (IR) of the next device maintain data flow
to the last device in the chain whenever space is available.
Figure 10 shows two SN54ACT7881 devices in word-width expansion. Word-width expansion is accomplished
by simply connecting all common control signals between the devices and creating composite input-ready (IR)
and output-ready (OR) signals. The aimost-full/aimost-empty flag (AF/AE) and half-full flag (HF) can be sampled
from anyone device. Word-clepth expansion and word-width expansion can be used together.

CLK

WRTCLK
WRTEN1
SN54ACT7881

WRTCLK
WRTEN1
ROCLK
OR
1 WRTCLK
WRTEN1
SN54ACT7881

ROCLK
ROEN1
ROCLK
ROEN1
WRTEN2 WRTEN2 ROEN1 L WRTEN2 ROEN2 ROEN2
IR IR ROEN2 1 IR OR OR
OE - 5 V OE OE
00-017 DO-017 QO-Q17 00-017 QO-Q17 QO-Q17

Figure 9. Word-Depth Expansion: 20481409818192 Words x 18 Bits, N =2

SN54ACT7881
WRTCLK WRTCLK ROCLK ROCLK
WRTEN WRTEN1 ROEN1 ROEN
WRTEN2 ROEN2
- IR OR
~
018-035
I DO-017 QO-Q17
OE
T I I
OE
Q18-Q35

IR I SN54ACT7881 I OR
'-- WRTCLK ROCLK
- WRTEN1 ROEN1 - r-
WRTEN2 ROEN2
IR OR
OE -
00-017 00-017 QO-Q17
> QO-Q17

. Figure 10. Word-Width Expansion: 1024 Words x 36 Bits

~TEXAS
INSTRUMENTS
POST OFFICE BOX 665303 • DAUAS. TEXAS 75285 14-69
14-70
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING

• Free-Running ClKA and ClKB Can Be • EFB, FFB, AEB, and AFB Flags
Asynchronous or Coincident Synchronized by CLKB
• Two Independent 64 x 36 Clocked FIFOs • Passive Parity Checking on Each Port
Buffering Data In Opposite Directions • Parity Generation Can Be Selected for Each
• Mailbox Bypass Register for Each FIFO Port
• Dynamic Port-B Bus Sizing of 36 Bits (long • low-Power Advanced BiCMOS Technology
Word), 18 Bits (Word), and 9 Bits (Byte) • Supports Clock Frequencies up to 50 MHz
• Selection of Big- or llttle-Endian Format for • Fast Access Times of 12 ns
Word and Byte Bus Sizes
• PCB Package Released as DESC SMD
• Three Modes of Byte-Order Swapping on (Standard Microcircuit Drawing)
Port B 5962-9560901 NXD
• Almost-Full and Almost-Empty Flags • PCB Package Qualified as a Military Plastic
• Microprocessor Interface Control logic Device Per Mll-PRF-38535 (QMl)
• EFA, FFA, AEA, and AFA Flags • Package Options Include Space-Saving
Synchronized by ClKA 12Q.Pln Thin Quad Flat (PCB) and 132-Pin
Ceramic Pin Grid Array (GB) Packages

description
The SN54ABT3614 is a high-speed,low-power BiCMOS bidirectional clocked FIFO memory. It supports clock
frequencies up to 50 MHz and has read-access times as fast as 12 ns. Two independent 64 x 36 dual-port SRAM
FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags (almost full and almost empty) to indicate when a selected number of words is
stored in memory. FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats with a choice
of big- or Iittle-endian configurations. Three modes of byte-order swapping are possible with any bus-size
selection. Communication betWeen each port can bypass the FIFOs via two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port
and can be ignored if not desired. Parity generation can be selected for data read from each port.
The SN54ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free~running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses controlled by a synchronous interface.
The full flag and almost-full flag of a FIFO are tWo-stage synchronized to the port clock that writes data to its
array. The empty flag and almost-empty flag of a FIFO are two-stage synchronized to the port clock that reads
data from its array.
The SN54ABT3614 is characterized for operation from -55°C to 125°C.

Copyright <!:) 1996. Texas Instruments Incorporated

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-71
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

PCB PACKAGE
(TOP VIEW)

A23 90 822
A22 89 821
A21 88 GND
GND 87 820
A20 86 819
A19 85 818
A18 84 817
A17 83 816
A16 82 815
A15 81 814
A14 80 813
A13 79 812
A12 78 811
A11 14 77 810
A10 15 76 GND
GND 16 75 89
A9 17 74 88
A8 73 87
A7 72
71
Vee
Vee 70
86
A6 85
A5 69 84
A4 68 83
A3 67 GND
GND 66 82
A2 65 81
A1 64 80
AO 63 EF8
EFA 62 AE8
AEA 61 AF8

~1ExAs
INSTRUMENTS
14-72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B- AUGUST 1995 - REVISED FEBRUARY 1996

GBPACKAGE
crOP VIEW)

@@@@@@@@@@@@@@ p
@@@@@@@@@@@@@@ N
@@@@@@@@@@@@@@ M
@@@ @@@ L
@@@ @@@ K
@@@ @@@ J
@@@ @@@ H

@@@ @@@ G
@@@ @@@ F

@@@ @@@ E
@@@ @@@ D
@@@@@@@@@@@@@@ c
@@@@@@@@@@@@@@ B
@@@@@@@@@@@@@@ A

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Terminal Assignments
TERMINAL NAME TERMINAL NAME TERMINAL NAME
AOl FFA B07 RST C13 BO
A02 ClKA B08 SWl C14 83
A03 PGA B09 SIZO DOl GND
A04 GND Bl0 PEFB D02 A2
A05 MBF2 Bll W/RB D03 AO
A06 FSO B12 CSB D12 EFB
A07 ODD/EVEN B13 GND D13 GND
A08 SWO B14 Bl D14 B5
A09 SIZl COl Al EOl A5
Al0 GND CO2 EFA E02 A4
All VCC C03 GND E03 A3
A12 ClKB C04 CSA E12 B2
A13 FFB C05 W/RA E13 B4
A14 AEB C06 MBA E14 B6
BOl AEA C07 GND FOl A7
B02 AFA C08 BE F02 VCC
B03 ENA C09 MBFl F03 A6
B04 VCC Cl0 PGB F12 VCC
B05 PEFA Cll ENB F13 B7
B06 FSl C12 AFB F14 B8

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-73
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

Terminal Assignments (Continued)

TERMINAL NAME TERMINAL NAME TERMINAL NAME
G01 A8 L01 A15 N05 Vee
G02 A9 L02 A18 N06 A32
G03 GND L03 A21 N07 A34
G12 810 L12 GND N08 835
G13 GND L13 819 N09 GND
G14 89 L14 818 N10 Vee
HO"I Vee M01 A17 N11 828
H02 A11 M02 GND N12 826
H03 A10 M03 Vee N13 Vee
H12 811 M04 A26 N14 822
H13 Vee M05 A29 001/POl A22
H14 812 M06 A31 002/P02 A24
JOl A12 M07 A35 003/P03 GND
J02 A13 M08 GND 004/P04 A28
J03 A14 M09 832 005/P05 A30
J12 GND M10 827 006/P06 GND
J13 814 Mll 825 007/P07 A33
J14 813 M12 823 008/P08 834
KOl GND M13 821 009/P09 833
K02 A16 M14 820 010/Pl0 831
K03 A19 N01 A20 011/P11 830
K12 817 N02 A23 0121P12 829
K13 816 N03 A25 013/P13 GND
K14 815 N04 A27 014/P14 824

-!!11EXAS
INSTRUMENTS
14-74 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

functional block diagram

CLKA
CSA Port·A
WiRA Control r--------------------------------MBF1
ENA
MBA
Logic
I r-~pa-r~I~--~I----------------,iP~E~FB
.4+1=+=!:l~ __....r-MM~ali111--l+'tr:lGeniCheckJ+1
I ~ I Reglster~
1-=i==~==:1=====::::j..!----- PGB
r-~----------~-~l~~
H+!
I ,- ~=
6 162'
2"a
~~\
I
'61
Ii'. 64x36 ~'C;
1"":, c '"' :ci. ~ I
I
i ll:i!
t-+-+-++I-II+I
SRAM
Cl)
[P ~
()
10 fI)
-
-=&.
T - " .1-+--, 36
Device
ODDl __ Control
i .5
1"-- ~
I
----.!... ""-- I
:::EQ)
!l~ 0

EVEN

II I Write
Pointer
11 Reed
Pointer
I
I I
I

I t of I
FFA
AFA -
!
-----+++++--l----j
....
Status-Flag
Logic
I
I-----------!----I-H-+-II---
EFB
AEB
I FIF01 I
36 L _ _ _ _ _ _~-----------~

FSO------~44~~------~ Programmable-Flag
FS1----~44~~----~ Offset Register
AO-A35-.......- ...... BO-B35
r;~;---- __r 1
1 Status-Flag ~-------t----I-+44-1------ FFB
I + Logic + I AFB

!
I LPointer
I Read JI Write
Pointer
I !I 36

I I
1.-- .....-- r;- .-- I
L...1.
P! i
~
j
162'
II
.. ~
~I-!·
I I -E' i! t.. l..o.. -fi ~!..r.. Z'
!I
:it
L.. 64x36
I _ r" OJ :!! rr SRAM r- iU (I) r"'" II:
&. -S.I
•t";
Q.Q) :::EQ)

I ~" ~~ ~ .....Iio-I-I-~...
~~ L=:_~ _______ ~__~_J
PGA
.---r ~ Mall2
~i-I Parity ....,~iol..~R~e~gl~st~er~J-....
.....- - -..... ---:ttjjj:t'
PEFA --------------<lI------l GeniCheck I CLKB
CSB
MBF2----------~~----------~ WiRB
Port·B ENB
Control BE
SIZO
Logic SIZ1
SWO
SW1

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-75
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

Terminal Functions
PIN NAME 1/0 DESCRIPTION
AO-A35 1/0 Port-A data. The 36-bit bidirectional data port for side A.
0 Port-A almost-empty flag. Programmable almost-empty flag synchronized to ClKA. AEA is low when the number of
AEA
(portA) 36-bit words in FIF02 is less than or equal to value in offset register X.
0 Port-B almost-empty flag. Programmable almost-empty flag synchronized to ClKB. AEB is low when the number of
AEB
(port B) 36-bit words in FIFOI is less than or equal to value in offset register X.
0 Port-A almost-full flag. Programmable almost-full flag synchronized to ClKA. AFA is low when the number of 36-bit
AFA
(portA) empty locations in FIFOI is less than or equal to the value in offset register X.
0 Port-B almost-full flag. Programmable almost-full flag synchronized to ClKB. AFB is low when the number of 36-bit
AFB
(port B) empty locations in FIF02 is less than or equal to the value in offset register X.
BO-B35 1/0 Port-B data. The 36-bit bidirectional data port for side B.
Big-endian select. Selects the bytes on port B used during byte or word data transfer. A Iowan BE selects the most
BE I
significant bytes on BO-B35 for use, and a high selects the least significant bytes.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
ClKA I
or coincident to ClKB. EFA, FFA, AFA, and AEA are synchronized to the low-to-high transition of ClKA.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchrunous
ClKB I or coincident to ClKA. Port-B byte swapping and data port sizing operations are also synchronous to the low-ta-high
transition of ClKB. EFB, FFB, AFB, and AEB are synchronized to the low-to-high transition of ClKB.
Port-A chip select. CSA must be low to enable a low-ta-high transition of ClKA to read or write data on port A. The
CSA I
AO-A3S outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-ta-high transition of ClKB to read or write data on port B. The
CSB I
BO-B35 outputs are in the high-impedance state when CSB is high.
Port-A empty flag. EFA is synchronized to the low-to-high transition of ClKA. When EFA is low, FIF02 is empty and
0 reads from its memory are disabled. Data can be read from FIF02 to the output register when EFA is high. EFA is forced
EFA
(portA) low when the device is reset and is set high by the second low-to-high transition of ClKA after data is loaded into empty
FIF02 memory.
Port-B empty flag. EFB is synchronized to the low-ta-high transition of ClKB. When EFB is low, FIFOI is empty and
0 reads from its memory are disabled. Data can be read from FIFOI to the output register when EFB is high. EFB is forced
EFB
(port B) low when the device is reset and is set high by the second low-to-high transition of ClKB after data is loaded into empty
FIFOI memory.
ENA I Port-A enable. ENA must be high to enable a low-to-high transition of ClKA to read or write dala on port A.
ENB I Port-B enable. ENB must be high to enable a low-to-high transition of ClKB to read or write data on port B.
Port-A full flag. FFA is synchronized to the low-to-high transition of ClKA. When FFA is low, FIFOI is full and writes to
0
FFA its memory are disabled. FFA is forced low when the device is reset and is set high by the second low-la-high transition
(portA)
of ClKA after reset.
Port-B full flag. FFB is synchronized to the low-to-high transition of ClKB. When FFB is low, FIF02 is full and writes to
0
FFB its memory are disabled. FFB is forced low when the device is reset and is set high by the second low-to-high transition
(port B)
of ClKB after reset.
Flag offset selects. The low-to-high transition of RST latches the values of FSO and FS1, which selects one offour preset
FS1, FSO I
values for the almost-empty flag and almost-full flag offset.
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
MBA I AO-A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects
FI F02 output register data for output.
Maill register flag. MBFl is set low by the low-to-high transition of ClKA that writes data to the maill register. Writes
MBFl 0 to the mail 1 register are Inhibited while MBFl is low. MBFl is set high by a low-to-high transition of ClKB when a port-B
read is selected and both SIZI and SIZO are high. MBFl is set high when the device is reset.
Mail2 register flag. MBF2 is set low by the low-ta-high transition of ClKB that writes data to the mail2 register. Writes
MBF2 0 to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-ta-high transition of ClKA when a port-A
read is selected and MBA is high. MBF2 is set high when the device is reset.

~ThXAS
INSTRUMENTS
14-76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B- AUGUST 1995 - REVISED FEBRUARY 1996

Terminal Functions (Continued)

PIN NAME 1/0 DESCRIPTION
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/
I ODD/EVEN is low. ODDIEVEN also selects the type of parity generated for each port if parity generation is enabled
EVEN
for a read operation.
Port-A parity-error flag. When any byte applied to terminals AO-A35 fails parity, PEFA is low. 8ytes are organized as
AO-A8, A9-A17, A18-A26, and A27 -A35, with the most significant bit of each byte serving as the parity bit. The
PEFA
a type of parity checked is determined by the state of ODD/EVEN.
(portA) The parity trees used to check the AO- A35 inputs are shared by the mail2 register to generate parity if parity generation
is selected by PGA; therefore, if a mail2 read with parity generation is set up by having WiRA low, M8A high, and PGA
high, the PEFA flag is forced high regardless of the state of the AO-A35 inputs.
Port-8 parity-error flag. When any valid byte applied toterminals 80-835 fails parity, PEF8 is low. 8ytes are organized
as 80-88, 89-817, 818-826, and 827 -835, with the most significant bit of each byte serving as the parity bit. A
byte is valid when it is used by the bus size selected for port 8. The type of parity checked is determined by the state
PEF8
a of ODD/EVEN.
(port 8)
The parity trees used to check the BO - B35 inputs are shared by the mail 1 register to generate parity if parity generation
is selected by PGB; therefore, if a mail 1 read with parity generation is set up by having WiR8 low, Sill and SilO high,
and PGB high, the PEF8 flag is forced high regardless of the state of the BO- B35 inputs.
Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity generated
PGA I is selected by the state of ODD/EVEN. Bytes are organized as AO-A8, A9-A17, A18-A26, and A27-A35. The
generated parity bits are output in the most significant bit of each byte.
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated
PGB I is selected by the state of ODD/EVEN. Bytes are organized as BO-B8, B9-817, 818-826, and 827-B35. The
generated parity bits are output in the most significant bit of each byte.
Reset. To reset the device, four low-to-high transitions of ClKA and four low-to-high transitions of ClKB must occur
while RST is low. This sets AFA, AFB, MBF1, and MBF2 high and EFA, EFB, AEA, AEB, FFA, and FF8 low. The
RST I
low-to-high transition of RST latches the status of the FSl and FSO inputs to select almost-full flag and almost-empty
flag offset.
Port-B bus-size selects. The low-to-high transition of ClKB latches the states of SilO, Sill, and 8E, and the following
I
SilO, Sill low-to-high transition of ClKB implements the latched states as a port-B bus size. Port-B bus sizes can be long word,
(port B)
word, or byte. A high on both SilO and Sill accesses the mailbox registers for a port-8 36-bit write or read.
Port-8 byte-swap selects. At the beginning of each long word transfer, one of four modes of byte-order swapping is
I
SWO,SWI selected by SWO and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. 8yte-order
(port B)
swapping is possible with any bus-size selection.
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
W/RA I
low-to-high transition of ClKA. The AO-A35 outputs are in the high-impedance state when WiRA is high.
Port-8 write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
WiR8 I
low-to-high transition of ClKB. The 80-835 outputs are in the high-impedance state when WiRB is high.

detailed description
reset
The SN54ABT3614 is reset by taking the reset (RST) input low for at least four port-A clock (ClKA) and four
port-B clock (ClKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the
empty flags (EFA, EFB) low, the almost-empty flags (AEA, AEB) low, and the almost-full flags (AFA, AFB) high.
A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high
transitions of ClKA and FFB is set high after two low-to-high transitions of ClKB. The device must be reset after
power up before data is written to its memory.
A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected
by the flag-select (FSQ, FS1) inputs. The values that can be loaded into the register are shown in Table 1.

~ThXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-77
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

reset (continued)

Table 1. Flag Programming

ALMOST-FULL AND
FS1 FSO RST ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H H l' 16
H L l' 12
L H l' 8
L L l' 4

FIFO write/read operation

The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (WiRA). The AO-A35 outputs are in the high-impedance state when either CSA or WiRA is
high. The AO-A35 outputs are active when both CSA and WiRA are low. Data is loaded into FIF01 from the
AO-A35 inputs on a low-to-high transition of ClKA when CSA is low, WiRA is high, ENA is high, MBA is low,
and FFA is high. Data is read from FIF02 to the AO-A35 outputs by a low-to-high transition of ClKA when CSA
is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2).

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA AO-A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L l' In high-impedance state FIF01 write
L H H H l' In high-impedance state Mail1 write
L L L L X Active, FIF02 output register None
L L H L l' Active, FI F02 output register FIF02 read
L L L H X Active, mail2 register None
L L H H l' Active, mail2 register Mail2 read (set MBF2 high)

The state of the port-B data (BO-B35) outputs is controlled by the port-B chip select (CSB) and the port-B
write/read select (W/RB). The BO-B35 outputs are in the high-impedance state when either CSB or W/RB is
high. The BO-B35 outputs are active when both CSB and W/RB are low. Data is loaded into FIF02 from the
BO-B35 inputs on a low-to-high transition of ClKB when CSB is low, W/RB is high, ENB is high, FFB is high,
and either SilO or SIl1 is low. Data is read from FIF01 to the BO-B35 outputs by a low-to-high transition of
ClKB when CSB is low, W/RB is low, ENB is high, EFB is high, and either SilO or SIl1 is low (see Table 3).
The setup- and hold-time constraints to the port clocks for the port chip selects (CSA, CSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port chip select and write/read select
can change states during the setup- and hold-time window of the cycle.

~1ExAs
INSTRUMENTS
14-78 POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS30BB - AUGUST 1995 - REVISED FEBRUARY 1996

FIFO wrlterlread operation (continued)

Table 3. Port·B Enable Function Table

CSB W/RB ENB SIZ1,SIZO ClKB BO-B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H One, both low i In high-impedance state FIF02write
L H H Both high i In high-impedance state Mail2write
L L L One, both low X Active, FIF01 output register None
L L H One, both low i Active, FIF01 output register FIF01 read
L L L Both high X Active, mail1 register None
L L H Both high i Active, mail1 register Mail1 read (set MBF1 high)

synchronized FIFO flags

Each FI FO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability
by reducing the probability of metastable events on the output when ClKA and ClKB operate asynchronously
to one another (see the application report Metastability Performance of Clocked FIFOs in the 1996
High-Performance FIFO Memories Data Book, literature number SCAD003C). EFA, AEA, FFA, and AFA are
synchronized to ClKA. EFB, AEB, FFB, and AFB are synchronized to ClKS. Tables 4 and 5 show the
relationship of each port flag to FIF01 and FIF02.

Table 4. FIF01 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF 36-BIT TOClKB TOClKA
WORDS IN FIF01t
EFB AEB AFA FFA
0 L L H H
1 to X H L H H
(X + 1) to [64 - (X + 1)1 H H H H
(64- X) to 63 H H L H
64 H H L L
t XIS the value In the almost-empty flag and almost-full flag offset register.

Table 5. FIF02 Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF 36-BIT TOClKA TOClKB
WORDS IN FIF02t
EFA AEA AFB FFB
0 L L H H
1 toX H L H H
(X + 1) to [64 - (X + 1)] H H H H
(64-X)to 63 H H L H
64 H H L L
t X IS the value in the almost-empty flag and almost-full flag offset register.

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-79
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

empty flags (EFA, EFB)

The empty flag of a FIFO is synchronized to the port clock that reads data from its array. When the empty flag
is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and
attempted FIFO reads are ignored. When reading FIF01 with a byte or word size on port B, EFB is set low when
the fourth byte or second word of the last long word is read.
The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state
machine that controls an empty flag monitors a write-pointer and rea,d-pointer comparator that indicates when
the FIFO SRAM status is empty, empty+ 1, or empty+2. A word written to a FIFO can be read to the FIFO output
register in a minimum of three cycles of the empty flag synchronizing clock; therefore, an empty flag is low if
a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that
reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is
set high by the second low-to-high transition of the synchronizing clock and the new data word can be read to
the FIFO output register in the following cycle.
A low-to-high transition on an empty-flag synchronizing clock begins the first synchronization cycle of a write
if the clock transition occurs at time tsk1' or greater, after the write. Otherwise, the subsequent clock cycle can
be the first synchronization cycle (see Figures 13 and 14).
full flags (FFA, FFB)
The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is high,
a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is
low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a full
flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full,
full-1, or full-2. From the time a word is read from a FIFO, the previous memory location is ready to be written
in a minimum ofthree cycles of the full-flag synchronizing clock; therefore, a full flag is low if less than two cycles
of the full-flag synchronizing clock have elapsed since the next memory write location has been read. The
second low-to-high transition on the full-flag synchronizing clock after the read sets the full flag high and data
can be written in the following clock cycle.
A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the
clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the
first synchronization cycle (see Figures 15 and 16).
almost-empty flags (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state
machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty state is
defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of
four preset values during a device reset (see reset). An almost-empty flag is low when the FIFO contains X or
less long words in memory and is high when the FIFO contains (X + 1) or more long words.
Two low-to-high transitions of the almost-empty flag synchronizing clock are requiretl after a FIFO write for the
almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1)
or more long words remains low if two cycles of the synchronizing clock have not elapsed since the write that
filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of
the synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an
almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater,
after the write that fills the FIFO to (X + 1) long words. Otherwise, the subsequent synchronizing clock cycle can
be the first synchronization cycle (see Figures 17 and 18).

~TEXAS
INSTRUMENTS
14-80 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

almost-full flags (AFA, AFB)

The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine
that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the value of
the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during
a device reset (see rese~. An almost-full flag is low when the FIFO contains (64 - X) or more long words in
memory and is high when the FIFO contains [64 - (X + 1)] or less long words.
Two low-to-high transitions of the almost-full-flag synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [64 - (X + 1)]
or less words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced
the number of long words in memory to [64 - (X + 1)]. An almost-full flag is set high by the second low-to-high
transition of the synchronizing clock after the FIFO read that reduces the number of long words in memory to
[64 - (X + 1)]. A low-to-high transition of an almost-full-flag synchronizing clock begins the first synchronization
cycle if it occurs at time tsk2, or greater, after the read that reduces the number of long words in memory to
[64 - (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see
Figures 19 and 20).
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port data transfer operation. A low-to-high transition on elKA writes AO-A35 data to the mail1 register
when a port-A write is selected by eSA, WiRA, and ENA, and MBA is high. A low-to-high transition on elKB
writes BO-B35 data to the mail2 register when a port-B write is selected by eSB, W/RB, and ENB and both SilO
and SIl1 are high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted
writes to a mail register are ignored while the mail flag is low.
When the port-A data outputs (AO-A35) are active, the data on the bus comes from the FIF02 output register
when MBA is low and from the mail2 register when MBA is high. When the port-B data outputs (BO-B35) are
active, the data on the bus comes from the FIF01 output register when either one or both SIl1and SilO are
low and from the mail2 register when both SIl1 and SilO are high. The mail1 register flag (MBF1) is set high
by a rising elKB edge when a port-B read is selected by eSB, W/RB, and ENB and both port-B bus-size select
(Sll1 and SilO) inputs are high. The mail2 register flag (MBF2) is set high by a rising elKA edge when a port-A
read is selected by eSA, W/RA, and ENA and MBA is high. The data in the mail register remains intact after
it is read and changes only when new data is written to the register.
dynamic bus sizing
The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FIF01
or written to FIF02. Word- and byte-size bus selections can utilize the most significant bytes of the bus (big
endian) or least significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and
synchronous to elKB to communicate with peripherals of various bus widths.
The levels applied to SilO and SIl1 and the big-end ian select (BE) input are stored on each elKB low-to-high
transition. The stored port-B bus-size selection is implemented by the next rising edge on elKB according to
Figure 1.
Only 36-bit long-word data is written to or read from the two FIFO memories on the SN54ABT3614.
Bus-matching operations are done after data is read from the FIF01 RAM and before data is written to the FI F02
RAM. Port-B bus sizing does not apply to mail-register operations.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-81
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

dynamic bus sizing (continued)

A35 A27 A26 A18 A17 A9 A8 AO

BYTE ORDER ON PORT A: [:] 8 0 0 Write to FIF01/Read From FIF02

B35 B27 B26 B18 B17 B9 B8 BO

BE

X
SIZ1

L
SIZO

L
[:] 8 0 8 Read From FIF01IWrite to FIF02

(a) LONG WORD SIZE

B35 B27 B26 B18 B17 B9 B8 BO

BE

L
SIZ1

L
SIZO

H
[:] 8 ~ ~ 1st:ReadFromFIF01lWrltetoFIF02

o 8
B35 B27 B26 B18 B17

~
B9

(b) WORD SIZE - BIG ENDIAN

B8

~
BO

2nd: Read From FIF01IWrite to FIF02

8 8
B35 B27 B26 B18 B17 B9 B8 BO

~ ~
BE SIZ1 SIZO
1st: Read From FIF01IWrite to FIF02
H L H

B35 B27 B26 B18 B17 B9 B8 BO

~ ~ 0 8 2nd: Read From FIF01/Write to FIF02

(e) WORD SIZE - LITTLE ENDIAN

B35 B27 B26 B18 B17 B9 B8 BO

BE SIZ1 SIZO [:] ~ ~ ~ 1st: Read From FIF01lWrlte to FIF02

L H L
B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ ~ 2nd: Read From FIF01/Wrlte to FIF02

8
B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ 3rd: Read From FIF01lWrite to FIF02

o
B35 B27 B26

~
B18 B17

~
B9

(d) BYTE SIZE - BIG ENDIAN

B8

~
BO

4th: Read From FIF01/Wrlte to FIF02

Figure 1. Dynamic Bus Sizing

~TEXAS
INSTRUMENTS
14-82 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

dynamic bus sizing (continued)

B35 B27 B26 B18 B17 B9 B8 BO

BE

H
SlZ1

H
SIZO

L
~ ~ ~ 0 1st: Read From FIF01JWrite to FIF02

B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ 0 2nd: Read From FIF01JWrite to FIF02

B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ 0 3rd: Read From FIF01/Writeto FIF02

0
B35 B27 B26 B18 B17 B9 B8 BO

~ ~ ~ 4th: Read From FIF01JWrite to FIF02

(e) BYTE SIZE - LITTLE ENDIAN

Figure 1. Dynamic Bus Sizing (continued)

bus-matching FIF01 reads

Data is read from the FIF01 RAM in 36-bit long-word increments. If a long-word bus size is implemented, the
entire long word immediately shifts to the FIF01 output register. If byte or word size is implemented on port 8,
only the first one or two bytes appear on the selected portion of the FIF01 output register with the rest of the
long word stored in auxiliary registers. In this case, subsequent FIF01 reads with the same bus-size
implementation output the rest of the long word to the FIF01 output register in the order shown by Figure 1.
Each FIF01 read with a new bus-size implementation automatically unloads data from the FIF01 RAM to its
output register and auxiliary registers. Therefore, implementing a new port-8 bus size and performing a FIF01
read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread
long-word data.
When reading data from FIF01 in byte or word format, the unused 80-835 outputs remain inactive but static
with the unused FIF01 output register bits holding the last data value to decrease power consumption.
bus-matching FIF02 writes
Data is written to the FIF02 RAM in 36-bit long-word increments. FIF02 writes, with a long-word bus size,
immediately store each long word in FIF02 RAM. Data written to FIF02 with a byte or word bus size stores the
initial bytes or words in auxiliary registers. The elKS rising edge that writes the fourth byte or the second word
of long word to FIF02 also stores the entire long word in FIF02 RAM. The bytes are arranged in the manner
shown in Figure 1.
Each FIF02 write with a new bus-size implementation resets the state machine that controls the data flow from
the auxiliary registers to the FIF02 RAM. Therefore, implementing a new bus size and performing a FIF02 write
before bytes or words stored in the auxiliary registers have been loaded to FIF02 RAM results in a loss of data.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-83
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

port-S mali-register access

In addition to selecting port-B bus sizes for FIFO reads and writes, the port-B bus size select (SIZO, SIZ1) inputs
also access the mail registers. When both SIZO and SIZ1 are high, the mail1 register is accessed for a port-B
long-word read and the mail2 register is accessed for a port-B long-word write. The mail register is accessed
immediately and any bus-sizing operation that can be underway is unaffected by the the mail-register access.
After the mail-register access is complete, the previous FIFO access can resume in the next elKB cycle. The
logic diagram in Figure 2 shows that the previous bus-size selection is preserved when the mail registers are
accessed from port B. A port-B bus size is implemented on each rising elKB edge according to the states of
SIZO_O, SIZ1_0, and BE_O.

elKB

MUX

IrD '--
~1

'--- 1
SIZO_Q
0 Q SIZ1_Q
SIZO BE_Q
SIZl "1
BE

Figure 2. logic Diagram for SIZO, SIZ1, and BE Register

byte swapping
The byte-order arrangement of data read from FIF01 or data written to FIF02 can be changed synchronous
to the rising edge of elKB. Byte-order swapping is not available for mail-register data. Four modes of byte-order
swapping (including no swap) can be done with any data-port-size selection. The order of the bytes are
rearranged within the long word, but the bit order within the bytes remains constant.
Byte arrangement is chosen by the port-B swap select (SWO, SW1) inputs on a elKB rising edge that reads
a new long word from FIF01 or writes a new long word to FIF02. The byte order chosen on the first byte or first
word of a new long-word read from FIF01 or written to FiF02 is maintained until the entire long word is
transferred, regardless of the SWO and SW1 states during subsequent writes or reads. Figure 3 is an example
of the byte-order swapping available for long words. Performing a byte swap and bus size simultaneously for
a FIF01 read rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 1.
Simultaneous bus-sizing and byte-swapping operations for FIF02 writes load the data according to Figure 1,
then swap the bytes as shown in Figure 3 when the long word is loaded to FIF02 RAM.

~1ExAs
INSTRUMENTS
14-84 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

byte swapping (continued)

A35 A27 A26 A18 A17 A9 A8 AO

~~~~
~

B35 B27 B26 B18 B17 B9 B8 BO

(a) NO SWAP

A35 A27 A26 A18 A17 A9 A8 AO

ffiL H

B35 B27 B26 B18 B17 B9 B8 BO

(b) BYTE SWAP

A35 A27 A26 A18 A17 A9 A8 AO

~ H L

B35 B27 B26 B18 B17 B9 B8 BO

(e) WORD SWAP

A35 A27 A26 A18 A17 A9 A8 AO

~
~

B35 B27 B26 B18 B17 B9 B8 BO

(d) BYTE-WORD SWAP

Figure 3. Byte Swapping (Long-Word Size Example)

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-85
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B-AUGUST 1995- REVISED FEBRUARY 1996

parity checking
The port-A data inputs (AO-A35) and port-8 data inputs (80-835) each have four parity trees to check the parity
of incoming (or outgoing) data. A parity failure on one or more bytes of the port-A data bus is reported by a low
level on the port-A parity-error flag (PEFA). A parity failure on one or more bytes of the port-8 data inputs that
are valid for the bus-size implementation is reported by a low level on the port-8 parity-error flag (PEF8). Odd-
or even-parity checking can be selected, and the parity-error flags can be ignored if this feature is not desired.
Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select
input. A parity error on one or more valid bytes of a port is reported by a low level on the corresponding port
parity-error flag (PEFA, PEF8) output. Port-A bytes are arranged as AO-AS, A9-A17, A1S-A26, and
A27-A35. Port-8 bytes are arranged as 80-8S, 89-817, 81S-826, and 827-835, and its valid bytes are
those used in a port-8 bus-size implementation. When odd/even parity is selected, a port parity-error flag
(PEFA, PEFB) is low if any valid byte on the port has an odd/even number of low levels applied to the bits.
The four parity trees used to check the AO-A35 inputs are shared by the mail2 register when parity generation
is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is
selected with CSA low, ENA high, WiRA low, MBA high, and PGA high, the port-A parity-error flag (PEFA) is
held high regardless of the levels applied to the AO-A35 inputs. Likewise, the parity trees used to check
the BO-B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads
(PGB = high). When a port-B read from the mail1 register with parity generation is selected with CSB low, ENB
high, and WiRB low, both SIZO and SIZ1 high, and PG8 high, the port-B parity-error flag (PEFB) is held high
regardless of the levels applied to the 80-835 inputs.
parity generation
A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the
SN54ABT3614 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged
as AO-AS, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte used as the parity bit.
Port-B bytes are arranged as BO-B8, 89-817, 818-B26, and 827 -835, with the most significant bit of each
byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte
regardless of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity
generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on
the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the most
significant bits of each byte as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the
output register; therefore, the port-A parity-generate select (PGA) and odd/even parity select (ODD/EVEN)
have setup- and hold-time constraints to the port-A clock (ClKA) and the port-8 parity generate select (PGB)
and ODD/EVEN have setup and hold-time constraints to the port-B clock (ClKB). These timing constraints only
apply for a rising clock edge used to read a new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port-B bus (BO- B35) to check parity and
the circuit used to generate parity for the mail2 data is shared by the port-A bus (AO-A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in a mail register when the port chip
select (CSA. CSB) is low, enable (ENA, ENB) is high, writelread select (W/RA, W/RB) input is low, the mail
register is selected (M8A is high for port A; both SIZO and SIZ1 are high for port B), and port parity-generate
select (PGA, PG8) is high. Generating parity for mail register data does not change the contents of the register.

~TEXAS
INSTRUMENTS
14-86 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B- AUGUST 1995 - REVISED FEBRUARY 1996

ClKA
I.-- Ih(RS)
ClKB
I

RST----~
-.I If- Isu(RS)
Ii
I
I
Isu(FS) ~ Ih(FS)
ill
I I
II
I I I I I I I
FS1, FSO

I Ipd(C-FF) J.-±----+! Ipd(C-FF) ~

FFA ~~~ I ,,----
EFA ~\\\\\'~~~
..,. I I I
I
I
I Ipd(C-FF) ~ Ipd(C-FF)~
FFB~~~~ y--
I Ipd(C-~F) ~ ~
EFB~~
Ipd(R-F) \4-----t! I I I
~~F~ 2IlZZ2lZZZiJ I i iti
Ipd(C-AE) I" I
AEA~~
Ipd(C-AF) I" I tI
AFA7~A
Ipd(C-AE) It .1
AEB~~~
Ipd(C-AF) ~ tI

Figure 4. Device Reset Loading the X Register With the Value of Eight

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-87
SN54ABT3614
64 x 36x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1998

14
~ tw(CLKH) +
te

tw(CLKL) ~
-I

CLKA } ~ r \ I
I
\ ( '--
I I
I I I
FFA High
II" I I
tBu(EN) -:'" th(EN) I I
I
~I" 1/
CSA
tBu(EN)
I-
-I" ~ th(EN)
I
I
I
I
W/RA :2222222'7L7.L7I
tBu(EN) I"
IF
-I"~ th(EN)
I
I
I
I %\\Y\\\'
I
MBA I I I

: : ~
0001 ~
EVEN
tpd(D.PE) ~ tpd(D-PE) ~
PEFA

tWritten to FIF01
Figure 5. Port·A Wrlte·Cycle Timing for FIF01

-!!1TEXAS
INSTRUMENTS
14-88 POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS30BB - AUGUST 1995 - REVISED FEBRUARY 1996

elKB _ _.....( ,'----..Jf( ' ...._ _..J/ ' ....___1

I I I
High I I
I I I
I tsu(EN)~ I
I ~,---+I _ _ _ _ _ _ _ _ _ _ _ _ _ _~:;----
I tSU(EN)R I
WiRB '/77//?////////////1

000/0<v
EVEN~--------------------~------------~----------------------_____

t SIZO =Hand SIZ1 =H writes data to the mail2 register.

DATA SWAP TABLE FOR lONG-WORD WRITES TO FIF02
SWAP MODE DATA WRITTEN TO FIF02 DATA READ FROM FIF02
SW1 SWO B35-B27 B26-B18 B17-B9 B8-BO A35-A27 A26-A18 A17-A9 A8-AO
L L A B C D A B C D
L H D C B A A B C D
H L C D A B A B C D
H H B A D C A B C D

Figure 6. Port-B Long-Word Write-Cycle Timing for FIF02

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-89
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

ClKB ,'-_ _ _(
,
, (
,
,'-_ _ _(
, '-
, , ,
High , , ,
, , ,
Isu(EN) ~, ~ Ih(EN)
I

WiRB
* ~~J-j+-! --------!i....J)
ENB

Ih(SZ)
SIZ1, SIZO ~ (0 1) (0 1 Nol (1 1)1
,L _~~.i Ih(D)
Isu(D) . ..
Little { BO-B17
Endlan
Isu(D) ~ ~r ~ ~ VXXXXXXXXJ
End~~~ {
B18-B35 ~""'-.L.r-~ ~~
ODD/EVEN
__
me
~'------.----I-P-d(-C--P-E-) 1""1- - _ - - ~I-Pd-(-D--P-E)---.------
PEFB.Valld~
t SIZO = Hand SIZ1 = H writes data to the mail2 register.
NOTE A: PEF8 indicates parity error for the following bytes: 835-827 and 826-818 for big-endian bus, and 817-89 and 88-80 for little-
end ian bus.

DATA SWAP TABLE FOR WORD WRITES TO FIF02

DATA WRITTEN TO FIF02
SWAP MODE WRITE DATA READ FROM FIF02
BIG ENDIAN LITTLE ENDIAN
NO.
SW1 SWO B35-B27 B28-B18 B17-B9 B8-BO A35-A27 A28-A18 A17-A9 A8-AO
1 A 8 C D
L L A 8 C D
2 C D A 8
1 D C 8 A
L H A 8 C D
2 8 A D C
1 C D A 8
H L A 8 C D
2 A 8 C D
1 8 A D C
H H A 8 C D
2 D C 8 A

Figure 7. Port·B Word Write-Cycle Timing for FIF02

~TEXAS
INSTRUMENTS
14-90 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

elKB
I I
I I
High I I
I I
tsu(EN) I+---'i It-tI th(EN)

I
III
I tSU(EN)H
'--~I------------------------~.!
1
i
1-

W/RB VlT/C77/;Zf' I I
I tsU(EN)~_ ~ .r~
ENB?ZZZ2';Czzzzzz. I '<200&
I tsu(SW) ~ th(EN)
~~~
S W 1 , S W O .
tsu~SZinOit.h(SZ)
II~
I I
~ _ _
BE
tsu(SZ) I th(SZ) I I I
I tsu(SZ) th(SZ)
SIZ1, SIZO (1,0) I (1,0) (1,0) 1[;:,02!):XZ;~~=:::>
tsu(o} ~ Not (1, 1)t
little {BO-B8 _ _ _ _
Endlan I
Big
Endian
~B27-B35 _
tsu(o} ~11.1
_ _ _
.
I I I
ODD/EVEN
~----~:~:--~:--~:
H -~ tpd(C-PE) I4-tI tpd(O-PE) tpd(D-PE) tpd(O-PE)
PEFB ~~QQ~~82~~~~~82~~~~~22~~~~algld~~22~~~~a~lid[)
Valid
t SIZO = Hand SIZI = H writes data to the mail2 register.
NOTE A: PEF8 indicates parity error for the following bytes: 835-827 for big-endian bus and 817-89 for little-end ian bus.

Figure 8. Port-B Byte Write-Cycle Timing for FIF02

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-91
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

DATA SWAP TABLE FOR BYTE WRITES TO FIF02

DATA WRITTEN
TOFIF02
SWAP MODE WRITE DATA READ FROM FIF02
BIG LITTLE
NO.
ENDIAN ENDIAN
SW1 SWO B35-B27 B8-BO A35-A27 A26-A18 A1'I-AS A8-AO
1 A 0
2 B C
L L
B A B C 0
3 C
4 0 A
1 0 A
2 C B
L H A B C 0
3 B C
4 A 0
1 C B
2 0 A
H L A B C 0
3 A 0
4 B C
1 B C
2 A 0
H H A B C 0
3 0 A
4 C B

Figure 8. Port-B Byte Write-Cycle Timing for FIF02 (continued)

~1ExAs
INSTRUMENTS
14-92 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

elKB ---.Jf \1----1( \ ~ \ I '--

I I I
EFB High I I I
I I I
I I I
I I : (
I I
I : ~""2"'2""2""2""2"";

t SIZO =Hand SIZ1 =H selects the mail1 register for output on BO-B35.
:j: Data read from FIF01

DATA SWAP TABLE FOR lONG-WORD READS FROM FIF01

DATA WRITTEN TO FIF01 SWAP MODE DATA READ FROM FIF01
A35-A27 A26-A18 A17-A9 A8-AO SW1 SWO 635-B27 B26-B18 B17-B9 B8-BO
A B C D L l A B C D
A B C D L H D C B A
A B C D H L C D A B
A B C D H H B A D C

Figure 9. Port-B Long-Word Read-Cycle Timing for FIF01

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-93
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

''---~I
elKB _ __
''-----.IffI ''-_ _..J/
EFB High

lltlle{
Endlan:!: BO-B17------~L~~:!!!!~~

Endl:~i{B18-B35------~(C:j~~~!E:J ---~=~-- '--_"';';;=~_.....I

t SIZO = Hand SIZl = H selects the maill register for output on 80-835.
:I: Unused word 80-817 or 818-835 holds last FIFOl output register data for word-size reads.

DATA SWAP TABLE FOR WORD READS FROM FIF01

DATA READ FROM FIFOl
DATA WRITTEN TO FIFOl SWAP MODE READ
BIGENDIAN liTTLE ENDiAN
NO.
A35-A27 A26-A18 A17-A9 A8-AO SW1 SWO B35-B27 B26-B18 B17-B9 B8-BO
1 A 8 C D
A 8 C D L· L
2 C D A 8

A 8 C D
1 D C 8 A
L H
2 8 A D C
1 C D A 8
A 8 C D H L
2 A 8 C D
1 8 A D C
A 8 C D H H
2 D C 8 A

Figure 10. Port-B Word Read-Cycle Timing for FIF01

~1ExAS
INSTRUMENTS
14-94 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

ClKB

EFB High 1

1
1
CSB 'I !
l' 1 I '1
W/RB ~ i l I lI C!ZZ7b
1 ' I I
Isu(EN) ~ Ih(EN)

ENB
I
vzz;,zzzz(4 i ~ I ~ i ~ : ~~
I I
No qmzz
SW1,SWO

BEls ~
Isu(SZ) ~ th(SZ) I I I I I
SIZ1, SIZO +1(1,1!f @S888
Not (1" 1)t I Not(1,1)t I Not(1,1)t 1 1 I

PGB,
ODD/EVEN",~~~~~~~.

:~ la ~ ~~ la ~ ~ h
BO-B8
ten I+--.i
~ ,
Pr~vlous Dal~
~ la -+I
* R~ 1
I
* :1_ * 1_ *
~
1 I
la
R,ead 2

14- la ~
1
Read 3
I
I+-
la ---..!

1
Idls
Read 4
I
Idls ~
1
'J--
B27-B35 (*
Previous Dala
I+-
Read 1
Is
* Read 2 * Read 3
la - '
X Read 4 'J--
t SIZO = Hand SIZ1 = H selects the mail1 register for output on 80-835.
NOTE A: Unused bytes hold last FIF01 output register data for byte-size reads,

Figure 11. Port-B Byte Read-Cycle Timing for FIF01

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-95
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1998

DATA SWAP TABLE FOR BYTE READS FROM FIF01

DATA READ
FROMFIF01
DATA WRITTEN TO FIF01 SWAP MODE READ
BIG LITTLE
NO.
ENDIAN ENDIAN
A35-A27 A26-A18 A17-A9 A8-AO SW1 SWO B35-B27 B8-BO
1 A D
2 B C
A B C D L L
B
3 C
4 D A
1 D A
2 C B
A B C D L H
3 B C
4 A D
.
/

1 C B
2 D A
A B C D H L
3 A D
4 B C
1 B C
2 A D
A B C D H H
3 D A
4 C B

Figure 11. Port-B Byte Read-Cycle Timing for FIF01 (continued)

~. ~ ~
i+- tw(CLKH) - - tw(CLKL) ...I
CLKA )I {. ,,---~\ ( \ ,,...--....'---
I I I
I I I
High I I I
I I I
~ II iI II
I I
WiRA ~"'~~~~~~~~ i I I pzmzzz
_ _-+-1"""'"'\ I I I I
MBA I), I I I I
I I ~SU(EN~I. tau(EN) I tSU(EN) I I
I I ~ ~I
I I I --.r!+-- th(EN) I --tI I+- th(EN) I --tI !.- th(EN) -

ENA WLT{P4R> I~ I ts\\~ tvzzmz

tpd(M-DV) I I" ~I !.- Is --..l I No !.....J Id
AO-A35
ten i----.i I
. ~
I
prevlyus Data
I
* wif:
I+- Is -.I
X
Operation

W2t
r -j
j
Is

ODD/:!~~~~~~
t Read from FIF02
Figure 12. Port-A Read-Cycle Timing for FIF02

~1ExAs
INSTRUMENTS
14-96 POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

ClKA

CSA low

W/RA High I
tSU(EN):-=:l 14- th(E~)
MBA ~ ~,."T'"r~'
~:;:""'Z""'2""7Z"7Z"7Z7Z7Z7"Z7"z"?":;:r:;:r:;::>"";'//."''/''"''/''"'Z"''7Z"7/j"727Z727"z''?"zrzr:;:rz:>"";1/"''/''"''/''"'2''"'2"''72"7{;727{;7":;:7"Z7''';
ENA~ ~~
~t.h.(E~N~)~_______________________________________________
_______

I I
FFA High I I
tsu(O) I'-:!! I+- I

AO-A35
tsk1t I~ ~I- te ---+I
tw(ClKH) b~ tw(ClKl)
ClKB 1 2

EFB FIF01 Empty

CSB low
I
W/RB ____________________________________
low I
~I-----------------------------

I
SIZ1, SIZO low I
ts EN :::;i !+- th(EN)
ENB VZ/Z22ZZ2ZZZZ////ZZZZZZlZ/)i)71 ~~~
14- la --.I
BO-B35 ~.-------W~1----

t tsk1 is the minimum time between a rising ClKA edge and a rising ClKS edge for EFS to transition high in the next ClKS cycle. Ifthetime between
the rising ClKA edge and rising ClKS edge is less than tsk1, the transition of EFS high may occur one ClKS cycle later than shown.
NOTE A: Port-S size of long word is selected for FIF01 read by SIZ1 =l, SIZO = L. If port-S size is word or byte, EFS is set low by the last word
or byte read from FIF01, respectively.

Figure 13. EFB-Flag Timing and First Data Read When FIF01 Is Empty

~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-97
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

ClKB
I
CSB low I
I
I
W/RB High I
Isu(EN} ~I
I -+j 14- th(EN}
SIZ1. SIZO ~'S~\:~S:~S:"o:"S:"o:"s:-d~1 (2I!2?ZZZ2?ZV?T/l//Z7?//lZ?/ZZZZZ?ZZZ2ZZlfl/lZ2
tsu(EN) 1+-+1 t Ih(EN}

ENB RZZV19 ~\"'::-"':"';::-"':"';:~"T:-...:..,;::\...,),--------------------

I I
FFB High I I
tsU(D} ....1 I
I ~ 14- th(D}
BO-B35

I t 14 ' - Ie ~
skl ~ I~ tw(ClKl}
tw(ClKH} ~ 1

ClKA

EFA _ _ _ ~FI~FO~2~E~m~p~~~ ____ IP_d_(~_E_F_}~14_-_-_-_-~) ~!4====~\~tP_d(_~_E_F_}

__ _ _ _ _ _ _ _ _ _ __

CSA~lO~W~ _______________________ I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ ~1

W/RA low I
~~---------------------~I-------------------
I
MBA low I
tsu(EN} ~I 14- Ih(EN}
~
ENA VZ/l/ZZZZ2ZlZZZZllZ/2ZZTJG »~
14- ta -tI
AO-A35 ~.....-------""":'::W~l--------

t tskl is the minimum time between a rising ClKB edge and a rising ClKA edge for EFA to transition high in the next ClKA cycle. lithe time between
the rising ClKB edge and rising CLKA edge is less than tskl. the transition of EFA high may occur one CLKA cycle later than shown.
NOTE A: Port-B size of long word is selected for FIF02 wr~e by SIZl =l. SIZO =L. If port-B size is word or byte. tsk1 is referenced 10 the rising
ClKB edge that writes the last word or byte of the long word. respectively.

Figure 14. EFA·Flag Timing and First Data Read When FIF02 Is Empty

~TEXAS
INSTRUMENTS
14-98 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

r--IC~
I" ~" ~
k ,'-_--JI
Iw(CLKH) Iw(CLKL)
CLKB

CSB
I
~Lo~w~
\.
________ ~1
' ....._---1 '''''_--JI ''---__
__________________________________________________
1

WffiB ~Lo~w~ ________ _rl____________________________________________________

~I---------------------------------------------------
SIZi. SIZO -=Lo:::w;....________
tsu(EN) I~ Ih(EN)
ENB b0001 I t~$~~~~~\~__________________
I
High

Next Word From FIF01

I+- Iskit -tI...

i4 _ __
I tc~
Iw(CLKH) I" tj4 tl tw(CLKL)

CLKA ~""_--JI"'-""""'\ j f2 1 " '''''_--'':1 \"--_..Jr-

Ipd(C-FF) 141,,-----.ltl 141,,----tltl Ipd(C-FF)
FFA ______________F_IF_O_i_F_U_II____________________~j I \~_________

CSA Low 1
~~------------------~I--------
1
WiRA

ENA
ZVZZl~I~
Isu(D) ~+-tI th(D)
AO-A35
To FIFOi

t tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition high in the next CLKA cycle. lithe time between
the rising CLKB edge and rising CLKA edge is less than tsk1. FFA may transition high one CLKA cycle later than shown.
NOTE A: Port-B size of long word is selected for the FIF01 read by SIZ1 = L. SIZO = L. If port-B size is word or byte. tsk1 is referenced from the
rising CLKB edge that reads the first word or byte of the long word. respectively.

Figure 15. FFA-Flag Timing and First Available Write When FIF01ls Full

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265 14-99
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

Lt-- Ie ----.I
I_ ~i- ~I Iw(CLKL)
'...._-
tw(CLKH)

CLKA I \ I1 ' ...._--JI 1

' ...._ - - 1
'\-_...JI
1
CSA _=Lo~w~ ________-rl____________________________________________________
1
WffiA -=Lo~w~ ________ ~1

1 ____________________________________________________
MBA ________ 1 ____________________________________________________
-
=
L
o
~
w
~
~
1
Isu(EN) I~I Ih(EN)
ENA _ _ oL.l'l"""Z"""iJ7 i t:'\,;l:'(...:.0...:.$..;,.:\~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
1
High

Next Word From FIF02

' - Isk1 t --tI

i4~--- Ie ----.j
14 ~ ~I Iw(CLKL)
CLKB ~'-_--JI'-----"
Iw(CLKH)
11 " f2 ' .... _----:1 ,_____r--
Ipd(C-FF) 14 ,...__ ~I ~I_~=~.I Ipd(C-FF)
FFB ___________F~IF~O~2~FU~II~________________~) : \~_________
I
CSB Low 1

--~--------------------------------------------+I------------------
1
WiRB High

SIZ1, SIZO

ENB

BO-B35
To FIF02

t tsk1 is th~ minimum time between a rising CLKA edge and a rising ClKB edge for FFB to transition high in the next ClKB cycle. lithe time between
the rising ClKA edge and rising ClKB edge is less than tsk1, FFB may transition high one ClKB cycle later than shown.
NOTE A: Port-B size of long word is selected for FIF02 write by SIZ1 = l, SIZO = L. If port-B size is word or byte, FFB is set low by the last word
or byte write of the long word, respectively.

Figure 16. FFB-Flag Timing and First Available Write When FIF021s Full

~1ExAs
INSTRUMENTS
14-100 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

ClKA

tsu(EN) If -:l It- th(EN)

ENA nza}) I~,""S:..;,:-':..;,:-':..;,:-':",::~",::'",,;,,--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
14- tsk2t -.j
ClKB

tpd(C-AE) 14----.t~ If
l
tpd(C-AE)
AEB X long Words In FIF01
(X + 1) long Words In FIF01
tsu(EN) r.-=:: j4- th(EN)
ENB _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ,t~2~2~2~2~2~~ ~~

ttsk2 is the minimum time between a rising ClKA edge and a rising ClKB edge for AEB to transition high in the next ClKB cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tsk2, AEB may transition high one ClKB cycle later than shown.
NOTES: A. FIF01 write (CSA = l, WiRA = H, MBA = l), FIF01 read (CSB = l, W/RB = l, MBB = l)
B. Port-B size of long word is selected for FIF01 read by SIZ1 = l, SIZO = L. If port-B size is word or by1e, AEB is set low by the first
word or by1e read of the long word, respectively.

Figure 17. Timing for AEB When FIF011s Almost Empty

ClKB

tsu(EN) I. -:: I- th(EN)

ENB t/IITA Ii~
~~~~-----------------------
It- tsk2t --t/
ClKA
I
tpd(C-AE) 14----+1.1 tpd(C-AE) if .1
AEA X long Words In FIF02 I (X + 1) long Words In FIF02 \..
~
I. ~th(EN)
ENA ~
tSU(EN!J. 1..
.....________________________________ ~r~/~2~2.2~2~~ '\SSS\'\
t tsk2 is the minimum time between a rising ClKB edge and a rising ClKA edge for AEA to transition high in the next ClKA cycle. If the time between
the rising ClKB edge and rising ClKA edge is less than tsk2' AEA may transition high one ClKA cycle later than shown.
NOTES: A. FIF02 write (CSB = l, WiRB = H, MBB = l), FlF02 read (CSA = l, W/RA = l, MBA = l)
B. Port-B size of long word is selected for FIF02 write by SIZ1 = l, SIZO = L. If port-B size is word or by1e, tsk2 is referenced from the
rising ClKB edge that writes the last word or by1e of the long word, respectively.

Figure 18. Timing for AEA When FIF021s Almost Empty

~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265 14-101
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1996 - REVISED FEBRUARY 1996

If- tslc2t ~
ClKA I , ( ' ....._oJ/~--+:""'" Y~1-"""''__--Ij/2 ' ....._oJl
_I I I
tsU(EN)H....... i+" th(EN)
L I 1
ENA
~~~~$~~~~~~~~$~$\~-------+I--------------------~I~-------------
tpd(C-AF) i4 ~ I tpd(C-AF) ~14---tltj
AFA [64 - (X + 1)) long Words In FIF01 _(_64_-_X_)_l_on...;g;..w'l"'0_rd_s_l_n_F_IF_O_1__________________J
I
-----/,.-~''__ _.JI,.-~\ },.-~\......._..I1
ClKB

tau (EN) .. -:I 14- th(EN)

',-_-oJ/ '----
ENB ____________________~t~2~2~z~z~~2~2P ~~~~$~0~$~~~~~~\~__________________________

t tsk2 is the minimum time between a rising ClKA edge and a rising ClKB edge for AFA to transition high in the next ClKAcycle.lfthetime between
the rising ClKA edge and rising ClKB edge is less than tsk2, AFA may transition high one ClKB cycle later than shown.
NOTES: A. FIFOI write (CSA =l, WiRA =H, MBA = l), FIFOI read (CSB =l, W/RB =l, MBB = l)
B. Port-B size of long word is selected for FIFOI read by SIZI • l, SIZO - L. If port-B size is word or byte, tsk2 is referenced from the
first word or byte read of the long word, respectively.
Figure 19. Timing for AFA When FIF01 Is Almost Full

i4- tslc2t ~
ClKB I \ I \ / I \ Y1 \ \ I
(2
I
tsu(EN) ~ I+- th(EN) 1 I
ENB IlZl/lA I~ I
I
I
I
I
tpd(C-AF) Ie .1 tpd(C-AF) 14
I I
AFB (64 - X) long Words In FIF02
[64 - (X + 1)] long Words In FIF02

ClKA - - - '
'----
ENA

t tsk2 is the minimum time between a rising ClKB edge and a rising ClKA edge for AFB to transition high In the next ClKB cycle. If the time between
the rising elKB edge and rising ClKA edge Is less than tsk2, AFB may transition high one ClKA cycle later than shown.
NOTES: A. FIF02 wr~e (CSB =l, W/RB. H, MBB - l), FIF02 read (CSA =l, W/RA =l, MBA =l)
B. Port-B size of long word is selected for FIF02 write by SIZI =l, SIZO =L. If port-B size is word or byte, AFB is set low by the last
word or byte write of the long word, respectively.
Figure 20. Timing for AFB When FIF02 Is Almost Full

~1ExAs
INSTRUMENTS
14-102 POST OFFICE BOX 656303 • DALlAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

CLKA I \1o...----1( \~_--..J/ \Io.._ _--J/

tsu(EN) ~ ~ th(EN)
CSA --------~il~ I
I~-------------------------------
I y
I I I
W/RA 2Z?J2Z?pa:a W I
II i
MBA 22??I?/?ZZZ? IW
I I I

CLKB I

ENB

NOTE A: Port-B parity generation off (PGB = L)

Figure 21. Timing for Mall1 Register and MBF1 Flag

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-103
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

CLKB I , ........----1( '-._--

\. / \'-__--J/
tau(EN) ~ ~ th(EN)
~ --------~~~~---------------------------------------
I I I
vzzzrazzzz} :_
W/RB
tau(SZ) A r th(SZ)

ENB ?7!lI/Zll/'d? I ~
BO-B35 ~~
I
CLKA I \\.,,----r!-J/ \'-----{ ,'-----
MBF2 ________________"I"I+-......;.tp_d(;..C-_M...;F)~-.I : - tpd(C-MF) ~L-----
: {\.,,--------~I-------!
I I
)I II II tI
WIRA o/Z274 I I ~\\"~
MBA

ENA

AO-A35
F1F02 Output Register
NOTE A: Port-A parity generation off (PGA =L)

Figure 22. Timing for Mall2 Register and MBF2 Flag

~1ExAs
INSTRUMENTS
14-104 POST OFFICE BOX _ . DALLAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS30BB - AUGUST 1995 - REVISED FEBRUARY 1996

0001
EVEN
"I iI
WIRA II II '\
I~--------~I
tr-----

MBA ?/VZl2Z?zzzzvz;Zza;vflfll??Zt ts\\~~\\"\

I I I I
PGA VWZTAz;mzzzzzz/flZZlflll2l22Z7 ~
tpd(O.PE) ~
w
tpd(O.PE) ~
.u
tpd(E·PE) 14----+17- tpd(E.PE) I~
~
Valid X Valid X Valid \, Valid

NOTE A: ENA is high and eSA is low.

Figure 23. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing

0001
EVEN
I I
WIRB II II '\I~---------It
SIZ1,
SIZO o/!l2TJVzzzzT//lIT/,z2ZZ7?lz7?lZd ~
I I I I
PGB
0VZT~LIllZl/?24 %»~
tpd(o-PE)

Valid
~

NOTE A: ENS is high and ess is low.

* tpd(o-PE)

Valid
~
* Ipd(E·PE)

Valid
~
1
tpd(E·PE) ~
\, Valid

Figure 24. ODD/EVEN, W/RB, SIZ1, SIZO, and PGB to PEFB Timing

-!!J'TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-105
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

0001
EVEN
\~-------------------------
1
1
Low
1
1

~------------------+i--------------------------
WiRA
1 1
MBA vTfllllllZf I
1 I 1
PGA vT4VZZ2Z?J+-- tpd(E.PB) ----.j
I )'-------
1 1 I
I+- ten -tI 14- tpd(M.OV) ~ 1 I+-- tpd(O-PB) --+j j4-- tpd(E.PB) --+j
A8,A17,
A26,A35 ---~~ Generated Parity )I( Generated Parity *"""'M""'all""'2"'"Oa"-ta
Mall2
Data
NOTE A: ENA is high.

Figure 25. Parity-Generation Timing When Reading From the Mail2 Register

0001
EVEN
\--------------------------------
1

Low 1
1
1

~-----------------------~i~----------------------------
WiRB
1 1
SIZ1,
SIZO wZzrav4 I
1
1 I 1
PGB ~ 1 )~_ _ _ _ _ _ _ _ _ __
1 J+-- tpd(E.PB) ----.j 1 I
I+- ten +1 I+- tpd(M.OV) -tI 1 I+-- tpd(O-PB) -+I j4-- tpd(E.PB) --+I
:2~,~~5 -----i~-~G~e~ne~ra~te~d":::pa~r:":"lty---"\X,..-~G~e~ne~ra~te~d':::"pa~rl::""ty-"""*r:M~a":':'1I1:"':0::"'a":""ta
Malll
Data
NOTE A: ENB is high.

Figure 26. Parity-Generation Timing When Reading From the Mail1 Register

~TEXAS
INSTRUMENTS
14-106 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Vecl ............................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vecl ........................................... ±50 mA
Continuous output current, 10 (Vo = 0 to Vee) ............................................. ±50 mA
Continuous current through Vee or GND ................................................. ±500 mA
Operating free-air temperature range, TA .......................................... -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxim urn-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
VIH High-level input voltage 2 V
Vil low-level input voltage 0.8 V
IOH High-level output current -4 rnA
IOl low-level output current B rnA
TA Operating free-air temperature -55 125 ·e

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP:j: MAX UNIT
VOH Vee=4.5V, IOH =-4 rnA 2.4 V
VOL Vee = 4.5 V, IOl=8 rnA 0.5 V
II Vee- 5.5V, VI =VeeorO ±50 !1A
IOZ Vee = 5.5 V, Vo=Vee orO ±50 !1A
Outputs high 30
lee§ Vee=5.5 V, lo=OmA, VI = Vee or GND Outputs low 130 rnA
Outputs disabled 30
ei vI =0, f = 1 MHz 4 pF
Co VO=O, f = 1 MHz B pF
tAli tYPical values are at Vee = 5 V, TA = 25·e.
§ ICC is measured in the A to B direction.

~TEXAS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-107
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 4 through 26)
MIN MAX UNIT
fclock Clock frequency, ClKA or ClKB 50 MHz
tc Clock cycle time, ClKA or ClKB 20 ns
tw(ClKH) Pulse duration, ClKA and CLKB high 8 ns
tw(CLKL) Pulse duration, CLKA and CLKB low 8 ns
tsu(D) Setup time, AO-A35 before CLKAi and BO- B35 before CLKBi 5 ns
tsulENI Setup time, CSA, W/RA, ENA, and MBA before ClKAi; CSB, W/RB, and ENB before ClKBi 5 ns
tsu(SZ) Setup time, SIZO, SIZ1, and BE before CLKBi 5 ns
tsu(SW) Setup time, SWO and SW1 before CLKBi 7 ns
tsulPGI Setup time, ODD/EVEN and PGA before CLKAi; ODD/EVEN and PGB before CLKBit 6 ns
isu(RS) Setup time, RSf low before CLKAi or CLKB1i 6 ns
tsulFSI Setup time, FSO and FS1 before RSf high 6 ns
th(D) Hold time, AO-A35 after CLKAi and BO-B35 after CLKBi 1 ns
th(EN) Hold time, CSA, W/RA, ENA, and MBA after CLKAi; CSB, W/RB, and ENB after CLKBi 1 ns
th(SZ) Hold time, SIZO, SIZ1, and BE after CLKBi 2 ns
th(SW) Hold time, SWO and SW1 after CLKBi 7 ns
thlPGl Hold time, ODD/EVEN and PGA after ClKAi; ODD/EVEN and PGB after ClKBit 0 ns
th(RS) Hold time, RST low after CLKAi or CLKBi:l: 6 ns
thlFSI Hold time, FSO and FS1 after RST high 4 ns
tsk1§ Skew time between CLKAi and CLKBi for EFA, EFB, FFA, and m 8 ns
tSk2§ Skew time between CLKAi and CLKBi for ill, AEB, AFA, and m 16 ns
t Only applies for a clock edge that does a FIFO read
:I: Requirement to count the clock edge as one of at least four needed to reset a FIFO
§ Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and
CLKBcycle.

~1ExAs
INSTRUMENTS
14-108 POST OFFICE eox 656303 • DAlLAS. TtxAS 75285
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B- AUGUST 1995 - REVISED FEBRUARY 1996

switching characteristics over recommended ranges of supply voltage and operating free-air
=
temperature, CL 30 pF (see Figures 4 through 26)
PARAMETER MIN MAX UNIT
ta Access time, CLKAi to AO-A35 and CLKBito BO-B35 2 12 ns
1!P9lC-Fl:t Propagation delay time, CLKAi to FFA and CLKBi to FFB 2 12 ns
tpdCC-EF) Propagation delay time, CLKAi to EFA and CLKBi to EFB 2 12 ns
tpd(C-AE) Propagation delay time, CLKAi to AEA and CLKBi to AEB 2 12 ns
tpdCC-AFl Propagation delay time, CLKAi to AFA and CLKBi to AFB 2 12 ns
tpd(C-MF) Propagation delay time, CLKAi to MBF1 low or MBF2 high and CLKBi to MBF2 low or MBF1 high 1 12 ns
l!pd(C-MR) Propagation delay time, CLKAi to BO-B35t and CLKBi to AO-A35:!: 3 13 ns
i lodCC-PE)§ Propagation delay time, CLKBi to PEFB 2 12 ns
! !Pd(M-DV) Propagation delay time, MBA to AO-A35 valid and SIZ1, SIZO to BO-B35 valid 1 11.5 ns
tpdCD-PE) Propagation delay time, AO-A35 valid to PEFA valid; BO-B35 valid to PEFB valid 3 12.5 ns
tpdCO-PE) Propagation delay time, ODD/EVEN to PEFA and PEFB 3 12 ns
tpd(O-PB)lI Propagation delay time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35) 2 12 ns
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB, SIZ1, SIZO,
!Pd(E-PE) 1 12 ns
or PGB to PEFB
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17, A26, A35); CSB,
tpd(E_PB)lI 3 19 ns
ENB, WiRB, SIZ1, SIZO, or PGB to parity bits (B8, B17, B26, B35)
tpdCR-F) Propagation delay time, RST to (MBF1 , MBF2) high 1 20 ns
Enable time, CSA and W/RA low to AO-A35 active and CSB low and W/RB high to BO-B35
ten 2 12 ns
active
Disable time, CSA or W/RA high to AO-A35 at high impedance and CSB high or W/RB low to
ldis 1 9 ns
BO-B35 at high impedance
..
tWnting data to the mal11 register when the BO-B35 outputs are active and SIZ1, SIZO are high
:!: Writing data to the mail2 register when the AO-A35 outputs are active and MBA is high
§ Only applies when a new port-B bus size is implemented by the rising CLKB edge
~ Only applies when reading data from a mail register

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-109
SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
VB
CLOCK FREQUENCY
400 I ,J. I 1 _I,
fdata = 1/2 fclo k Vcc = 5.5 V /
-TA = 25°C
350 ~
CI.=OpF
1I / ~
300
V
~::I 250
VCC=5Z
/ .//
~,/
i"'"
(,)
b
Co
200
/
~ ~ /'VCC=4.5V
Co
cilI
150
e:
8 100
k% ~
50 ,~ V

o
o 10 20 30 40 50 60 70 80

fclock - Clock Frequency - MHz

Figure 27

calculating power dissipation

The ICC(f) current for the graph in Figure 28 was taken while simultaneously reading and writing the FIFO on
the SN54ACT3614 with ClKA and ClK8 set to fclock. All data inputs and data outputs change state during each
clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to
a zero-capacitance load. Once the capacitive load per data-output channel is known, the power dissipation can
be calculated with the equation below.
With ICC(f) taken from Figure 28, the maximum power dissipation (Pr) of the SN54A8T3614 can be calculated
by:
Pr = VCC x ICC(f) + L(CL x VOH2 x fo)
where:
CL = output capacitive load
fo = switching frequency of an output
VOH = high-level output voltage
When no reads or writes are occurring on the SN54ABT3614, the power dissipated by a single clock (CLKA
or ClK8) input running at frequency fclock is calculated by:
Pr = Vce x fclock x 0.29 mA/MHz

~1ExAs
INSTRUMENTS'
14-110 POST OFFICE BOX 666303 • DALLAS, TEXAS 75265
 SN54ABT3614
64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST·IN, FIRST·OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308B - AUGUST 1995 - REVISED FEBRUARY 1996

PARAMETER MEASUREMENT INFORMATION

5V

1.1 kn
From Output
Under Test - .....- - - - .

6800 ;::1=' 30 pF
(see Note A)

LOAD CIRCUIT

~
--3V
Timing
Input i-
__---I.q..
1•5V
- - - -
3V

GND
High-Level
Input
1.5 V 1.5 V
I I GND
tsu~th 14- tw --+I
I I
Data, ~-:::- 3V
~
I 3V
Enable --I 1.5 V ~ Low-Level 1.5 V 1.5 V
Input GND Input _ _ _ _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

3V
Output
Enable JiL 1.5 V GND
--+I l~tPLZ
Low-Level
Output
i 1 ----~
Input --11.5 V ::0
_-+.JI VOL
){5-; - -
~tPZH
VOH tpd~ ~tpd
High-Level
In-Phase
......_~ 1_- VOH
Output 1 I
~OV Output 11.5V 'S..1.5V
--+j
1 I
l~tPHZ
_ _-oJ. 'C VOL

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 28_ Load Circuit and Voltage Waveforms

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-111
14-112
 SN54ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY

• Free-Running ClKA and ClKB Can Be • Output-Ready (OR) and Almost-Empty (AE)
Asynchronous or Coincident Flags Synchronized by ClKB
• Clocked FIFO Buffering Data From Port A • low-Power O.8-Mlcron Advanced CMOS
to Port B Technology
• Memory Size: 1024 x 36 • Supports Clock Frequencies up to 50 MHz
• Synchronous Read-Retransmit Capability • Fast Access Times of 15 ns
• Mailbox Register In Each Direction • Released as DESC SMD (Standard
• Programmable Almost-Full and Microcircuit Drawing) 5962-9560801NXD
Almost-Empty Flags • PCB Package Qualified as Military Plastic
• Microprocessor Interface Control logic Device Per Mll-PRF-38535 (QMl)
• Input-Ready (IR) and Almost-Full (AF) Flags • Available in Space-Saving 120-Pin Thin
Synchronized by ClKA Quad Flat (PCB) Package

description

The SN54ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies
up to 50 MHz and has read access times as fast as 15 ns. The 1024 x 36 dual-port SRAM FIFO buffers data
from port A to port S. The FIFO memory has retransmit capability, which allows previously read data to be
accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words is stored in memory. Communication
between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal
when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths.
Expansion is also possible in word depth.
The SN54ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to ClKA. The
output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to ClKS. Offset
values for the almost-full and almost-empty flags of the FIFO can be programmed from port A or through a serial
input.
The SN54ACT3641 is characterized for operation from - 55 c C to 125c C.
For more information on this device family, see the application reports FIFO Patented Synchronous Retransmit:
Programmable DSP-Interface Application for FIR Filtering and FIFO Mailbox-Bypass Registers: Using Bypass
Registers to Initialize DMA Control in the 1996 High-Performance FIFO Memories DeSigner's Handbook,
literature number SCAA012A.

Copyright © 1995, Texas Instruments Incorporated

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-113
SN54ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309-AUGUST 1995

PCB PACKAGE
(TOP VIEW)

A35 1 635
A34 2 634
A33 3 633
A32 4 632
Vee 5 GND
A31 6 631
A30 630
GND 629
A29 628
A28 627
A27 626
A26 Vee
A25 625
A24 624
A23 GND
GND 623
A22 622
Vee 621
A21 620
A20 619
A19 618
A18 GND
GND 617
A17 616
A16 Vee
A15 615
A14 614
A13 613
Vee 612
A12 GND

Ne - No internal connection

-!I1TEXAS
INSTRUMENTS
14-114 POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
 SN54ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309 - AUGUST 1995

functional block diagram

•
Mall1 I
MBF1

~~
Register I
ClKA -
CSA - Port-A
WiRA - Control ~
ENA - logic I-- -
~ ~ ~
MBA - f--

r
'5
~
1024 x 36
SRAM ... ~
:J
Reset a.
.5 ~ f+-
logic

36
i....-
+
.c~" RTM
g ~.Q~
>toe
~(/)'ai..J
° ... RFM
I Write
I Pointer II Read
Pointer
a:

AO-A35

IR
+
Status-Flag
+ eO-B35

OR
AF logic 1 AE

+
FSO/SD Flag-Offset
FS1/SEN
10
Register
l...-
I--
I-- Port-B ::= ClKB
CSB

..., I Mall2
Register
I ....
Control
logic ::=
+-
W/RB
ENB
MBB

'f

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-115
SN54ACT3641
1024x 36
CLOCKED FIRST-IN, FIRST·OUT MEMORY
SGBS309 - AUGUST 1995

Terminal Functions
TERMINAL
1/0 DESCRIPTION
NAME
AO-A35 1/0 Port-A data. The 36-bit bidirectional data port for side A.
Almost-empty flag. Programmable flag synchronized to ClKB. AE is low when the number of words in the FIFO is less
AE 0
than or equal to the value in the almost-em ply offset register (X).
Almost-full flag. Programmable flag synchronized to ClKA. AF is low when the number of empty locations in the FIFO
AF 0
is less than or equal to the value in the almost-full offset register (y).
BO-B35 1/0 Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. ClKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
ClKA I
or coincident to ClKB. IR and AF are synchronous to the low-to-high transition of ClKA.
Port-B clock. ClKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
ClKB I
or coincident to ClKA. OR and AE are synchronous to the low-to-high transition of ClKB.
Port-A chip select. CSA must be low to enable a low-to-high transition of ClKA to read or write data on port A. The
CSA I
AO-A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of ClKB to read or write data on port B. The
CSB I
BO-B35 outputs are in the high-impedance state when CSB is high.
ENA I Port-A master enable. ENA must be high to enable a low-to-high transition of ClKA to read or write data on port A.
ENB I Port-B master enable. ENB must be high to enable a low-to-high transition of ClKB to read or write data on port B.
Flag offset select llserial enable, flag offset select O/serial data. FS1/SEN and FSOISD are dual-purpose inputs used
for flag offset register programming. During a device reset, FS1/SEN and FSO/SD select the flag offset programming
method. Three offset register programming methods are available: automatically load one of two preset values, parallel
FS1/SEN, load from port A, and serial load.
I
FSO/SD When serial load is selected for flag offset register programming, FS1/SEN is used as an enable synchronous to the
low-to-high transition of ClKA. When FS1/SEN is low, a rising edge on ClKA loads the bit present on FSO/SD into the
X and Y offset registers. The number of bit writes required to program the offset registers is 20. The first bit write stores
the V-register MSB and the last bit write stores the X-register lSB.
Input-ready flag. IR is synchronized to the low-to-high transition of ClKA. When IR is low, the FIFO is full and writes to
IR 0 its array are disabled. When the FIFO is in retransmit mode,lR indicates when the memory has been filled to the point
of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset.
MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
MBB I BO-B35 outputs are active, a high level on MBB selects data from the maill register for output and a low level selects
FIFO data for output.
Maill register flag. MBFl is set low by the low-to-high transition of ClKA that writes data to the maill register. MBFl
MBFl 0 is set high by a low-to-high transition of ClKB when a port-B read is selected and MBB is high. MBFl is set high by a
reset.
Mail2 register flag. MBF2 is set low by the low-to-high transition of ClKB that writes data to the mail2 register. MBF2
MBF2 0 is set high by a low-to-high transition of ClKA when a port-A read is selected and MBA is high. MBF2 is set high by a
reset.
Output-ready flag. OR is synchronized to the low-to-high transition of ClKB. When OR is low, the FIFO is emply and
OR 0 reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during
the reset and goes high on the third low-to-high transition of ClKB after a word is loaded to empty memory.
Read from mark. When the FI FO is in retransmit mode, a high on RFM enables a low-to-high transition of ClKB to reset
RFM I
the read pointer to the beginning retransmit location and output the first selected retransmit data.
Reset. To reset the device, four low-to-high transitions of ClKA and four low-to-high transitions of ClKB must occur
RST I
while RST is low. The low-to-high transition of RST latches the status of FSO and FSI for AF and AE offset selection.
Retransmit mode. When RTM is high and valid data is preSent in the FIFO output register (OR is high), a low-to-high
transition of ClKB selects the data forthe beginning of a retransmit and puts the FIFO in retransmit mode. The selected
RTM I
word remains the initial retransmit point until a low-to-high transition of ClKB occurs while RTM is low, taking the FIFO
out of retransmit mode.

-!11
TEXAS
INSTRUMENTS
14-116 POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
 SN54ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309-AUGUST 1995

Terminal Functions (Continued)

TERMINAL
1/0 DESCRIPTION
NAME
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a
WiRA I
low-te-high transition of CLKA. The AO-A35 outputs are in the high-impedance state when WiRA is high.
Port-B writelread select. A low on W/RB selects a write operation and a high selects a read operation on port B for a
W/RB I
low-ta-high transition of ClKB. The BO-B35 outputs are in the high-impedance state when W/RB is low.

detailed description
reset
The SN54ACT3641 is reset by taking the reset (RST) input low for at least four port-A clock (ClKA) and four
port-B clock (ClKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset
initializes the memory read and write pointers and forces the input-ready (IR) flag low, the output-ready (OR)
flag low, the almost-empty (AE) flag low, and the almost-full (AF) flag high. Resetting the device also forces the
mailbox flags (MBF1, MBF2) high. After a FIFO is reset, its input-ready flag is set high after at least two clock
cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory.
almost-empty flag an.d almost-full flag offset programming
Two registers in the SN54ACT3641 are used to hold the offset values for the almost-empty and almost-full flags.
The almost-empty (AE) flag offset register is labeled X, and the almost-full (AF) flag offset register is labeled Y.
The offset registers can be loaded with a value in three ways: one of two preset values are loaded into the offset
registers, parallel load from port A, or serial load. The offset register programming mode is chosen by the flag
select (FS1, FSO) inputs during a low-to-high transition on RST (see Table 1).

Table 1. Flag Programming

FS1 FSO RST X AND Y REGISTERSt
H H l' Serial load
H l l' 64
l H l' 8
l l l' Parallel load from port A
t X register holds the offset for AE; Y register holds the
offset for AF.

preset values
If a preset value of 8 or 64 is chosen by FS1 and FSO at the time of a RST low-to-high transition according to
Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is
necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on ClKA.
parallel load from port A
To program the X and Y registers from port A, the device is reset with FSO and FS1 low during the low-to-high
transition of RST. After this reset is complete, IR is set high after two low-to-high transitions on ClKA. The first
two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X. Each offset
register ofthe SN54ACT3641 uses port-A inputs (A9-AO). Data input A9 is used as the most significant bit of
the binary number. Each register value can be programmed from 1 to 1020. After both offset registers are
programmed from port A, subsequent FIFO writes store data in the SRAM.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-117
SN54ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGBS309 - AUGUST 1995

serial load
To program the X and Y registers serially, the device is reset with FSO/SD and FS1/SEN high during the
low-to-high transition of RST. After this reset is complete, the X and Y register values are loaded bitwise through
FSO/SD on each low-to-high transition of CLKA that FS1/SEN is low. Twenty-bit writes are needed to complete
the programming. The first-bit write stores the most significant bit of the Y register, and the last-bit write stores
the least significant bit of the the X register. Each register value can be programmed from 1 to 1020.
When the option to program the offset registers serially is chosen, IR remains low until all 20 bits are written.
IR is set high by the low-to-high transition of CLKA after the last bit is loaded to allow normal FIFO operation.
FIFO write/read operation
The state of the port-A data (AO-A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (WiRA). The AO-A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The AO-A35 outputs are active when both CSA and W/RA are low.
Data is loaded into the FIFO from the AO-A35 inputs on a low-to-high transition of CLKA when CSA and the
port-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the input-ready (IR) flag are high (see
Table 2). Writes to the FIFO are independent of any concurrent FIFO reads. .

Table 2. Port·A Enable Function Table

CSA W/RA ENA MBA CLKA AO-A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L i In high-impedance state FIFO write
L H H H i In high-impedance state Mail1 write
L L L L X Active, mail2 register None
L L H L i Active, mail2 register None
L L L H X Active, mail2 register None
L L H H i Active, mail2 register Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A with the exception that the port-B write/read select
(W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (BO-B35) outputs is
controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The BO-B35 outputs are
in the high-impedance state when either CSB is high or W/RB is low. The BO-B35 outputs are active when CSB
is low and W/RB is high.
Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB and the port-B
mailbox select (MBB) are low, W/RB, the port-B enable (ENB), and the output-ready (OR) flag are high (see
Table 3). Reads from the FIFO are independent of any concurrent FIFO writes.

~1ExAs
INSTRUMENTS
14-118 P9ST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ACT3641
1024 x36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGBS309 - AUGUST 1995

FIFO write/read operation (continued)

Table 3. Port·B Enable Function Table

CSB W/RB ENB MBB CLKB BO-B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L L L X X In high-impedance state None
L L H L i In high-impedance state None
L L H H i In high-impedance state Mail2write
L H L L X Active, FI FO output register None
L H H L i Active, FIFO output register FIFO read
L H L H X Active, mail1 register None
L H H H i Active, mail1 register Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select can change states during the
setup- and hold-time window of the cycle.
When OR is low. the next data word is sent to the FIFO output register automatically by the ClKB low-to-high
transition that sets the output-ready flag high. When OR is high, an available data word Is clocked to the FIFO
output register only when a FIFO read is selected by the port-B chip select (CSB), write/read select (W/RB),
enable (ENB), and mailbox select (MBB).
synchronized FIFO flags
Each FI FO is synchronized to its port clock through at least two flip-flop stages. This is done to improve the flags'
reliability by reducing the probability of metastable events on their outputs when ClKA and ClKB operate
asynchronously to one another (see the application report Metastability Performance of Clocked FIFOs in the
1996 High-Performance FIFO Memories Data Book, literature number SCAD003C). OR and AE are
synchronized to ClKB. IR and AF are synchronized to ClKA. Table 4 shows the relationship of each flag to the
number of words stored in memory.

Table 4. FIFO Flag Operation

SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS IN TOCLKB TOCLKA
FIFOt*
OR AE AF IR
0 L L H H
1 toX H L H H
(X + 1) to [1024 - f'{ + 1)] H H H H
(1024 - y) to 1023 H H L H
1024 H H L L
t X is the almost-empty offset for AE. Y is the almost-full offset for AF.
:I: When a word is present in the FIFO output register, its previous memory
location is free.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265 14-119
SN54ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SG8S309 - AUGUST 1995

output-ready flag (OR)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array (ClKS). When
the output-ready flag is high, new data is present in the FIFO output register. When OR is low, the previous data
word is present in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pOinter is incremented each time a new word is clocked to its output register. The state machine
that controls an output-ready flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is empty, empty+ 1, or empty+2. From the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of ClKS; therefore, an output-ready flag is low if a word
in memory is the next data to be sent to the FI FO output register and three ClKS cycles have not elapsed since
the time the word was written. The output-ready flag ofthe FIFO remains low until the third low-to-high transition
of ClKS occurs, simultaneously forcing OR high and shifting the word to the FIFO output register.
A low-to-high transition on ClKS begins the first synchronization cycle of a write if the clock transition
occurs at time tsk(1), or greater, after the write. Otherwise, the subsequent ClKS cycle can be the first
synchronization cycle (see Figure 6).
input-ready flag (IR)
The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array (ClKA). When IR
is high, a memory location is free in the SRAM to write new data. No memory locations are free when the
input-ready flag is low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an
input-ready flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM
status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready
to be written in a minimum of three cycles of ClKA. Therefore, IR is low if less than two cycles of ClKA have
elapsed since the next memory write location has been read. The second low-to-high transition on ClKA after
the read sets IR high, and data can be written in the following cycle.
A low-to-high transition on ClKA begins the first synchronization cycle of a read if the clock transition
occurs at time tsk(1), or greater, after the read. Otherwise, the subsequent ClKA cycle can be the first
synchronization cycle (see Figure 7).
almost-empty flag (AE)
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array (ClKS). The
state machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that
indicates when the FIFO SRAM status is almost empty, almost empty+ 1, or almost empty+2. The almost-empty
state is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset,
programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset
programming). AE is low when the FIFO contains X or less words and is high when the FIFO contains (X + 1)
or more words. A data word present in the FIFO output register has been read from memory.
Two low-to-high transitions of ClKS are required after a FI FO write for the almost-empty flag to reflect the new
level of fill. Therefore, the almost-empty flag of a FI FO containing (X + 1) or more words remains low if two cycles
of ClKS have not elapsed since the write that filled the memory to the (X + 1) level. AE is set high by the second
low-to-high transition of ClKS after the FIFO write that fills memory to the (X + 1) level.
A low-Io-high transition of ClKB begins the first synchronization cycle if it occurs at time tsk(2), or greater, after
the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent ClKS cycle can be the first
synchronization cycle (see Figure 8).

~1ExAS
INSTRUMENTS
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 SN54ACT3641
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CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGBS309 - AUGUST 1995

almost-full flag (AF)

The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array (ClKA). The state
machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by
the contents of register Y. This register is loaded with a preset value during a FIFO reset, programmed from port
A, or programmed serially (see almost-empty flag and almost-full flag offset programming). AF is low when the
number of words in the FIFO is greater than or equal to (1024 - V). AF is high when the number of words in the
FIFO is less than or equal to [1024 - (Y + 1)]. A data word present in the FIFO output register has been read
from memory.
Two low-to-high transitions of ClKA are required after a FIFO read for its almost-full flag to reflect the new level
offill. Therefore, the almost-full flag of a FIFO containing [1024- (Y + 1)] or less words remains low if two cycles
of ClKA have not elapsed since the read that reduced the number of words in memory to [1024 - (Y + 1)]. AF
is set high by the second low-to-high transition of ClKA after the FIFO read that reduces the number of words
in memory to [1024 - (y + 1)]. A low-to-high transition of ClKA begins the first synchronization cycle if it occurs
at time tsk(2), or greater, after the read that reduces the number of words in memory to [1024 - (Y + 1)].
Otherwise, the subsequent ClKA cycle can be the first synchronization cycle (see Figure 9).
synchronous retransmit
The synchronous-retransmit feature of the SN54ACT3641 allows FIFO data to be read repeatedly starting at
a user-selected pOSition. The FIFO is first put into retransmit mode to select a beginning word and prevent
on-going FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three
words can retransmit repeatedly starting at the selected word. The FIFO can be taken out of retransmit mode
at any time and allow normal device operation.
The FIFO is put in retransmit mode by a low-to-high transition on ClKS when the retransmit-mode (RTM) input
is high and OR is high. This rising ClKS edge marks the data present in the FIFO output register as the first
retransmit data. The FIFO remains in retransmit mode until a low-to-high transition occurs while RTM is low.
When two or more reads have been done past the initial retransmit word, a retransmit is initiated by a low-to-high
transition on ClKS when the read-from-mark (RFM) input is high. This rising ClKS edge shifts the first
retransmit word tothe FIFO output register and subsequent reads can begin immediately. Retransmit loops can
be done endlessly while the FIFO is in retransmit mode. RFM must be low during the ClKS rising edge that takes
the FIFO out of retransmit mode.
When the FIFO is put into retransmit mode, it operates with two read pointers. The current read pointer operates
normally, incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE
flags. The shadow read painter stores the SRAM location at the time the device is put into retransmit mode and
does not change until the device is taken out of retransmit mode. The shadow read pointer is used by the IR
and AF flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set low by the write that
stores (102 - Y) words after the first retransmit word. The IR flag is set low by the 1024th write after the first
retransmit word.
When the FIFO is in retransmit mode and RFM is high, a rising ClKS edge loads the current read pointer with
the shadow read-pointer value and the OR flag reflects the new level of fill immediately. If the retransmit changes
the FIFO status out of the almost-empty range, up to two ClKS rising edges after the retransmit cycle are
needed to switch AE high (see Figure 11). The rising ClKS edge that takes the FIFO out of retransmit mode
shifts the read painter used by the IR and AF flags from the shadow to the current read pointer. If the change
of read pointer used by IR and AF should cause one or both flags to transition high, at least two ClKA
synchronizing cycles are needed before the flags reflectthe change. A rising ClKA edge after the FIFO is taken
out of retransmit mode is the first synchronizing cycle of IR if it occurs at time tsk(1), or greater, after the rising
ClKS edge (see Figure 12). A rising ClKA edge after the FIFO is taken out of retransmit mode is the first
synchronizing cycle of AF if it occurs at time tsk(2), or greater, after the rising ClKS edge (see Figure 14).

-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265 14-121
SN54ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST·OUT MEMORY
SGBS309 - AUGUST 1995

mailbox registers
Two 36-bit bypass registers are on the SN54ACT3641 to pass command and control information between portA
and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data
transfer operation. A low-to-high transition on ClKA writes AO-A35 data to the mail1 register when a portA write
is selected by CSA, WiRA, and ENA with MBA high. A low-to-high transition on ClKB writes BO-B35 data to
the mail2 register when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mail
register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while
its mail flag is low.
When the port-B data (BO-B35) outputs are active, the data on the bus comes from the FIFO output register
when the port-B mailbox select (MBB) input is low and from the mail 1 register when MBB is high. Mail2 data
is always present on the port-A data (AO-A35) outputs when they are active. The mail1 register flag (MBF1)
is set high by a low-to-high transition on ClKB when a port-B read is selected by CSB, W/RB, and ENB with
MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on ClKA when a port-A read
is selected by CSA, W/RA, and ENA with MBA high. The data in a mail register remains intact after it is read
and changes only when new data is written to the register.

ClKA

ClKB
I I I It
....I ~ h(FS)
_ _ _ _-..1
RST \
j4- tsu(RS) 1
I
I
I
I
tsu(FS) 1;-r'1
I
I I
I
I
1 I 1 I
FS1, FSO

L ~ i---1
IR ~~\§\'\
tpd(C-IR)
lI tpd(C-IR)
/r"---
I tpd(C-OR) 1.----.1
OR ~~\\\\\\\\\\\\
tpd(R-F) !-----ti
AES\~~
tpd(R-F) I.----.j
AF ?I2lld(zzz)'
__ tpd(R-F) i+------.I
~:F~ WlZ2Zl??A
Figure 1. FIFO Reset loading X and Y With a Preset Value of Eight

~1ExAs
INSTRUMENTS
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 SN54ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGBS309 - AUGUST 1995

CLKA

ENA //ZlZWWLVWAZT/?Z7/1A ! WW \<XX88? \\\\\S\\

I.~ ~th(D)

~~!-=--
A O - A 3 5 .
AF Offset AE Offset First Word Stored In FIFO
(V) (X)
NOTE A: eSA =L. WiRA - H. MBA =L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values From Port A

CLKA
1 I
RST _ _ _ _ 1 " 11 II

: I tpd(C-IR) it-~----ti~1
IR ______ ~I1--------------~~----------~S\~~--~:
- ~ 4j
th(SP)
~-----------Jy--
--+I I+-
i+-1h(SEN) +- th(SEN)
tau(FS) 1++1 tau(SEN) i+-'I 1 ~~~ 1
FS1/SEN Z222J'7"'7'.;..,.;7r-iI-----=::::..:I,\ 1.tX'X')QQ\ ~ Y4.""Z""'Z""'Z""'Z""'Z""'Z""Z""Z""Z""Z""Z"'Z..,z,..,
"'Z
1 I ::::;j ~ - ii=th(SD)
tau(FS)
FSo/SD?22ZI
~ ~~:-:_-.le~L.:::::====
•
AF Offset AE Offset
(y) MSB (X) LSB
NOTE A: It Is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored untillR is set high.

Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially

~1ExAs
INSTRUMENTS
POST OFFICE BOX 665303 • DALlAS, TEXAS 75265 14-123
SN54ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGBS309 - AUGUST 1995

I. te _I
tw(ClKH) 14

ClKA }
I .~

~
I
-: tw(ClKl)

r
I
,'---_---", I
''----'IfI '-
I I I
IR High
tsu(EN2) 14 -: 4, th(EN2)
I
I
II
CSA
~
tsu(EN2) 14
i-.
-I. ~ th(EN2)
I
WiRA
?IZlZIZZ/ZlZ{ iF : \\\\\\\\\\;
tsu(EN2) ~ _1 4 ~ th(EN2) I
MBA I I

ENA
tsu(O) 14 _1 ..1th(O)
AO-A35 /i.lo djieratfon i88888888
Figure 4. FIFO Write-Cycle Timing

tw(ClKH) :;+4
~14---te----~_1
---""_1... ----.1-:--":y tw(ClKl)
, (
ClKB , . - - - \ ' -_ _
I I
,'-----':y
I '-
I I I
OR High
I I
I I
CSB - - " " \ \ I I
I I I
I I I
W/RB .?..2..2....2u{ : :
MBB ---I!--""\\!I
1 I
1
I I tsu(EN1) tsu(EN1)1 tsu(EN1)I
I I ~ 1+----.1 1.---.1
I I 1 " 1 : ' - th(EN1) I --tj It-- th(EN1) I -' I+- th(EN1)
ENB
Vzq>ft$ I~ : \\\\\\\\»::i W/ZZ2V?
I I~I -II ~ ta -JI I ope~~tlon !.....J tdls
*
tpd(M.OV)
~~~ ~~~ rl
BO-B35 ----_~ W1 W2 X---:::W::""3- - - j

Figure 5. FIFO Read-Cycle Timing

~1ExAs
INSTRUMENTS
14-124 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGBS309 - AUGUST 1995

CLKA
I
CSA ~LO~W~ ____ ~I I______ ~ ________________________________________________
I
WiRA High I
tsu(EN2) ~ I.- th(EN2)
MBA /lZl/ZZU. rr-""/'''''Z;'''%''''Z';''Z~Z~Z~Z"7'Z"7'Z"7'Z"7'Z''''Z""Z""Z""Z""Z'rZ'rZ'rZ'rZ'r,?rzrz"'z"'Z'"V"'~"'-:/''''-:'/''''/'''''(':''''/'''''/'''''2''''Z''''Z''''Z~Z~6~6~Z"7'Z"7'6-r;
tSU(EN:!.J.~ ~ :~N1!
ENA R/llZi I \:_$~S:...~o.,l~~~~--------------------
i I
IR High tsu(D) f:!! I I
th(D)
AO-A35 Wi
tSk(i)t t4 ~ to
tw(CLKH)-, ~ w(CLKL)
CLKB 1 2 3

OR Old Data In FIFO Output Register

tpd(C-OR) ~It--~--l!:==~
--------~-~-----~I-~ ~---------
I ________~-------------------
CSB ~LO~w__________________________________~I
I
W/RB High

t tsk(1) is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition high and to clock the next word to the FIFO
output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tsk(1). the transition of OR high
and the first word load to the output register can occur one CLKB cycle later than shown.

Figure 6. OR-Flag Timing and Flrst-Data-Word Fallthrough When the FIFO Is Empty

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 14-125
SN54ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGBS309 - AUGUST 1995

It-- te --tI
tw(CLKH) I.. ,.. .\ tw(CLKL)
CLKB I \. J \I--_..J/ \\"._-..J/ \1--__
I
CSB ~LO~W~................_:~................................................................................................___
I
W/RB High I
I
MBB ~Lo~w~~....~...._I~~...................................................................................._______
tsu(EN1) 1~h."(EN1)
ENB IIZ?77
I X~:>;lo.,;$~~~,,--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

OR High I
I.- ta-.l
BO-B35 FIFO Output Resls/er . *, "~N;: ext=w.: :or:.;:d.:.F~ro: .:m:. :F.: IF. .;:O;. . ....................................................._ ...._

1'- tsk(l)t -.I", te - - - '

CLKA ~\"'_-..Jlr-~\
tw(CLKH) '"
11
~
'\
t.,- tw(CLKL)
2 \'-_---'!( \'-_---Jr-
tpd(C-IR) J41"---~.I..-....-I:I"!::==~.1 tpd(C-IR)
IR_........................~F~IF~O~F~U~II............................................~1 I , I \------
CSA Low I

WiRA
----------------------------------------~I
High I
---------------

ENA

AO-A35

t tsk(l) is the minimum time between a rising ClKS edge and a rising ClKA edge for IR to transition high in the next ClKA cycle. If the time between
the rising ClKS edge and rising ClKA edge is less than tsk(I). IR can transition high one ClKA cycle later than shown.

Figure 7. IR-Flag Timing and First Available Write When the FIFO Is Full

~TEXAS
INSTRUMENTS
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 SN54ACT3641
1024 x 36
CLOCKED FIRST.IN, FIRST·OUT MEMORY
SGBS3D9 - AUGUST 1995

ClKA
tsu~:1}~
1///7~~~0~~~S~S~~~\~
r- th(EN1)
_____________________________________
ENA

jf- tsk(2)t -t/

ClKB
~
! 4 - - - -.. tpd(CoAE) If ~
Y(X + 1) Words In FIFO
HJ ~
AE X Words In FIFO
~th(EN1) tsu(EN1)
ENB ______________________________________________~~~,???~?~/~~ ~~

t tsk(2) is the minimum time between a rising ClKA edge and a rising ClKB edge for AE to transition high in the next ClKB cycle. If the time between
the rising ClKA edge and rising CJ:KB edge is less than tsk(2)' AE can tra~ition high one ClKB cycle later than shown.
NOTE A: FIFO write (CSA =l, W/RA - H, MBA =l), FIFO read (ese - l, W/RB = H, MBB =l)

Figure 8, Timing for AE When FIFO Is Almost Empty

I.- tsk(2)t -tI

CLKA / \ I \ 1'---+1""\\ Y""!'"1-~\ y2 \....--'1
tsu(EN1) ~ I+- th(EN1) I I
ENA t2l?ZT~1 ts\\\\\ I 1
1
tpd(CoAF) Ie tpd(CoAF) 4 - - " ' "
1+1

ir----
AF [1024-(y+1)]WordslnFIFO

I
ClKB---I \'-__-J/ \
tsu(EN1} ~
1-~\
t:
h (EN1)
/ \ _____..1/
'---
ENB ____________________~~~,???~?~Z~:~ ~~~~S.S~S~S~,~~ __________________________
t tsk(2) is the minimum time between a rising ClKA edge and a rising ClKB edge for AF to transition high in the next ClKA cycle.lfthetime between
the rising ClKB edge and rising CJ:KA edge is less than tsk(2), AF can tra~ition high one ClKA cycle later than shown.
NOTE A: FIFO write (GSA = l, W/RA = H, MBA =l), FIFO read (CSB =l, W/RB =H, MBB =L)

Figure 9, Timing for AF When FIFO Is Almost Full

-!11 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-127
SN54ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGBS309 - AUGUST 1995

ClKB I \ t \ I
I
\ ~ \ !I \
I~ th(EN1)
tsu(EN1) I
I
I
ENB
//II I '@I
tsu(RM) ~ th(RM)
I
I \2$' tsu(RM) ~
I
th(RM)
I I
RTM 1//1 I~ I
I
I
I
~I~
I
I I tsu(RM) ~ th(RM) I
I
RFM
I
I
I Il?/J I ts\\ I
I
I I I I
OR
I I I I
High
I I I I
i+-la-.i I+-- ta -tI Ie- ta-tl /4- ta-tl
BO-B35 WO
Initiate Retransmit Mode
With WO as First Word
* Wi

* W2
Retransmit From *
Selected Position
WO
*
End Retransmit
Mode
Wi

NOTE A: eSB = L, W/RB = H, MBB = L. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit.
Other enables are shown only to relate retransmit operations to the FIFO output register.

Figure 10. Retransmit Timing Showing Minimum Retransmit Length

' _......
.... / '...._-

I+--~~I- tpd(C.AE)
- _ _ _ _ _ _ _ _ _ _ _ _~::.-_ _ _ _ _ _ _...J ex + 1) or More Words From Empty
NOTE A: X is the value loaded in the almost-empty flag offset register.

Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X

~ThxA.s
INSTRUMENTS
14-128 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309 - AUGUST 1995

14- tsk(1)t .-.j

CLKA , 1,----41"""" ''''1---''' 12 '\,_-.JI '\.._...,,1
1 tpd(C-IR) ~
IR FIFO Filled to Firat Ratrsnsm1lt Word Ir.:"O-ne-o-r"='M:-o-re-=W'!"!'r":':lte-:-Lo-ca-t~lo-n-a-=A-va-::lI:-:ab:-:-le
1
1
----1 1 I I I
CLKB \
tau(RM) I.. -I" -I
1
th(RM)
\ \ \ '--
RTM
~~ ~
t Isk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge lor IR to transition high in the next CLKA cycle. lithe time between
the rising CLKB edge and rising CLKA edge is less than tsk(1). IR can transition high one CLKA cycle later than shown.

Figure 12. IR Timing From the End of Retransmit Mode When One or More Write Locations Are Available

14- tak(2)t.-.j
CLKA '\._-.JI"'--;I~\ ''''!''1-~\ 12 ''-_-....II ''-_-....Ir
1 tpd(C-AE) ~
..:(~1024;;;.;,_-..;.Y):.;o;;;.r.;,;M.;,;o;;.;rs;.;w;,;;o;;;.rd,;;;;a;.;p;.;a;;;at;.;'F;.;,lr;.;;at;;.;R;,;;at;;,;;r;.;;a;,,;;na;;;m;;,;,lt;.;W;,;;o;;;.rd=-_ _ _ _ _-JIr(Y~+~1~)o-r-=M~o-rs~W~r-::lt-e~Lo-ca~tlo-n-a~A-va~I:-la~bl-e
1
CLKB ----1 ''----k~-~\'---JI ' " , _ _oJ I ''-_-....II '---
1
tsu(RM) ,.. -I" -, th(RM)
RTM
\W\1. ,ws&sM.
t Isk(2) isthe minimum time between a rising CLKB edge and ariSing CLKA edge lor AF to transition high in the next CLKA cycle. lithe time between
the rising CLKB edge and rising CLKA edge Is less than Isk(2). AF can transition high one CLKA cycle later than shown.
NOTE A: Y Is the value loaded In the almost-full flag offset register.

Figure 13. AF Timing From the End of Retransmit Mode When (y + 1)

or More Write Locations Are Available

~1ExAs
INSTRUMENTS
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SN54ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309 - AUGUST 1995

ClKA I
~
\
tsu(EN2)
th(EN2)
(r- 'I..__..J/ ,\-__--J/
'-
------==~~~------------------------------

W/RA 'lZZZ//IlT/4 : m
2Z7?ZZZZZZ?1 :m
I I I
MBA
I I I

ClKB I

W/RB
W2V1: :~
MBB _ _ _,...1_ _~/I i. _,
tSU(EN1)~~
~\\\'<
ENB

Ln
:L-4
I
II
II

14 II
P'tZZI
~I tpd(M-OV)I tpd(C-MR)
th(EN1)
~~$~$_$~~.....I~
tdls L
I

_I
____
... I" OJ .. • ~
BO-B35 W1 remains valid In mall1 re Ister after read)
FIFO Output Register

Figure 14. Timing for Mail1 Register and MBF1 Flag

~1EXAS
INSTRUMENTS
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 SN54ACT3641
1024 x 36
CLOCKED FIRST·IN, FIRST·OUT MEMORY
SGBS309 - AUGUST 1995

ClKB / \
tsu(EN2) H
------===~,-----------------
I
r- th(EN2)
'''-__..J/ ,'-_ _--1/
'-
, ,
W/RB
~\\).~ 'Pm
1 i'
MBB

ENB

BO-B35
1_
//ZZZ2ZIZ?IZ{
mz?flWJ4
~.
iW

,
ClKA /
' ....----1 ,'-----
------~--~\
'F
' ....---r'-oJ/
,
tpd(C.MF) -.j
~ ____________
r tpd(C-MF)
,)~-----
~I~-------J
-.j

\'
I '
'i,...-----
I ,
WiRA ~s~s:~s:~s:~s:~Si i I (/"""/,:"""/,:""";:"""/,:"'2"',/:"'<:'"";""'"

MBA
I ' tsu(EN1) ~ ~I th(EN1) ,
ENA

ten
I
1
H
':+I.----~I ' I//d)
tpd(C-MR)
\\\\\\'
~~~~I-----
tdls j.--...I
AO-A35 W1 (remains valid In mal12 re Ister after read)

Figure 15. Timing for Mall2 Register and MBF2 Flag

~1EXAs
INSTRUMENTS
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SN54ACT3641
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SGBS309 - AUGUST 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 7 V
Input voltage range, VI (see Note 1) .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo (see Note 1) ........................................ -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Vecl ............................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vecl ........................................... ±50 mA
Continuous output current, 10 (Vo = 0 to Vecl ............................................. ±50 mA
Continuous current through Vee or GND ................................................. ±400 mA
Operating free-air temperature range, TA .......................................... -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" Is not
Implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The Input and output voltage ratings may be exceeded provided the Input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT
Vee Supply voltage 4.5 5.5 V
VIH High-level Input voltage 2 V
VIL Low-level Input voltage 0.8 V
IOH High-level output current -4 mA
IOL Low-level output current 8 mA
TA Operating free-air temperature -55 125 ·e

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT
VOH Vee = 4.5 V, IOH --4 mA 2.4 V
VOL Vee=4.5V, IOL=8 mA 0.5 V
II Vee-5.5 V, VI_ Veeoro ±5 IiA
IOZ Vee=5.5V, Vo-Vee orO ±5 IiA
lee§ Vee = 5.5 V, VI = Vee - 0.2 V or 0 400 IiA
eSA-vIH AO-A35 0
eS8.v1H 80-835 0
Vee-5.5 V, One Input at 3.4 V,
dleell eSA=vIL AO-A35 1 mA
Other inputs at Vee or GND
eS8.VIL 80-835 1
All other Inputs 1
el VI = 0, f.1 MHz 4 pF
Co VO=O, f= 1 MHz 8 pF
:j: All typical values are at Vee = 5 V, TA = 25·e.
§ ICC is measured In the A to 8 direction.
11 This is the supply current when each Input is at one of the specified TTL voltage levels rather than 0 V or Vee.

-!I11ExAs
INSTRUMENTS
14-132 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 SN54ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309 - AUGUST 1995

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 15)
MIN MAX UNIT
fclock Clock frequency, ClKA or ClKB 50 MHz
Ie Clock cycle time, ClKA or ClKB 20 ns
twlCIj) Pulse duration, ClKA and ClKB high 8 ns
twlCl) Pulse duration, ClKA and ClKB low 8 ns
tsulD) Setup time, AO-A35 before ClKAi and BO-B35 before ClKBi 6 ns
tsulEN1) Setup time, ENA to ClKA!; ENB to ClKBi 6 ns
ISetup time, CSA, W/RA, and MBA to ClKAi; ese, W/RB, and MBB to ClKBi 7.5
ns
tsu(EN2)
IW/RA to ClKAi 9
tsulRM) Setup time, RTM and RFM to ClKB! 6.5 ns
tsulRS) Setup time, RST low before ClKAi or ClKBit 6 ns
tsulFS) Setup time, FSO and FSI before RST high 10 ns
tsulSD)* Setup time, FSO/SD before ClKAi 6 ns
tSUlSEN)* Setup time, FSl/SEN before ClKA! 6 ns
th(D) Hold time, AO-A35 after ClKAi and BO-B35 after ClKBi 0 ns
tnlEN1) Hold time, ENA after ClKAi; ENB after ClKBi 0 ns
Hold time, CSA, W/RA, and MBA after ClKAi;
tn(EN2) 0 ns
CSB, W/RB, and MBB after ClKBi
. tnlRM) Hold time, RTM and RFM aiter ClKB! 0 ns
th(RS) Hold time, RST low after ClKAi or ClKBi t 6 ns
thlFsl Hold time, FSO and FSI after RST high 0 ns
thlSP)* Hold time, FSl/SEN high after RST high 0 ns
th(SD)* Hold time, FSO/SD after ClKAi 0 ns
thlSEN)* Hold time, FSl/SEN after ClKAi 0 ns
tskll)§ Skew time between ClKAi and ClKBi for OR and IR 11 ns
t sk(2)§ Skew time between ClKAi and ClKB! for AE and AF 16 ns
t ReqUIrement to count the clock edge as one of at least four needed to reset a FIFO
* Only applies when serial load method is used to program flag offset registers
§ Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and
ClKBcycle.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALL.A$. TEXAS 75265 14-133
SN54ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309 - AUGUST 1995

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 1 through 15)
PARAMETER MIN MAX UNIT
ta Access time, CLKBi to BO-B35 3 15 ns
todIC-IR) Propagation delay time, CLKAi to IR 1 10 ns
tpdlC-ORI Propagation delay time, CLKBi to OR 1 10 ns
tpd(C-AE) Propagation delay time, CLKBi to AE 1 10 ns
tpdlC-AFI Propagation delay time, CLKA i to AF 1 10 ns
Propagation delay time, CLKA i to MBFl low or MBF2 high and
tpd(C-MF) 0 10 ns
CLKBi to MBF2 low or MBFl high
todIC-MRI Propagation delay time, CLKAito BO-B35t and CLKBi to AO-A35:j: 3 15 ns
tpd(M-DV) Propagation delay time, MBB to BO-B35 valid 3 15 ns
todIR-F) Propagation delay time, RST low to AE low and AF high 1 20 ns
Enable time, eSA and W/RA low to AO-A35 active and
ten 2 13 ns
CSB low and W/RB high to BO-B35 active
,
Disable time, CSA or W/RA high to AO-A35 at high impedance and
tdis 1 10 ns
CSB high or W/RB low to BO-835 at high impedance
..
t Wntlng data to the malll register when the BO-B35 outputs are active and MBB IS high
:j: Writing data to the mail2 register when the AO-A35 outputs are active and MBA is high

~1ExAs
INSTRUMENTS
14-134 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 SN54ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309 - AUGUST 1995

TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250~--r---r---r---r---r---r---'

~ 200 I---=-+--'--+----+----+---+-~-r--.,~
I

~
(3 1501---t---t---t---t7''--7'h,;c-t---I
~

JI 100 1---t---t-~'I7'"'7't---t---t---I
IE
8
501---~~r---t---t---t---t---I

10 20 30 40 50 60 70
fclock - Clock Frequency - MHz

Figure 16

calculating power dissipation

The lee(f) current in Figure 16 was taken while simultaneously reading and writing the FIFO on the
SN54ACT3641 with CLKA and CLKS set to fclock. All data inputs and data outputs change state during each
clock cycle to consume the highest supply current. Data outputs are disconnected to normalize the graph to a
zero-capacitance load. Once the capacitive load per data-output channel and the number of SN54ACT3641
inputs driven by TTL high levels are known, the power dissipation can be calculated with the equation below.
With lee(l) taken from Figure 16, the maximum power dissipation (PT) of the SN54ACT3641 can be calculated
by:
PT =Vee x [lee(l) + (N x Alec x dc)] + L(CL x Vee 2 x fa)
where:
N = number of inputs driven by TTL levels
Alec = increase in power supply current for each input at a TTL high level
dc = duty cycle of inputs at a TTL high level of 3.4 V
CL = output capacitive load
fa = switching frequency of an output
When no reads or writes are occurring on the SN54ACT3641 , the power dissipated by a single clock (CLKA
or CLKS) input running at frequency fclock is calculated by:
PT = Vee x fclock x 0.29 mA/MHz

-!II TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14-135
SN54ACT3641
1024 x 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGBS309 - AUGUST 1995

PARAMETER MEASUREMENT INFORMATION

SV

11000
From Output
Under Test - ......- - - - .

6800 -:: =-
30 pF
;;;" (see Note A)

LOAD CIRCUIT

Timing
Input ______ "
i ~~ __ _
3V High-Level
Input ----.Ii~
,.~ .
~.~
~
- 3V
GND
J~ GND

tsu~th 14-
I
tw ---.rI
Data, ~-:-,,--::- 3V
Enable ~ 1.SV ~ Low-Level ~ 1.S V _~ 3V
Input GND Input ~ ~~~ _ GND

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES PULSE DURATIONS

Output
Enable
J I 1.S V
\1.;-V---
3V

GND
-+i i~tPLZ ~ i4-tPZL

~
~3V
Low-Level 3V
\-;S:--
Output
! I(L+300mv I VOL
Input --1(1.SV
GND
I -+I ~tPZH ~tpd
VOH-300mV VOH
tpd --j4---+J
High-Level I VOH
I I
~
Output In-Phase
~OV
I I Output 11.sv
-+i l~tpHZ VOL

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES PROPAGATION DELAY TIMES

NOTE A: Includes probe and jig capacitance

Figure 17. Load Circuit and Voltage Waveforms

~ThxAs
INSTRUMENTS
14-136 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
15-1
 Contents
Page
FIFO Solutions for Increasing Clock Rates and Data Widths ...•.......... 15-5
FIFO Surface-Mount Package Information ••.......................•..•.. 15-15
FIFO Memories: Fine-Pitch Surface-Mount Manufacturability ........•.... 15-25
Metastability Performance of Clocked FIFOs ...•.•.•.•..•..........•.... 15-35
FIFO Memories: Solution to Reduce FIFO Metastability ...........•...... 15-47
Multiple-Queue First-In, First-Out Memory SN74ACT53861 ............... 15-53

»
""-
~
o
:::s
::c
CD

"a
o

lEI

15-2
INTRODUCTION
This section of application reports complements the information contained in the Texas Instruments 1996
High-Performance FIFO Memories Designer's Handbook (literature number SCAA012A) which provides an
expanded series of FIFO application reports and complete list of available very high-speed integrated circuits
(VHSIC) hardware-description language (VHDL) models. This section of the FIFO data book contains
information that is useful to the designer, such as sample power-dissipation calculations, mechanical packaging
data, thermal resistance data, and quality/reliability assurance information.
For further information on Texas Instrument FIFO products or applications, please contact the Advanced
System Logic holline at 903-868-5202.

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15-3
 FIFO Solutions
for Increasing Clock Rates
and Data Widths

First-In, First-Out Technology

Kam Kittrell
Advanced System Logic - Semiconductor Group

SZZAOO1A

:lllExAs
INSIRUMENTS

15-5
 IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.

TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale iii accordance with Tl's standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage ("Critical Applications',).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED

TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.

In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.

Copyright © 1996, Texas Instruments Incorporated

15-6
 Contents
Title Page
Introduction ............................................................................. 15-9
Clocked FIFOs ........................................................................... 15-9
Flag Synchronization ...................................................................... 15-9
Compact Packaging ...................................................................... 15-11
New Clocked FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-12
Conclusion ............................................................................. 15-13

List of Dlustrations
Figure Title Page
Triggering a Metastable Event With a One-Stage Synchronizer .............................. 15-10
2 Two-Stage Synchronizer ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
3 Storage Oscilloscope Plots Taken Over a 15-Hour Duration ................................ 15-11
4 Surface-Mount Package Area Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
5 Bidirectional Configuration for the SN74ACT7803 ....................................... 15-13

15-7
1!5-8
 Introduction
Steady increases in microprocessor operating frequencies and bus widths over recent years have challenged system designers
to fmd FIFO memories that meet their needs. To assist the designer, new FIFOs from Texas Instruments (TI) are available with
features that complement these microprocessor trends.
Higher data-transfer rates have dictated the need for FIFOs to evolve into clocked architecture wherein data is moved in and out
of the device with synchronous controls. Each synchronous control of the clocked FIFO uses enable signals that synchronize the
data exchange to afree-running (continuous) clock.
Since the continuous clocks on each port of a clocked FIFO can operate asynchronously to each other, internal status signals
indicating when the FIFO is empty or full can change with respect to either clock. To use a status signal for port control, it is
synchronized to the port's clock on a clocked FIFO. Synchronization of these signals with flip-flops introduces metastability
failures that increase with clock frequency. TI uses two-stage flag synchronization to greatly improve reliability.
Higher clock frequencies augment raw speed, but greater bandwidth is also achieved by increasing the data width. Wider
datapaths can have the associated cost oflarge board area due to increased package sizes. New compact packages for TI's FIFOs
reduce this cost.

Clocked FIFOs
Clocked FIFOs have become popular for relieving bottlenecks in high-speed data traffic. Data transfers for many systems are
synchronized to a central clock with read and write enables. These free-running clocks can be input directly to a clocked FIFO
with the saine enables controlling its data transfer on the low-to-high transition of the clock.
Reducing the number of clocks keeps the interface simple and easy to manage. Extra logic is needed to produce a gated pulse
when using a FIFO that accepts a clock only for a data transfer request. The generated clock signal is a derivative of the master
clock with a margin of timing uncertainty. At high clock frequencies, this timing uncertainty is not tolerable and costly
adjustments are needed.
Additional logic also is conserved by implementing flag synchronization on the clocked FIFO. Tracking is done to generate flags
that indicate when the memory is empty or full. In many applications, the input and output to the FIFO are asynchronous and the
flag signals must be synchronized for use as control. A read is not completed on the FIFO ifno data is ready, so the EMPTY signal
is synchronized to the read clock. This synchronous output-ready (OR) flag is useful for controlling read operations. Likewise,
the FULL signal is synchronized to the write clock, producing the input-ready (IR) flag.

Flag Synchronization
As previously explained, one of the advantages of the clocked FIFO is the on-board synchronization of the EMPTY and FULL
status flags when the input and output are asynchronous. In one method of synchronization, a single flip-flop captures the
asynchronous flag's value (see Figure 1). With this method, the rising transition of data can violate the flip-flop's setup time and
produce a metastable event (metastability is a malfunction of a flip-flop wherein the latch hangs between high and low states for
an indefinite period of time).

15-9
 Clock Q Synchronized
Flag

Asynchronous 0
Fisg

Clock I
--::o;!'"T1-I j.- tau

Flag_l..I..IfIJ
I
OR _ _ _ _.. I__t
tpd --I j.- tr
Figure 1. Triggering a Metastable Event With a One-Stage Synchronizer

Once a metastable event is triggered, the probability of the output recovering to a high or low level increases exponentially with
increased resolve time (tr). The expected time until the output of a single flip-flop with asynchronous data has a metastable event
that lasts tr or longer is characterized by the following mean time between failures (MTBF) equation:

exp(¥)
MTBFl = to fo fd

Where:
to - flip-flop constant representing the time window during which changing data invokes a failure
tr - resolve time allowed in excess of the normal propagation delay
t - flip-flop constant related to the settling time of a metastable event
fc - clock frequency
fd - asynchronous data frequency. For OR-flag analysis, it is the frequency at which data is
written to empty memory. For IR-flag analysis, it is the frequency at which data is read from
full memory.

The MTBF decreases as clock and data frequency increase and as the time allowed for a metastable event to settle (tr) decreases.
Metastability failures are a formidable issue for short-clock cycle times. Increasing the clock frequency linearly increases the
number of metastable events triggered, but the shortened available resolve time exponentially increases the failure rate. It is
impossible to eliminate the possibility of a metastable event under these conditions, but solutions exist to reliably increase the
expected time between failures.

Clock Q Q Synchronized
Flag

Asynchronous o o
Flag

Figure 2. 'TWo-Stage Synchronizer

15-10
TI increases the metastable MTBF by several orders of magnitude for IR and OR flags by employing two-stage synchronization
(see Figure 2). For the output of the second stage to be metastable, the first stage must have a metastable event that lingers until
it encroaches upon the setup time of the second stage. Adding another stage to a single flip-flop synchronizer is statistically
equivalent to increasing its resolve time by the clock period minus its propagation delay. The mean time between failures for a
two-stage synchronizer is given by:

exp [t' +t-tp]

"c

Where:
1:p - propagation delay of the first flip-flop

Sync f---J---J-,
EMPTY
I
H---+---I--+---+-H---t--- ----I
• •• •. . . . ~_B2!!1.~6. .-oLJ--~"&7.iU·-J
3 ns/dlv

=
fc 50 MHz, fd =5 MHZ, VCC =5 V fc =68.7 MHz, fd =6.7 MHz, Vee =5 V
(e) ONE-sTAGE SYNCHRONIZATION (b) TWO-STAGE SYNCHRONIZATION

Figure 3. Storage Oscilloscope Plots Taken Over a i5-Hour Duration

Figure 3 compares the two synchronization methods previously discussed. Both plots were taken at room temperature and
nominal Vee while each data transition violated setup time. Figure 3(a) shows the performance of an EMPTY flag.synchronizer
using only one flip-flop, while Figure 3(b) is the IR flag of an SN74ACT7807 with the write clock operating at maximum
frequency.

Compact Packaging
Microprocessor bus widths have continuously doubled every few years to maximize their performance. Bus widths of32 and 64
bits are commonplace today, whereas they were almost unheard of a few years ago. The downside to the increased bit count is
that each subordinate device in the system must match this width with corresponding increases in board size.
New shrink packages for TI's clocked FIFOs provide a solution to this problem. Multiple-byte datapaths can be buffered while
covering only a fraction of the area of conventional packages. These new FIFO packages are presently available in 56-, 64-, and
80-pin configurations. Dubbed shrink quad flat package (SQFP), the 64-pin package is used for 9-bit-wide FlFOs, and the 80-pin
package is used for 18-bit-wide FlFOs. Both SQFP packages have a lead pitch of 0.5 mm. The 56-pin shrink small-outline
package has aO.025-inch lead pitch and also houses 18-bit-wideFlFOs.Avariety ofTI'sFlFOs are offered in these new packages
(see Table 1).

15-11
 Table 1. FIFOs Available In Space-Efficient Packages
CLOCKCVCLE
DEVICE CLOCKED ORGANIZATION PACKAGES
TIME (ns)
64 TQFP
SN74ACT2235 No 1K x 9 x 2 20,3040,50
44 PLCC
80TQFP
SN74ACT7802 No 1Kx 18 25,40,60
68 PLCC
80TQFP
SN74ACT7811 Ves lKx 18 15,18,20,25
68 PLCC
SN74ACT7803 512 x 18
SN74ACT7805 Yes 256 x 18 15,20,25,40 56SS0P
SN74ACT7813 64x 18
SN74ACT7804 512 x 18
SN74ACT7806 No 256 x 18 20,25,40 56SS0P
SN74ACT7814 64x 18
64 TQFP
SN74ACT7807 Yes 2Kx9 15,20,25,40
44 PLCC
64 TQFP
SN74ACT7808 No 2Kx9 20,25,30,40
44 PLCC

Figure 4 compares the space savings of the new compact packages compared to competitive surface-mount solutions. A 4-byte
path constructed with four clocked FlFOs in 32-pin PLCC packages occupies 1.16 in2, while two 56-pin SSOP packages occupy
only 0.59 in2.

0.9

0.8

0.7

C'II 0.6
c
0::-
0.5
~
c( 0.4

0.3

0.2

0.1

0
64 TQFP 56 SSOP 80 SQFP 32 PLCC 44 PLCC 68 PLCC

Figure 4. Surface-Mount Package Area Comparison

New Clocked FIFOs

Four new CMOS clocked FIFOs from TI offer a variety of memory depths. All four can match applications that require maximum
clock frequencies of 67 MHz and access times of 12 ns. Suited for buffering long packets, the 2K x 9 SN74ACT7807 is the deepest
of the four and is available in the 44-pin PLCC or 64-pin TQFP. The SN74ACT7803, SN74ACT7805, and SN74ACT7813 are
organized as 512 x 18,256 x 18, and 64 x 18, respectively, and have the same pin arrangement in the 56-pin SSOP. Every TI

15-12
clocked FIFO is easily expanded in word width, and the SN74ACT7803/05/13 can also be arranged to fonn a bidirectional FIFO.
With the two FIFOs connected as in Figure 5, no extra logic is needed for bidirectional operation.
'ACT7803
ClKA WflTCLK flDCLI( ClKB
W/RA WIITENi OEi wiRB
CSA WR'i'EN2 flDEN CSB
OE2 U
18
DO-Di7 QO-Qi7 BO-B17

'ACT7803
flDCLK WflTCLK r-
" - OEi WIITENi f - -
flDEN WIITEN2
L OE2

18
AO-A17 , QO-Qi7 DO-Di7

Figure 5. Bidirectional Configuration for the SN74ACT7803

Silicon is currently available for a bidirectional clocked FIFO fabricated in TI's Advanced BiCMOS (ABT) process. The
SN7 4ABT7819 is organized as 512 x 18 x 2 with two internal independentFIFOs. Each port has a continuous free-running clock,
a chip select (CS), a read/write select (RJw), and two separate read and write enables for control. It supports clock frequencies
in excess of 80 MHz and a maximum access time below 10 ns. This device is packaged in the 80-pin QFP and SO-pin SQFP.

Conclusion
Several semiconductor manufacturers, including TI, have responded to customer needs by providing clocked FIFOs whose
synchronous interfaces confonn to the requirements of many high-perfonnance systems. Capitalizing on the available continuous
system clocks, this architecture limits the amount of necessary glue logic and the number of timing constraints.
Flag synchronization is important for clocked FIFOs buffering between asynchronous systems. Flip-flop synchronizers used for
this task have a metastable failure rate that grows exponentially with clock frequency. TI employs two stages of synchronization
that improve the flags' reliability significantly.
Finally, providing a FIFO buffer for wide buses has historically consumed large amounts of board area. Designers seeking relief
from this problem can fmd it in the packaging options offered for TI's FIFOs. Used to house 9- and 18-bit devices, these packages
require only about 50% of the space required for conventional surface-mount packages.

15-13
15-14
 FIFO Surface-Mount
Package Information
First-In, First-Out Technology

Tom Jackson and Mary HelmIck

Advanced System LogIc - SemIconductor Group

SSPAOO1A

:'IlExAs
INSTRUMENTS

15-15
 IMPORTANT NOTICE
Texas Instruments (TIl reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.

TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with Tl's standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage ("Critical Applications'1.

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED

TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written a.pproval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.

In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.

Copyright © 1996, Texas Instruments Incorporated

15-16
 Contents
Title Page
Introduction ............................................................................ 15-19
Thermal Resistance ...................................................................... 15-19
Package Moisture Sensitivity .............................................................. 15-20
Shipping Methods/QuantitieslDry Pack .................................................... 15-21
Package Dimensions and Area Comparison .................................................. 15-21
Test Sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-23

15-17
15-18
 Introduction
Texas Instruments provides seven types of plastic surface-mount packages for CMOS FIFO memory devices. These packages
and the data bus width that each package can provide are listed in Table 1.

Table 1. Plastic Surface-Mount FIFO Packages

PACKAGE NO. OF DATA BITS
44-pin PLCC 9
64-pinTQFP 9
56-pin SSOP 18
68-pin PLCC 18
80-pinTQFP 18
80-pin QFP 18
120-pin TQFP 32 or 36
SSOP = shrink small-outline package
PLCC = plastic leaded chip carrier
TQFP = thin quad flat package
QFP = quad flat package

This application report discusses several topics concerning the FIFO packages listed in Table 1:
• The thermal resistance, RElJA, and the chip junction temperature of the device
• The need for dry packing to maintain safe moisture levels inside the package
• The three methods used by Texas Instruments for shipping FIFOs to customers
• The package dimensions, including two-dimensional drawings that show areas, heights, and lead pitches
• The area comparison of surface-mount packages used for commercial FIFO memories
• The test sockets available for surface-mount FIFO packages

Thermal Resistance
Thermal resistance is defined as the ability of a package to dissipate heat generated by an electronic device and is characterized
by RElJA. RElJA is the thermal resistance from the integrated circuit chip junction to the free air (ambient). Units for this parameter
are in degrees Celsius per watt. Table 2 lists RElJA for SSOP, PLCC, TQFP, and QFP packages under five different air-flow
environments: 0, 100, 200, 250, and 500 linear feet/minute. The chip junction temperature (TJ) can be determined using
equation 1.

(1)

Where:
TJ chip junction temperature (0C)
ReJA - thermal resistance, junction to free-air (OC/watt)
PT - total power dissipation of the device (watts)
TA - free-air (ambient) temperature in the particular environment in which the device is operating CC)

15-19
 Table 2. Thermal Resistance, RaJA, for FIFO Packages
LEAD ReJA("C/W)
PACKAGE
FRAME OLFPM 100 LFPM 200LFPM 250LFPM 500LFPM
56-pin SSOP Copper 94.2 82.2 N/A 70 57.8
44-pin PLCC Copper 65 N/A N/A NlA N/A
68-pin PLCC Copper 47.2 43.4 N/A 32.7 27.8
64-pinTQFP Copper 92.5 87.8 N/A 72.9 57.8
80-pinTQFP Copper 87.8 79.1 N/A 67.3 54.2
120-pin TQFPt Copper 49.6 44.3 N/A 3S.3 28.6
SO-pin QFP Alloy 42 SO 67 61 N/A N/A
t Heat slug molded inside the package
NIA = not available
The RaJA generally increases with decreasing package size; however, this is not true with the 120-pin SQFP package. A heat
slug molded inside the package absorbs a large amount of heat dissipated by the device. As a result, this package provides a
relatively low RaJA.

Package Moisture Sensitivity

When a plastic surface-mount package is exposed to temperatures typical of furnace reflow, infrared (IR) soldering, or wave
soldering (215°C or higher), the moisture absorbed by the package turns to steam and expands rapidly. The stress caused by this
expanding moisture results in internal and external cracking of the package that leads to reliability failures. Possible damage
includes the delamination of the plastic from the chip surface and lead frame, damaged bonds, cratering beneath the bonds, and
external package cracks.
To prevent potential damage, packages that are susceptible to the effects of moisture expansion undergo a process called dry pack.
This dry pack process helps to reduce moisture levels inside the package. The process consists of a 24-hour bake at 125°C
followed by sealing of the packages in moisture-barrier bags with desiccant to prevent reabsorption of moisture during the
shipping and storage processes. These moisture-barrier bags allow a shelf storage of 12 months from the date of seal. Once the
moisture-barrier bag is opened, the devices in it must be handled by one of the following four methods, listed in order of
preference:
The devices may be mounted within 48 hours in an atmospheric environment ofless than 60% relative humidity and
less than 30°C.
The devices may be stored outside the moisture-barrier bag in a dry-atmospheric environment ofless than 20% relative
humidity until future use.
The devices may be resealed in the moisture-barrier bag adding new fresh desiccant to the bag. When the bag is opened
again, the devices should be used within the 48-hour time limit or resealed again with fresh desiccant.
The devices may be resealed in the moisture-barrier bag using the original desiccant. This method does not allow the
floor life of the devices to be extended. The cumulative exposure time before reflow must not exceed a total of 48 hours.
All plastic surface-mount FIFO devices are tested for moisture sensitivity in accordance with Texas Instruments
JESD A112 procedure.

15-20
 Shipping Methods/Quantities/Dry Pack
Three methods are used by Texas Instruments for shipping FIFOs to customers. These methods are tubes, tape/reel, and trays.
The quantities for each of the shipping methods are listed in Table 3. The shipping quantity is defmed as the maximum number
of packages that can be packed in a single shipping unit (e.g., the maximum number of 56-pin SSOP packages that can be packed
in a tube is 20). Whether or not the packages require dry pack before shipping is noted in the dry-pack column.

Table 3. Shipping Methods and Quantities

SHIPPING METHOD
PACKAGE DRY PACK
TUBEt TAPEIREELt TRAYSt
56-pin SSOP 20 500 N/A No
44-pin PLCC 27 500 N/A No
6S-pin PLCC 18119:1= 250 N/A Yes
64-pin TQFP NlA N/A 160 Yes
SO-pin TQFP NlA N/A 119 Yes
120-pin TQFP NlA N/A 90 Yes
So-pinTQFP N/A N/A 50 Yes
.. at any time without
t Texas Instruments reserves the right to change any olthe shipping quantities
notice.
Eighteen packages can be packed in a single tube when pin is used as a tap or nineteen
:1=
packages can be packed in a tube when plug is used as a tap.
N/A = not applicable

Package Dimensions and Area Comparison

Figure 1 contains two-dimensional drawings of the seven available surface-mount FIFO packages. For detailed mechanical
drawings of these packages, please refer to the mechanical drawing section of the 1994 High-Performance FIFO Memories Data
Book, literature #SCADOO3B.

15-21
 ~14.0-~
14--- 16.0 --.t

I T 12().pln
14.0
I
.1
8().pln
TQFP
0 (PN) 1
16.0
0
TQFP
(PCB)

Area: 144.00 mm 2 Area: 196.00 mm2 Area: 256.00 mm2

Height: 1.50 mm (PM) Height: 1.50 mm Height: 1.6mm
Height: 1.0 mm (PAG) Lead Pitch: 0.5 mm Lead Pitch: 0.4 mm
Lead Pitch: 0.5 mm

~14--25.2 --to!

1
~~·
I+-.- 17.6 --+I

I 44-pln
PLCC
1
25.2
68-pln
PLCC

~
1 (FNI

Area: 309.60 mm2 Area: 635.04 mm2

Height: 4.37 mm Height: 4.37 mm
Lead Pitch: 1.27 mm Lead Pitch: 1.27 mm

I+- 23.6 --~~

~16.4~
,I
Area: 189.50 mm2
1 Area: 415.40 mm2
Height: 2.59 mm Height: 2.95 mm
Lead Pitch: 0.635 mm Lead Pitch: 0.8 mm

Figure 1. Package Dimensions

15-22
Figure 2 shows the area comparison of surface-mount packages for FIFOs from Texas Instruments and other FIFO vendors.

64-PlnTQFP
9-Blt-Wlde
Data { 32-Pln PLCC

44-Pln PLCC

56-PlnSSOP

SO-PlnTQFP
18-Blt-Wlde
Data
{ SO-Pln QFP

68-Pln PLCC

32- or
36-Blt-Wlde { 12o-Pln TQFP • • • • • • • • • • • • •
Data 132-Pln QFP l1li

o 100 200 300 400 500 600 700 600 9001000

Area (mm 2)

Figure 2. Surface-Mount Package Area Comparison

Test Sockets
For prototype development of a system, it is often an advantage to have sockets for surface-mount products. Test sockets available
for use with Texas Instruments FIFO packages are listed in Table 4. Only one manufacturer is listed for each socket type, although
other vendors may offer comparable sockets.

Table 4. Test Sockets for FIFO Packages

PACKAGE MANUFACTURER NUMBER DESCRIPTION
56-pin SSOP Yamaichi IC51-0562-13S7 Solder through hole
44-pin PLCC NEY 6044 Solder through hole
6S-pin PLCC NEY 606S Solder through hole
64-pinTQFP Yamaichi IC51-0644-807 Solder through hole
SO-pin TQFP Yamaichi IC51-0S04-80S Solder through hole
120-pin TQFP Yamaichi IC51-1204-1596 Solder through hole
SO-pin QFP Yamaichi IC51-0S04-394 Solder through hole

15-23
15-24
 FIFO Memories:
Fine-Pitch Surface-Mount
Man ufac turability
First-In, First-Out Technology

Tom Jackson
Advanced System Logic - Semiconductor Group

SCZA003A

~TEXAS
INSTRUMENTS

15-25
 IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.

TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage ("Critical Applications").

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED

TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.

In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.

Copyright © 1996, Texas Instruments Incorporated

15-26
 Contents
Title Page
Introduction ............................................................................ 15-29
Improved Function Density ............................................................... 15-29
Manufacturing .......................................................................... 15-29
Palladium-Plated Lead Frames ............................................................ 15-31
Testability .............................................................................. 15-32
Design/Preproduction Considerations ...................................................... 15-32
Conclusion ............................................................................. 15-33
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-33

List of Tables
Table Title Page
1 Fine-Pitch Packages ................................................................ 15-29
2 Defect Causes and Effects .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-30
3 Results of Soldered loint Strength .................................................... 15-31
4 Lead-Frame Platings by Package Type •••••..•.•.•......•........•.•....•••......•.•••. 15-32
5 Available Fine-Pitch Test Sockets and Mechanical Packages ................................ 15-33

15-27
15-28
 Introduction
Recent advances in semiconductor processing and packaging have produced highly integrated, fme-pitch devices to satisfy the
demand for smaller systems. With the trend towards higher chip complexity occupying less board space, device manufacturers
must increase bit density while decreasing package size. To accommodate these requirements, manufacturers have two choices:
increase bit density, keeping the number of pins constant while reducing pitch and area, or reduce the package lead pitch, keeping
area constant while increasing pin count. Manufacturers of hand-held and laptop computers and data communications and
telecommunications equipment require the use of fine-pitch packages to build and maintain a competitive advantage.

Improved Function Density

Texas Instruments (TI) provides five types offine-pitch plastic surface-mount packages for its FIFO product line (see Table 1).
Each of these surface-mount packages has lead-to-Iead spacing less than or equal to 0.635 mm (0.025 in.). All of these packages
offer designers critical board-space savings that is required for advanced systems. Compared to the commonly used 68-pin plastic
leaded chip carrier (PLCC) for I8-bit FIFOs, n's Widebus™ package, in either the 56-pin shrink small-outline package (SSOP)
or the 80-pin thin quad flat package (TQFP), reduces board space by 70%. A 67% saving of board space is available with TI's
36-bit FIFO family in the 120-pin TQFP compared to the 132-pin plastic quad flat package (PQFP).
Table 1. Fine-Pitch Packages
THIN SHRINK
THIN QUAD FLAT PACKAGE (TQFP) SMALL-OUTLINE
PACKAGE (SSOP)
Pin count 64 80 120 132 56
Lead pitch (mm) 0.5 0.5 0.4 0.635 0.635
Footprint (mm) 12 x 12 14 x 14 16 x 16 28x28 10.35 x 18.42
Board area (mm 2) 144 196 256 784 190.6
Package suffix PM PN PCB PO DL

Manufacturing
Manufacturers are currently employing high-volume board-assembly techniques using standard lead pitches of 0.5 mm (20 mils)
and greater. However, as lead pitch continues to decrease, questions must be asked of both the manufacturer and the supplier:
Are fine-pitch packaging capabilities available?
Does production equipment have sufficient accuracy to produce high-volume, high-quality parts?
Do the manufacturing personnel have experience inhigh-volume, high-quality production using fine-pitch packaging?
Have the testability issues of fine-pitch packaging been considered?
Standard processing techniques such as those used with surface-mount rigid-lead packages become difficult with fine-pitch
packaging. Manufacturing issues may arise from compromises in screen-printing techniques, solder boardllead coplanarity,
placement-accuracy requirements of components, and solder deposition methods (e.g., mass reflowing). All of these factors can
result in shorts or opens due to poor placement, too much solder, or not enough solder. These issues influence the overall yield
and reliability of the product.

Widebus is a trademark of Texas Instruments Incorporated.

15-29
Equipment for the placement of fme-pitch packaging must feature a highly accurate positioning system. Placement accuracy for
fine-pitch packages must increase as lead pitch decreases. Misaligned packages and boards greatly reduce production yields as
well as throughput. Systems that feature state-of-the-art machine vision, align and inspect leads, and calculate registration with
an extremely high degree of accuracy and repeatability, ensure high production yields. There must also be careful control over
the Z-axis pressure when placing these fme-pitch packages to protect the lead coplanarity. Currently, there are systems available
with accurate placement as fme as O.1-mm pitch.
One of the most critical issues facing the manufacturer is the reliability of the footprint design. Constraints include the length
and width of the footprint and the amount of solder paste used to produce a good joint. If too much solder is used, the footprint
can bridge, causing a short (see Table 2). The minute dimensions associated with fine-pitch packages require that the footprint
be drawn to the highest level of accuracy in order to ensure consistent reliability. Board assemblers must be able to match the
footprint with the same level of accuracy and repeatability.
Table 2. Defect Causes and Effects
DEFECT CONTROL
Solder bridging Control the solder-paste quantity
Open circuits Control solder-paste thickness and maintain lead coplanarity
Shorts and opens Control equipment accuracy in the placement of parts

As previously discussed, the key to ensuring high yield is an accurate footprint pattern. Many manufacturers request footprint
patterns and dimensions to assist in their board assembly. There are several factors to consider when designing a footprint pattern
to ensure reliability:
• Device design - JEDEC or EIAJ Standard
• PWB - foil thickness, number of layers, supplier's capabilities
• Solder paste - type, solder mesh
• Printer - manufacturer, standoff control, squeegee pressure
• Print mask - type (stencil/mesh), tension, bias
• Reflow process - preheat, temperature, dwell, etc.
The key dimensions for designing an accurate footprint layout are shown in Figure 1.

A = Distance Package Edge to End of Pad

B1 = Pad Extension Beyond Heel of Foot
B2 = Pad Extension Beyond Toe of Foot
L = Lead Foot Length
P = Lead Pitch
S = Distance From Center of Pin to Center of Pin
l----i-..,,-z~ ~ s
~Zzzz.z.!Zilf­
-~

Figure 3. Footprint Diagram

15-30
 Palladium· Plated Lead Frames
Another area for manufacturers to investigate is metallization, or bonding of the leads to the circuit board with solder. There are
several widely used localized reflow techniques including hand soldering, hot bar, focused infrared (IR), and laser. With each
technique, heat is applied to the leads until the solder melts. When the heat source is removed, the solder cools forming the joint.
Each manufacturer must make the choice between precision point-to-point systems (one chip at a time) and the speed of gang
bonding (multiple chip bonding). Another area of metallization to consider is preplating of the leads by the device manufacturer.
TI has begun to implement palladium (Pd) lead plating on many fme-pitch packages. These efforts began with joint testing of
palladium-plated leads with several large computer and telecom customers in 1987. Since then, TI has begun high-volume
manufacturing with over five billion palladium-plated devices in the field.
Palladium preplating is essentially a nickel- (Ni) plated lead frame that has a minimum of 3 micro inches (0.076 micron) of Pd.
The Pd finish protects the Ni from oxidation and eliminates the need for silver spotting. Silver (Ag) spots are used to attach the
fme wires from the die to the lead frames. However, the silver can migrate over time to form extraneous electrical contacts that
greatly impact reliability. Many problems associated with fine-pitch manufacturing can be eliminated with palladium preplating:
• Reduces excess solder
• Excellent Pd wetting characteristics
• Reduced handling
• Improved package integrity
• Reduced mechanical damage
• Tarnish resistant
• Compatible with existing assembly processes
• Excellent adhesion to mold compounds
Table 3 shows the results of a SOlder-joint strength test comparing Pd solder joints to traditional solder joints. The results
demonstrate an equal performance between the two techniques. Palladium preplating also exhibits adhesion to most mold
compounds, which reduces moisture ingress and plastic-to-Iead-frame delimitation.
Table 3. Results of Soldered Joint Strength
HOURS OF HEAT AGING
SAMPLE
OHR 8HR 16HR 24HR
3 microinches Pd 5.171bf 5.951bf 5.851bf 4.711bf
Solder dip 5.071bf 4.511bf 5.551bf 5.501bf

In many cases, the cause for shorts and opens can be attributed to lead coplanarity, or the extent to which all leads lie in a single
plane. This holds especially true for fine-pitch packaging due to the smaller geometries and delicate leads. Traditional
solder-dipped leads tend to have more pin-to-pin alignment problems than the Pd-plated leads. The Pd-preplated leads have a
more conformal and uniform coating thim those that are solder dipped since the plating is performed prior to the packaging process
(see Figure 4). An increase in coplanarity improves overall circuit reliability. The excellent wetting characteristics ofPd improve
the wicking effects of solder and form a better solder jointl fillet. The thin Pd coating and minimal handling reduce the chance
of coplanarity problems (Le., shorts and opens) and also produce uniform solder joints with a minimum amount of solder. Table
4 lists TI's fine-pitch packages that implement Pd plating. '

1H1
 COPLANARITY
vs
%OFVALUE
40

35

30

!
25 o PdUnlts

:i 20 • Dipped Units
'0
'#. 15

10

0 n ,..,. •
0.2 0.4 0.6 0.8 1.2 1.4 1.8
Coplanarlty (mm)

Figure 4. Coplanarlty Results

Table 4. Lead-Frame Platings by Package Type

PACKAGE SUFFIX LEAD FRAME
132-pin PQFP PQ Palladium
120-pin TQFP PCB Palladium
SO-pin TQFP PN Solder
64-pin TQFP PM Solder
56-pin SSOP DL Palladium

Testability
Another issue introduced by the onset of fme-pitch surface-mount packages involves testing circuit boards. With denser
printed-circuit boards heavily populated with fine-pitch surface-mount packages, the issues involved with functional testing
should be addressed. One of the most cost-effective solutions is the implementation of boundary-scan methodology defmed by
the joint test action group (JTAG) and adopted by the IEEE 1149.1 committee. JTAG devices incorporate on-chip test points
called boundary-scan cells and utilize a serial-scan protocol through the device. Devices with JTAG can be designed into the
datapath and provide the controllability and observability needed to troubleshoot manufacturing defects.

Deslgnl Preproduction Considerations

For designers who wish to implement fine-pitch packaging, TI provides an easy alternative for the development of prototypes
and breadboarding. TI has worked with several test-socket manufacturers who provide accurate and easy-to-use through-hole
test sockets for all of their surface-mount packaging. In addition to test sockets, TI also offers mechanical packages. These are
packages that include lead frames without the silicon and meet all mechanical specifications. Mechanical packages provide an
inexpensive means for manufacturing capability studies, machine setup, personnel training, and process-development work (see
Table 5).

15-32
 Table 5. Available Fine-Pitch Test Sockets and Mechanical Packages
SOCKET MANUFACTURER PART NUMBER DESCRIPTION
TYPE
64-plnTQFP Yamaichi 1051-0644-807 Through hole
56-pinSSOP Yamaichi IC51-0562-1514 Through hole
8O-pinTQFP Yamaichl 1051-0804-808 Through hole
12D-pln TQFP Yamaichi IC51-1204-1596 Through hole
132-pin PQFP Yamaichi IC51-828-KS 12338 Through hole

PACKAGE TI PART NUMBER

64-pinTQFP SN700870PM
58-plnSSOP SN250011DLR
8D-pinTQFP SN700871PN
12D-pln TQFP SN700782PCB

Conclusion

Designs that incorporate fine-pitch packages have the advantage of critical board-space reduction. As designers continue to
implement higher levels of integration, board space remains at a premium. With the implementation of concurrent engineering
practices from design to test to manufacturing, many packaging difficulties can be overcome. Fine-pitch packaging is the
designers' easiest option to reduce critical board space without the loss of higher chip integration.

References

Abbott, D.C., Brook, R.M., Mclelland, N., Wiley, J.S., "Palladium as a Lead Finish for Surface Mount Integrated Circuit
Packages," IEEE Transaction on Components, Hybrid Manufacturing Tech., Vol. 14, No.3, Sept. 1991.
Romm, D., Mclellan, N., "Evaluation of Water Soluble and No-Clean Solder Pastes with Palladium Plated and Solder Plated
SMT Devices."

15-33
15-34
Metastability Performance
of Clocked FIFOs

First-In, First-Out Technology

Chris WeI/heuser
Advanced System Logic - Semiconductor Group

SCZA004A

~TEXAS
INSTRUMENTS

15-35
 IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.

TI warrants performance of Its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with Tl's standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage ("Critical Applications',.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.

Inclusion of TI products In such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to Tlthrough a local SC sales office.

In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.

Copyright © 1996, Texas Instruments Incorporated

15-36
 Contents
TItle Page

Introduction ............................................................................ 15-39

Metastability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-39
TI Clocked FlFOs ....................................................................... 15-41
Test Setup for Measuring FIFO Flag Metastablllty ............................................ 15-42
Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-44
MTBF Comparisons ..................................................................... 15-45
Conclusion ............................................................................. 15-46
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-46

15-37
15-38
 Introduction
This report is intended to help the user understand more clearly the issues relating to the metastable performance of Texas
Instruments (TI) clocked FIFOs in asynchronous-system applications. It discusses basic metastable-operation theory, shows the
equations used to calculate metastable failure rates for one and two stages of synchronization, and describes the approach TI has
used for synchronizing the status flags on its series of clocked FIFOs. Additionally, a test setup for measuring the failure rate of
a device to determine its metastability parameters is shown and results are given for both an advanced BiCMOS (ABT) FIFO
and an advanced CMOS (ACT) FIFO. Using these parameters, calculations of MTBF under varying conditions are performed.

Metastability
Metastability in digital systems occurs when two asynchronous signals combine in such a way that their resulting output goes
to an indeterminate state. A common example is the case of data violating the setup and hold specifications of a latch or a flip-flop.
In a synchronous system, the data always has a fixed relationship with respect to the clock. When that relationship obeys the setup
and hold requirements for the device, the output goes to a valid state within its specified propagation delay time. However, in
an asynchronous system, the relationship between data and clock is not fixed; therefore, occasional violations of setup and hold
times can occur. When this happens, the output may go to an intermediate level between its two valid states and remain there for
an indefinite amount of time before resolving itself or it may simply be delayed before making a normal transition 1. In either case,
a metastable event has occurred.
Metastable events can occur in a system without causing a problem, so it is necessary to define what constitutes a failure before
attempting to calculate a failure rate. For a simple CMOS latch, as shown in Figure I, valid data must be present on the input for
a specified period of time before the clock signal arrives (setup time) and must remain valid for a specified period of time after
the clock transition (hold time) to assure that the output functions predictably. This leaves a small window of time with respect
to the clock (to) during which the data is not allowed to change. If a data edge occurs within this aperture, the output may go to
an intermediate level and remain there for an indefinite amount of time before resolving itself either high or low, as illustrated
in Figure 2. This metastable event can cause a failure only if the output has not resolved itself by the time that it must be valid
for use (for example, as an input to another stage); therefore, the amount of resolve time allowed a device plays a large role in
calculating its failure rate.

Data
Input

Clock
C$] I ~ J
~ Output

Figure 1. A Simple CMOS Latch

{
j4--tau-'"
I J4- th-t\
Clock
~.~-~*
I 1

1
Data 1
Input 1
1 I.- tr ~I
1 1 I
Output 1 1
I I I i<
Figure 2. Output at Intermediate Level Due to Data Edge Within to Aperture

15-39
The probability of a metastable state persisting longer than a time, tr. decreases exponentially as tr increases2. This relationship
can be characterized by equation 1:

f - e{ - tr/t) (1)
(r) -

where the function f(r) is the probability ofnonresolution as a function of resolve time allowed, tr. and the circuit time constant
t (which has also been shown to be inversely proportional to the gain-bandwidth product of the circuit)3.4.
For a single-stage synchronizer with a given clock frequency and an asynchronous data edge that has a uniform probability density
within the clock period, the rate of generation of metastable events can be calculated by taking the ratio of the setup and hold time
window previously described to the time between clock edges and multiplying by the data edge frequency. This generation rate
of metastable events coupled with the probability of nonresolution of an event as a function of the time allowed for resolution
gives the failure rate for that set of conditions. The inverse of the failure rate is the mean time between failure (MTBF) of the
device and is calculated with the formula shown in equation 2:

1 e{tr/t)
(2)
failure rate = MTBF I = to fc fd

Where:
tr - resolve time allowed in excess of the normal propagation delay time of the device
t - metastability time constant for a flip-flop
to - a constant related to the width of the time window or aperture wherein a data edge
triggers a metastable event
fc = clock frequency
fd _ asynchronous data edge frequency

The parameters to and t are constants that are related to the electrical characteristics of the device in question. The simplest way
to determine their values is to measure the failure rate of the device under specified conditions and solve for them directly. If the
failure rate of a device is measured at different resolve times and plotted, the result is an exponentially decaying curve. When
plotted on a semilogarithmic scale, this becomes a straight line the slope of which is equal to t; therefore, two data points on the
line are sufficient to calculate the value of t using equation 3:
tr2 - trl
(3)
t = In(NI/N2)
Where:
trl - resolve time I
tr2 - resolve time 2
NI - number of failures relative to trl
N2 - number of failures relative to tr2

After determining the value for t, to may be solved for directly.

The formula for calculating the MTBF of a two-stage synchronizer, equation 4, is merely an extension of equation 2:

(4)

Where:
trl - resolve time allowed for the first stage of the synchronizer
tr2 - resolve time allowed in excess of the normal propagation delay
feo fd, t, and to are as previously defined, with t and to assumed to be the same for both stages.

15-40
The first term calculates the MTBF of the first stage of the synchronizer, which in effect becomes the generation rate of metastable
events for the next stage. The second term then calculates the probability that the metastable event will be resolved based on the
value of tr2, the resolve time allowed external to the synchronizer. The product of the two terms gives the overall MTBF for the
two-stage synchronizer.

TI Clocked FIFOs
The TI clocked FIFOs are designed to reduce the occurrence of metastable errors due to asynchronous operation. This is achieved
through the use of two- and three-stage synchronizing circuits that generate the status-flag outputs input ready (IR) and output
ready (OR). In a typical application, words may be written to and then read from the FIFO at varying rates independent of one
another, resulting in asynchronous flag-signal generation (internally) at the boundary conditions of full and empty; for example,
the operation when the FIFO is at the full boundary condition with writes taking place faster than and asynchronous to reads. The
IR flag is low, signifying that the FIFO is full and can accept no more words. When a read occurs, the FIFO is no longer completely
full. This causes an internal flag signal to go high, allowing another write to take place. Since the exit from the full state happens
asynchronously to the write clock (WRTCLK) of the FIFO, this flag is not useful as a system write-enable signal. The solution
is to synchronize this internal flag to the write clock through two D-type flip-flop stages and output this synchronized signal as
the IR flag (see Figure 3). The OR status flag is generated in a similar manner at the empty boundary condition and is synchronized
to the read clock through a three-stage synchronizing circuit.

Internal
Asynchronous IR
Flag Signal
Internal Logic Delay

WRTCLK----~----------------------------------------~

Figure 3. IR-Flag Synchronizer

The remainder of this report pertains to the metastability performance of the two-stage IR synchronizer, which is the limiting case
of the two in terms of MTBF characteristics. The internal flag signal that goes high on a read and low on a write is synchronized
to the write clock through two D-type flip-flop stages. Since this results in the IR flag status of the FIFO being delayed for two
clock cycles, a predictive circuit is used to clock the status into the synchronizer at (full minus two) words so that the action of
the IR flag going low coincides with the actual full status of the FIFO. However, once the FIFO is full and IR is low, a read that
causes the internal flag to go high is not reflected in the status of the IR flag until two write clocks occur.
With the FIFO full and the IR flag low, a read causes the internal flag signal to go high. This signal is clocked into the first stage
of the two-stage synchronizer on the next write clock. Because these two signals are asynchronous to one another, the potential
for the output of the first stage of the synchronizer to go to a metastable state exists. If this condition persists until the next write
clock rising edge, a metastable condition could be generated in the second stage and reflected on the IR flag output. This
metastable condition manifests itself as a delay in propagation time and is considered a failure only if it exceeds the maximum
delay allowed in a design.
The effectiveness of the two-stage synchronizer becomes apparent when attempting to generate failures at a rate high enough
to count in a reasonable period of time. A metastable event generated in the first stage must persist until the next write clock, i.e.,
when that data is transferred to the second stage. The resolve time for the first stage is governed by the frequency or period of
the write clock. At slower frequencies, the failure rate of the first stage is very low, resulting in a low metastable generation rate
to the second stage. The second stage of the synchronizer further reduces the probability of a metastable failure based on the
resolve time allowed at the output. The overall failure rate of the device may be affected by increasing the initial asynchronous
data generation rate (adding jitter to the data centered about the setup and hold window), by decreasing the resolve time of the
first stage (increasing the write clock frequency), and by reducing the external resolve time at the output.

15-41
 Test Setup for Measuring FIFO Flag Metastability
The failure rate of a device is measured on a test fixture as shown in Figure 4. The input waveforms used. on this setup are also
shown in Figure 4. Rising data is jittered asynchronously about the setup and hold aperture of the device under test (DUT) in a
±400-ps window with respect to the device clock (CLK). The output of the DUT is then clocked into two separate flip-flops, FF1
and FF2, by two different clock signals, CLK1 and CLK2. The resolve time, tr. is set by the relationship between CLK 1 and CLK
and is measured as the delta between the normal output transition time and the rising edge of CLK1 minus the setup time required
for FFl. CLK2 occurs long enough after CLK1 to allow sufficient time for the DUT to have resolved itself to a valid state. The
outputs of FFI and FF2 are compared by the exclusive OR gate, the output state of which is latched into FF3 by CLK3. When
a metastable failure occurs, the output of the exclusive OR gate goes high caused by FFl and FF2 having opposite data due to
theDUT not having resolved itself by time te. On the next cycle, low data is clocked into the DUT andFFI andFF2 in order to
reset the status latch, FF3. Failures are counted for different resolve times, and't is then calculated using equation 3.
Using the test setup in Figure 4, failure rates are measured for both an SN74ABT78I9, 512 x 18 x 2 clocked FIFO, and an
SN74ACT7807, 2K x 9 clocked FIFO. The device is initially written full to set IR low at the boundary condition. A read clock
is generated to send the internal flag high, and a jitter signal is superimposed on it to sweep asynchronously with respect to the
write clock in an 800-ps-wide envelope and centered such that the IR flag goes high alternately on the second and third write
clocks. The nominal write-clock frequency of the test setup is 40 MHz, but to increase the failure rate to an observable level, a
pulse is injected into the write-clock stream just after the read clock occurs such that the first and second write clocks (the ones
that clock the status through the synchronizer) are only 5.24 ns apart. This increases the effective write clock frequency to
191 MHz, reducing the resolve time allowed in the first stage and increasing the failure rate.
This test setup and these actions together create the necessary conditions to generate a metastable occurrence on the IR output
that is seen after the second write clock and manifests itself as a delay in propagation time. In this instance, the write clock is the
synchronizing clock and the read clock generates the asynchronous internal data signal. CLKI is adjusted to vary the external
resolve time, ta, and the resulting failure rates are recorded (see Table 1).

15-42
 RDCLK
(data) ________ ~~:--. -.~~~-JI-tte-r-----------------------------------------
WRTCLK
(clock)

Metastable Event

IR (out) //II 7 X__\_______

i
I Load FF1 Reset FF1

CLK1 ~¥
I
________________________~r_~t_r_,,~ I~____________~.n~
_
Load FF2 Reset FF2

CLK2
______________________________~Il~¥_____~Il~
____________________________________~Il¥ IL. Load FF3 Reset FF3

CLK3

Figure 4. Metastable Event Counter and Input Waveforms

15-43
 Test Results
Table 1. SN74ABT7819 Failure Rates t
RESOLVE TIME, NUMBER OF NUMBER OF MTBF
tr2 (ns) FAILURES/HOUR FAILURES/SECOND (seconds)
0.27 890 0.2472 4.04
0.39 609 0.1692 5.91
0.53 396 0.1101 9.08
tvcc - 4.5 V, TA - 25°C
After measuring the metastable performance of the SN74ABT7819, some assumptions must be made to calculate the parameters
t and to. Because the individual flip-flops comprising the two-stage synchronizer cannot be measured separately, it is first
assumed that the values for t and to are the same for both. This is a safe assumption, as these constants are driven by the process
technology and because the schematics are identical. The other assumption made involves determining the resolve time allowed
in the first stage of the synchronizer. The clock period is set at 5.24 ns, but the delay through the flip-flop and the setup time to
the next stage must be subtracted from the clock period to arrive at the true resolve time (trl). These values could not be measured
directly and were, therefore, estimated from SPICE analysis to be 1.3 ns.
Using equation 4 and the measured failure rates to calculate tresults in a value of 0.33 ns for the conditions given. The following
values from the test setup must be used to solve for to:
Where:
trl - 3.94 ns (5.24-ns clock period - 1.3-ns setup and delay time)
tr2 - 0.27 ns (set externally at IR output by CLK1)
fc - 40MHz
fd - 125 MHz (4-MHz input adjusted by 25/0.8 jitter ratio)
MfBp2 - 4.04 s

Substituting these values into equation 4 and solving for to yields a value of 16.9 ps.
Table 2 summarizes the results for the SN74ABT7819 and SN7 4ACT7807 clocked PIFOs. An internal setup and delay time of
1.8 ns was assumed for the SN7 4ACT7807.

Table 2. Values of t and to for SN74ABT7819 and SN74ACT7807

SN74ABT7819 SN74ACT7807
TA vcc tens} to (ps) tens} to (ps)
4.5V 0.33 16.9 0.50 1.13
25°C 5V 0.30 7 0.40 2.05
5.5 V 0.23 28.8 0.30 9.40

These numbers indicate the performance of only a few devices and are not intended to represent a fully characterized parameter.
However, they should be valid for the purpose of relative performance comparisons, and the values do fall within the expected
range given the circuit configuration and process technology in which the devices are fabricated.

15-44
 MTBF Comparisons
With the constants t and to now known, calculations of the MTBF of the device under different operating conditions may be
performed. First, however, consider an example of the metastability performance of a single-stage synchronizer using equation
1 and the circuit constants t and to from Table 2. Assume an application running with a 33-MHz write clock, an 8-MHz read clock,
a 9-ns maximum propagation delay time for the IR path, and a 5-ns setup time for IR to the next device. Therefore:
tr - 16 ns (30-ns clock period - 9-ns propagation delay - 5-ns tsu)
fc - 33MHz
fd - 8MHz
Using equation 2 to calculate the MTBF gives 2.55 y 1017 seconds or a little bit more than 8 billion years.
The reliability of a one-stage synchronizer degrades as operating frequency increases. With a 50-MHz write clock, a 12-MHz
read clock, a 9-ns maximum delay, and a 5-ns setup time:
tr - 6 ns (20-ns clock period - 9-ns propagation delay - 5-ns tsu>
fc - 50MHz
fd- 12MHz
Substituting these values into equation 2 yields an MTBF of about 2 hours. This performance is unacceptable, even with a device
fabricated in the 0.8-mm BiCMOS process, which is more resistant to metastability than other processes.
The benefits oftwo-stage synchronization become evident with the next example. Using the conditions stated in the last example:
tr1 - 18.7 ns (20-ns clock period - 1.3-ns setup and delay time)
tr2 - 6 ns (20-ns clock period - 9-ns propagation delay - 5-ns tsu )
fc - 50MHz
fd = 12MHz
Using equation 4 to calculate the MTBF gives 3.16 y 1028 seconds or 1.00 y 1021 years.
Table 3 gives a performance summary of both one- and two-stage synchronizing solutions under different conditions.
Table 3. MTBF Comparisonst
CONDITIONS ACT 1 STAGE ABT 1 STAGE ACT 2 STAGE ABT2STAGE
fc = 33 MHz, fd = 8 MHz 8400 years 8.1 x 109 years 2.62 x 1028 years 4.77 x 1047 years
fc .40 MHz, fd-10MHz 92 days 1400 years 3.56 x 1019 years 2.18 x 1034 years
Ic= 50 MHz, Id= 12MHz 2 hours 4.90 x 1010 years 1.00 x 1021 years
Ic= 67 MHz. Id = 16 MHz 417 years 1.28 x 109 years
Ic = 80 MHz. Id=20 MHz 2900 years
t Assumptions for the MTBF comparisons:
- The values lor to and ~ are those given previously for both the ABT and ACT devices with VCC= 4.5 V. TA = 25°C.
- Flag propagation delay time (IR or OR) is assumed to be 9 ns.
- Setup times to the next device are 5 ns (up to 50-MHz operation). 4 ns (up to 67-MHz operation). and 3 ns (up
to 80-MHz operation).

15-45
 Conclusion
Metastability failures must be accounted for in the design of asynchronous digital circuits. These failures become increasingly
prevalent at higher operating frequencies. When higher frequencies are used, extreme care must be taken to ensure that system
reliability is not adversely affected due to inadequate synchronization methods.
Clocked FlFOs from TI provide a solution to this problem by synchronizing the boundary flags with at least two flip-flop stages
to improve the metastable MTBF over one-stage synchronization. This architecture allows designers to utilize the
high-throughput performance of the memory without endangering the reliability of their end products.

References
1. J. Horstrnarm, H. Eichel, and R. Coates, "Metastability Behavior of CMOS ASIC Flip-Flops in Theory and Test," p. 146,
IEEE Journal of Solid State Circuits, February 1989.
2. H. Veendrick, "The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate," p. 169, IEEE
Journal of Solid State Circuits, April 1980.
3. S. T. Flarmagan, "Synchronization Reliability in CMOS Technology," p. 880, IEEE Journal of Solid State Circuits, August
1985.
4. T. Kacprzak and A. Albicki, "Analysis of Metastable Operation in RS CMOS Flip-Flops," p. 59, IEEE Journal of Solid State
Circuits, February 1987.
5. L. Kleeman and A. Cantoni, "Metastable Behavior in Digital Systems," p. 4, IEEE Design and Test of Computers, December
1987.

15-46
 FIFO Memories:
Solution to Reduce FIFO Metastability

First-In, First-Out Technology

Tom Jackson
Advanced System Logic - Semiconductor Group

SCM011A

~TEXAS
INSTRUMENTS

15-47
 IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.

TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage ("Critical Applications'~.

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED

TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to Tlthrough a local SC sales office.

In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.

Copyright © 1996, Texas Instruments Incorporated

15-48
As system operating frequencies continue to increase in excess of 33 MHz, designers must begin to address the issues of overall
system reliability due to increased chance of a metastable event occurring. A metastable event is defined as the time period when
the output of a logic device is neither at a logic high nor at a logic low but rather in an indeterminate level. The chance of a
metastable occurrence is exponentially increased if single-stage synchronization is employed, as in the case of the '722xx
synchronous-style devices versus the two-stage synchronization that is implemented by Texas Instruments (TI) (see Figure 1).
The following information assists designers in understanding and improving upon the metastable characteristics of '722xx
synchronous-style devices and their reliability.

•
1.00E+S7
1.00E+S2

1.00E+47

1.00E+42

..I
1.00E+37

1.00E+32 • •• • Two-Stage Synchronization

Ii.
m
!iii
1.00E+27

1.00E+22
.~
o One-Stage Synchronization

1.00E+17
0 .1
1.00E+12

1.00E+07

1.00E+02
0
(,)
'T'
•
1.00E~3
0-
1.00E~8
o 10 20 30 40 so 60 70
Frequency - MHz

Figure 1. MTBF for Metastability as a Function of Frequency

Metastability may occur when using a FIFO to synchronize two digital signals operating at different frequencies. This type of
application is a familiar one to many design engineers. Triggering a metastable event is common in single-stage (single flip-flop)
synchronized FIFOs that are used to synchronize different clock signals (see Figure 2). With this method, the asynchronous input
might change states too close to the clock transition, violating the flip-flop's setup and hold times. This causes an increase in
resolve time (tr) which then results in an overall increase in propagation delay (lpd)' Once a metastable event is triggered, the
probability of the output recovering to a high or low level increases exponentially with the increased resolve time. The expected
time until the output of a single flip-flop with asynchronous data has a metastable event is described by the mean time between
failure (MTBF) equation (see equation 1). The first term of the equation is the probability that the asynchronous data will trigger
a metastable event. The second term is the data rate. The third and final term is the probability of the metastable event recovering
given the resolve time. A linear increase in resolve time exponentially increases the MTBF of a metastable event.

15-49
 Synchronized
Clock Q
Flag

Asynchronous
,Flag o

Clock

~~
I tsu
\ r
Aaynchronous
Flag [;J I
Synchronized
Flag
I
I I
I
{
~ tpd 14'"- tr 4
Figure 2. Single-Stage Synchronizer

MTBFl = _1_ x 1.. x exp(!r) (2)

10fe fd 1:

Where:
to - flip-flop constant representing the time window during which changing data invokes a failure
tr - resolve time allowed in excess of the normal propagation delay
1: - flip-flop constant related to the settling time of a metastable event
fc - clock frequency
fd - asynchronous data frequency (for OR-flag analysis, it is the frequency at which data is written to
empty memory; for IR-flag analysis, it is the frequency at which data is read from full memory).

11 has increased the metastable MTBF by several orders of magnitude over single-stage synchronization with its advanced FIFO
family by employing two-stage synchronization (see Figure 3). The output of the frrst flip-flop is clocked into the second flip-flop
on the next clock cycle. For the output of the second stage to become metastable, the frrst stage must have a metastable event that
lasts long enough to encroach upon the setup time of the second stage. The addition of the second flip-flop to the single-stage
synchronizer allows the flip-flops more time to resolve any metastable output. This is statistically equivalent to increasing its
resolve time by the clock period minus its propagation delay. MTBF for a two-stage synchronizer is given in equation 2. All terms,
except for the third one, are the same as in equation I. The third term represents the additional propagation delay through the added
flip-flop.

(3)
MTBF2 = _1_ x 1.. x exp[t - tpd] x exp(!r)
tofc fd 1: 1:

tpd - propagation delay through the first flip-flop

MTBF2 - MTBF 1

Where:

15-50
 Q Synchronized
Clock Q
Flag

Asynchronous
Flag o o

Clock J \"--____'1
Asynchronous
Flag

First Stage
---'

____
m ~r
tau

,----<{ ~ ______ ~ /
Synchronized
-+ tpd : . - tr ---.I
Flag
P/////////////d
!
High or Low (does not matter)

Figure 3. Two-Stage Synchronizer

The functional block diagram in Figure 4 illustrates the connections necessary to add the second-stage synchronization to
the '72211 synchronous FIFO. A quick and inexpensive schematic to resolve metastability of a synchronous FIFO is shown in
Figure 5. In this case, the FIFO is the '72211U and, by implementing a single TI SN74F74 D-type positive-edge-triggered
flip-flop and a TI SN74F08 two-input positive AND gate, the metastability characteristics of this circuit can be dramatically
improved. The TI SN74F74 acts as the second stage for this circuit, increasing the resolve time as described in the previous
paragraphs. The TI SN74F08 is implemented to act as the control-empty and control-full flags to the receiving device. These
control lines of the first-stage and second-stage synchronized flags are then ANDed together to create the control flags (control
empty and control full). The control lines are essentially read enables that ensure the synchronization of the device. As is shown
in the logic diagram and truth table, synchronization is complete only when the empty flags (EF) of both the second stage (truth
table input A) and the device (truth table input B) are high. The empty flag is used for read control and the full flag (FF) is used
for write control. If either flag from the synchronizer or the device is held low or becomes metastable, a read is not permitted (truth
table output Y) until the write flag is synchronized.
As can be seen in today's digital systems, synchronous and asynchronous operations can and will produce random errors due to
metastability in single-stage FIFO designs like those of the '722xx synchronous FIFO family. The described method of
implementing a second stage for flag synchronization is extremely useful for clock speeds that are either approaching or
exceeding 33 MHz. Metastability can be virtually eliminated in the '722xx synchronous FIFO family by the simple addition of
a second flip-flop. The second-stage synchronizer greatly reduces metastability, thereby increasing the MTBF and allowing
designers to use faster microprocessors and higher data-transfer rates for greater overall system performance and reliability.
To reduce metastability and improve system reliability, TI offers a complete line of high-performance FIFO memory devices.
TI's FIFOs have dual-stage synchronization designed onto each chip. This eliminates the need for any external discrete solution
and reduces critical board space by fully utilizing TI's family of fme-pitch surface-mount packaging.

15-51
 '72211 Second Stage EF I FF Control Logic

WCLK RCLK~-------;~ Centrol Empty

EF

Q Control Full
FF
~----------~~~D

Figure 4. Connecting the Second·Stage Synchronizer to the '72211 Synchronous FIFO

TISN74F74 TISN74F08
D·Type 2-lnput
Positive-Edge-Triggered Positive
'72211 Flip-Flop AND Gate

Control Empty EF

To
Receiving
Device
11

Control Full FF

Two Stage E
_ F = = O - Control Empty FF
Two Stage _ . = = O - Control Full
EF FF

INPUTS OUTPUT
A B. Y
H H H
L X L
X L L

Figure 5. Resolving Metastability of a Synchronous FIFO

15-52
 Multiple-Queue
First-In, First-Out Memory
SN74ACT53861

Peter Forstner
Semiconductor Group

SCAA026A

I~TEXAS
NSTRUMENTS

15-63
 IMPORTANT NOTICE
Texas Instruments (TIl reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders; that the information being relied on is current.

TI warrants performance of Its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with Tl's standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage ("Critical Applications,,).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED

TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.

In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.

Copyright © 1996, Texas Instruments Incorporated

15-54
 Contents
Title Page

Introduction ............................................................................ 15-57

Main Areas of Application . ................................................................ 15-58
The Multi-Q FIFO ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-59
Construction of the Multi-Q FIFO ......................................................... 15-59
Configuration Registers ............................................................... 15--61
Allocation of Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15--61
Cells Instead of Words of Data .......................................................... 15--62
Flags .............................................................................. 15--64
Programming ........................................................................ 15--65
Extension of Word Width ................................................................ 15--67
Programming Examples ............................ '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-71
Applications ............................................................................ 15-73
Summary ............................................................................... 15-76

15-55
 List of IDustrations
Figure Title Page
FIFO Data Flow 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 000 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-57
2 ATM Telecommunications Exchange System Block Diagram 0000 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 15-58
3 ATM-Header Structure 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 00 0 0 0 0 0 0 15-59
4 Multi-Q FIFO Functional Block Diagram 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 15-60
5 Data Stream With Odd Cell Size 0000000000000000000000000000000000000000000000000000 0 0 15-62
6 Writing Cells Into the FIFO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-63
7 Faulty Writing of Cells Into the FIFO: ISOC Comes Too Soon 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-63
8 Faulty Writing of Cells Into the FIFO: ISOC Comes Too Late or Not at All 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-63
9 Reading Cells Out of the FIFO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-64
10 Hysteresis of the PFI Flags With Configuration Registers PFCWand PFl_R 0 000 0 00 0 0 0 0 0 0 0 0 0 0 0 15-65
11 Connection of a Microcontroller to the Auxiliary Bus 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 00 0 00 0 0 0 0 0 0 0 0 15-65
12 Extension of Word Width With 18-Bit or 36-Bit Input and/or Output Data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-68
13 Extension of Word With 9-Bit Input Data 00000000000000000000000000000000000000000000000 15-69
14 Data Flow of anATM Data Stream in Two Multi-Q FIFOs 000000000000000000000000000000000 15-70
15 ATM-Exchange Receiving Unit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-73
16 ATM-Exchange Transmitting Unit 000000000000000000000000000000000000000000000000000 0 15-73
17 Connection of a Multi-Q FIFO to a Receiving Unit
Using an 8-Bit or 16-Bit UTOPIA Interface With One Queue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 15-74
18 Priority-Controlled Connection of a Multi-Q FIFO to a Receiving Unit
Using an 8-Bit or 16-Bit UTOPIA Interface 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 15-74
19 Connection of a Multi-Q FIFO to a Transmitting Unit
Using an 8-Bit or 16-Bit UTOPIA Interface With One Queue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-75
20 Priority-Controlled Connection of a Multi-Q FIFO to a Transmitting Unit
Using an 8-Bit or l6-Bit UTOPIA Interface do 0000000000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-75
21 Switching Matrix With Bottleneck Between Two Switching Elements 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-76

List of Tables
Table Title Page
1 Selecting the Queue When Reading the FIFO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-60
2 Configuration Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-61
3 Port-Control Register PORT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-62
4 Multi-Q FIFO Flags 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-64
5 Configuration-Registers Access Order 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-66
6 Example of Configuration Registers Programming: 18-Bit Write, 18-Bit Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-71
7 Example of Configuration Registers Programming: 9-Bit Write, 18-Bit Read . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15-71
8 Example of Configuration Registers Programming: 18-Bit Write, 9-Bit Read 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 15-72

15-56
 Introduction
This application report presents a detailed description of the versatile functions of the SN74ACT53861 multiple-queue
(Multi-QTM) first-in, first-out (FIFO) memory. Examples of circuits show how the device can be controlled and cascaded. Typical
application examples show how the device can be used in asynchronous transfer mode (ATM) telecommunications exchange
systems.
Memories are indispensable circuit components of digital-system subassemblies. There are a large number of memories in
various configurations for many application requirements. Each memory is suited for specific and specialized applications.
One of these specialized memories is the FIFO memory, which provides intermediate storage of data being transferred between
two electronic systems. The designation FIFO indicates how the data flows. A FIFO has separate data
input and data output; however, the first word of data written into the memory is the first to leave when it is read
(see Figure 1). Within the FIFO, words of data wait in a data queue. If a FIFO is configured between two systems that are working
asynchronously, the FIFO must be able to manage the synchronization of the data flow to both systems to prevent metastable
situations.

I Input Data I
II
'\J
FIFO I Stored Data I
t
I Stored Data I
t
I Stored Data I
••
•
Stored Data
I I
T
I Stored Data I
t
I Stored Data I
U
I Output Data I
Figure 1. FIFO Data Flow
FIFOs differ from one another in their word widths, memory capacity, and in the way they are controlled. Texas Instruments (11)
offers FIFOs with word widths from 1 to 36 bits and memory capacities from 64 to 4096 words. Because FIFOs have alternative
methods of control, 11 offers strobed FIFOs and clocked FIFOs. A detailed description of the various methods of controlling
FIFOs can be found in other 11 application reports. The various word widths and memory capacities available are described in
the 1996 High-Performance FIFO Memories Data Book, literature number SCADOO3C.
In addition to standard FIFOs, versions for special purPoses have been designed for specific applications. The TI Multi-Q FIFO
is an application-specific FIFO designed for ATM telecommunications exchange systems.

Multi-Q is a trademark of Texas Instruments Incorporated.

15-57
 Main Areas of Application
The SN74ACT53861 Multi-Q FIFO is designed specifically for ATM telecommunications exchange systems.
As shown in Figure 2, ATM telecommunications exchange systems can have three functional parts:
• Receiving unit (one per channel)
• Switching matrix
• Transmitting unit (one per channel)
The ATM used for data transmission supplies the receiving unit with digital information, which is usually apportioned in cells
having a length of 53 bytes. Each cell consists of a 5-byte cell header and a 48-byte payload. The cell header includes:
• Ultimate destination: virtual channel identifier (VCI)
• Immediate next destination, i.e., the next ATM exchange installation through which the ultimate destination is reached:
virtual path identifier (VPI)
• The type of information contained in the cell: payload type (PT)
• The importance, or priority, of the cell: cell-loss-priority (CLP) bit
• Error-correction controller: header error control (HEC)
In certain applications, extending the cell header by one to two bytes provides the ATM exchange installation with internal
information (tagged cells) (see Figure 3).
Interfaces Interfaces

SwItchIng MatrIx
• •
• •

Controller

Figure 2. ATM Telecommunications Exchange System Block Diagram

15-58
 Bit: 8 7 6 5 4 3 2

User Definable VPI

VPI VCI 2

VCI 3

VCI PT
I CLP 4

HEC 5

Figure 3. ATM·Header Structure

If delays occur because transmission channels in the ATM exchange are not available, the Multi-Q FIFO allocates cell priorities,
known as quality of service (QOS), by interpreting the PT information and the CLP bit in the cell header. Data that is critical as
to the time taken for transmission, such as audio or video signals, is swept more rapidly through the ATM exchange than, for
example, less critical computer data. If the CLP bit is set to 0, the cell contains important data that must reach its destination;
whereas cells with the CLP bit set to 1 can be deleted. In a digital ATM exchange system, a priority control for cell transmission
must be implemented. •
The cells being received arrive asynchronously to the clock signal of the exchange system; therefore, synchronization of the input
data stream to the system clock is necessary.
The Multi-Q FIFO solves synchronization problems and controls transmission priority with minimal complexity. The
architecture of this FIFO, unlike conventional FIFOs, is not based on words of data but on cells. This device can control up to
three priorities. The writing of the input data can be performed completely asynchronously with respect to the reading of the
output data.

The Multi-Q FIFO

The most remarkable feature of the Multi-Q FIFO is that memory can be allocated to three independent queues. These queues
allow the implementation of three QOS priorities.
Construction of the Multl·Q FIFO
Figure 4 shows the functional block diagram of the Multi-Q FIFO, which is clocked; i.e., it has inputs for free-running write and
read clocks. Write accesses occur at the rising edges of the write clock when one of the three write-enable-x, (WRTENx) (x-
1, 2, or 3) lines is set. Read accesses are implemented at the rising edges of the read clock by setting the read-enable (RDEN)
line. Reading or writing stops when a low level is applied to WRTENx or RDEN. For writing operations, the three control lines,
WRTENx per queue, are individually brought out. The control lines for write accesses are operated by a multiplexer. The desired
queue is chosen with MUXO and MUXI selecting access to the chosen queue using RDEN (see Table 1).
Before use, this device must be reset by four rising edges of the write clock (WRTCLK) and four rising edges of the read clock
(RDCLK) while the reset input (RST) is high.

1~9
 Table 1. Selecting the Queue When Reading the FIFO
MUX1 MUXO SELECTED QUEUE
0 0 Queue 1
0 1 Queue 1
1 0 Queue 2
1 1 Queue 3

POE
OS
RiW
-B-
REQ Auxlllary-Bua
8 Control 8
PO-P7
OW ROY

WRTCLK I I Raset
Logic
I RDCLK

WRTEN1 ......
WRTEN2 ......
ri- Configuration
Reglstera
ri-f-+-
f-+- MUXO
MUX1
WRTEN3 ...... RDEN
ABRT ...... T '-r-r+-
ISOC ...... ' - r - - OSOC
Flags
ALER --" CR1

tJ
PF1
Queue1 -~

FF1
r CR2
~-------
PF2
Queue2 r- .,..... --" CR3
FF2
~-------
PF3
Queue3 .....Q)::I'!ij
-Gi
....
FF3
T
r+- i!i
aOa:
~

Write-Address Generation
r- T-
1 2 15 16 rF
~
4098 x 18 OE
~ Dual-Port ~-:&
d·! ~
00-017 1
'S
SRAM
In 16 ::I::1i'
aOa: r+'
QO-Q17

c. 256 x 18
.5 Divisions
""-
Raad-Address Generation

~-I&
::I::1'!ij
L....+- !l~ ~
aOa:

"'---

Figure 4. Multl·Q FIFO Functional Block Diagram

15-60
Configuration Registers
Eleven configuration registers allow matching the FIFO to requirements of a particular application (see Table 2). These
configuration registers can be written to and read from using a microcontroller through the auxiliary-bus control interface.
Table 2. Configuration Registers
REGISTER
REGISTER NAME
NO. OF DEFAULT PROGRAMMABLE RANGE FUNCTION
SYMBOL BITS VALUE
Chooses the data input and output bus size and
PORT Port control 5 0 Bit-slice control
format. Controls output byte destuffing.
Defines the number of 256 x 18 memory blocks
Qll Queue 1 length 5 8 0-16
for Queue 1
Defines the number of 256 x 18 memory blocks
QL2 Queue 2 length 4 6 0-15
for Queue 2
Defines the number of 256 x 18 memory blocks
Ql3 Queue 3 length 4 2 0-15
for Queue 3
ClSZ Cell size 6 27 10-32 Defines the cell size in 18-bit words
Programmable flag 1, Defines the number of cells in Queue 1 to set
PF1_W 9 71 0-409
write threshold PFllow
Programmable flag 1, Defines the number of cells in Queue 1 to set
PF1_R 9 70 1-408
read threshold PFl high
Programmable flag 2, Defines the number of cells in Queue 2 to set
PF2_W 9 51 0-383
write threshold PF210w
Programmable flag 2, Defines the number of cells in Queue 2 to set
PF2_R 9 50 1-382
read threshold PF2 high
Programmable flag 3, Defines the number of cells in Queue 3 to set
PF3_W 8 13 1-383
write threshold PF310w
Programmable flag 3, Defines the number of cells in Queue 3 to set
PF3_R 8 12 0-382
read threshold PF3 high

Allocation of Queues
The Multi-Q FIFO memory consists of 4096 18-bit words that have a maximum of three independent queues. These queues can
be called up to control up to three QOS priorities of ATM cells. Using configuration registers QL1, QL2, and QL3, the sizes of
the individual queues can be allocated in steps of 256 18-bit words. The initial value of QL1 = 8 if Queue 1 has a size of 8 x 256
= 2048 18-bit words. The development engineer has access only to configuration registers QL1 and QL2 and can only determine
the size of the first two queues; after that, the Multi-Q FIFO automatically reserves the part of the memory that is still available
for the third queue. Programming queue lengths of zero allocates the memory to one or two queues.
The word width of the memory is 18 bits; however, the development engineer can choose between 9-bit and 18-bit access when
reading and writing. In these cases, the bus widths for reading and writing operations can be different. For example, it is possible
to write with 9-bit access but implement the reading cycle with a word width of 18 bits. If the 9-bit access is chosen, the FIFO
can write the first 9-bit word to the lower significant half of the 18-bit memory and the second 9-bit word to the higher significant
half (little endian). Alternatively, this order can be reversed (big endian). The programming for write accesses is performed in
the configuration register PORT using bits INSIZ, OUTSIZ, and INBE (see Table 3). With read accesses, the 9-bit data word is
output on bits Q8-QO in little-endian data format and on the bits Q17-Q9 in big-endian format. In this case, the hardware wiring
determines the data format; whereas with the input data, the software programming determines the data format.

15-61
 Table 3. Port·Control Register PORT
OUTSTF OUTSIZ INST INBE INSIZ FUNCTION
Bit 4 Bit 3 BIU BH1 Bit 0
X X X X 0 18-blt Input bus
9-bit input bus with an even number of bytes per cell in
X X 0 0 1 1I1I1e-endlan data format

X X 1 1 9-bitlnput bus with an even number of bytes per cell in

0 big-endian data format
9-bit input bus with an odd number of bytes per cell in 1111-
X X 1 0 1 le-endlan data fonnat
9-bitlnput bus with an odd number of bytes per cell in bi-
X X 1 1 1 g-endian data format
X 0 X X X 18-bit output bus
0 1 X X X 9-blt output bus with an even number of bytes per cell
1 1 X X X 9-bit output bus with an odd number of bytes per cell

Cells Instead of Words of Data

The Multi-Q FIFO flags (e.g., empty, full, etc.) indicate the presence or the absence of complete cells. The cell size can be set
with the configuration register CLSZ in the range of 10 to 3218-bit words to allow a cell size of20 to 64 bytes. The Multi-QFIFO
can also be programmed to odd cell sizes (e.g., 53 bytes) with 9-bit writing access by byte stuffing and with 9-bitreading access
by removing the stuffmg bytes (see Figure 5). This property can be chosen in the configuration register PORT with the help of
bits INST and OUTSTF (see Table 3).

9-Blt Input Data Stream 18-Blt Data Stream In FIFO 9-Blt Output Data Stream

53-Blt Cell 53-Blt Cell 53-Blt Cell 53-Blt Cell

Multl-Q FIFO
~ ~

Stuffing Bytes

Figure 5. Data Stream With Odd Cell Size

When writing into a cell, the Multi-Q FIFO must be informed of the beginning of a cell with the input start-of-cell (ISOC) signal,
as shown in Figure 6. At the rising clock-pulse edge when the first data word of a cell is written into the FIFO, both ISOC and
the valid data word must be set high. If a cell has been written completely into the FIFO, ISOC must again be set with the beginning
of the next cell. The FIFO compares the beginning of a cell, which has been indicated, with the expected cell beginning in
accordance with the previously implemented programming of the cell size and indicates any fault at the alarm (ALER) output
(see Figure 7 and Figure 8). If a fault of this kind occurs and ALER is low, the fault must be reset with the abort (ABR1) input
signal before further cells can be written into the FIFO.
When reading from cells, the output start-of-cell (OSOC) signal indicates the beginning of a cell. OSOC can be used to control
subsequent parts of the circuit (see Figure 9).

15-82
 Figure 6. Writing Cells Into the FIFO

00-018

I I
fI I I
ALER
))
\ II
I
((
IJ I I
ABRT I 'w...I
Figure 7. Faulty Writing of Cells Into the FIFO: ISOC Comes Too Soon

00-018

I I
ALER
((
JJ
\
I
I
t-
I
ABRT
If
II I
I \...l.r
Figure 8. Faulty Writing of Cells Into the FIFO: ISOC Comes Too Late or Not at All

15-63
 RDCLK
I
_ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~_ _ _ _ _ _ _ _-J~~~_ _ _ __ _

Figure 9. Reading Cells Out of the FIFO

Flags
Table 4 defines the functions of flags that indicate the extent to which the memory is filled in the Multi-Q FIFO. A form of
hysteresis is implemented with the programmable flags PFl, PF2, and PF3. The number of required cells in Queue 1 to set PFl
low is determined using the configuration register. At subsequent readout, PFI is reset to high as soon as the number of the cells
still remaining in the memory reaches the value PFl_R in the configuration register. The extent to which the FIFO is filled can
be set with configuration register PFl_W. From that point, ATM cells whose eLP bit is set to 1 are erased and no longer written
into the FIFO. Only when the FIFO is again filled below the value in configuration register PFl_R does an external cell-priority
logic accept the writing in of cells whose eLP bit has a value of 1.
The purpose of adjustable hysteresis is explained using as an example a standard FIFO having only one simply programmable
almost-full (AF) flag without hysteresis. If the FIFO is filled to the predetermined value, the FIFO displays this at the AF flag
output. This process is repeated when the FIFO again exceeds the predetermined value and ignores eLP - 1 cells. As a result
of the reading out of a cell, the AF flag is reset and the external cell-priority logic immediately allows the storage of eLP - 1 cells.
At this point, the external cell-priority logic switches between acceptance and rejection of eLP - 1 cells.
The implementation of hysteresis in the Multi-Q FIFO allows the user to suppress continuous switching between acceptance and
rejection of eLP = 1 cells (see Figure 10).
Hysteresis can be suppressed by an appropriate choice of threshold values for PFl_Wand PFLR.
Table 4. Multl-Q FIFO Flags
FLAG SYNCHRONIZED TO FUNCTION
DWRDY WRTCLK Data write ready. DWRDY must be high before data can be written into the FIFO.
FF1 WRTCLK Full flag, Queue 1. When FF1 is low, there is no more room for an additional cell in Queue 1.

PF1 Programmable flag, Queue 1. Indicates the extent to which Queue 1 is occupied, as previously
WRTCLK
defined with configuration registers PF1 Wand PF1 R
FF2 WRTCLK Full flag, Queue 2. When FF2 is low, there is no more room for an additional cell in Queue 2.

PF2 Programmable flag, Queue 2. Indicates the extent to which Queue 2 is occupied, as previously
WRTCLK
defined with configuration registers PF2 Wand PF2 R
FF3 WRTCLK Full flag, Queue 3. When FF3 is low, there is no more room for an additional cell in Queue 3.

PF3 WRTCLK Programmable flag, Queue 3. Indicates the extent to which Queue 3 is occupied, as previously
defined with configuration registers PF3 Wand PF3 R
CR1 RDCLK Cell ready, Queue 1. If there is at least a complete cell in Queue 1, CR1 is high.
CR2 RDCLK Cell ready, Queue 2. If there is at least a complete cell in Queue 2, CR2 is high.
CR3 RDCLK Cell ready, Queue 3. If there is at least a complete cell in Queue 3, CR3 is high.

15-64
 Cell 74
081170
Cell 66
081180

.:
i.!at!
....
11
.011

8';.
081156
081150
081145
081140
Cell 36
=
PF1 W From this pOint, CLP 1 cells
- sre no longer accepted.

PF1_R From this point, CLP =1 cella

are again accepted.

lD. 081130

JI Cell 25
081120
081115
081110
CeliS
08111

Figure 10. Hysteresis of the PF1 Flags With Configuration Registers PF1_W andPF1_R

Programming
The Multi-Q FIFO can be set up to meet the requirements of a particular application after resetting and before writing in the ftrst
word of data with the conftguration registers. These registers are written to and read from using a microcontroller via the
auxiliary-bus control interface (see Figure 11).

MC68302 MuIU·QFIFO
A23-A0 I
24
I Address Decode
I
BREQ
AS

OTACK
r---
~1 I OWROY

i5I
---- 1 i5I
074:10 P7-PO
8
RIW RIW

I ,-'" .. POE

Figure 11. Connection of a Mlcrocontroller to the Auxiliary Bus

15-65
 Table 5. Configuration-Registers Access Order

ACCESS REGISTER PROGRAM BUS

REGISTER NAME
ORDER SYMBOL BIT WIDTH MSB LSB
1 PORT Port control 5 P4 PO
2 QL1 Queue 1 length 5 P4 PO
3 QL2 Queue 2 length 4 P3 PO
4 CLSZ Cell size 6 P5 PO
5 PF1 W Programmable flag 1, write threshold 9 P7 PO
6 PF1_R Programmable flag 1, read threshold 9 P7 PO
7 PF2 W Programmable flag 2, write threshold 9 P7 PO
8 PF2 R Programmable flag 2, read threshold 9 P7 PO
9 PF3 W Programmable flag 3, write threshold 8 P7 PO
10 PF3 R Programmable flag 3, read threshold 8 P7 PO

The writing into the configuration registers is perfonned sequentially (see Table 5). Access to register QL3 is unnecessary because
the content of this register always consists of the memory size of the Multi-Q FIFO of 4096 words of data minus the values of
registers QL1 and QL2.
To open access to the configuration registers, the bus request (BREQ) signal must be low. As a result, the data write ready
(DWRDY) output replies with a low level after two rising edges of the write clock (WRTCLK). DWRDY indicates an active data
access. When DWRDY is high, access to the FIFO is through the D inputs. When DWRDY is low, access is through the P
tenninals to the configuration registers (see Figure 4). At every falling edge of the data strobe (DS) signal, the FIFO writes an
8-bit data word from the P tenninals in sequence to the configuration registers. If all ten configuration registers from Table 5 are
filled with values, the FIFO ignores all further write accesses. Only after a renewed reset of the device are write accesses to the
configuration registers again possible.
The following rules apply for the values that are permitted to be written into the configuration registers.
Rules for the length of the queues QL1, QL2, QL3 are:
• The minimum value is O.
• For QL1, the maximum value is 16.
• For QL2 or QL3, the maximum value is 15.
• The sum of QL1 and QL2 must not exceed a value of 16; it can be less than 16.
• Only QL1 and QL2 can be programmed by the user. The value of QL3 is determined by the Multi-Q FIFO in that it
is infonned of the length of the memory that is still available.
Rules for the cell-size (CLSZ) register are:
• The minimum value is 10.
• The maximum value is 32.
Rules for programmable flag values PFI_W, PF2_W, and PF3_Ware:
• The minimum value is I.
• The value may not be larger than the number of whole cells for which there is room in the queue.
• The PFLW, PF2_W, and PF3_W registers are nine bits. The higher-valued eight bits are programmable by the
development engineer. The least significant bit (LSB) is always I. Accordingly, all PFx_W values are odd numbers.
Rules for programmable flag values PFI_R, PF2_R, and PF3_R are:
• The minimum value is 1.
• The value must be smaller than the value of the corresponding PFx_W register.
• The PFI_R, PF2_R, and PF3_R registers each consist of nine bits. The higher-valued eight bits are programmable by
the development engineer. The LSB is always O. Accordingly, all PFx_R values are even numbers.

15-66
Extension of Word Width
An extension of word width is possible with a 36-bit access. As shown in Figure 12 (36-bit access), all input control lines must
be switched in parallel while the flag outputs are connected together with AND or OR gates. In theory, both FIFOs must have
the same internal state and, accordingly, signal-identical flags; however, when there is unfavorable overlapping, the flag of one
device can change one clock cycle later than the other device. This does not cause differences in the contents of memory or loss
of data. The flag synchronization can decide on a clock-pulse edge sooner or later, resulting in differences in the display. In this
case, the connection with AND or OR gates ensures reliable results.
If an 18-bit access is desired with an extension of word width, this can be achieved as shown in Figure 12. The only difference,
in this case, is that both FIFOs are programmed for 9-bit access and only nine data lines per FIFO (08-00 and Q8-QO) are used.

15-67
 Multl·Q FIFO
RST RST
WRTCLK WRTCLK RDCLK RDCLK

WRTEN1 WRTEN1 RDEN RDEN

WRTEN2 WRTEN2 MUXO MUXO
WRTEN3

--
WRTEN3 MUX1 MUX1

PF1 '&' PF1 CR1 & CR1

FF1

=
FF1 :51

PF2 & PF2 CR2

r====[fr- CR2
FF2 :51 FF2

PF3

FF3
~
~
PF3

FF3
CR3
r==rrr- CR3

ISOC ISOC OSOC

r=ill- OSOC
ALER
ABRT
-0= ALER

ABRT
OE OE

D35-00 D17-00 Q17-Q0 Q35-Q0

36 18 18 36
Multl-Q FIFO
RST
'-- WRTCLK RDCLK
'--- WRTEN1 RDEN r-
- WRTEN2 MUXO f---

WRTEN3 MUX1

PF1 CR1

FF1 CR2

PF2 CR3

FF2

PF3

FF3
ISOC OSOC

ALER OE

ABRT

D17-00 Q17-Q0
18 8

Figure 12. Extension of Word Width With 18-Blt or 36-Bit Input and/or Output Data

15-68
 FIF02
RST
WRTCLK
-- WRTCLK
WRTEN

......- J
~KF""""lf~
Q
ISOC
ALER
WRTEN
ABRT
C
.--"'-
~
DB-DO
RST -
K
R
Qt- '7'
D Flip-Flop
FIF01
D
ISOC - C
Q L-- - RST

"'- R WRTCLK
--r&L WRTEN
ISOC
ALER J"il- ALER
ABRT ABRT
DB-DO D8-00
9 9

Figure 13. Extension of Word With 9·Blt Input Data

If a 9-bit access to two Multi-Q FIFOs having extended word width is desired, these devices must be provided with extemallogic
to control them in accordance with the ping-pong principle. In Figure 13, WRTEN and ISOC control lines demonstrate the
ping-pong principle; i.e., the first 9-bit word is read into FIFO 1 and the second 9-bit word is read into FIF02. In this case, ISOC
must also be generated for the second 9-bit data word, because this data word represents the beginning of a cell of FIF02. The
order in which the 9-bit words are read into the two FIFOs is shown in Figure 14.

15-69
 W3 W2 WI W55
W2 WI W54 W54
WI WS3 WS3 WS3
d WS2
e.fA
gj!5 WS2
d WS2
e.fA
~!5 WS2
f~
(/)C\I WSI .=~ WSI
(/)fa
f~
(/);1; WSI -~
(/)18 WSI
B~ B ..
21.~ ~~ ~~ 2111

~ ~ ~ ~
::IE(/) ::IE(/) ::IE(/) ::IE(/)
~~
W3 W3 W3 W3
W2
~~ W2
~~ W2
~~ W2

• '" " "

WI WI WI WI

WI W3 W2 W4 WI W3 W2 W4 WI W3 W2 W4 WI W3 W2 W4
WS W? W6 WS WS W7 W6 wa WS W? W6 WS WS W7 W6 WS
W9 Wll Wla W12 W9 Wll Wla W12 W9 Wll Wla W12 W9 Wll Wla W12

W49 WSI wsa WS2 W49 WSI wsa WS2 W49 WSI wsa WS2 W49 WSI WSO WS2
WI W3 W2 W4 WS3 J:{;' W2 W4 WS3 1:i'I:: WS41IEiIj WS3 WSS W54 I;i';:i'i
WS W? W6 WS WI W3 W6 WS WI W3 W2 W4 WI W3 W2 W4
W9 Wll Wla W12 WS W? Wla W12 WS W7 W61WSI WS W? W6 ws

FIFO 1 FIFO 2 FIFO 1 FIFO 2 FIFO 1 FIFO 2 FIFO 1 FIFO 2

Cell Cell Cell Cell Cell Cell Cell Cell
Size: Size: Size: Size: Size: Size: Size: Size:
13 13 14 13 14 14 14 14
18-BII 18-BII 18-BII 18-BII 18-BII 18-BII 18-BII 18-BIt
Words Words Words Words Words Words Words Words

~ =9-Bft Dala Word, Third Word of ATM Dala Siream

11m =Sluffing Byte
NOTE A: Two Multi-Q FIFOs are connected as a 36-bil-wide FIFO with 9-bit data access.

Figure 14. Data Flow of an ATM Data Stream in Two Multi-Q FIFOs

15-70
Programming Examples
Before use, the Multi-Q FIFO must be reset and programmed to perform the desired function using the configuration registers
(see Table 2). Table 6, Table 7, and Table 8 show examples of register programming.
Table 6. Example of Configuration Registers Programming: 18-Blt Write, 18-Blt Read
Cell size: 53 bytes --I 27 18-blt words
Wr~e access: 18bn
Read access: 18 bit
Size of Queue 1: 75 ATM cells --I 2048 18-bit words
Size of Queue 2: 56 ATM cells --11536 18-bit words
Size of Queue 3: 18 ATM cells --I51218-bit words
Function:
PF1 W: 65ATMcelis
PF1-R: 55ATMcelis
PF2-W: 50ATMcelis
PF2:::R: 40ATMcelis
PF3 W: f5ATM cells
PF3:::R: 10ATMcelis
REGISTER P7 P6 P5 P4 P3 P2 P1 PO HEX DESCRIPTION
PO = 0 --I 18-bit input bus
PORT 0 0 0 0 0 0 0 0 00
P3 - 0 --I 18-bit output bus
QU 0 0 0 0 1 0 0 0 08 8 x 256 - 2048 18-bit words
QL2 0 0 0 0 0 1 1 0 06 6 x 256 - 1536 18-bit words
CLSZ 0 0 0 1 1 0 1 1 18 53 cells --I 27 18-bit words
PF1 W 0 1 0 0 0 0 0 1 41 65ATMcelis
PF1 R 0 0 1 1 0 1 1 1 37 55 ATM cells
PF2 W 0 0 1 1 0 0 1 0 32 50ATMcelis
PF2 R 0 0 1 0 1 0 0 0 28 40ATMcelis
PF3 W 0 0 0 0 1 1 1 1 OF 15ATMcelis
PF3 R 0 0 0 0 1 0 1 0 A 10ATMcelis

Table 7. Example of Configuration Registers Programming: 9-Blt Write, 18-Blt Read

Cell size: 53 bytes --I 27 18-bit words
Write access: 9 bit, little endian
Read access: 18 bit
Size of Queue 1: 66 ATM cells --I 1792 18-bit words
Size of Queue 2: 56 ATM cells --I 1536 18-b~ words
Size of Queue 3: 28 ATM cells --I 768 18-bit words
Function:
PF1 W: 60 ATM cells
PF1-R: 50ATMcelis
PF2-W: 50ATMcelis
PF2:::R: 40 ATM cells
PF3 W: 24ATMcelis
PF3:::R: 16 ATM cells
REGISTER P7 P6 P5 P4 P3 P2 P1 PO HEX DESCRIPTION
PO • 1 --I 9-b~ input bus
PORT 0 0 0 0 1 1 P1 - 0 --I little endian
0 0 00 P2 = 1 --I odd-numbered cell size
P3 - 0 --I 18-bit output bus
QU 0 0 0 0 0 1 1 1 07 7 x 256 - 1792 18-bit words
QL2 0 0 0 0 0 1 1 0 06 6 x 256 - 1536 18-bit words
CLSZ 0 0 0 1 1 0 1 1 18 53 cells --I 27 18-bit words
PF1 W 0 0 1 1 1 1 0 0 3C 60 ATM cells
PF1 R 0 0 1 1 0 0 1 0 32 50 ATM cells
PF2 W 0 0 1 1 0 0 1 0 32 50ATMcelis
PF2 R 0 0 1 0 1 0 0 0 28 40 ATM cells
PF3 W 0 0 0 1 1 0 0 0 18 24 ATM cells
PF3 R 0 0 0 1 0 0 0 0 10 16 ATM cells

15-71
 Table 8. Example of Configuration Registers Programming: 18-81t Write, 9·81t Read
Cell size: 54 bytes ~ 27 18-bit words
Write access: 18 bit
Read access: 9 bit
Size of Queue 1: 56 ATM cells ~ 1536 18-bit words
Size of Queue 2: 56 ATM cells ~ 1536 18-bit words
Size of Queue 3: 37 ATM cells ~ 1024 18-bit words
Function:
PFl W: 50ATMcelis
PF1-R: 40ATMcelis
PF2::::W: 50 ATM cells
PF2 R: 40 ATM cells
PF3::::W: 30 ATM cells
PF3_R: 20ATMcelis
Register P7 P6 P5 P4 P3 P2 P1 PO HEX Description
PO =0 ~ 18-bit input bus
PORT 0 0 0 0 1 0 0 0 00 P3 = 1 ~ 9-bit output bus
P4 = 0 ~ even-numbered cell size
Qll 0 0 0 0 0 1 1 0 07 6 x 256 =1536 18-bit words
QL2 0 a 0 0 0 1 1 0 06 6 x 256 - 1536 18-bit words
ClSZ a a a 1 1 a 1 1 18 54 cells ~ 27 18-bit words
PFCW a a 1 1 a a 1 0 32 50ATMcelis
PFl R a a 1 0 1 a a a 28 40 ATM celis
PF2_W a 0 1 1 0 0 1 0 32 50 ATM celis
PF2 R a 0 1 a 1 a 0 0 28 40ATMcelis
PF3 W 0 0 0 1 1 1 1 0 lE 30ATMcelis
PF3 R 0 0 0 1 0 1 0 0 14 20ATMcelis

15-72
 Applications

The Multi-Q FIFO provides several alternatives for arranging the priority control of various QOS classes. A common
implementation is the priority control in the receiving unit (see Figure 15) and transmitting unit
(see Figure 16) of an ATM exchange. If the content of the transmitted ATM cells in the receiving unit is larger than the capacity
of the switching matrix, a priority control must be installed and cells of less importance put in a waiting queue or eliminated
completely. The same phenomenon can arise with the transmitting unit when the capacity of the outgoing line cannot accept the
cells received from the switching matrix. In both cases, use of a Multi-Q FIFO is recommended.

Flags

,.
r--
I Control
Lines +
ATM To
Data Stream ---+- PHY
8
Priority Control
9
Multl-Q FIFO
9,18,36
Switching
Matrix

'--
PHY =Physical Interface
Figure 15. ATM-Exchange Receiving Unit

Flags

~
I Control
Lines t -
From
Switching
Matrix 9,18,36
Priority Control
9,18,36
Multl-QFIFO
8
PHY ---. ATM
Data Stream

PHY =Physical Interface

-
Figure 16. ATM-Exchange Transmitting Unit

/15-73
The universal test and operations physical interface to ATM (UTOPIA) in 8-bit and 16-bit bus widths has become the preferred
interface between the physical interface (PHy) and the subsequent or preceding stages. Figure 17 shows the connection of the
Multi-Q FIFO on the receiving side to a PHY with a UTOPIA interface when one queue is used. When priority control of the
ATM cells is implemented, an arrangement as shown in Figure 18 can be used. Similarly, the connection on the transmitting side
to a PHY with a UTOPIA interface can be implemented as shown in Figure 19 and Figure 20.

UTOPIA
Multl·Q FIFO
07-00,015-00
8,18
>- 08,016-017
:c
Q. 1,2
Start of Cell
ATM g) ISOC
c
Data Stream "> RxEmpty
WRTEN1
] FF

WRTCLK

PHY = Physical Interface

Figure 17. Connection of a Multl·Q FIFO to a Receiving Unit Using an a·Blt or

16-Blt UTOPIA Interface With One Queue

UTOPIA
Multl·Q FIFO

Header Shift 07-00,015-00

8,18 Register
08,016-017
1,2
ISOC

WRTEN1

WRTEN2

WRTEN3
Priority Logic
PF1

PF2
PF3

WRTCLK

PHY =Physical Interface ' - - - - - - - 1 Oscillator

Figure 18. Priorlty·Controlied Connection of a Multl·Q FIFO to a Receiving Unit Using an

80BIt or 16-Blt UTOPIA Interface

15-74
 UTOPIA
Multl·Q FIFO
Q7-00, Q15-00t--..... -------+----'T----+..
8,18
Q8, Q18..Q17 I - -.....-----~'----...:.-......:~---+
OSOC~----1-,2--------~---s-m-rt-o-f-C-e-II--~------~~
.
ATM
TxFull Dam Stream
RDEN1 ~~----------_+------~----7_------~

CR1

MUXO

MUX1

RDCLK ........4-------...
L.....-.-;:=:==.
Oscillator ~----.....J

PHY =Physical Interface

Figure 19. Connection of a Multl-Q FIFO to a Transmitting Unit Using an 8-Blt or
16-Bit UTOPIA Interface With One Queue

Multl·Q FIFO
Q7-00, Q 1 5 - 0 0 t - - - - - - -....---~.,...---~--~~

Q8, Q18..Q17 t - - - - - - -....---+--....;;-~r---~H

OSOC~-------------------r~~~~~_T----.,

RDEN

MUXO

MUX1
CR1
eR2
CR3

RDCLK

Oscillator 1-_ _ _ _--'

PHY =Physical Interface

Figure 20. Priority-Controlled Connection of a Multl-Q FIFO to a Transmitting Unit Using an
8-Blt or 16-Bit UTOPIA Interface

15-75
 11 000

12 001

13 010

To Output OOO-+- 14 011

15 100

16 101

17 110

To Output 001-+- 18 111

Figure 21. Switching Matrix With Bottleneck Between Two Switching Elements
There are different versions of the switching matrix. A simple example is shown in Figure 21. In this case, a bottleneck arises
between the next-to-Iast and the last switching elements. This problem can be solved by increasing the transmission bandwidth
of this part of the transmission path to double that of an input channel or by installing a priority control for the ATM cells to be
transmitted. A Multi-Q FIFO is a suitable device for implementing this priority control.
In view of the many ways in which an ATM exchange system can be implemented, there are certainly a large number of potential
applications for the Multi-Q FIFO. When the priority control of up to three QOS classes is required, the Multi-Q FIFO is the
logical choice.

Summary
The Multi-Q FIFO is designed to fulfill the particular requirements of ATM telecommunications exchange systems by:
• Buffering ATM cells until they are passed on to the switching matrix
• Matching asynchronous rates of data flow between a transmission line and the switching matrix
• Managing up to three different priorities (QOS classes) of ATM cells
• Matching the bus width (for example, from a 9-bit input bus to a 36-bit output bus, or vice versa)
Programming the device by using ten configuration registers allows it to be used in a variety of applications. The TI
SN74ACT53861 Multi-Q FIFO is an outstanding component that fulfills the requirements of telecommunications applications.

15-76
16-1
 Contents
Page
Ordering Information .................................................. 16-3
Mechanical Data ...................................................... 16-5

16-2
 ORDERING INFORMATION

Electrical characteristics presented in this data book, unless otherwise noted, apply for the circuit type(s) listed in the
page heading regardless of package. The availability of a circuit function in a particular package is denoted by an
alphabetical reference above the pin-connection diagram(s). These alphabetical references refer to mechanical
outline drawings shown in this section.
Factory orders for circuits described in this catalog should include a four-part type number as explained in the
following example.
EXAMPLE: SN 74ACT7803 -15 DL R

preflXSN---------------------'I/
Standard prefix
SNJ MIL-STD-883, Class B

Unique Circuit Description - - - - - - - - - - - - - - - - - '

MUST CONTAIN FIVE TO NINE CHARACTERS
(from individual data sheet)

SpeedSort-----------------------------------------~

In nanoseconds

Package----------------------------J
MUST CONTAIN ONE TO THREE LETIERS
DL, DV, DW plastic small-outline package (SOIC)
FK lead less ceramic chip carrier
FN,RJ plastic J-Ieaded chip carrier
GB ceramic pin grid array package
N, NP, NT plastic dual-in-line package
PH JEDEC metric plastic quad fiat package
PAG, PCB, PZ,
PM, PN plastic thin quad flat package
PO JEDEC plastic quad flat package

Tape and Reel Packaging _____________________- . . J

Valid for surface-mount packages only. All orders for tape and reel must be for whole reels.

~TEXAS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 16-3
 MECHANICAL DATA

DL (R·PDS()'G**) PLASTIC SMALL·OUTLINE PACKAGE

48 PIN SHOWN

~ DIM
28 48 56

0.380 0.630 0.730

A MAX
(9.65) (16.00) (18.54)

0.370 0.620 0.720

A MIN (9,40) (15.75) (18.29)

0.299 (7,59)

J
0.291 (7,39)

o 0.420 (10,67)
~m~~~

!-m-r~1
IT'TTTTTI"TT'M'TTTTTT'TTTM
A
T I'T~'~ I'IT 'I~T~T T~TI~~i
~ ~+--i_-..K.l

r ~
t 1 1 0 (2,79) MAX 0.008 (0,20) MI:J
40400481 B 02195

NOTES: A. All linear dimensions are in Inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0.15).

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 16-5
MECHANICAL DATA

DV (R-PDS()'G28) PLASTIC SMALL-OUTLINE PACKAGE

~~~ 1-$-1 0.010 (0,25) @1

I 0.350 (8,89)

~
0'340 (8,84~.478 (12,14)
0.462 (11,73)
~O______________________________4

L
~~~~~~~~~~~~~~~

0.728,,,,,,, ________
0.718 (18,24)
1_4~

rt ~
0.014 (O,36:!J r'".c.--r--.,----,
0.120 (3,05) MAX 0.005 (0,13) L-...I-_-=-~~

40400761 B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC M0-059

~TEXAS
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16-6 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 MECHANICAL DATA

OW (R-POSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16PIN SHOWN

~DIM
16 20 24 28

."..c.-~,-!- I~I 0.010 (0,25) @I A MAX

0.410 0.510 0.610 0.710
(10,41) (12,95) (15,49) (18,03)

0.400 0.500 0.600 0.700

A MIN

fll
(10,16) (12,70) (15,24) (17,78)

O'419 (10,65)
D.400 (10,15)
0.299 (7,59)
0.293 (7,45)

Ir--------.lJ
rt hllIllliJlJlllJ~
0.104 (2,65) MAX
0.012 (0,30t}
0.004 (0,10)

4040000/803195

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013

~TEXAS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 16-7
MECHANICAL DATA

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

NO. OF A B
18 17 16 15 14 13 12
TERMINALS
MIN MAX MIN MAX
**
0.342 0.358 0.307 0.358
19 11 20
(8,69) (9,09) (7,80) (9,09)
20 10 0.442 0.458 0.406 0.458
28
(11,23) (11,63) (10,31) (11,63)
21 9
BSQ 0.640 0.680 0.495 0.560
22 44
8 (16,26) (16,76) (12,58) (14,22)
ASQ
7 0.740 0.761 0.495 0.560
52

llil
(18,78) (19,32) (12,58) (14,22)
24 6
0.938 0.962 0.850 0.858
68
(23,83) (24,43) (21,6) (21,8)
25 5
1.141 1.165 1.047 1.063
84
(28,99) (29,59) (26,6) (27,0)
26 27 28 2 3 4

~. 0.080 (2,03)
~I 0.064(1,63)

0.020 (O,51)
0.010 (O,25)

4040140/C 11/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

~TEXAS
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16-8 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 MECHANICAL DATA

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

~
D1
0.020 (0,51) MIN
3

0 0.032 (0,81)
0.026 (0,66)
4 18
D2/E2

E E1

-*-
C
D2/E2

ll.
14

9 13 0.013 (0,33)
1-$-1 0.007 (0,18) @I
NO. OF DIE D1/E1 D2/E2

..
PINS
MIN MAX MIN MAX MIN MAX

20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29)

28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56)

44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10)

52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37)

68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

40400051 B 03195

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018

~TEXAS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 16-9
MECHANICAL DATA

GA-GB (8-CPGA-P9 X 9) CERAMIC PIN GRID ARRAY PACKAGE

r----- AorA1 SQ I 0.800 (20,32) TYP

J o 0 0 0 0 0 0 0 0

H o @ 0 0 0 0 0 @ 0

G o 0 0 0 0 0 0

F o 0 0 0 0 0 0 0 0

E 0 0 0 0 0 0 000

D 0 0 0 0 0 0 000

Coo 0 0 0 0 000

B o@ooooo@o
A 0 0 0 0 0 0 000

23456789

DIM MIN MAX Notee

A 0.940 (23,88) 0.980 (24,89) Large

Outline
Al 0.880 (22,35) 0.935 (23,75) Small
Outline
B 0.110 (2,79) 0.205 (5,21) Cavity
Up
Bl 0.095 (2,41) 0.205 (5,21) Cavity
CorCl Down
0.140 (3,56) C 0.040 (1,02) 0.060 (1,52) Cavity
Up
0.120 (3,05)
Cl 0.025 (0,63) 0.060 (1,52) Cavity
Down
MAXIMUM PINS WITHIN MATRIX - 81

4040114-2/B 10/94

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Index mark may appear on top or bottom depending on package vendor.
D. Pins are located within 0.005 (0,13) radius 01 true position relative to each other at maximum material condition and within
0.015 (0,38) radius relative to the center 01 the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass lri!.
F. The pins can be gold plated or solder dipped.
G. Falls w~hin MIL-STD-1835 CMGA l-PN and CMGA 13-PN and JEDEC M0-067AA and M0-066AA, respectively

~TEXAS
INSTRUMENTS
16-10 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 MECHANICAL DATA

GA-GB (S-CPGA-P11 X 11) CERAMIC PIN GRID ARRAY PACKAGE

AorA1SQ --------~i 1.100 (25,40) TYP

L 0 0 0

K 0 @) 0 0 0 0 @) 0

0 0
J
0 0 0 0 0
H
0 0 0 0 0
G
F
0 0 0 0
E
D
C
B 0 @) 0 0 0 0 @) 0

A
2 3 4 5 6 7 8 9 10 11

DIM MIN MAX Notes

B orB1 A 1.140 (28,96) 1.180(29,97) Large

Outline
A1 1.080 (27,43) 1.135 (28,83) Small
Outline
B 0.110 (2,79) 0.205 (5,21) Cavity
Up
B1 0.095 (2,41) 0.205 (5,21) Cavity
Down
C 0.040 (1 ,02) 0.060 (1,52) Cavity
Up
C1 0.025 (0,63) 0.060 (1,52) Cavity
Down
MAXIMUM PINS WITHIN MATRIX - 121

4040114-4/B 10/94

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Index mark may appear on top or bottom depending on package vendor.
D. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within
0.015 (0,38) radius relative to the center of the ceramic.
E. This package can be hermetically sealed with metal lids or w~h ceramic lids using glass flit.
F. The pins can be gold plated or solder dipped.
G. Falls within MIL-STD-1835 CMGA3-PN and CMGA 15-PN and JEDEC MO-067AC and Mo-066AC, respectively

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 16-11
MECHANICAL DATA

GA·GB (8-CPGA.P14 X 14) CERAMIC PIN GRID ARRAY PACKAGE

r AorA1 SQ ----+l~1

P o 0 0 0
1.300 (33,02) TYP

0 0 0 0 0 0 0 0 0 0

N o @ 0 0 oooo@o
M o 0 0 0 0 0 000 0 0 000

L o 0 000 0 0 0 0 000

K o 0 0 0 0 0 0 0 0 0 0 0 0 0

J o 0 0 0 0 0 0 0 0 0 0 0 0 0

H o 0 0 0 0 0 000 0 0 0 0 0

G o 0 0 0 0 0 0 0 0 0 0 0 0 0

F o 0 0 0 0 0 0 0 0 0 0 0

E o 0 0 0 0 0 0 0 0 0 0 0 0 0

D o 0 0 0 0 0 o 0 0 0

C o 0 0 0 0 0 0 0 0 0 0 0 0 0

B o@oooo oo@o
A 0 0 0 0 0 0 000 0 0 0 0 0

1 2 3 4 5 6 7 8 9 1011 12 1314

DIM MIN MAX Notes

A 1.440 (33.58) 1.480 (37.59) Large

Outline
B or B1
Ai 1.380 (35,05) 1.435 (36,45) Small
Outline
B 0.110(2,79) 0.205 (5,21) Cavity
Up
B1 0.095 (2,41) 0.205 (5,21) Cavity
Down
C 0.040 (1,02) 0.060 (1,52) Cavity
Up
C1 0.025 (0,63) 0.060 (1,52) Cavity
Down
MAXIMUM PINS WITHIN MATRIX-196

4040114-7/B 10/94

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Index mark may appear on top or bottom depending on package vendor.
D. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within
0.015 (0,38) radius relative to the center of the ceramic.
E. This package can be hermetically sealed wHh metal lids or with ceramic lids using glass frit.
F. The pins can be gold plated or solder dipped.
G. Falls within MIL-STD-1835 CMGA6-PN and CMGA18-PN and JEDEC MO-067AF and MO-066AF, respectively

~ThXAS
INSTRUMENTS
16-12 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 MECHANICAL DATA

N (R·PDIP·T**) PLASTIC DUAL·IN·LINE PACKAGE

16 PIN SHOWN

~DIM
14

0.775
16

0.775
18

0.920
20

0.975
A MAX (19,69) (19,69) (23.37) (24,77)

0.745 0.745 0.850 0.940

A MIN (18,92) (18,92) (21.59) (23.88)

f
0.260 (6,60)
0.240 (6,10)

1 j ~ 0.070 (1~78) MAX

*

r"~=====:\1-
0.035 (0,89) MAX 0.020 (0,51) MIN
,.. • 0.290 17,37)
0.310 (7,8?)

Seating Plane f

JL ~:~~! f~:=J
~ 0.100(2,54) I
'it' 0.010 (0,25) @I
-... \..- 0°-15°

14/18 PIN ONLY

4040049/C 08/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 16-13
MECHANICAL DATA

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

22 PIN SHOWN

A
~.
12
1 DIM

A MAX
22

1.120
(28,45)
24

1.222
(31,04)

0.355 0.360
B MAX
B (9,02) (9,14)

0.020 (0,51) MINRA~ ".001 MAX I~r------.l

~. ~
0.200 (5,08) MAX
Seating Plane
1(\
_ _ _ _ _-'

JL ~0.100(2,54)1
0.021 (0,53) 1-$-1 0.010 (0 25)
0.015 (0,38) ,
@1
0.125 (3,18) MIN

f
0.010 (0,25) NOM
Jl 0'-15'-.
u

4040051/B 10194

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-01 0

~TEXAS
INSTRUMENTS
16-14 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
 MECHANICAL DATA

NP (R-PDIP-T28) PLASTIC DUAL-IN-LINE PACKAGE

1.375
1.345 (34,93)
(34,16) ----------.!I 15
•

I 0.295 (7,49)
0.270 (6,86)

~~~~~~~~~~~
14
0.065 (1,65)
0.045 (1,14)
0.180 (4,57)

r
0.145 (3,68)
0.030 (0,76) 0.325 (8,26)

l
0.015 (0,38) 0.300 (7,62)

~----z----L Seating Plane

Jl
0.150 (3,81)
0.120 (3,05)

JL 0.022 (0,56)
0.015 (0,38)
I.--.I--! 0.100(2,54)

1-$-1 0.010 (0,25) @1

1 f
0.010 (0,25) NOM
0°_15° - - .

4040075/810/94

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimemsions do not include mold flash or protrusion.
D. Falls within JEDEC MO-095

~1EXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265 16-15
MECHANICAL DATA

NT (R·PDIP·T**) PLASTIC DUAL·IN·LINE PACKAGE

24 PIN SHOWN

~DIM
24 28

1.260 1.425
A MAX (32,04) (36,20)

f
0.280 (7,11) A MIN
1.230
(31,24)
1.385
(35,18)
0.250 (6,35)
0.310 0.315
B MAX
* (7,87) (8,00)

j ~ 0.070 (1,78) MAX

12
B MIN
0.290
(7,37)
0.295
(7,49)

GMMWMW
0.020 (0,51) M I N R

J.-.l
.~_"AX ~ Seating Plane r
~18)MIN

JL 0.021 (0,53)
0015 (0 38)
. ,
~ 0.100 (2,54) I
1-$-1 0.010 ( O ' 2 5 ) @ IJL
0.010 (0,25) NOM
t L
0°_15°--..
U

40400501 B 10/94

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

~1ExAs
INSTRUMENTS
16-16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 MECHANICAL DATA

PAG (S·PQFP·G64) PLASTIC QUAD FLATPACK

11: ~:~~ I~I 0,08 @I

49 32

64
o 17

0,13 NOM

1~7."TYP~1
~10'20SQ~ .L.-......--.~=
9,80
1 + - - - - - 12,20 SQ ----~
11,80
I
0,05 MIN

40402821 B 03195

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC M0-136

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 16-17
MECHANICAL DATA

PCB (S·PQFP·G120) PLASTIC QUAD FLATPACK

~11 11 0,23
0,13
61
1-$-1 o,07@1

Heat Slug

91 60

120 31

30
11,60TVP ----+I
14,20 SQ _ _ _~
13,80
16,20 SQ - - - - - . t
15,80

Ef
1,45
1;3s
rbr--U-U-UU-UU-UU-U-UU-UU-UU-U-UU-UU-UU-U-UU-UU""'1IT2h\ l Seating Plane

1,60 MAX V 1C.IO,08 1

4040202/810/94

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MQ-136
D. Thermally enhanced molded plastic package with a heat slug (HSL)

~TEXAS
INSTRUMENTS
16-18 POST OFFICE eox 655303 • DALLAS. TEXAS 75265
 MECHANICAL DATA

PH (R-PQFP-G80) PLASTIC QUAD FLATPACK

64 ~r- 11 ~::: I!'-------------------r

0,16@,

65

~l
14,20 18,00
12,00TVP
13,80 17,20

80 ~J
1 + - - - - - - 18,40TVP - - - - - - - + 1
20,20
19,80
24,00
23,20

2,70TVP
0,70

Seating Plane

4040011/803/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 16-19
MECHANICAL DATA

PM (8-PQFP·G64) PLASTIC QUAD FLATPACK

11 °,27 1•
0,17
33
1 0,08@1

49 32

64 17
o

I~ 7~TVP
~10'20SQ~
rnmr l
9,80
~___________ 12,20SQ ____________~
11,80

Seating Plane

40401521 B 03/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136

~1ExAs
INSTRUMENTS
16-20 POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
 MECHANICAL DATA

PN (8-PQFP·G80) PLASTIC QUAD FLATPACK

1r- 0,271-$-1 0,08 @I

0,17 L.....J;...L-';':';"-=="-'
41

61 40

80
o

I~
L.:==== ,~TVP moor I 12,20 S Q = = = : : . . J
11,80
14-------- 14,20 S Q - - - - - - - - . t
13,80

Seating Plane

1,60 MAX

40401351 A 03/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MD-136

:lllExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 76265 16-21
MECHANICAL DATA

PQ (S·PQFP·G***) PLASTIC QUAD FLATPACK

100 LEAD SHOWN

13 1100 89

14

T
"03"SQ
L
~
0.012 (0,30)
0.006 (0,20)
I-$-I 0.006 (0,15) ® 1
L...J:.-L-~":"":'''''':'''~

1 ~ 0.025 (0,635)

39 63
1 4 - - - - - "01" SQI----~
1 4 - - - - - - "0" SQ - - - - - " " "
14------ "02" S Q - - - - - - - . !

~*
DIM 100 132

MAX 0.890 (22.61) 1.090 (27,69)

"0"
MIN 0.870 (22,10) 1.070(27,18)
MAX 0.766 (19,46) 0.966 (24,54)
"01"
MIN 0.734 (18,64) 0.934 (23,72)
MAX 0.912 (23,16) 1.112 (28,25)
"02"
MIN 0.888 (22,56) 1.088 (27,64)
"03" NOM D.600 (15,24) 0.800 (20,32)
4040045/C 11/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing Is subject to change without notice.
C. Falls within JEOEC MO-o69

~1ExAs
INSTRUMENTS
16-22 POST OFFICE SOX 656303 • DALlAS. TEXAS 75285
 MECHANICAL DATA

PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK

11. 51
0,271-$-1 0,08@1
0,17

76 50

100 26

16,20 SQ - - - - - - - + I
15,80

1,45
1,35

Seating Plane

1,60 MAX

4040149/A 03195

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136

~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 16-23
MECHANICAL DATA

RJ (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER

0.045 (1,14) X 45°

5 29

0.595 (15,11)
0.585 (14,86)

J
0.400 (10,16)
0.553 (14,05) TYP
0.549 (13,94) 0.530 (13,46)
0.490 (12,45)

1..,--.....,.-
.---~~

.I-f----f~=? ~
21 -x--+--f==~

14 20
0.021 (0,53)
0032 (0 81) 0.050 (1 ,27) TYP
0.013 (0,33)
~
0.01 2 (0,30)
0.008 (0,20) --- 0:026 (0:66)

~ H H H H H H t---
f
~--I--- Seating Plane

I.-- 0.300 (7,62)

TYP
----.I 1.<::::>.1 0.004 (0,10) 1

0.430 (10,92)
0.390 (9,91)
4040077/8 02196

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.

~1ExAs
INSTRUMENTS'
16-24 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
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• TEXAS
INSTRUMENTS
 ~lExAs
INSTRUMENTS
Printed in U.S.A. SCAD003C
0496-CP '